S E M I C O N D U C T O R HI1396, CXA1396 8-Bit, 125 MSPS Flash A/D Converter February 1996 Features * * * * * * * * * * * * Description Differential Linearity Error 0.5 LSB (Typ) or Less Integral Linearity Error 0.5 LSB (Typ) or Less Built-In Integral Linearity Compensation Circuit Ultra High Speed Operation with Maximum Conversion Rate of 125 MSPS (Min) Low Input Capacitance 18pF (Typ) Wide Analog Input Bandwidth 200MHz (Min for FullScale Input) Single Power Supply -5.2V Low Power Consumption 870mW (Typ) Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50 Loads Evaluation Board Available The HI1396, CXA1396 is an 8-bit ultra high speed flash analog-to-digital converter IC capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K. The HI1396, CXA1396 is available in the Commercial and Industrial temperature ranges and is supplied in a 68 lead ceramic LCC, 42 lead ceramic DIP and plastic DIP packages. Ordering Information PART NUMBER Applications * Video Digitizing * Communication Systems * HDTV (High Definition TV) * Radar Systems * Direct RF Down-Conversion * Digital Oscilloscopes TEMPERATURE RANGE PACKAGE HI1396JCJ, CXA1396D -20oC to +75oC 42 Lead Ceramic DIP HI1396AIL, CXA1396K -20oC to +100oC 68 Lead Ceramic LCC HI1396JCP, CXA1396P -20oC to +75oC 42 Lead Plastic DIP Pinouts AVEE 1 42 NC NC 2 41 VRT LINV 3 40 NC DVEE 4 39 AVEE DGND1 5 38 AVEE DGND2 6 37 NC (LSB) D0 7 36 NC D1 8 35 AGND D2 9 34 VIN D3 10 33 AGND D4 11 32 VRM D5 12 31 AGND D6 13 30 VIN 29 AGND DGND2 15 28 NC DGND2 16 27 NC DVEE 17 26 AVEE MINV 18 25 AVEE NC 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 NC AVEE AVEE NC VRT NC AVEE NC NC NC LINV NC DVEE NC DGND1 DGND2 NC 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 23 VRB CLK 21 22 NC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright (c) Harris Corporation 1996 NC AVEE AVEE NC VRB NC NC NC CLK CLK NC MINV NC DVEE NC NC NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 24 NC CLK 20 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 NC NC NC NC (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 NC DGND2 DGND1 NC NC (MSB) D7 14 HI1396, CXA1396 (LCC) TOP VIEW NC NC NC NC NC AGND VIN AGND VRM AGND VIN AGND NC NC NC NC NC HI1396, CXA1396 (CDIP, PDIP) TOP VIEW 1 File Number 3576.2 HI1396, CXA1396 Functional Block Diagram MINV R1 COMPARATOR VRT R/2 R 1 R D7 (MSB) 2 R D6 63 D5 R 64 VIN R D4 65 OUTPUT D3 R 126 D2 R 127 R2 VRM ENCODE LOGIC R D1 128 R D0 (LSB) 129 R 191 R 192 VIN R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 2 Specifications HI1396, CXA1396 Absolute Maximum Ratings TA = +25oC Thermal Information Supply Voltage (AVEE, DVEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT, VRB, VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA Storage Temperature Range (TSTG). . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Thermal Resistance JA JC HI1396JCP, CXA1396P . . . . . . . . . . . . . . 52oC/W HI1396JCJ, CXA1396D. . . . . . . . . . . . . . 36oC/W 12oC/W HI1396AIL, CXA1396K . . . . . . . . . . . . . . 38oC/W 10oC/W Maximum Power Dissipation Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.61W Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44W Operating Temperature (Note 4) HI1396JCP, CXA1396P TA . . . . . . . . . . . . . . . . . . -20oC to +75oC HI1396JCJ, CXA1396D TA . . . . . . . . . . . . . . . . . . -20oC to +75oC HI1396AIL, CXA1396K TC. . . . . . . . . . . . . . . . . . -20oC to +100oC Maximum Junction Temperature HI1396JCP, CXA1396P . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC HI1396JCJ, CXA1396D HI1396AIL, CXA1396K . . . . . . . . +175oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions (Note 1) Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock TPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns Min. TPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns Min. Supply Voltage AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE-DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND-DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Electrical Specifications TA = +25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 - - Bits - - 0.5 LSB - - 0.8 LSB - - 0.5 LSB - - 0.7 LSB 200 - - MHz - 18 - pF 50 190 - k 20 130 400 A 75 110 155 SYSTEM PERFORMANCE Resolution Integral Linearity Error, (INL) HI1396JCJ, CXA1396D HI1396AIL, CXA1396K FC = 125MHz HI1396JCP, CXA1396P Differential Linearity Error, (DNL) HI1396JCJ, CXA1396D HI1396AIL, CXA1396K FC = 125MHz HI1396JCP, CXA1396P ANALOG INPUT Input Bandwidth VIN = 2VP-P Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS Analog Input Resistance, RIN Input Bias Current, IIN VIN = -1V REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT VRT 8 19 32 mV EOB VRB 0 9 24 mV 3 Specifications HI1396, CXA1396 Electrical Specifications TA = +25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.50 V DIGITAL INPUTS Logic H Current, IIH Input Connected to -0.8V 0 - 50 A Logic L Current, IIL Input Connected to -1.6V 0 - 50 A - 7 - pF Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 50 to -2V -1.10 - - V Logic L Level, VOL RL = 50 to -2V - - -1.62 V TIMING CHARACTERISTICS Output Rise Time, TR RL = 50 to -2V, 20% to 80% 0.5 0.9 1.2 ns Output Fall Time, TF RL = 50 to -2V, 20% to 80% 0.5 1.0 1.3 ns Output Delay, TOD 3.0 3.6 4.2 ns H Pulse Width of Clock, TPW1 4.0 - - ns L Pulse Width of Clock, TPW0 4.0 - - ns 125 - - MSPS Aperture Jitter, TAJ - 10 - ps Sampling Delay, TDS - 1.5 - ns Input = 1MHz, Full Scale FC = 125MHz - 46 - dB Input = 31.5MHz, Full Scale FC = 125MHz - 40 - dB Error Rate Input = 31.249MHz, Full Scale Error > 16 LSB, FC = 125MHz - - 10-9 TPS (Note 2) Differential Gain Error, DG NTSC 40IRE Mod. Ramp, FC = 125 MSPS - 1.0 - % - 0.5 - Degree -230 -160 - mA - 870 - mW DYNAMIC CHARACTERISTICS Maximum Conversion Rate, FC Signal to Noise Ratio (SINAD) RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion Differential Phase Error, DP Error Rate 10-9 TPS (Note 2) POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption Note 3 NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 3. P D = I EE *V V 2 -V RT RB + -----------------------------------------EE R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. 4 HI1396, CXA1396 Timing Diagram ANALOG IN N+1 N N+2 TPW1 TPW0 CLK CLK DIGITAL OUT N-1 80% 20% N 20% N+1 80% TR TOD TF FIGURE 1. Pin Descriptions and I/O Pin Equivalent Circuit PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 29, 31, 33, 35 49, 51, 53, 55 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. 1, 25, 26, 38, 39 41, 42, 62, 63, 67 AVEE - -5.2V Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4 to 6). Bypass with 0.1F to AGND. 21 35 CLK I ECL EQUIVALENT CIRCUIT DESCRIPTION CLK Input DGND1 20 34 CLK R R R R CLK CLK R DVEE 5 R Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. HI1396, CXA1396 Pin Descriptions and I/O Pin Equivalent Circuit PIN NUMBER (Continued) DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 5, 16 7, 24 DGND1 - 0V Digital GND for internal circuits. 6, 15 8, 23 DGND2 - 0V Digital GND for output transistors. 4, 17 5, 30 DVEE - -5.2V Digital VEE. Internally connected to AVEE (resistance: 4 to 6). Bypass with 0.1F to DGND 7 14 D0 O ECL EQUIVALENT CIRCUIT DESCRIPTION DGND2 8 15 D1 9 16 D2 10 17 D3 11 18 D4 12 19 D5 13 20 D6 14 21 D7 3 3 LINV Data outputs. External pull-down resistors are required. DI MSB of data outputs. External pull-down resistor is required. DVEE I ECL Input pin for D0 (LSB) to D6 output polarity inversion (see A/D Output Code Table). Pulled low when left open. DGND1 18 32 MINV I ECL Input pin for D7 (MSB) output polarity inversion (see A/D Output Code Table). Pulled low when left open. R R 30, 34 50, 54 VIN LSB of data outputs. External pull-down resistor is required. I LINV OR MINV R DVEE R -1.3V VRT to VRB AGND VIN VIN AVEE 6 Analog input pins. These two pins must be connected externally, since they are not internally connected. HI1396, CXA1396 Pin Descriptions and I/O Pin Equivalent Circuit PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 23 39 VRB I -2V (Continued) EQUIVALENT CIRCUIT VRT DESCRIPTION Reference voltage (bottom). Typically -2V. Bypass with a 0.1F and 10F to AGND. R1 R/2 32 52 41 65 VRM VRT I VRB/2 I Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically 0V. When a voltage different from AGND is applied to this pin, bypass with a 0.1F and 10F to AGND. R COMPARATOR 1 0V R COMPARATOR 2 R VRM COMPARATOR 127 R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 1, 2, 4, 6, 9-13, 25-29, 31, 33, 36-38, 40, 43-48, 56-61, 64, 66, 68 NC - R/2 R3 - Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended. A/D OUTPUT CODE TABLE MINV 1, LINV 1 VIN (Note 1) STEP 0V 0 1 -1V 127 128 254 255 -2V D7 D0 0, 1 D7 1, 0 D0 D7 0, 0 D0 D7 D0 000 * * * * * 00 000 * * * * * 00 000 * * * * * 01 * * * 011 * * * * * 11 100 * * * * * 00 * * * 111 * * * * * 10 111 * * * * * 11 100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 111 * * * * * 11 011 * * * * * 11 100 * * * * * 00 000 * * * * * 00 NOTE: 1. VRT = 0V, VRB = -2V. 7 HI1396, CXA1396 Test Circuits SIGNAL SOURCE fCLK 4 VIN 8 HI1396, CXA1396 CLK A ECL LATCH COMPARATOR A>B B CLK -1kHz ECL LATCH + 2VP-P SINEWAVE DATA 16 SIGNAL SOURCE FCLK/4 fCLK FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT HI20201 DUT HI1396, CXA1396 VIN AMP CLK 8 8 ECL LATCH 10 BIT D/A CLK NTSC SIGNAL SOURCE DELAY SG (CW) 50 VBB VECTOR SCOPE DG.DP FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT +V S2 - S1 : A < B : ON S2 : A > B : ON S1 + -V A<B VIN DUT HI1396, CXA1396 A>B COMPARATOR 8 "0" A8 B8 A1 A0 B1 B0 8 BUFFER "1" DVM 8 CLK (125MHz) 00000000 TO 11111110 CONTROLLER FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 8 PULSE COUNTER HI1396, CXA1396 Test Circuits (Continued) IIN 42 1 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 12 HI1396JCJ HI1396JCP CXA1396D/P 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 32 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 -1V -2V A IIN 33 10 11 A -1V 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 HI1396AIL CXA1396K 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 -2V A IEE -5.2V A IEE -5.2V FIGURE 5A. FIGURE 5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS 0V -1V VIN -2V 67.5MHz AMP OSC1 : VARIABLE CLK VIN fR CLK HI1396, CXA1396 LOGIC ANALYZER t t VIN OSC2 67.5MHz 8 1024 SAMPLES ECL BUFFER CLK 129 128 127 126 125 (LSB) APERTURE JITTER Aperture jitter is defined as follows: T FIGURE 6A. AJ 256 = ------- = ---------- x 2f t 2 FIGURE 6B. APERTURE JITTER TEST METHOD Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 9 HI1396, CXA1396 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A- D42.6 LEAD FINISH 42 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE -DBASE METAL E b1 M (b) M -Bbbb S C A - B S INCHES (c) SECTION A-A D S D BASE PLANE S2 Q -C- SEATING PLANE A L S1 eA A A b2 b e ccc M C A - B S D S eA/2 c aaa M C A - B S D S SYMBOL MIN MAX MIN MAX NOTES A 0.142 0.225 3.60 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.022 0.36 0.56 3 b2 0.035 0.043 1.90 1.10 - b3 - - - - 4 c 0.009 0.015 0.23 0.38 2 c1 0.009 0.012 0.23 0.30 3 D 2.083 2.122 52.9 53.9 - E 0.510 0.620 12.95 15.75 - e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - 7.62 BSC - eA/2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. MILLIMETERS 0.300 BSC L 0.130 - 3.30 - - Q 0.039 - 1.00 - 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 90o 105o 90o 105o - aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. M - 0.0015 - 0.038 2 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. N 42 42 8 Rev. 0 4/94 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. 10 HI1396, CXA1396 Ceramic Leadless Chip Carrier Packages (CLCC) J68.A 0.010 S E H S 68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE D INCHES D3 j x 45o E3 B E SYMBOL MIN MAX MIN MAX NOTES A 0.067 0.087 1.70 2.20 6, 7 A1 0.058 0.072 1.47 1.83 - B - - - - - B1 0.033 0.039 0.85 0.99 2, 4 B3 0.006 0.022 0.15 0.56 - D 0.940 0.965 23.88 24.51 D1 D2 h x 45o 0.010 S E F S A1 2 E 0.940 0.965 23.88 24.51 - PLANE 2 PLANE 1 e1 e -H- L3 - 16.05 j L 10.16 BSC 15.65 E3 B1 - 0.632 E2 0.007 M E F S H S 0.400 BSC 20.32 BSC 0.616 e -E- 0.800 BSC D3 E1 A MILLIMETERS 0.800 BSC 0.400 BSC 0.616 0.632 0.050 BSC 0.015 20.32 BSC 10.16 BSC 15.65 - 16.05 1.27 BSC - 0.38 0.040 Ref - 2 - - 2 1.00 Ref 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 17 17 3 NE 17 17 3 N 68 68 3 Rev. 0 5/18/94 NOTES: -F- 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. B3 E1 E2 L2 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) B2 L1 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. D2 e1 D1 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 11 HI1396, CXA1396 Dual-In-Line Plastic Packages (PDIP) E42.6 N 42 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL MIN MAX MIN MAX NOTES A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - -B-AE D BASE PLANE A2 -C- SEATING PLANE e B1 D1 C L 0.010 (0.25) M 0.014 0.022 0.356 0.558 - 0.030 0.070 0.77 1.77 8, 10 C 0.008 0.015 D 1.980 2.095 D1 0.005 - 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 eA A1 eC B B B1 A L D1 C eB C A B S NOTES: e 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. MILLIMETERS 0.204 0.381 50.3 0.100 BSC - 53.2 5 - 5 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 42 42 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor P. O. 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