FINAL Advanced Micro Devices Am27LV010/Am27LV010B 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS EPROM DISTINCTIVE CHARACTERISTICS Single +3.3 V power supply -- Regulated power supply 3.0 V-3.6 V -- Unregulated power supply 2.7 V-3.6 V (for battery operated systems) Fast Flashrite programming -- Typical programming time of 16 seconds Low power consumption: -- 10 A typical CMOS standby current -- 30 W typical standby power -- 20 mW typical power at 5 MHz High noise immunity Compact 32-pin DIP, PDIP, PLCC, and TSOP packages Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions Fast access time--100 ns JEDEC-approved pinout -- Pin compatible with 5.0 V 1 Mbit EPROM -- Easy upgrade from 28-pin EPROMs Latch-up protected to 100 mA from -1 V to VCC +1 V GENERAL DESCRIPTION The Am27LV010 is a low voltage, low power 1 Mbit, ultraviolet erasable, progammable read-only memory, organized as 128K words by 8 bits per word. The Am27LV010 operates from a single power supply of 3.3 V and is offered with two power supply tolerances. The Am27LV010 has a VCC tolerance range of 3.3 V 0.3 V making it suitable for use in systems that have regulated power supplies. The Am27LV010B has a voltage supply range of 2.7 V-3.6 V making it an ideal part for battery operated systems. Maximum power consumption of the Am27LV010 in standby mode is only 90 W. If the device is constantly accessed at 5 MHz, then the maximum power consumption increases to 54 mW. These power ratings are significantly lower than typical EPROMs. Also, as power consumption is proportional to voltage squared, 3.3 V BLOCK DIAGRAM CE PGM A0-A16 Address Inputs The Am27LV010 is packaged in the industry standard 32-pin windowed ceramic DIP packages, as well as one-time programmable (OTP) packages. This device is pin-compatible with the 5.0 V devices. The Am27LV010 uses AMD's Flashrite programming algorithm (100 s pulses) resulting in typical programming time of 16 seconds. This device is manufactured on AMD's sub-micron process technology which provides high speed, low power and high noise immunity. Data Outputs DQ0-DQ7 VCC VSS VPP OE devices consume at least 57% less power than their 5.0 V counterparts. Due to its lower current and voltage, the Am27LV010 is well-suited for battery operated and portable systems as it extends the battery life in these systems. Typical applications are notebook and handheld computers as well as cellular phones. Output Enable Chip Enable and Prog Logic Output Buffers Y Decoder Y-Gating X Decoder 1,048,576-Bit Cell Matrix 17341C-1 3-4 Publication# 17341 Rev. C Issue Date: May 1995 Amendment /0 AMD PRODUCT SELECTOR GUIDE Family Part No Am27LV010/Am27LV010B Ordering Part No: Am27LV010 (3.0 V - 3.6 V) Am27LV010B (2.7 V - 3.6 V) Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) -100 -120 -120 120 120 50 100 100 50 -150 -150 150 150 65 -200 -200 200 200 75 CONNECTION DIAGRAMS Top View DIP -250 -250 250 250 100 -300 -300 300 300 120 32 VCC A16 2 31 PGM (P) A15 3 30 NC A16 VPP A12 4 29 A14 4 3 2 1 32 31 30 A7 5 28 A13 A7 5 29 A14 A6 6 27 A8 A6 6 28 A13 A5 A4 7 8 27 26 A8 A9 A3 9 25 A11 A2 10 24 OE (G) A1 11 23 A10 A0 12 22 CE (E) DQ0 13 21 DQ7 8 25 A11 9 A2 10 24 23 OE (G) A10 A1 11 22 CE (E) A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 14 15 16 17 18 19 20 DQ1 DQ2 A3 17341C-2 DQ6 A4 DQ5 A9 DQ4 26 VSS 7 DQ3 A5 PGM (P) NC 1 VCC VPP A12 A15 PLCC 17341C-3 Note: 1. JEDEC nomenclature is in parentheses. TSOP* A11 A9 A8 A13 A14 NC PGM VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Standard Pinout *Contact local AMD sales office for package availability. Am27LV010/Am27LV010B 17341C-4 3-5 AMD PIN DESCRIPTION A0-A16 = Address Inputs CE (E) = Chip Enable Input LOGIC SYMBOL 17 A0-A16 DQ0-DQ7 = Data Input/Outputs NC = No Internal Connection OE (G) = Output Enable Input PGM (P) = Program Enable Input PGM (P) VCC = VCC Supply Voltage OE (G) VPP = Program Voltage Input VSS = Ground 3-6 8 DQ0-DQ7 CE (E) 17341C-5 Am27LV010/Am27LV010B AMD ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27LV010 -100 D C B OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27LV010 - 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS UV EPROM with 3.0 V- 3.6 V VCC Tolerance Am27LV010B - 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS UV EPROM with 2.7 V - 3.6 V VCC Tolerance Valid Combinations AM27LV010-100 AM27LV010-120 AM27LV010-150 AM27LV010-200 AM27LV010-250 AM27LV010-300 AM27LV010B-120 AM27LV010B-150 AM27LV010B-200 AM27LV010B-250 AM27LV010B-300 DC, DCB Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC, DCB, DI, DIB Am27LV010/Am27LV010B 3-7 AMD ORDERING INFORMATION OTP Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27LV010 -120 J C OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE E = 32-Pin Thin Small Outline Plastic Package (TS 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27LV010 - 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS OTP EPROM with 3.0 V-3.6 V VCC Tolerance Am27LV010B - 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS OTP EPROM with 2.7 V-3.6 V VCC Tolerance Valid Combinations AM27LV010-120 AM27LV010-150 AM27LV010-200 AM27LV010-250 AM27LV010-300 AM27LV010B-150 AM27LV010B-200 AM27LV010B-250 AM27LV010B-300 3-8 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. JC, EC, JI, EI Am27LV010/Am27LV010B AMD FUNCTIONAL DESCRIPTION Erasing the Am27LV010 In order to clear all locations of their programmed contents, it is necessary to expose the Am27LV010 to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase an Am27LV010. This dosage can be obtained by exposure to an ultraviolet lamp -- wavelength of 2537 A -- with intensity of 12,000 W/ cm2 for 15 to 20 minutes. The Am27LV010 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27LV010, and similar devices, will erase with light sources having wavelengths shorter than 4000 A . Although erasure times will be much longer than with UV sources at 2537 A , nevertheless the exposure to fluorescent light and sunlight will eventually erase the Am27LV010 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27LV010 Upon delivery, or after each erasure, the Am27LV010 has all 1,048,576 bits in the "ONE", or HIGH state. "ZEROs" are loaded into the Am27LV010 through the procedure of programming. The programming mode is entered when 12.75 V 0.25 V is applied to the VPP pin, CE and PGM are at VIL and OE is at VIH. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite programming algorithm reduces programming time by using initial 100 s pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the EPROM. The Flashrite programming algorithm programs and verifies at VCC = 6.25 V and VPP = 12.75 V. After the final address is completed, all bytes are compared to the original data with VCC = VPP = 5.25 V. Am27LV010 can be programmed using the same algorithm as the 5 V counterpart Am27C010. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27LV010s in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27LV010 may be common. A TTL low-level program pulse applied to an Am27LV010 CE input with VPP = 12.75 0.25 V, PGM LOW, and OE HIGH will program that Am27LV010. A high-level CE input inhibits the other Am27LV010s from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at VIL, PGM at VIH, and VPP between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the Am27LV010. To activate this mode, the programming equipment must force 12.0 0.5 V on address line A9 of the Am27LV010. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. For the Am27LV010, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27LV010 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC-tOE. Standby Mode The Am27LV010 has a CMOS standby mode which reduces the maximum VCC current to 25 A. It is placed in CMOS-standby when CE is at VCC 0.3 V. The Am27LV010 also has a TTL-standby mode which reduces the maximum VCC current to 0.6 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Am27LV010/Am27LV010B 3-9 AMD Mixed Power Supply System Am27LV010 (in 3.0 V to 3.6 V regulated power supply) can be interfaced with 5 V system only when the I/O pins (DQ0-DQ7) are not driven by the 5 V system. VIHmax = VCCLV + 2.2 V for address and clock pins and VIHmax = VCCLV + 0.5 V for I/O pins should be followed to avoid CMOS latch-up condition. Output OR-Tieing To accommodate multiple memory connections, a twoline control function is provided to allow for: Low memory power dissipation Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Pins CE OE PGM A0 A9 VPP VIL VIL X X X X DOUT Output Disable X VIH X X X X High Z Standby (TTL) VIH X X X X X High Z High Z Mode Read Outputs VCC 0.3 V X X X X X Program VIL VIH VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP High Z Auto Select (Note 3) Manufacturer Code VIL VIL X VIL VH X 01H Device Code VIL VIL X VIH VH X 0EH Standby (CMOS) Notes: 1. VH = 12.0 V 0.5 V 2. X = VIH or VIL 3. A1-A8 = A10-A16 = VIL 4. See DC Programming Characteristics for VPP voltage during programming. 3-10 Am27LV010/Am27LV010B AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: OTP Products . . . . . . . . . . . . . . -65C to +125C All Other Products . . . . . . . . . . . -65C to +150C Commercial (C) Devices Ambient Temperature (TA) . . . . . . . 0C to +70C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Voltage with Respect to VSS: All pins except A9, VPP, and VCC (Note 1) . . . . . . . . . . . . -0.6 V to VCC + 0.6 V A9 and VPP (Note 2) . . . . . . . . . . . -0.6 V to 13.5 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to 7.0 V Industrial (I) Devices Ambient Temperature (TA) . . . . . -40C to +85C Supply Read Voltages: VCC for Am27LV010 . . . . . . . . . . +3.0 V to +3.6 V VCC for Am27LV010B . . . . . . . . . +2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Notes: 1. During transitions, the input may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. During transitions, A9 and VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. A9 and VPP must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. This is a stress rating only; functional operation of the devices at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Am27LV010/Am27LV010B 3-11 AMD DC CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 2, 3, and 4) Parameter Symbol Parameter Description Test Conditions Min TTL and CMOS Inputs for Am27LV010 (VCC = 3.0 V to 3.6 V) Output HIGH Voltage IOH = -2.0 mA VOH VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current VIN = 0 V to VCC ILO Output Leakage Current ICC1 Max 2.4 IOL = 2.0 mA Unit V 0.4 V 2.0 VCC + 0.3 V -0.3 +0.8 V 1.0 A VOUT = 0 V to VCC 5 A VCC Active Current (Note 3) CE = VIL, f = 5 MHz IOUT = 0 mA (Open Outputs) 15 mA ICC2 VCC TTL Standby Current CE = VIH 0.6 mA ICC3 VCC CMOS Standby Current CE = VCC 0.3 V 25 A IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 1.0 A Parameter Symbol Parameter Description Test Conditions Max Unit CMOS Inputs for Am27LV010B (VCC = 2.7 V to 3.6 V) Output HIGH Voltage IOH = -20 A VOH IOH = -100 A Min VCC VCC - 0.1 - 0.2 IOL = 20 A IOL = 100 A V V VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current ILO Output Leakage Current VOUT = 0 V to +VCC 5 A 15 mA ICC1 VCC Active Current (Note 3) CE = VIL, f = 5 MHz, IOUT = 0 mA (Open Outputs) ICC2 VCC TTL Standby Current CE = VIH 0.6 mA ICC3 VCC CMOS Standby Current CE = VCC 0.3 V 25 A IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 1.0 A VIN = 0 V to +VCC 0.1 0.2 V V 2.0 VCC + 0.3 V -0.3 0.8 V 1.0 A Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. Caution: The Am27LV010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 4. Minimum DC Input Voltage is -0.3 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC +0.3 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 3-12 Am27LV010/Am27LV010B 10 10 7.5 7.5 Supply Current in mA Supply Current in mA AMD 5 2.5 0 1 2 3 4 5 6 7 8 9 10 5 2.5 0 -75 -50 -25 0 25 50 75 100 125 150 Temperature in C Frequency in MHz Figure 1. Typical Supply Current vs. Frequency VCC = 3.6 V, T = 25C Figure 2. Typical Supply Current vs. Temperature VCC = 3.6 V, f = 5 MHz 17341C-6 17341C-7 CAPACITANCE Parameter Symbol CIN COUT CDV032 PL 032 TS 032 Parameter Description Test Conditions Typ Max Typ Max Typ Max Unit Input Capacitance VIN = 0 V 10 12 8 10 10 12 pF Output Capacitance VOUT = 0 V 12 15 9 12 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz. Am27LV010/Am27LV010B 3-13 AMD SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 3, and 4) Am27LV010/Am27LV010B Parameter JEDEC Standard Description Test Conditions -100 -120 -150 -200 -250 -300 Unit ns tAVQV tACC Address to Output Delay CE = OE =VIL Min Max - 100 - 120 - 150 - 200 - 250 - 300 tELQV tCE Chip Enable to Output Delay OE = VIL Min - - - - - - Max 100 120 150 200 250 300 Output Enable to Output Delay CE = VIL tGLQV tEHQZ tGHQZ tAXQX tOE tDF tOH Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float (Note 2) Output Hold from Addresses, CE, or OE, whichever occurred first Min - - - - - - Max 50 50 65 75 100 100 Min 0 0 0 0 0 0 ns ns Max 40 40 50 60 60 60 Min 0 0 0 0 0 0 Max - - - - - - ns Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27LV010 must not be removed from, or inserted into, a socket when VPP or VCC is applied. 4. Output Load: 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.40 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2.0 V inputs and outputs 3-14 ns Am27LV010/Am27LV010B AMD SWITCHING TEST CIRCUIT 2.7 k Device Under Testing 5.0 V CL Diodes = IN3064 or Equivalent 6.2 k 17341C-8 CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORM 2.4 V 2.0 V 2.0 V Test Points 0.8 V 0.8 V 0.45 V Input Output 17341C-9 AC Testing: Inputs are driven at 2.4 V for a Logic "1" and 0.45 V for a Logic "0". Input pulse rise and fall times are 20 ns. Am27LV010/Am27LV010B 3-15 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Changing from H to L May Change from L to H Will Be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance "Off" State KS000010 SWITCHING WAVEFORM 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE tCE OE Output High Z tACC (Note 1) tOE tOH Valid Output Notes: High Z 17341C-10 1. OE may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first. 3-16 tDF (Note 2) Am27LV010/Am27LV010B