Publication# 17341 Rev. CAmendment/0
Issue Date: May 1995
3-4
Am27LV010/Am27LV010B
1 Megabit (131,072 x 8-Bit) Low Voltage CMOS EPROM
Advanced
Micro
Devices
FINAL
DISTINCTIVE CHARACTERISTICS
■Single +3.3 V power supply
— Regulated power supply 3.0 V–3.6 V
— Unregulated power supply 2.7 V–3.6 V
(for battery operated systems)
■Low power consumption:
— 10 µA typical CMOS standby current
— 30 µW typical standby power
— 20 mW typical power at 5 MHz
■Fast access time—100 ns
■JEDEC-approved pinout
— Pin compatible with 5.0 V 1 Mbit EPROM
— Easy upgrade from 28-pin EPROMs
■Fast Flashrite programming
— Typical programming time of 16 seconds
■Latch-up protected to 100 mA from –1 V to
VCC +1 V
■High noise immunity
■Compact 32-pin DIP, PDIP, PLCC, and TSOP
packages
■Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
GENERAL DESCRIPTION
The Am27LV010 is a low voltage, low power 1 Mbit,
ultraviolet erasable, progammable read-only memory,
organized as 128K words by 8 bits per word.
The Am27LV010 operates from a single power supply of
3.3 V and is offered with two power supply tolerances.
The Am27LV010 has a VCC tolerance range of 3.3 V ±
0.3 V making it suitable for use in systems that have
regulated power supplies. The Am27LV010B has a volt-
age supply range of 2.7 V–3.6 V making it an ideal part
for battery operated systems.
Maximum power consumption of the Am27LV010 in
standby mode is only 90 µW. If the device is constantly
accessed at 5 MHz, then the maximum power consump-
tion increases to 54 mW. These power ratings are sig-
nificantly lower than typical EPROMs. Also, as power
consumption is proportional to voltage squared, 3.3 V
devices consume at least 57% less power than their
5.0 V counterparts. Due to its lower current and voltage,
the Am27LV010 is well-suited for battery operated and
portable systems as it extends the battery life in these
systems. Typical applications are notebook and hand-
held computers as well as cellular phones.
The Am27LV010 is packaged in the industry standard
32-pin windowed ceramic DIP packages, as well as
one-time programmable (OTP) packages. This device
is pin-compatible with the 5.0 V devices.
The Am27LV010 uses AMD’s Flashrite programming
algorithm (100 µs pulses) resulting in typical program-
ming time of 16 seconds. This device is manufactured
on AMD’s sub-micron process technology which pro-
vides high speed, low power and high noise immunity.
17341C-1
VCC
VPP
OE
CE
PGM
Output Enable
Chip Enable
and
Prog Logic
X
Decoder
Y
Decoder
Output Buffers
Y-Gating
1,048,576-Bit
Cell Matrix
A0–A16
Address
Inputs
Data Outputs
DQ0–DQ7
BLOCK DIAGRAM
VSS
AMD
3-5Am27LV010/Am27LV010B
PRODUCT SELECTOR GUIDE
Family Part No
Ordering Part No:
Am27LV010 (3.0 V – 3.6 V) -100 -120 -150 -200 -250 -300
Am27LV010B (2.7 V – 3.6 V) -120 -150 -200 -250 -300
Max Access Time (ns) 100 120 150 200 250 300
CE (E) Access (ns) 100 120 150 200 250 300
OE (G) Access (ns) 50 50 65 75 100 120
Am27LV010/Am27LV010B
CONNECTION DIAGRAMS
Top View DIP
Note:
1. JEDEC nomenclature is in parentheses.
17341C-2
PLCC
VPP VCC
DQ0
A5
A12
A7 A14
1
3
5
7
9
11
12
10
2
4
8
6
32
30
28
26
24
14
21
23
31
29
25
27
A15
13
22
20
19
A6
15
16 18
17
A4
A3
A2
A1
A0
DQ1
PGM (P)
NC
A13
A8
A9
A11
OE (G)
A10
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
A16
VSS
DQ2
17341C-3
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE (G)
A10
CE (E)
DQ7
A12
A15
A16
VPP
VCC
PGM (P)
NC
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
17341C-4
*Contact local AMD sales office for package availability.
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
NC
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Standard Pinout
TSOP*
AMD
3-6 Am27LV010/Am27LV010B
17341C-5
A0–A16
DQ0–DQ7
CE (E)
PGM (P)
OE (G)
8
17
LOGIC SYMBOL
PIN DESCRIPTION
A0–A16 = Address Inputs
CE (E) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
NC = No Internal Connection
OE (G) = Output Enable Input
PGM (P) = Program Enable Input
VCC =V
CC Supply Voltage
VPP = Program Voltage Input
VSS = Ground
AMD
3-7Am27LV010/Am27LV010B
ORDERING INFORMATION
UV EPROM Products
AM27LV010-100
AM27LV010-120
AM27LV010-150
AM27LV010-200
AM27LV010-250
AM27LV010-300
AM27LV010B-120
AM27LV010B-150
AM27LV010B-200
AM27LV010B-250
AM27LV010B-300
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27LV010 – 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS UV EPROM with
3.0 V–3.6 V VCC Tolerance
Am27LV010B – 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS UV EPROM with
2.7 V–3.6 V VCC Tolerance
AM27LV010 -100 D C
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
DC, DCB
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard processing
B = Burn-in
B
DC, DCB,
DI, DIB
AMD
3-8 Am27LV010/Am27LV010B
ORDERING INFORMATION
OTP Products
AM27LV010-120
AM27LV010-150
AM27LV010-200
AM27LV010-250
AM27LV010-300
AM27LV010B-150
AM27LV010B-200
AM27LV010B-250
AM27LV010B-300
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 32-Pin Thin Small Outline Plastic
Package (TS 032)
J = 32-Pin Rectangular Plastic Leaded
Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27LV010 – 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS OTP EPROM with
3.0 V–3.6 V VCC Tolerance
Am27LV010B – 1 Megabit (131,072 x 8-Bit) Low Voltage CMOS OTP EPROM with
2.7V–3.6 V VCC Tolerance
AM27LV010 -120 J C
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard processing
JC, EC, JI, EI
AMD
3-9Am27LV010/Am27LV010B
FUNCTIONAL DESCRIPTION
Erasing the Am27LV010
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27LV010 to an ul-
traviolet light source. A dosage of 15 W seconds/cm2 is
required to completely erase an Am27LV010. This dos-
age can be obtained by exposure to an ultraviolet lamp
— wavelength of 2537A
° — with intensity of 12,000 µW/
cm2 for 15 to 20 minutes. The Am27LV010 should be di-
rectly under and about one inch from the source and all
filters should be removed from the UV light source prior
to erasure.
It is important to note that the Am27LV010, and similar
devices, will erase with light sources having wave-
lengths shorter than 4000 A
°. Although erasure times will
be much longer than with UV sources at 2537A
°,
nevertheless the exposure to fluorescent light and sun-
light will eventually erase the Am27LV010 and exposure
to them should be prevented to realize maximum sys-
tem reliability. If used in such an environment, the pack-
age window should be covered by an opaque label
or substance.
Programming the Am27LV010
Upon delivery, or after each erasure, the Am27LV010
has all 1,048,576 bits in the “ONE”, or HIGH state.
“ZEROs” are loaded into the Am27LV010 through the
procedure of programming.
The programming mode is entered when 12.75 V
± 0.25 V is applied to the VPP pin, CE and PGM are at VIL
and OE is at VIH.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
The Flashrite programming algorithm reduces program-
ming time by using initial 100 µs pulses followed by a
byte verification to determine whether the byte has been
successfully programmed. If the data does not verify, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through
each address of the EPROM.
The Flashrite programming algorithm programs and
verifies at VCC = 6.25 V and VPP = 12.75 V. After the final
address is completed, all bytes are compared to the
original data with VCC = VPP = 5.25 V. Am27LV010 can
be programmed using the same algorithm as the 5 V
counterpart Am27C010.
Please refer to Section 6 for programming flow chart
and characteristics.
Program Inhibit
Programming of multiple Am27LV010s in parallel with
different data is also easily accomplished. Except for
CE, all like inputs of the parallel Am27LV010 may be
common. A TTL low-level program pulse applied to an
Am27LV010 CE input with VPP = 12.75 ± 0.25 V, PGM
LOW, and OE HIGH will program that Am27LV010. A
high-level CE input inhibits the other Am27LV010s from
being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with OE and CE at VIL, PGM
at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the Am27LV010.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the
Am27LV010. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH. All other address lines must be
held at VIL during auto select mode.
Byte 0 (A0 = VIL) represents the manufacturer code, and
Byte 1 (A0 = VIH), the device identifier code. For the
Am27LV010, these two identifier bytes are given in the
Mode Select table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
Read Mode
The Am27LV010 has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC–tOE.
Standby Mode
The Am27LV010 has a CMOS standby mode which re-
duces the maximum VCC current to 25 µA. It is placed in
CMOS-standby when CE is at VCC ± 0.3 V. The
Am27LV010 also has a TTL-standby mode which re-
duces the maximum VCC current to 0.6 mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
AMD
3-10 Am27LV010/Am27LV010B
Mixed Power Supply System
Am27LV010 (in 3.0 V to 3.6 V regulated power supply)
can be interfaced with 5 V system only when the I/O pins
(DQ0–DQ7) are not driven by the 5 V system. VIHmax =
VCCLV + 2.2 V for address and clock pins and VIHmax =
VCCLV + 0.5 V for I/O pins should be followed to avoid
CMOS latch-up condition.
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
■ Low memory power dissipation
■ Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the power
supply is connected to the array.
MODE SELECT TABLE
Mode CE OE PGM A0 A9 VPP Outputs
Read VIL VIL XXXXD
OUT
Output Disable X VIH X X X X High Z
Standby (TTL) VIH X X X X X High Z
Standby (CMOS) VCC ± 0.3 V X X X X X High Z
Program VIL VIH VIL XXV
PP DIN
Program Verify VIL VIL VIH XXV
PP DOUT
Program Inhibit VIH XX XXV
PP High Z
VIL VIL XV
IL VHX 01H
VIL VIL XV
IH VHX 0EH
Manufacturer Code
Device Code
Auto Select
(Note 3)
Notes:
1. VH = 12.0 V
±
0.5 V
2. X = VIH or VIL
3. A1–A8 = A10–A16 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.
Pins
AMD
3-11Am27LV010/Am27LV010B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature:
OTP Products –65°C to +125°C. . . . . . . . . . . . . .
All Other Products –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Voltage with Respect to VSS:
All pins except A9, VPP, and
VCC (Note 1) –0.6 V to VCC + 0.6 V. . . . . . . . . . . .
A9 and VPP (Note 2) –0.6 V to 13.5 V. . . . . . . . . . .
VCC –0.6 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
1. During transitions, the input may overshoot V
SS
to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O may overshoot to V
CC
+ 2.0 V for periods up to
20 ns.
2. During transitions, A9 and V
PP
may overshoot V
SS
to
–2.0 V for periods of up to 20 ns. A9 and V
PP
must not ex-
ceed 13.5 V for any period of time.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. This is a stress rat-
ing only; functional operation of the devices at these or any
other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device
reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)0°C to +70°C. . . . . . .
Industrial (I) Devices
Ambient Temperature (TA) –40°C to +85°C. . . . .
Supply Read Voltages:
VCC for Am27LV010 +3.0 V to +3.6 V. . . . . . . . . .
VCC for Am27LV010B +2.7 V to +3.6 V. . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
AMD
3-12 Am27LV010/Am27LV010B
DC CHARACTERISTICS over operating ranges unless otherwise specified
(Notes 1, 2, 3, and 4)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –20 µAV
CC – 0.1 V
IOH = –100 µAV
CC – 0.2 V
VOL Output LOW Voltage IOL = 20 µA 0.1 V
IOL = 100 µA 0.2 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Load Current VIN = 0 V to +VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to +VCC 5µA
CE = VIL,15mA
I
CC1 VCC Active Current (Note 3) f = 5 MHz,
IOUT = 0 mA
(Open Outputs)
ICC2 VCC TTL Standby Current CE = VIH 0.6 mA
ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 25
IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 1.0 µA
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. Caution: The Am27LV010 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. I
CC1
is tested with
OE
= V
IH
to simulate open outputs.
4. Minimum DC Input Voltage is –0.3 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
CC
+0.3 V, which may overshoot to V
CC
+ 2.0 V for periods less than 20 ns.
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –2.0 mA 2.4 V
VOL Output LOW Voltage IOL = 2.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage –0.3 +0.8 V
ILI Input Load Current VIN = 0 V to VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to VCC 5µA
ICC1 VCC Active Current (Note 3) CE = VIL,15mA
f = 5 MHz
IOUT = 0 mA
(Open Outputs)
ICC2 VCC TTL Standby Current CE = VIH 0.6 mA
ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 25 µA
IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 1.0 µA
TTL and CMOS Inputs for Am27LV010 (VCC = 3.0 V to 3.6 V)
µA
CMOS Inputs for Am27LV010B (VCC = 2.7 V to 3.6 V)
AMD
3-13Am27LV010/Am27LV010B
-75 -50 -25 0 25 50 75 100 125 150
Frequency in MHz
17341C-7
12345678910
10
7.5
5
2.5
0
Supply Current
in mA
Supply Current
in mA
Temperature in °C
Figure 1. Typical Supply Current
vs. Frequency
VCC = 3.6 V, T = 25°C
Figure 2. Typical Supply Current
vs. Temperature
VCC = 3.6 V, f = 5 MHz
17341C-6
10
7.5
5
2.5
0
CAPACITANCE
CDV032 PL 032 TS 032
Symbol Parameter Description Test Conditions Typ Max Typ Max Typ Max Unit
CIN Input Capacitance VIN = 0 V 10 12 8 10 10 12 pF
COUT Output Capacitance VOUT = 0 V 12 15 9 12 12 14 pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25
°
C, f = 1 MHz.
Parameter
AMD
3-14 Am27LV010/Am27LV010B
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
(Notes 1, 3, and 4)
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27LV010 must not be removed from, or inserted into, a socket when VPP or VCC is applied.
4. Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.40 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2.0 V inputs and outputs
Parameter Test
JEDEC Standard Description Conditions -100 -120 -150 -200 -250 -300 Unit
tAVQV tACC Address to CE = OE =VIL Min – – – – – –
Max 100 120 150 200 250 300
tELQV tCE Chip Enable Min – – – – – –
Max 100 120 150 200 250 300
tGLQV tOE Output Enable to Min – – – – – –
Max 50 50 65 75 100 100
tEHQZ tDF Chip Enable HIGH
tGHQZ or Output Enable Min 0 0 0 0 0 0
HIGH, whichever
comes first, to
Output Float Max 40 40 50 60 60 60
(Note 2)
tAXQX tOH Output Hold from Min 0 0 0 0 0 0
Addresses, CE, or
OE, whichever Max – – – – – –
occurred first
Output Delay
to Output Delay
Output Delay
OE = VIL
CE = VIL
ns
Am27LV010/Am27LV010B
ns
ns
ns
ns
AMD
3-15Am27LV010/Am27LV010B
SWITCHING TEST CIRCUIT
17341C-8
5.0 V
Diodes = IN3064
or Equivalent
CL6.2 kΩ
2.7 kΩ
CL = 100 pF including jig capacitance
Device
Under
Testing
SWITCHING TEST WAVEFORM
Test Points
2.0 V
0.8 V 0.8 V
2.0 V
2.4 V
0.45 V Input Output 17341C-9
AC Testing: Inputs are driven at 2.4 V for a Logic “1” and 0.45 V for a Logic “0”. Input pulse rise and fall times are ≤ 20 ns.
AMD
3-16 Am27LV010/Am27LV010B
KEY TO SWITCHING WAVEFORMS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010
SWITCHING WAVEFORM
Addresses
CE
OE
Output
17341C-10
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF
(Note 2)
tOH
Notes:
1.
OE
may be delayed up to t
ACC
– t
OE
after the falling edge of the addresses without impact on t
ACC.
2. t
DF
is specified from
OE
or
CE
, whichever occurs first.
