5962-9954001NXD - Texas Instruments

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

10-Bit Resolution 20 MSPS Sampling

Analog-to-Digital Converter (ADC)

Power Dissipation . . . 107 mW Typ

5-V Single Supply Operation

Differential Nonlinearity . . . ±0.5 LSB Typ

No Missing Codes

Power Down (Standby) Mode

Three State Outputs

Digital I/Os Compatible With 5-V or 3.3-V

Logic

Adjustable Reference Input

Small Outline Package (SOIC), Super Small

Outline Package (SSOP), or Thin Small

Outline Package (TSOP)

Pin Compatible With the Analog

Devices AD876

applications

Communications

Multimedia

Digital Video Systems

High-Speed DSP Front-End ...TMS320C6x

description

The TLC876 is a CMOS, low-power, 10-bit, 20

MSPS analog-to-digital converter (ADC). The

speed, resolution, and single-supply operation

are suited for applications in video, multimedia,

imaging, high-speed acquisition, and commu-

nications. The low-power and single-supply operation satisfy requirements for high-speed portable

applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color

scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with

output error correction logic provides for no missing codes over the full operating temperature range. Force and

sense connections to the reference inputs provide a more accurate internal reference voltage to the reference

resistor string.

A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or

3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output

data is straight binary coding.

A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876

distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively

higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a

small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within

each of the stages permits the first stage to operate on a new input sample while the second through the fifth

stages operate on the four preceding samples.

The TLC876C is characterized for operation from 0°C to 70°C, the TLC876I is characterized for operation from

–40°C to 85°C, and the TLC876M is characterized for operation over the full military temperature range of –55°C

to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

AGND

DRVDD

DRGND

DGND

AVDD

AIN

CML

REFBS

REFBF

REFTF

REFTS

DGND

AGND

DVDD

STBY

CLK

(TOP VIEW)

NC – No internal connection

DB, DW, OR PW PACKAGE

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

TASUPER SMALL

OUTLINE

(DB)

SMALL

OUTLINE

(DW)

TSSOP

(PW)

0°C to 70°C TLC876CDB TLC876CDW TLC876CPW

–40°C to 85°C TLC876IDB TLC876IDW TLC876IPW

–55°C to 125°C — TLC876MDW —

functional block diagram

ADC DAC ADC DAC ADC DAC

ADC

Correction Logic

Output Buffers

SHA†SHA†GAIN SHA†GAIN SHA†GAIN

AIN

(MSB) D9

(LSB) D0

†Sample and hold amplifier

22 22

ADC DAC

SHA†GAIN

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent input and output circuits

DVDD

DGND

DRVDD

DRGND

DVDD DRVDD

DGND DRGND

AVDD

AGND

AVDD

AVSS

AVDD

AGND

REFTF

REFTS

Internal Reference

Voltage

AVDD

AGND

AVDD

AVSS

REFBF

REFBS Internal Reference

Voltage

D0–D9 OUTPUT CIRCUIT ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT

REFERENCE INPUT CIRCUIT

D0–D9 CLK AIN 0.5 pF typ

30 Ω typ

0.3 pF

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AGND 1, 19 Analog ground

AIN 27 IAnalog input

AVDD 28 5-V analog supply

CLK 15 IClock input

CML 26 OBypass for an internal bias point. Typically a 0.1 µF capacitor minimum is connected from this terminal to ground.

DGND 14, 20 Digital ground

DVDD 18 5-V digital supply

DRVDD 23.3-V/5-V digital supply. Supply for digital input and output buffers.

DRGND 13 3.3-V/5-V digital ground. Ground for digital input and output buffers.

D0–D9 3–12 ODigital data out. D0:LSB, D9:MSB

OE 16 IOutput enable. When OE = low or NC, the device is in normal operating mode. When OE = high, D0–D9 are high

impedance.

REFBF 24 IReference bottom force

REFBS 25 IReference bottom sense

REFTF 22 IReference top force

REFTS 21 IReference top sense

STBY 17 IStandby enable. When STBY = low or NC, the device is in normal operating mode. When STBY = high, the device

is in standby mode.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, AVDD to AGND, DVDD to DGND –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range to AGND, VI(REFTF), VI(REFBF), VI(REFBS),

VI(REFTS) –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range applied from external source –0.5 V to DVDD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLC876C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC876I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC876M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

DISSIPATION RATING TABLE

PACKAGE TA ≤ 25°C

POWER RATING DERATING FACTOR

ABOVE TA = 25°C ‡TA = 70°C

POWER RATING TA = 85°C

POWER RATING TA = 125°C

POWER RATING

DB 1353 mW 10.82 mW/°C866 mW 703 mW —

DW 1598 mW 12.78 mW/°C 1023 mW 831 mW 320 mW

PW 1207 mW 9.65 mW/°C772 mW 627 mW —

‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistance is not production tested,

and values given are for informational purposes only.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

analog and reference inputs

MIN NOM MAX UNIT

Reference input voltage (top), VI(REFT) VI(REFB) + 1 3.6 4.5 V

Reference input voltage (bottom), VI(REFB) 0 1.6 VI(REFT) – 1 V

Analog input voltage, VI(AIN) 1 2 Vpp

power supply

MIN NOM MAX UNIT

AVDD †4.5 5.25

Supply voltage DVDD†4.5 5.25 V

DRVDD 3 5.25

†The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.

digital inputs

MIN NOM MAX UNIT

DRVDD = 3 V 2.4

High-level input voltage, VIH DRVDD = 5 V 4V

DRVDD = 5.25 V 4.2

DRVDD = 3 V 0.6

Low-level input voltage, VIL DRVDD = 5 V 1V

DRVDD = 5.25 V 1.05

Clock period, tc (see Figure 1) 50 ns

Pulse duration, clock high, tw(CLKH) 23 25 ns

Pulse duration, clock low, tw(CLKL) 23 25 ns

TLC876C 0 70

Operating free-air temperature, TATLC876I –40 85 °C

TLC876M –55 125

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,

fCLK = 20 MSPS (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AVDD†17 25 mA

IDD Operating supply current DVDD†2.7 5 mA

DRVDD 25 100 µA

PDPower dissipation 107 150 mW

PD(STBY)

Standby

ower

STBY = High

CLK running 45 85

D(STBY)

Standb

STBY

High

CLK inhibited at VDD or 0 V 15 35

†The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.

digital logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IIH High-level input current, STBY, OE DVDD = 5 V 1.9 mA

IIH High-level input current, all other inputs DVDD = 5 V 10 µA

IIL Low-level input current DVDD = 5V –50 50 µA

IIL(CLK) Low-level input current, CLK DVDD = 5V –10 10 µA

CiInput capacitance 5 pF

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOH =50µA

DRVDD = 3 V 2.4

VOH High-level output voltage

OH =

DRVDD = 5 V 3.8 V

IOH = 0.5 mA DRVDD = 5 V 2.4

IOL =50µA

DRVDD = 3.6 V 0.7

VOL Low-level output voltage

OL =

DRVDD = 5.25 V 1.05 V

IOL = 0.6 mA DRVDD = 5.25 V 0.4

CoOutput capacitance 5 pF

IOZ High-impedance-state output current –10 10 µA

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,

fCLK = 20 MSPS (unless otherwise noted)

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Integral nonlinearity (INL) ±1.5

LSB

Differential nonlinearity (DNL) (see Note 1) ±0.5 <±1

LSB

Offset error –0.4 %FSR

Gain error 0.2 %FSR

NOTE 1: A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

analog input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CiInput capacitance 5 pF

reference input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Rref Reference input resistance 350 500 Ω

Iref Reference input current 4 mA

Reference top offset voltage 35 mV

Reference bottom offset voltage 35 mV

dynamic performance†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

All suffixes fI = 1 MHz 8.5

Eff ti b f bit (ENOB)

All suffixes fI = 3.58 MHz,

TA = 25°C8 8.5

Bit

Effective number of bits (ENOB) C and I suffixes f

= 3.58 MHz, 8 8.5 Bits

M suffix

TA = Full Range 7.5

All suffixes fI = 10 MHz 8.1

All suffixes fI = 1 MHz 53

nal-to-total harmonic distortion+noise All suffixes fI = 3.58 MHz,

TA = 25°C50 53

Signal to total

harmonic

distortion+noise

(S/(THD+N)) C and I suffixes f

= 3.58 MHz, 50 53 dB

M suffix

TA = Full Range 47

All suffixes fI = 10 MHz 51

fI = 1 MHz –63

Total harmonic distortion (THD) fI = 3.58 MHz –62 –56 dB

fI = 10 MHz –61

Spurious free dynamic range fI = 3.58 MHz –64 dB

BW Analog input full-power bandwidth 200 MHz

Differential phase 0.5 degrees

Differential gain 1%

†The voltage difference between A VDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At input clock rise times less than

20 ns, the offset full-scale error increases approximately by a factor of (20/tr)0.5 where tr equals the actual rise time in nanoseconds.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,

fCLK = 20 MSPS (unless otherwise noted)

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fconv Maximum conversion rate (see Note 2) 20 MHz

td(o) Delay time, output CL = 20 pF 5 20 ns

td(pipe) Delay time, pipeline, latency 3.5 Clock

cycles

td(A) Delay time, aperture 4 ns

Aperture jitter 22 ps

tdis(DD) Disable time, OE↑ to Hi-Z

CL=20

5 15 ns

ten(HL) Enable time, OE↓ to valid data

L =

5 15 ns

NOTE 2: The conversion rate can be a minimum of 10 kHz without degradation in specified performance.

PARAMETER MEASUREMENT INFORMATION

D0 – D9 Data N–4 Data N–3 Data N–2 Data N–1 Data N

tw(CLKH) tw(CLKL)

Sample N Sample N+1 Sample N+2

AIN

CLK

td(o)

td(pipe)

td(A)

td(o)

Figure 1. Timing Diagram

tdis(DD) ten(HL)

High Impedance

Active

D0–D9

Figure 2. Output Enable to Data Output Timing Diagram

STBY

CLK

Output Data Valid

Figure 3. Standby Timing

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 4

–2

–4

–6

–10

–8

1 10 100 1000

G – Gain – dB

f – Input Frequency – MHz

GAIN

INPUT FREQUENCY

Figure 5

SINAD – Signal-to-Noise and Distortion – dB

f – Input Frequency – MHz

SIGNAL-TO-NOISE AND DISTORTION

INPUT FREQUENCY

110

fCLK = 20 MSPS

AIN = –0.5 dB

Figure 6

110

THD – Total Harmonic Distortion – dB

f – Input Frequency – MHz

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

–10

–30

–50

–70

–90

THD

2 nd

3 rd

Figure 7

40 5101520

SINAD – Signal-to-Noise and Distortion – dB

SIGNAL-TO-NOISE AND DISTORTION

CLOCK FREQUENCY

f – Clock Frequency – MHz

fIN = 3.58 MHz

AIN = –0.5 dB

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 8

120

110

800 5 10 15

– Power Dissipation – mW

f – Clock Frequency – MHz

POWER DISSIPATION

CLOCK FREQUENCY

100

130

140

150

Figure 9. Differential Nonlinearity

0.2

–0.2

–1

Input Code

255 511 767 10230

DNL – Differential Nonlinearity – LSB

–0.4

–0.6

–0.8

0.4

0.6

0.8

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10. Integral Nonlinearity

INL – Integral Nonlinearity – LSB

–3

Input Code

–1

255 511 767 10230

–2

SFDR : –64 dB 4th : –68 dB

SNRD : 52 dB 5th : –71 dB

SNR : 55 dB 6th : –71 dB

THD : –62 dB 7th : –70 dB

2nd : –69 dB 8th : –70 dB

3rd : –72 dB 9th : –80 dB

Figure 11. FFT Plot of Dynamic Performance

Frequency – MHz

74 2 983

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

definitions of specifications and terminology

integral nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points. This parameter is sometimes referred to as linearity error.

differential nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than

1 LSB ensures no missing codes. This parameter is sometimes

referred to as differential error.

offset error

The first transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual

first code transition from that point.

gain error

The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage

applied to the REFBF terminal). The last transition should occur for an analog value 1 1/2 LSB below nominal

positive full scale (the voltage applied to the REFTF terminal). Gain error is the deviation of the actual difference

between the first and last code transitions from the ideal difference between the first and last code transitions.

pipeline delay (latency)

The number of clock cycles between conversion initiation on an input sample and the corresponding output data

being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.

reference top/bottom offset

Resistance between the reference input and comparator input tap points causes offset errors. These errors can

be nulled out by using the force-sense connection as shown in the

driving the reference terminals

section.

driving the analog input

Figure 12 shows an equivalent input circuit of the TLC876 sample-and-hold amplifier and it represents an

excellent first order approximation.

The total equivalent capacitance, CE, is typically less than 5 pF and the input source must be able to charge

or discharge this capacitance to 10-bit accuracy in the sample period of one half of a clock cycle. When the

switch S1 closes, the input source must charge or discharge the capacitor CE from the voltage already stored

on CE (the previously captured sample) to the new voltage. In the worst case, a full-scale voltage step on the

input, the input source must provide the charging current through the switch resistance RSW (50 Ω) of S1 and

quickly settle (within 1/2 CLK period), and, therefore, the source is driving a low input impedance. However,

when the source voltage equals the value previously stored on CE, the hold capacitor requires no input current

to maintain the charge and the equivalent input impedance is extremely high.

Adding series resistance between the output of the source and the AIN terminal reduces the drive requirements

placed on the source, as shown in Figure 13. To maintain the frequency performance outlined in the

specifications, the resistor should be limited to 200 Ω minus the source resistance or less. The maximum source

resistance, RS, for 10-bit, 1/2 LSB accuracy is given by equation 1.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

driving the analog input (continued)

2f(CLK) (CEln 2048) –R

SW (1)

For f(CLK) = 20 MHz, CE = 10 pF, and RSW = 100 Ω, this equation gives 228 Ω as a maximum value; hence the

200 Ω limit on the total source resistance. For applications with an input clock less than 20 MHz, the size of the

series resistor can increase proportionally. Alternatively, adding a shunt capacitor between the AIN terminal and

analog ground can lower the ac source impedance. This capacitance value depends on the source resistance

and the required signal bandwidth.

The input span is determined by the reference voltages (see driving the reference terminals section).

Figure 12. TLC876 Simplified Equivalent Input

AIN

RSW

Driving

Source

TLC876

RS ≤ 200 ΩAIN

Figure 13. Sample TLC876 Drive Requirements

TLC876

Ideal Source

For many applications, particularly in single supply operation, ac-coupling offers a convenient way of biasing

the analog input signal at the proper signal range. Figure 14 shows a typical configuration for ac-coupling the

analog input signal to the TLC876. Maintaining the outlined specifications requires careful selection of the

component values. The most important concern is the f–3 dB high-pass corner that is a function of R2, and the

parallel combination of C1 and C2. The f–3 dB point can be approximated by equation 2.

3dB

(R2)Ceq (2)

where Ceq is the parallel combination of C1 and C2. Since C1 is typically a large electrolytic or tantalum

capacitor, the impedance becomes inductive at high frequencies. Adding a small ceramic or polystyrene

capacitor , C2 of approximately 0.01 µF, which is not inductive within the frequency range of interest, maintains

a low impedance. If the minimum expected input signal frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals

50 Ω, the parallel capacitance of C1 and C2 must be a minimum of 0.008 µF to avoid attenuating signals close

to 20 kHz.

AIN

VIN

–VBIAS

R1 TLC876

Figure 14. AC-Coupled Inputs

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

driving the analog input (continued)

The expanded input circuit shown in Figure 15 aids in understanding the voltage offset generation when using

the external input circuit in Figure 14.

The ac-coupling capacitors, C1 and C2, integrate the switching transients present at the input of the TLC876

causing a net dc bias current, IB, to flow into the input. The magnitude of this bias current increases with

increasing the dc signal level, VB, and also increases with sample frequency . When the sample clock frequency

is 20 MHz, the dc bias current is approximately 30 µA† at VBIAS equal to 3 V dc. This bias current causes an

offset error of (R1 + R2) x IB at the AIN terminal. Making R2 negligibly small or modifying VBIAS to account for

the resultant offset can compensate for this error. Note however that R2 loads the signal driving source, and

the value must be sufficient for the application.

For example, as shown in Figure 15, when VBIAS is 3 V and the resistor values stated above, the bias current

causes a 31.5 mV‡ offset from the 3 V bias, VBIAS, at the AIN terminal. For the TLC876, VBIAS can be as low

as 1 V for a 2 V peak-to-peak input signal swing.

AIN

VIN

–VBIAS

R1 TLC876

RSW

Figure 15. Bias Current and Offset

For systems that require dc-coupling, an op-amp can level-shift a ground-referenced signal to comply with the

input requirements of the TLC876. Figure 16 shows an amplifier in an inverting mode with ac signal gain of –1.

The dc voltage at the noninverting input of the op-amp controls the amount of dc level shifting. A resistive voltage

divider attenuates the REFBF signal and the op-amp then multiplies the attenuated signal by 2. In the case

where REFBF = 1.6 V, the dc output level is 2.6 V which is approximately equal to (V(REFTF) – V(REFBF)/2.

†IB(AVG) = CE (VB) fCLK ≈ 30 µA, with RSW = 50 Ω, CE = 5 pF, R1 = 50 Ω, and R2 = 1 kΩ

‡VOFFSET = IB(AVG) (R1 + R2)

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

driving the analog input (continued)

7NC

0.1 µF

VCC

RL = 4.99 kΩ

AIN

TLC876

14.7 kΩ

3 kΩ

RIN = 4.99 kΩ

2V(PP)

REFBF

0 V dc –

+A†

†Amplifier A can be an AD817 or AD818 with terminal numbers as shown. The AD817 and AD818

are wide bandwidth single supply op-amps.

Figure 16. Bipolar Level Shift

driving the reference terminals

dc considerations

The TLC876 requires an external reference on terminals REFTF and REFBF and a resistor array, nominally

500 Ω, is connected between terminals REFTF and REFBF. A Kelvin connection, using the TLC876 reference

sense terminals REFTS and REFBS, minimizes voltage drops caused by external and internal wiring

resistance.

Figure 17 shows the equivalent input structure for the reference terminals. There is approximately 5 Ω of

resistance between both REFTF and REFBF terminals and the reference ladder. If the force-sense connections

are not used, the voltage drop across the 5-Ω resistors results in a reduced voltage appearing across the ladder

resistance. This reduces the input span of the converter. Applying a slightly larger span between the REFTF

and REFBF terminals compensates for this error. Note that the temperature coefficients of the 5-Ω resistors are

1350 ppm. The effects of temperature should be considered when a force-sense reference configuration is not

used.

5 Ω

RARRAY

500 ΩC (Equivalent)

CLK

TLC876

REFTF

REFTS

REFBS

REFBF

DAC

10 Ω5 Ω5 Ω5 Ω

Figure 17. TLC876 Equivalent Reference Structure

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

dc considerations (continued)

The REFTS and REFBS terminals should not be connected in configurations that do not use a force-sense

reference. Connecting the force and sense lines together allows current to flow in the sense lines. Any current

allowed to flow through these lines must be negligibly small. Current flow causes voltage drops across the

resistance in the sense lines. Because the internal DACs tap different points along the sense lines, each DAC

would receive a slightly different reference voltage if current were flowing in these lines. T o avoid this undesirable

condition, leave the sense lines unconnected. Any current allowed to flow through these lines must be negligibly

small (< 100 µA).

The voltage drop across the internal resistor array (RARRAY) determines the input span. The nominal differential

voltage is 2 Vpp. The full-scale input span is given by equation 3.

Input Voltage Span = V(REFTS) – V(REFBS) (3)

Therefore, a full-scale input span is approximately 2 V when [V(REFTS) – V(REFBS)] = 2 V. The external

reference must provide approximately 4 mA for a 2-V drop across the internal resistor array.

Figure 18 shows the flexibility in determining both the full-scale span of the analog input and where to center

this voltage without degrading the typical performance.

2.5

0.5

00 0.5 1 1.5 2 2.5 3

REFTF, REFTS

3.5

4.5

REFBF, REFBS

3.5 4

1.5

2 V Span

1 V Span

Figure 18. TLC876 Reference Ranges

ac considerations

The simplified diagram of Figure 17 shows that the reference terminals connect to a capacitor for one half of

the clock period. The size of the capacitor is a function of the analog input voltage, therefore producing dynamic

impedance changes at the reference inputs.

The external reference source must be able to maintain a low impedance over all frequencies of interest to

provide the charge required by the capacitance. By supplying the requisite charge, the reference voltages

remain relatively constant maintaining specified performance. For some reference configurations, voltage

transients are present on the reference lines, especially during the falling edge of CLK. The reference must

recover from the transients and settle to the desired level of accuracy prior to the rising edges of CLK.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

ac considerations (continued)

Several useful reference configurations can be used depending on the application, desired level of accuracy,

and cost tradeoffs. The simplest configuration, shown in Figure 19, utilizes a resistor divider to generate the

reference voltages from the converters analog power supply. The 0.1 µF bypass capacitors reduce high

frequency transients. The 10 µF capacitors reduce the impedances at the REFTF and REFBF terminals at lower

frequencies; however , as input frequencies approach dc, the capacitors become ineffective, and small voltage

deviations appear across the biasing resistors. This reference method maintains 10-bit accuracy for input

frequencies above approximately 200 Hz and 8-bit accuracy applications for input frequencies above

approximately 50 Hz.

10 µF 0.1 µF

140 Ω (± 1%) NC

REFTS

REFTF

REFBF

REFBS

250 Ω (± 1%)

5 V 4 V

2 V

TLC876

NC – No connect

500 Ω

Figure 19. Low Cost Reference Circuit

The reference configuration in Figure 19 provides the lowest cost, but the disadvantages include reduced dc

power supply rejection and reduced accuracy due to the variability of the internal and external resistors.

The force-sense reference connections can eliminate the voltage drops associated with the internal

connections to the reference ladder . Figure 20 shows a circuit using a dual, rail-to-rail single-supply operational

amplifier. The operational amplifier should provide stable 3.6 V and 1.6 V reference voltages. Each half of the

amplifier is compensated to drive 1 µF and 0.1 µF decoupling capacitors at the REFTF and REFBF terminals

maintaining stability. The operational amplifiers are connected as voltage followers.

By connecting the operational amplifier feedback through the sense connections of the TLC876, the outputs

of the operational amplifiers automatically adjust to compensate for the voltage drops that occur within the

converter.

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

ac considerations (continued)

5 V C3

0.1 µF

REFT

REFB

REFTS

REFTF

REFBS

REFBF

TLC876

0.1 µF

Figure 20. Kelvin Connection Reference Using an Operational Amplifier

With Unlimited Capacitive Load Drive Capability

Figure 21 shows a circuit using a dual operational amplifier with unlimited capacitive load drive. The operational

amplifier should provide stable 3.6 V and 1.6 V reference voltages for REFTF and REFBF, respectively. The

amplifier must be able to maintain stability while driving unlimited capacitive loads, so the 0.1 µF capacitors C1

and C2 can connect directly to the outputs of the operational amplifiers, which reduces high frequency

transients. Capacitors C3 and C4 shunt across the internal resistors of the force-sense connections and prevent

instability. The stability of any operational amplifier used must be examined closely when driving capacitive

loads.

+1 µF

REFT

REFB

REFTS

REFTF

REFBS

REFBF

TLC876

0.1 µF

1 µF 0.1 µF

10 kΩ

10 Ω

10 kΩ

10 Ω

A†

†This device is 1/2 of a TLV2442. The TLV2442 is a rail-to-rail output dual operational

amplifier.

A†

10 kΩ0.1 µF

Figure 21. Kelvin Connection Reference Using an Operational Amplifier

With Unlimited Capacitive Load Drive Capability

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

layout and decoupling

With high-frequency high-resolution converters, the layout and decoupling of the reference is critical. The actual

voltage digitized by the TLC876 is relative to the reference voltages. In Figure 22, for example, the reference

return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the

ground of the analog input, that are common mode to the REFTF, REFBF, and AIN terminals because of the

common ground, are effectively removed by the TLC876 high common mode rejection. Also, these capacitors

should be connected as close to reference terminals as possible.

High-frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops

between the analog input ground and the reference bypassing points are treated as input signals by the

converter using the reference inputs. Consequently , the reference decoupling capacitors should be connected

to the same physical analog ground point used by the analog input voltage (see the grounding and layout rules

section).

AIN

REFTF

4 V VN1

4 V VN2

REFBF

TLC876

Figure 22. Recommended Bypassing for the Reference

clock input

The clock input is buffered internally with an inverter powered from the DRVDD terminal, which accommodates

either 5-V or 3.3-V CMOS logic input signal swings with the input threshold for the CLK terminal nominally at

DRVDD/2.

The internal pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty

cycle variations, the recommended logic family to drive the clock input is high-speed or advanced CMOS

(HC/HCT , AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and

fall times to support 20 MSPS operation.

The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency.

Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption.

digital inputs and outputs

Each of the digital control inputs, OE and STBY, has an input buffer powered from the DR VDD supply terminal.

With DRVDD set to 5 V, all digital inputs readily interface with 5 V CMOS logic. Using lower voltage CMOS logic,

DRVDD can be set to 3.3 V , lowering the nominal input threshold of all digital inputs to (3.3 V)/2 = 1.65 V , typically.

The digital output format is straight binary. For example, Table 1 shows the output format for voltage levels of

V(REFTS) = 4 V and V(REFBS) = 2 V.

A low power mode feature is provided such that when STBY is high and the clock is disabled, the static power

of the TLC876 drops significantly (see electrical characteristics table).

TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

digital inputs and outputs (continued)

Table 1. Output Data Format

AIN VOLTAGE THREE DATA

(APPROXIMATE) STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

> 4 V 0 1111111111

4 V 0 1111111111

3 V 0 1000000000

2 V 0 0000000000

< 2 V 0 0000000000

X 1 Z Z Z Z Z Z Z Z Z Z

grounding and layout rules

Proper grounding and layout techniques are essential for achieving optimal performance. The analog and digital

grounds on the TLC876 have been separated to optimize the management of return currents in a system. A

printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes should be used with

the TLC876. The use of ground and power planes offers distinct advantages:

Minimizes the loop area encompassed by a signal and its return path

Minimizes the impedance associated with ground and power paths

The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane

These characteristics produce a reduction of electromagnetic interference (EMI) and an overall improvement

in performance.

A properly designed layout prevents noise from coupling onto the input signal. Digital signal traces should not

run parallel with the input signal traces and should be routed away from the input circuitry . The separate analog

and digital grounds should be joined together directly under the TLC876. A solid ground plane under the TLC876

is also acceptable if no significant currents are flowing in that portion of the ground plane under the device. The

general rule for mixed signal layouts is that return currents from digital circuitry should not pass through or under

critical analog circuitry . The system design should minimize the analog lead-in to reduce potential noise pickup.

digital outputs

The DRVDD supply terminal powers each of the on-chip buf fers for the output bits (D0–D9) and is a separate

lead from AVDD or DVDD. The output drivers are sized to drive a variety of logic families, while minimizing the

amount of glitch energy generated. A recommended fan-out of one keeps the capacitive load on the output data

drivers below the specified 20 pF level.

For DRVDD = 5 V, the output signal swing can drive both high-speed CMOS and TTL logic families. For TTL,

the on-chip output drivers are designed to support several of the high-speed TTL families (F, AS, S). For

applications where the clock rate is below 20 MSPS, other TTL families are appropriate. For interfacing with

lower voltage CMOS logic, the TLC876 sustains 20 MSPS operation with DRV DD = 3.3 V . Refer to logic family

data sheets for compatibility with the TLC876 digital specifications.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

5962-9954001NXD ACTIVE SOIC DW 28 1 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC876CDB OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876CDBLE OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876CDBR OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876CDW OBSOLETE SOIC DW 28 TBD Call TI Call TI

TLC876CDWR OBSOLETE SOIC DW 28 TBD Call TI Call TI

TLC876CPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI

TLC876CPWR OBSOLETE TSSOP PW 28 TBD Call TI Call TI

TLC876IDB OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876IDBLE OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876IDBR OBSOLETE SSOP DB 28 TBD Call TI Call TI

TLC876IDW OBSOLETE SOIC DW 28 TBD Call TI Call TI

TLC876IDWR OBSOLETE SOIC DW 28 TBD Call TI Call TI

TLC876IPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI

TLC876IPWLE OBSOLETE TSSOP PW 28 TBD Call TI Call TI

TLC876IPWR OBSOLETE TSSOP PW 28 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

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