High IP3, 10 MHz to 6 GHz, Active Mixer ADL5801 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VPLO GND NC IFON IFOP GND 24 23 22 21 20 18 VPRF 17 GND 16 RFIP LOIN 4 15 RFIN GND 5 14 GND GND 6 13 VPDT GND 1 GND 2 ADL5801 LOIP 3 V2I BIAS APPLICATIONS Cellular base station receivers Radio link downconverters Broadband block conversion Instrumentation 19 7 8 9 DET 10 11 12 VPLO GND ENBL VSET DETO GND 08079-001 Broadband upconverter/downconverter Power conversion gain of 1.8 dB Broadband RF, LO, and IF ports SSB noise figure (NF) of 9.75 dB Input IP3: 28.5 dBm Input P1dB: 13.3 dBm Typical LO drive: 0 dBm Single-supply operation: 5 V at 130 mA Adjustable bias for low power operation Exposed paddle, 4 mm x 4 mm, 24-lead LFCSP package Figure 1. GENERAL DESCRIPTION The ADL5801 uses a high linearity, doubly balanced, active mixer core with integrated LO buffer amplifier to provide high dynamic range frequency conversion from 10 MHz to 6 GHz. The mixer benefits from a proprietary linearization architecture that provides enhanced input IP3 performance when subject to high input levels. A bias adjust feature allows the input linearity, SSB noise figure, and dc current to be optimized using a single control pin. An optional input power detector is provided for adaptive bias control. The high input linearity allows the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in degradation in dynamic performance. The adaptive bias feature allows the part to provide high input IP3 performance when presented with large blocking signals. When blockers are removed, the ADL5801 can automatically bias down to provide low noise figure and low power consumption. Rev. E The balanced active mixer arrangement provides superb LO-toRF and LO-to-IF leakage, typically better than -40 dBm. The IF outputs are designed to provide a typical voltage conversion gain of 7.8 dB when loaded into a 200 load. The broad frequency range of the open-collector IF outputs allows the ADL5801 to be applied as an upconverter for various transmit applications. The ADL5801 is fabricated using a SiGe high performance IC process. The device is available in a compact 4 mm x 4 mm, 24-lead LFCSP package and operates over a -40C to +85C temperature range. An evaluation board is also available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com ADL5801 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description......................................................................... 27 Applications ....................................................................................... 1 LO Amplifier and Splitter.......................................................... 27 Functional Block Diagram .............................................................. 1 RF Voltage-to-Current (V-to-I) Converter ............................. 27 General Description ......................................................................... 1 Mixer Core .................................................................................. 27 Revision History ............................................................................... 2 Mixer Output Load .................................................................... 27 Specifications..................................................................................... 3 RF Detector ................................................................................. 28 Absolute Maximum Ratings............................................................ 6 Bias Circuit .................................................................................. 28 ESD Caution .................................................................................. 6 Applications Information .............................................................. 31 Pin Configuration and Function Descriptions ............................. 7 Basic Connections ...................................................................... 31 Typical Performance Characteristics ............................................. 8 RF and LO Ports ......................................................................... 31 Downconverter Mode with a Broadband Balun ...................... 8 IF Port .......................................................................................... 32 Downconverter Mode with a Mini-Circuits(R) TC1-1-43M+ Input Balun .................................................................................. 12 Downconverting to Low Frequencies ...................................... 33 Downconverter Mode with a Johanson 3.5 GHz Input Balun .................................................................................. 14 Single-Ended Drive of RF and LO Inputs ............................... 36 Downconverter Mode with a Johanson 5.7 GHz Input Balun .................................................................................. 16 Upconverter Mode with a 900 MHz Output Match .............. 18 Broadband Operation ................................................................ 34 Evaluation Board ............................................................................ 38 Outline Dimensions ....................................................................... 40 Ordering Guide .......................................................................... 40 Upconverter Mode with a 2.1 GHz Output Match ................ 20 Spur Performance ....................................................................... 23 REVISION HISTORY 4/14--Rev. D to Rev. E Changes to Figure 1 .......................................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Figure 87 and Deleted Table 4; Renumbered Sequentially ..................................................................................... 27 Changes to RF Detector Section and Bias Circuit Section; Added Table 4 and Table 5; Renumbered Sequentially, and Added Figure 92, Figure 93, Figure 94, and Figure 95; Renumbered Sequentially.............................................................. 29 3/14--Rev. C to Rev. D Changes to Pin 9, Table 3 ................................................................. 7 8/13--Rev. B to Rev. C Changes to Table 8 .......................................................................... 38 7/13--Rev. A to Rev. B Added Disable Voltage and Enable Voltage; Table 1 .................... 3 Changes to Table 5 and Figure 96 ................................................. 31 Added Downconverting to Low Frequencies Section and Figure 97; Renumbered Sequentially ........................................... 32 Added Broadband Operation Section and Figure 98 to Figure 101 ........................................................................................ 33 Added Single-Ended Drive of RF and LO Inputs Section and Figure 102 to Figure 105 ................................................................ 35 Updated Outline Dimensions ....................................................... 39 7/11--Rev. 0 to Rev. A Changes to Specifications Section ...................................................3 Changes to Typical Performance Characteristics Section ...........8 Changes to Spur Performance Section ........................................ 23 Changes to RF Voltage-to-Current (V-to-I) Converter Section.............................................................................................. 27 Changes to RF Detector Section................................................... 28 Changes to RF and LO Ports Section........................................... 30 2/10--Revision 0: Initial Version Rev. E | Page 2 of 40 Data Sheet ADL5801 SPECIFICATIONS VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = (fRF - 153 MHz), LO power = 0 dBm, Z0 1 = 50 , VSET = 3.6 V, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 2 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER INTERFACE Supply Voltage Quiescent Current Disable Current Disable Voltage Enable Voltage Enable Time Disable Time DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz 3 Power Conversion Gain 4 Voltage Conversion Gain 5 SSB Noise Figure SSB Noise Figure Under Blocking 6 Input Third-Order Intercept 7 Input Second-Order Intercept 8 Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious 9 IF/3 Spurious9 Test Conditions Min Tunable to >20 dB over a limited bandwidth Typ LF 4.75 VS 0 15 50 10 4.75 fRF = 900 MHz fRF = 1900 MHz fRF = 900 MHz fRF = 1900 MHz fCENT = 900 MHz, VSET = 2.0 V fCENT = 1900 MHz, VSET = 2.0 V fCENT = 900 MHz fCENT = 1900 MHz fCENT = 900 MHz fCENT = 1900 MHz fCENT = 900 MHz fCENT = 1900 MHz fRF = 900 MHz fRF = 1900 MHz Unfiltered IF output 0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 1900 MHz 0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 1900 MHz Rev. E | Page 3 of 40 6000 dB MHz 600 5.25 MHz V 230 -10 Resistor programmable ENBL pin high to disable the device ENBL pin high to disable the device ENBL pin low to enable the device Time from ENBL pin low to enable Time from ENBL pin high to disable Unit 12 50 10 Differential impedance, f = 200 MHz Can be matched externally to 3000 MHz Externally generated Max +10 6000 5 130 50 182 28 V mA mA V V ns ns 1.8 1.8 7.8 7.8 9.75 11.5 19.5 20 28.5 26.4 63 49.7 13.3 12.7 -27 -30 -35 -67.5 -53 -65.5 -72.6 dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBc dBc dBc dBc dBc 2.5 0 5.25 200 dBm dB MHz 5 1.8 ADL5801 Parameter DYNAMIC PERFORMANCE at fRF = 2500 MHz 10 Power Conversion Gain 11 Voltage Conversion Gain5 SSB Noise Figure Input Third-Order Intercept 12 Input Second-Order Intercept 13 Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious9 IF/3 Spurious9 DYNAMIC PERFORMANCE at fRF = 3500 MHz 14 Power Conversion Gain 15 Voltage Conversion Gain5 SSB Noise Figure Input Third-Order Intercept7 Input Second-Order Intercept8 Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious9 IF/3 Spurious9 DYNAMIC PERFORMANCE at fRF = 5500 MHz 16 Power Conversion Gain 17 Voltage Conversion Gain5 SSB Noise Figure Input Third-Order Intercept7 Input Second-Order Intercept 8 Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious9 IF/3 Spurious9 DYNAMIC PERFORMANCE at fIF = 900 MHz 18 Power Conversion Gain 19 Voltage Conversion Gain5 SSB Noise Figure Output Third-Order Intercept 20 Output Second-Order Intercept 21 Output 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage IF/2 Spurious9 IF/3 Spurious9 Data Sheet Test Conditions fCENT = 2500 MHz, VSET = 2.0 V fCENT = 2500 MHz fCENT = 2500 MHz fCENT = 2500 MHz Unfiltered IF output 0 dBm input power, fRF = 2600 MHz 0 dBm input power, fRF = 2600 MHz fCENT = 3500 MHz, VSET = 3.6 V fCENT = 3500 MHz, VSET = 3.6 V fCENT = 3500 MHz, VSET = 3.6 V Unfiltered IF output 0 dBm input power, fRF = 3800 MHz 0 dBm input power, fRF = 3800 MHz fCENT = 5500 MHz, VSET = 3.6 V fCENT = 5500 MHz, VSET = 3.6 V fCENT = 5500 MHz, VSET = 3.6 V Unfiltered IF output 0 dBm input power, fRF = 5800 MHz 0 dBm input power, fRF = 5800 MHz fIF = 900 MHz, fRF = 250 MHz, VSET = 2.0 V fCENT = 153 MHz, VSET = 3.6 V fCENT = 153 MHz, VSET = 3.6 V Unfiltered IF output 0 dBm input power, fRF = 140 MHz, fIF = 806 MHz 0 dBm input power, fRF = 140 MHz, fIF = 806 MHz Rev. E | Page 4 of 40 Min Typ Max Unit -6.1 -0.1 10.6 25.5 45.3 13.8 -31.5 -31.2 -42.5 -50.6 -59.8 dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc -6.44 -0.44 15.8 26.5 42.3 12.5 -30.2 -29.4 -29.7 -47.1 -57.8 dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc -5.2 0.8 16.2 22.7 35.4 11.3 -42.6 -28.9 -46.7 -44 -47 dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc -6 0 10.6 30.6 68.7 11.1 -33.8 -33.4 -62.6 dB dB dB dBm dBm dBm dBm dBm dBc -68.9 dBc Data Sheet Parameter DYNAMIC PERFORMANCE at fIF = 2140 MHz 22 Power Conversion Gain 23 Voltage Conversion Gain5 SSB Noise Figure Output Third-Order Intercept 24 Output Second-Order Intercept 25 Output 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage IF/2 Spurious9 ADL5801 Test Conditions fIF = 2140 MHz, fRF = 190 MHz, VSET = 2.0 V fCENT = 170 MHz, VSET = 3.6 V fCENT = 170 MHz, VSET = 3.6 V Unfiltered IF output 0 dBm input power, fRF = 140 MHz, fIF = 2210 MHz Min Typ -7.25 -1.25 13.6 24 70 9.9 -23.8 -33.2 -51.5 Z0 is the characteristic impedance assumed for all measurements and the PCB. Supply voltage must be applied from an external circuit through choke inductors 3 VS = 5 V, TA = 25C, fRF = 900 MHz/1900 MHz, fLO = (fRF - 153 MHz), LO power = 0 dBm, Z01= 50 , VSET = 3.8 V, unless otherwise noted. 4 Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss. 5 ZSOURCE = 50 , differential; ZLOAD = 200 differential; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output. 6 fRF = fCENT, fBLOCKER = (fCENT - 5) MHz, fLO = (fCENT - 153) MHz, blocker level = 0 dBm. 7 fRF1 = (fCENT - 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT - 153) MHz, each RF tone at -10 dBm. 8 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT - 153) MHz, each RF tone at -10 dBm. 9 For details, see the Spur Performance section. 10 VS = 5 V, TA = 25C, fRF = 2500 MHz, fLO = (fRF - 211 MHz), LO power = 0 dBm, Z01 = 50 , VSET = 3.8 V, unless otherwise noted. 11 Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-43M+ and TC1-1-13M+ respectively), and PCB loss. 12 fRF1 = (fCENT - 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT - 211) MHz, each RF tone at -10 dBm. 13 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT - 211) MHz, each RF tone at -10 dBm 14 VS = 5 V, TA = 25C, fRF = 3500 MHz, fLO = (fRF - 153 MHz), LO power = 0 dBm, Z01 = 50 , VSET = 3.6 V, unless otherwise noted. 15 Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss. 16 VS = 5 V, TA = 25C, fRF = 5500 MHz, fLO = (fRF - 153 MHz), LO power = 0 dBm, Z01 = 50 , VSET = 3.6 V, unless otherwise noted. 17 Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL14B050), and PCB loss. 18 VS = 5 V, TA = 25C, fRF = 153 MHz, fLO = (fRF + 900 MHz), LO power = 0 dBm, Z01 = 50 , VSET = 3.6 V, unless otherwise noted. 19 Including 4:1 IF port transformer (TC4-14+), RF and LO transformers (TC1-1-13M+), and PCB loss. 20 fRF1 = (fCENT - 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT + 900 MHz), each RF tone at -10 dBm. 21 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT + 900) MHz, each RF tone at -10 dBm. 22 VS = 5 V, TA = 25C, fRF = 153MHz, fLO = (fRF + 2140 MHz), LO power = 0 dBm, Z01 = 50 , VSET = 4 V, unless otherwise noted. 23 Including 4:1 IF port transformer (1850BL15B200), RF and LO port transformers (TC1-1-13M+), and PCB loss. 24 fRF1 = (fCENT - 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT + 2140 MHz), each RF tone at -10 dBm. 25 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT + 2140) MHz, each RF tone at -10 dBm. 1 2 Rev. E | Page 5 of 40 Max Unit dB dB dB dBm dBm dBm dBm dBm dBc ADL5801 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter Supply Voltage, VPOS VSET, ENBL IFOP, IFON RFIN Power Internal Power Dissipation JA (Exposed Paddle Soldered Down)1 JC (at Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range 1 Rating 5.5 V 5.5 V 5.5 V 20 dBm 1.2 W 26.5C/W 8.7C/W 150C -40C to +85C -65C to +150C ESD CAUTION As measured on the evaluation board. For details, see the Evaluation Board section. Rev. E | Page 6 of 40 Data Sheet ADL5801 24 23 22 21 20 19 VPLO GND NC IFON IFOP GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADL5801 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VPRF GND RFIP RFIN GND VPDT NOTES 1. THERE IS AN EXPOSED PADDLE THAT MUST BE SOLDERED TO GROUND. 2. NC = NO CONNECT. 08079-002 VPLO 7 GND 8 ENBL 9 VSET 10 DETO 11 GND 12 GND GND LOIP LOIN GND GND Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 5, 6, 8, 12, 14, 17, 19, 23 3, 4 7, 24 9 Mnemonic GND Description Device Common (DC Ground). LOIP, LOIN VPLO ENBL 10 VSET 11 DETO 13 15, 16 VPDT RFIN, RFIP 18 20, 21 VPRF IFOP, IFON 22 NC EPAD Differential LO Input Terminal. Internally matched to 50 . Must be ac-coupled. Positive Supply Voltage for LO System. Detector and Mixer Bias Enable. Pull the pin high to disable the internal detector and mixer bias circuit. The device can be operated in this mode by setting the bias level using an external supply or connecting a resistor from the VSET pin to the positive supply. See the Circuit Description section for more details. Pull the pin low to enable the internal detector and mixer bias circuit. Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core and allows for adaptive control of the input IP3 and NF characteristics of the mixer core. Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin, the part auto biases and increases input IP3 performance when presented with large signal input levels. Positive Supply Voltage for Detector. Differential RF Input Terminal. Internally matched to 50 differential input impedance. Must be ac-coupled. Positive Supply Voltage for RF Input System. Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap of the IF transformer. Not Connected. The exposed paddle must be soldered to ground. Rev. E | Page 7 of 40 ADL5801 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS DOWNCONVERTER MODE WITH A BROADBAND BALUN VS = 5 V, TA = 25C, VSET = 3.8 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement. 6 6 35 5 30 4 25 5 4 3 TA = +25C GAIN (dB) GAIN (dB) 2 1 TA = +85C 0 -1 -2 GAIN = 900MHz GAIN = 1900MHz INPUT IP3 = 900MHz INPUT IP3 = 1900MHz 3 20 2 15 1 10 INPUT IP3 (dBm) TA = -40C -3 2000 1500 2500 3000 RF FREQUENCY (MHz) 0 -15 5 -10 0 -5 10 5 08079-006 1000 08079-003 -4 500 15 LO LEVEL (dBm) Figure 6. Power Conversion Gain and Input IP3 vs. LO Power Figure 3. Power Conversion Gain vs. RF Frequency 100 4.0 90 3.5 MEAN = 1.87 SD = 0.03 80 3.0 FREQUENCY (%) 70 GAIN (dB) 2.5 900MHz 2.0 1.5 60 50 40 30 1900MHz 1.0 20 0.5 10 0.10 0.5 0.08 0 0.06 -0.5 0.04 3.5 4.0 4.5 0.02 5.0 VSET (V) GAIN (dB) 1.0 SUPPLY CURRENT (A) 0.12 2.100 08079-007 TA = +25C 2.0 TA = +85C 1.5 1.0 0.5 08079-005 1.5 3.0 2.060 2.5 0.14 2.5 2.020 TA = -40C 0.16 2.0 -1.0 2.0 1.980 3.0 0 4.7 4.8 4.9 5.0 5.1 5.2 SUPPLY (V) Figure 8. Power Conversion Gain vs. Supply Voltage Figure 5. Power Conversion Gain and Supply Current vs. VSET Rev. E | Page 8 of 40 5.3 08079-008 2.5 GAIN (dB) Figure 7. Power Conversion Gain Distribution 0.18 GAIN = 900MHz GAIN = 1900MHz IPOS = 900MHz IPOS = 1900MHz 1.940 POWER CONVERSION GAIN (dB) Figure 4. Power Conversion Gain vs. IF Frequency 3.0 1.900 IF FREQUENCY (MHz) 1.860 250 1.820 200 1.780 150 1.740 100 1.700 50 0 08079-004 0 0 Data Sheet ADL5801 70 35 TA = +25C 60 TA = -40C TA = +25C TA = +85C TA = +85C 15 40 30 10 20 5 10 0 500 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) 0 500 1000 2000 1500 2500 3000 08079-012 20 250 08079-013 INPUT IP2 (dBm) 50 08079-009 INPUT IP3 (dBm) 25 5.0 08079-014 TA = -40C 30 RF FREQUENCY (MHz) Figure 9. Input IP3 vs. RF Frequency Figure 12. Input IP2 vs. RF Frequency 40 80 70 35 900MHz 30 900MHz INPUT IP2 (dBm) INPUT IP3 (dBm) 60 1900MHz 25 20 50 1900MHz 40 30 20 15 10 0 100 50 0 150 200 250 IF FREQUENCY (MHz) 08079-010 10 0 100 50 150 200 IF FREQUENCY (MHz) Figure 13. Input IP2 vs. IF Frequency Figure 10. Input IP3 vs. IF Frequency 30 20 25 18 80 70 900MHz 15 14 10 12 INPUT IP2 (dBm) 16 NOISE FIGURE (dB) 20 50 1900MHz 40 30 20 INPUT IP3 = 900MHz INPUT IP3 = 1900MHz NF = 900MHz NF = 1900MHz 5 10 10 0 8 0 2.0 2.5 3.0 3.5 4.0 4.5 VSET (V) 5.0 08079-011 INPUT IP3 (dBm) 60 Figure 11. Input IP3 and Noise Figure vs. VSET 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 14. Input IP2 vs. VSET Rev. E | Page 9 of 40 4.5 ADL5801 Data Sheet 20 25 18 TA = +25C TA = +85C 20 SSB NOISE FIGURE (dB) INPUT P1dB (dBm) 16 14 12 TA = -40C 10 8 6 15 1900MHz 10 900MHz 5 4 0 1000 2000 1500 2500 3000 RF FREQUENCY (MHz) 08079-015 0 500 0 100 300 200 400 500 600 700 IF FREQUENCY (MHz) 08079-018 2 Figure 18. SSB Noise Figure vs. IF Frequency (VSET = 2.0 V) Figure 15. Input P1dB vs. RF Frequency 30 20 18 25 14 900MHz 12 1900MHz SSB NOISE FIGURE (dB) INPUT P1dB (dBm) 16 10 8 6 4 RF = 1846MHz, IF = 153 MHz BLOCKER = 1841MHz 20 15 10 RF = 951MHz, IF = 153 MHz BLOCKER = 946MHz 5 50 100 150 200 250 IF FREQUENCY (MHz) 0 -30 -15 -10 -5 0 5 Figure 19. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V) 20 18 TA = +85C 16 14 18 16 SSB NOISE FIGURE (dB) TA = +25C 12 10 TA = -40C 8 6 14 10 900MHz 8 6 4 2 2 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) 1900MHz 12 4 0 -15 08079-017 SSB NOISE FIGURE (dB) -20 BLOCKER LEVEL (dBm) Figure 16. Input P1dB vs. IF Frequency 0 500 -25 -10 -5 0 5 LO LEVEL (dBm) 10 Figure 20. SSB Noise Figure vs. LO Power (VSET = 2.0 V) Figure 17. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V) Rev. E | Page 10 of 40 15 08079-020 0 08079-016 0 08079-019 2 Data Sheet ADL5801 0 -10 -15 5 LO-TO-IF LEAKAGE (dBm) RF RETURN LOSS (dB) -20 10 15 20 25 TA = -40C TA = +25C TA = +85C -25 -30 -35 -40 -45 -50 30 0 500 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) -60 500 08079-021 35 2500 3000 LO FREQUENCY (MHz) Figure 21. RF Return Loss vs. RF Frequency Figure 24. LO-to-IF Leakage vs. LO Frequency 0 -10 -15 5 LO-TO-RF LEAKAGE (dBm) -20 LO RETURN LOSS (dB) 2000 1500 1000 08079-024 -55 10 15 20 25 TA = -40C TA = +25C TA = +85C -25 -30 -35 -40 -45 -50 30 500 1000 1500 2000 2500 3000 LO FREQUENCY (MHz) -60 500 2500 3000 300 0 200 -2 100 RF-TO-IF OUTPUT ISOLATION (dBc) 2 CAPACITANCE (pF) 400 0 -4 -6 0 08079-023 RESISTANCE () 4 1000 2000 Figure 25. LO-to-RF Leakage vs. LO Frequency 500 100 1500 LO FREQUENCY (MHz) Figure 22. LO Return Loss vs. LO Frequency 10 1000 3000 IF FREQUENCY (MHz) Figure 23. IF Differential Output Impedance (R Parallel C Equivalent) Rev. E | Page 11 of 40 -10 -20 -30 TA = +85C -40 TA = -40C TA = +25C -50 -60 500 1000 1500 2000 2500 RF FREQUENCY (MHz) Figure 26. RF-to-IF Leakage vs. RF Frequency 3000 08079-026 0 08079-022 35 08079-025 -55 ADL5801 Data Sheet DOWNCONVERTER MODE WITH A MINI-CIRCUITS(R) TC1-1-43M+ INPUT BALUN VS = 5 V, TA = 25C, VSET = 3.8 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-43M+, TC4-1W+) is included in the gain measurement. 6 30 20 25 18 4 IIP3 2500MHz INPUT IP3 (dBm) 3 GAIN (dB) 2 1 0 -1 20 16 15 14 10 12 NOISE FIGURE (dB) 5 NF 2500MHz -2 10 5 -3 4.5 Figure 30. Input IP3 and Noise Figure vs. VSET 60 0.16 GAIN 2500M 50 0.10 IPOS 2500M -1.0 0.08 -1.5 0.06 -2.0 INPUT IP2 (dBm) 0.12 -0.5 SUPPLY CURRENT (A) 0.14 0 40 30 20 0.04 10 -2.5 3.0 3.5 4.0 4.5 0 5.0 0 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 08079-028 2.5 VSET (V) RF FREQUENCY (MHz) 08079-031 0.02 -3.0 2.0 Figure 31. Input IP2 vs. RF Frequency Figure 28. Power Conversion Gain and IPOS vs. VSET 30 80 29 70 28 60 INPUT IP2 (dBm) 27 26 25 24 50 40 30 23 20 22 20 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RF FREQUENCY (MHz) Figure 29. Input IP3 vs. RF Frequency 0 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 32. Input IP2 vs. VSET Rev. E | Page 12 of 40 4.5 5.0 08079-032 10 21 08079-029 INPUT IP3 (dBm) GAIN (dB) 4.0 VSET (V) 0.18 0.5 3.5 3.0 2.5 08079-030 2.0 Figure 27. Power Conversion Gain vs. RF Frequency 1.0 8 5.0 0 08079-027 -4 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RF FREQUENCY (MHz) ADL5801 -10 18 -15 16 -20 14 12 10 8 6 -25 -30 -35 -40 -45 4 -50 2 -55 0 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 -60 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RF FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 33. Input P1dB vs. RF Frequency Figure 36. LO to RF Leakage vs. LO Frequency 25 -20 +85C VSET 2V +25C VSET 2V -40C VSET 2V 15 10 0 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RF FREQUENCY (MHz) 08079-034 5 Figure 34. Noise Figure vs. RF Frequency -15 -25 -30 -35 -40 -45 -50 -55 08079-035 LO TO IF LEAKAGE (dBm) -20 LO FREQUENCY (MHz) -40 -50 -60 -70 -80 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 RF FREQUENCY (MHz) Figure 37. RF to IF Output Isolation vs. RF Frequency -10 -60 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 -30 Figure 35. LO to IF Leakage vs. LO Frequency Rev. E | Page 13 of 40 08079-037 +85C VSET 3.6V +25C VSET 3.6V -40C VSET 3.6V RF TO IF OUTPUT ISOLATION (dBc) NOISE FIGURE (dB) 20 08079-036 LO TO RF LEAKAGE (dBm) 20 08079-033 INPUT P1dB (dBm) Data Sheet ADL5801 Data Sheet DOWNCONVERTER MODE WITH A JOHANSON 3.5 GHZ INPUT BALUN VS = 5 V, TA = 25C, VSET = 3.6 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement. 5 4 28 30 6 -40C +25C +85C 25 2 1 0 18 15 10 -1 -2 IIP3, -40C IIP3, +25C IIP3, +85C NF, -40C NF, +25C NF, +85C 5 -3 RF FREQUENCY (MHz) 0 2.0 08079-038 -4 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 8 2.5 3.0 3.5 4.0 4.5 Figure 41. Input IP3 and Noise Figure vs. VSET 0.20 50 0.18 0 0.08 GAIN -40C GAIN +25C GAIN +85C IPOS -40C IPOS +25C IPOS +85C -12 2.0 2.5 40 35 30 0.04 25 0.02 3.0 3.5 4.0 4.5 0 5.0 20 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 VSET (V) RF FREQUENCY (MHz) Figure 42. Input IP2 vs. RF Frequency Figure 39. Power Conversion Gain and IPOS vs. VSET 80 30 25 08079-042 -10 0.06 08079-039 -8 INPUT IP2 (dBm) 0.10 -6 SUPPLY CURRENT (A) 0.12 -4 -40C +25C +85C 70 +85C +25C -40C 60 INPUT IP2 (dBm) 20 15 10 50 40 30 20 5 0 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 RF FREQUENCY (MHz) Figure 40. Input IP3 vs. RF Frequency 0 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 43. Input IP2 vs. VSET Rev. E | Page 14 of 40 4.5 5.0 08079-043 10 08079-040 INPUT IP3 (dBm) GAIN (dB) 0.14 +85C +25C -40C 45 0.16 -2 5.0 VSET (V) Figure 38. Power Conversion Gain vs. RF Frequency 2 13 08079-041 INPUT IP3 (dBm) GAIN (dB) 20 NOISE FIGURE (dB) 23 3 Data Sheet ADL5801 -10 20 -15 -20 12 10 8 -25 -30 -35 -40 -45 -50 2 -55 0 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 -60 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 RF FREQUENCY (MHz) 08079-044 4 LO FREQUENCY (MHz) Figure 47. LO to RF Leakage vs. LO Frequency Figure 44. Input P1dB vs. RF Frequency -20 25 +25C, 3.6V -40C, 3.6V RF TO IF OUTPUT ISOLATION (dBc) +85C, 3.6V NOISE FIGURE (dB) 20 15 +85C, 2.0V +25C, 2.0V -40C, 2.0V 10 0 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 RF FREQUENCY (MHz) 08079-045 5 -10 -15 +85C +25C -40C -25 -30 -35 -40 -45 -50 LO FREQUENCY (MHz) 08079-046 -55 -60 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 -30 -40 +85C +25C -40C -50 -60 -70 -80 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 RF FREQUENCY (MHz) Figure 48. RF to IF Output Isolation vs. RF Frequency Figure 45. Noise Figure vs. RF Frequency -20 08079-047 14 6 LO TO IF LEAKAGE (dBm) +85C +25C -40C Figure 46. LO to IF Leakage vs. LO Frequency Rev. E | Page 15 of 40 08079-048 INPUT P1dB (dBm) 16 +85C +25C -40C LO TO RF LEAKAGE (dBm) 18 ADL5801 Data Sheet DOWNCONVERTER MODE WITH A JOHANSON 5.7 GHZ INPUT BALUN VS = 5 V, TA = 25C, VSET = 3.6 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (5400BL14B050, TC4-1W+) is included in the gain measurement. 30 20 3 1 0 15 20 10 15 -1 IIP3, -40C IIP3, +25C IIP3, +85C NF, -40C NF, +25C NF, +85C 5 -2 -3 RF FREQUENCY (MHz) 0 2.0 08079-049 -4 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 70 0 0.18 65 -2 0.16 60 -6 0.10 -8 0.08 0.06 GAIN -40C GAIN +25C GAIN +85C IPOS -40C IPOS +25C IPOS +85C -14 -16 2.0 2.5 3.0 3.5 4.0 4.5 4.5 5 5.0 45 40 35 30 0.02 25 0 5.0 +85C +25C -40C 50 0.04 VSET (V) 20 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 RF FREQUENCY (MHz) Figure 53. Input IP2 vs. RF Frequency Figure 50. Power Conversion Gain and IPOS vs VSET 30 4.0 55 08079-050 GAIN (dB) 0.12 INPUT IP2 (dBm) 0.14 SUPPLY CURRENT (A) 0.20 -12 3.5 Figure 52. Input IP3 and Noise Figure vs. VSET 2 -10 3.0 10 VSET (V) Figure 49. Power Conversion Gain vs. RF Frequency -4 2.5 NOISE FIGURE (dB) 25 INPUT IP3 (dBm) GAIN (dB) 2 08079-052 4 -40C +25C +85C 08079-053 5 35 25 6 80 -40C +25C +85C 70 25 +85C +25C -40C INPUT IP2 (dBm) 20 15 50 40 30 10 20 5 0 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 RF FREQUENCY (MHz) 0 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 54. Input IP2 vs. VSET Figure 51. Input IP3 vs. RF Frequency Rev. E | Page 16 of 40 4.5 5.0 08079-054 10 08079-051 INPUT IP3 (dBm) 60 Data Sheet ADL5801 20 -15 -20 14 12 10 8 6 -25 -30 -35 -40 -45 -50 2 -55 0 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 -60 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 RF FREQUENCY (MHz) 08079-055 4 LO FREQUENCY (MHz) Figure 55. Input P1dB vs. RF Frequency Figure 58. LO to RF Leakage vs. LO Frequency 25 -20 +25C, 3.6V -40C, 3.6V RF TO IF OUTPUT ISOLATION (dBc) +85C, 3.6V NOISE FIGURE (dB) 20 15 +85C, 2.0V +25C, 2.0V -40C, 2.0V 10 0 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 RF FREQUENCY (MHz) 08079-056 5 Figure 56. Noise Figure vs. RF Frequency, VSET = 3.6 V -15 -25 -30 -35 -40 -45 -50 -55 LO FREQUENCY (MHz) 08079-057 LO TO IF LEAKAGE (dBm) +85C +25C -40C -60 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 -30 +85C +25C -40C -40 -50 -60 -70 -80 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 RF FREQUENCY (MHz) Figure 59. RF to IF Output Isolation vs. RF Frequency -10 -20 08079-058 LO TO RF LEAKAGE (dBm) INPUT P1dB (dBm) 16 +85C +25C -40C Figure 57. LO to IF Leakage vs. LO Frequency Rev. E | Page 17 of 40 08079-059 18 -10 +85C +25C -40C ADL5801 Data Sheet UPCONVERTER MODE WITH A 900 MHZ OUTPUT MATCH VS = 5 V, TA = 25C, VSET = 3.6 V, RF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-14) is included in the gain measurement. 2 35 1 +85C +25C -40C 0 30 OUTPUT IP3 (dBm) GAIN (dB) -1 -2 -3 -4 -5 25 20 15 OUTPUT IP3, -40C OUTPUT IP3, +25C OUTPUT IP3, +85C 10 -6 5 300 400 500 600 700 800 900 1000 1100 1200 1300 IF FREQUENCY (MHz) 0 2.0 08079-077 -8 2.5 5.0 0.16 75 0.14 0.12 0.2 0.1 0 0.08 -0.2 0.06 -0.4 OUTPUT IP2 (dBm) GAIN (dB) 0.4 4.5 80 SUPPLY CURRENT (A) 0.6 4.0 Figure 63. Output IP3 vs. VSET 0.18 GAIN -40C GAIN +25C GAIN +85C IPOS -40C IPOS +25C IPOS +85C 0.8 3.5 VSET (V) Figure 60. Power Conversion Gain vs. IF Frequency 1.0 3.0 08079-080 -7 +85C +25C -40C 70 65 60 0.04 -0.6 55 2.5 3.5 3.0 4.0 4.5 0 5.0 50 300 400 500 VSET (V) 800 900 1000 1100 1200 1300 Figure 64. Output IP2 vs. IF Frequency 35 80 30 75 70 OUTPUT IP2 (dBm) 25 20 +85C +25C -40C 15 10 65 +85C +25C -40C 60 55 50 5 45 400 500 600 700 800 900 1000 1100 1200 1300 IF FREQUENCY (MHz) 08079-079 OUTPUT IP3 (dBm) 700 IF FREQUENCY (MHz) Figure 61. Power Conversion Gain and IPOS vs. VSET 0 300 600 Figure 62. Output IP3 vs. IF Frequency 40 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 65. Output IP2 vs. VSET Rev. E | Page 18 of 40 4.5 5.0 08079-082 -1.0 2.0 08079-081 0.02 -0.8 Data Sheet ADL5801 -10 12 -15 -20 LO TO IF LEAKAGE (dBm) OUTPUT P1dB (dBm) 10 8 6 +85C +25C -40C 4 -25 +85C +25C -40C -30 -35 -40 -45 -50 2 400 500 600 700 800 900 1000 1100 IF FREQUENCY (MHz) -60 453 08079-083 0 300 553 653 753 853 953 1053 1153 1253 1353 1453 LO FREQUENCY (MHz) 08079-085 -55 Figure 68. LO to IF Leakage vs. LO Frequency Figure 66. Output P1dB vs. IF Frequency -10 16 -15 14 LO TO RF LEAKAGE (dBm) -20 10 8 6 NF NF NF 4 VSET = 3.6V, -40C VSET = 3.6V, +25C VSET = 3.6V, +85C NF NF NF VSET = 2.0V, -40C VSET = 2.0V, +25C VSET = 2.0V, +85C -25 -30 -35 -40 +85C +25C -40C -45 -50 2 750 800 850 900 950 IF FREQUENCY (MHz) 1000 -60 453 553 653 753 853 953 1053 1153 1253 1353 1453 LO FREQUENCY (MHz) Figure 69. LO to RF Leakage vs. LO Frequency Figure 67. Noise Figure vs. IF Frequency, FLO = 650 MHz Rev. E | Page 19 of 40 08079-086 -55 0 700 08079-084 NOISE FIGURE (dB) 12 ADL5801 Data Sheet UPCONVERTER MODE WITH A 2.1 GHZ OUTPUT MATCH VS = 5 V, TA = 25C, VSET = 4 V, RF = 170 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, 1850BL15B200) is included in the gain measurement. 4 35 3 30 2 OUTPUT IP3 (dBm) 0 -1 -2 -3 170 190 210 230 250 270 290 RF FREQUENCY (MHz) 0 110 0.16 75 0.08 -3.0 2.0 0.06 250 270 290 +85C +25C -40C 70 65 60 55 0.02 3.0 2.5 230 0.04 3.5 4.0 0 5.0 4.5 50 1900 08079-062 -2.5 VSET (V) 2000 2100 2200 2300 2400 2500 2600 2700 IF FREQUENCY (MHz) Figure 74. Output IP2 vs. IF Frequency Figure 71. Power Conversion Gain and IPOS vs. VSET 80 35 75 30 +85C +25C -40C 70 OUTPUT IP2 (dBm) 25 20 15 10 65 60 55 50 OUTPUT IP3 -40C OUTPUT IP3 +25C OUTPUT IP3 +85C 45 0 2.0 2.5 3.0 3.5 VSET (V) 4.0 4.5 5.0 40 2.0 2.5 3.0 3.5 4.0 VSET (V) Figure 75. Output IP2 vs. VSET Figure 72. Output IP3 vs. VSET Rev. E | Page 20 of 40 4.5 5.0 08079-070 5 08079-067 OUTPUT IP3 (dBm) GAIN (dB) 0.10 -1.5 OUTPUT IP2 (dBm) 0.12 SUPPLY CURRENT (A) 0.14 GAIN -40C GAIN +25C GAIN +85C IPOS -40C IPOS +25C IPOS +85C 210 80 -0.5 -2.0 190 Figure 73. Output IP3 vs. RF Frequency 0.18 -1.0 170 RF FREQUENCY (MHz) Figure 70. Power Conversion Gain vs. RF Frequency 0 150 130 08079-065 150 08079-060 130 -40C +25C +85C 15 5 -5 -6 110 20 10 -40C +25C +85C -4 25 08079-069 GAIN (dB) 1 Data Sheet ADL5801 -10 12 -15 -20 LO TO RF LEAKAGE (dBm) OUTPUT P1DB (dBm) 10 +85C +25C -40C 8 6 4 +85C +25C -40C -25 -30 -35 -40 -45 -50 2 2100 2200 2300 2400 2600 2500 2700 IF FREQUENCY (MHz) -60 2070 08079-072 2000 2170 2270 2370 2470 2570 2670 2770 08079-075 -55 0 1900 2870 LO FREQUENCY (MHz) Figure 76. Output P1dB vs. IF Frequency Figure 79. LO to RF Leakage vs. LO Frequency -65 25 RF TO IF OUTPUT ISOLATION (dBc) -66 NOISE FIGURE (dB) 20 15 10 NF NF NF 5 VSET = 3.6V, -40C VSET = 3.6V, +25C VSET = 3.6V, +85C NF NF NF VSET = 2.0V, -40C VSET = 2.0V, +25C VSET = 2.0V, +85C +85C +25C -40C -67 -68 -69 -70 -71 -72 -73 2150 2200 2250 2300 IF FREQUENCY (MHz) -75 110 -15 1 -20 0 -25 -1 GAIN (dB) +85C +25C -40C -40 -6 -55 -7 2370 2470 2570 2670 2770 LO FREQUENCY (MHz) 2870 230 250 270 290 -40C +25C +85C -4 -50 2270 210 -3 -5 2170 190 -2 -45 08079-074 LO TO IF LEAKAGE (dBm) 2 -60 2070 170 Figure 80. RF to IF Output Isolation vs. RF Frequency -10 -35 150 RF FREQUENCY (MHz) Figure 77. Noise Figure vs. IF Frequency, FLO = 1950 MHz -30 130 -8 1900 2000 2100 2200 2300 2400 2500 2600 IF FREQUENCY (MHz) Figure 81. Power Conversion Gain vs. IF Frequency Figure 78. LO to IF Leakage vs. LO Frequency Rev. E | Page 21 of 40 2700 08079-061 2100 08079-073 2050 08079-076 -74 0 2000 ADL5801 Data Sheet 5 40 80 4 35 78 0 15 -1 OUTPUT IP3 (dBm) 20 OUTPUT IP3 -40C OUTPUT IP3 +25C OUTPUT IP3 +85C GAIN -40C GAIN +25C GAIN +85C -3 -4 -10 -8 -6 -4 0 -2 2 4 6 8 74 72 5 68 0 66 110 10 LO POWER (dBm) 150 170 190 210 230 250 270 290 270 290 Figure 85. Output IP2 vs. RF Frequency 20 0 18 -40C +25C +85C 16 OUTPUT P1dB (dBm) -0.4 GAIN (dB) 130 RF FREQUENCY (MHz) Figure 82. Power Conversion Gain and Output IP3 vs. LO Power -0.2 -40C +25C +85C 76 70 10 -2 08079-063 GAIN (dB) 25 1 OUTPUT IP2 (dBm) 30 2 08079-068 3 -0.6 -0.8 -1.0 +85C +25C -40C 14 12 10 8 6 4 -1.2 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY (V) Figure 83. Power Conversion Gain vs. Supply 20 15 10 5 2000 2100 2200 2300 2400 2500 IF FREQUENCY (MHz) 2600 2700 08079-066 OUTPUT IP3 (dBm) -40C +25C +85C 25 0 1900 130 150 170 190 210 230 250 RF FREQUENCY (MHz) Figure 86. Output P1dB vs. RF Frequency 35 30 0 110 Figure 84. Output IP3 vs. IF Frequency Rev. E | Page 22 of 40 08079-071 4.85 4.80 08079-064 -1.4 4.75 2 Data Sheet ADL5801 SPUR PERFORMANCE All spur tables are (N x fRF) - (M x fLO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies less than 6 GHz only. The typical noise floor of the measurement system is -100 dBm. 900 MHz Downconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 . 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -48.8 -35.9 -68.8 -47.5 -95.6 -85.7 1 -33.1 0.0 -74.9 -64.8 -80.7 -74.7 -96.4 -100 2 -23.3 -51.5 -67.5 -94.3 -78.0 -89.8 -83.1 -100 -100 3 -45.8 -19.0 -66.1 -65.9 -78.4 -70.7 -98.5 -95.9 -100 -100 4 -23.6 -65.1 -73.5 -86.3 -95.1 -84.8 -83.3 -100 -99.0 -100 5 -45.9 -29.6 -80.5 -70.2 -73.5 -90.7 -96.7 -97.2 -99.8 -100 -100 6 -30.7 -78.0 -65.0 -76.3 -89.4 -86.7 -100 -83.1 -86.0 -90.9 -100 -100 M 7 -55.4 -50.3 -89.8 -70.6 -87.3 -86.4 -89.4 -84.1 -100 -88.4 -100 -100 -100 8 -41.5 -74.4 -71.3 -74.5 -100 -83.1 -99.6 -100 -100 -83.5 -97.9 -92.6 -100 9 -57.7 -88.5 -81.4 -92.7 -73.7 -96.1 -100 -100 -87.6 -95.5 -87.4 -100 -100 10 11 12 13 14 -86.8 -100 -99.5 -78.7 -96.1 -99.7 -100 -100 -99.0 -88.2 -100 -100 -100 -98.8 -99.6 -99.4 -80.7 -95.4 -87.9 -100 -100 -100 -92.3 -100 -95.1 -100 -100 -100 -100 -91.1 -95.5 -88.8 -100 -100 -100 -99.3 -100 -96.5 -100 -100 -100 -100 -100 -85.7 -100 -100 -100 -100 -100 -90.4 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 13 14 1900 MHz Downconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 1900 MHz, fLO = 1703 MHz, Z0 = 50 . M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -40.4 -38.4 -100 1 -31.4 0.0 -66.0 -66.2 -100 2 -17.1 -53.6 -52.9 -73.2 -89.4 3 -51.4 -38.5 -68.1 -72.6 -86.4 -83.7 4 -71.0 -64.2 -79.9 -94.6 -66.2 -100 5 -86.8 -65.2 -87.4 -79.3 -86.4 -100 6 -92.8 -81.5 -89.0 -100 -92.4 -100 7 -100 -75.2 -99.0 -92.7 -100 -100 Rev. E | Page 23 of 40 8 9 -100 -87.7 -100 -97.5 -100 -100 -100 -100 -98.4 -100 -100 -97.2 -100 10 -100 -100 -95.4 -100 -95.6 -100 -100 11 12 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 ADL5801 Data Sheet 2600 MHz Downconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 2600 MHz, fLO = 2350 MHz, Z0 = 50 . M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -40.3 -71.7 1 -31.5 0.0 -73.6 -83.9 2 -30.3 -55.8 -50.6 -66.5 -94.7 3 4 -33.8 -70.4 -59.8 -77.6 -91.4 -64.8 -71.3 -92.6 -71.1 5 -84.7 -83.8 -89.7 -83.1 6 -90.6 -98.2 -90.3 <100 7 8 -96.3 -92.9 -91.4 <100 <100 -97.3 <100 -96.6 <100 9 <100 <100 <100 -97.9 <100 10 <100 -91.8 <100 -93.5 <100 11 <100 -98.5 <100 <100 <100 12 <100 -98.8 <100 <100 <100 13 14 <100 <100 <100 <100 <100 <100 <100 <100 <100 15 <100 <100 <100 <100 3800 MHz Downconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 3800 MHz, fLO = 3500 MHz, Z0 = 50 . M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -33.7 1 -27.3 0.0 -78.5 2 -54.9 -47.1 -63.6 3 -66.4 -57.8 -89.6 4 -81.4 -77.2 <100 5 6 -72.2 -88.0 <100 -99.2 -80.4 -90.0 <100 7 8 <100 -90.4 -79.1 <100 <100 <100 -85.2 Rev. E | Page 24 of 40 9 <100 <100 <100 10 <100 <100 <100 11 <100 -95.9 <100 12 <100 <100 <100 13 <100 <100 <100 14 <100 <100 <100 15 <100 <100 <100 Data Sheet ADL5801 5800 MHz Downconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 5800 MHz, fLO = 5600 MHz, Z0 = 50 . 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -43.9 1 -44.9 0.0 2 3 -68.9 -44.0 -78.0 -47.0 4 -93.3 -60.6 5 -87.8 -62.7 6 M 8 7 -85.7 -70.2 -97.8 -79.5 9 -85.3 -71.2 10 <100 <100 <100 <100 11 12 <100 <100 <100 <100 13 14 <100 -100.3 15 <100 -95.6 -96.0 <100 806 MHz Upconvert Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 140 MHz, fLO = 946 MHz, Z0 = 50 . 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -66.0 -67.8 -99.2 -77.1 -88.7 -86.1 -90.2 -73.8 -91.1 -66.2 -87.7 -69.5 -85.2 -65.2 -91.3 1 -35.2 0.0 -66.0 -66.2 -97.2 <100 <100 <100 <100 -96.3 <100 -93.6 -89.1 -95.7 -85.9 -93.5 2 -22.9 -67.7 -62.9 -92.2 -85.1 -88.5 -92.7 <100 -94.8 <100 <100 <100 <100 <100 <100 <100 3 -42.8 -14.0 -65.3 -69.2 -97.8 -92.9 -95.8 -84.6 -96.4 -91.5 <100 -95.9 <100 <100 -93.1 -96.6 4 -28.4 -70.0 -61.1 -84.9 -82.0 -96.4 -87.5 <100 -93.4 -100.3 -88.3 <100 -93.8 -97.7 -94.5 v98.7 5 -59.1 -37.1 -84.1 -84.3 <100 -93.6 -99.5 -88.0 -99.6 -93.3 -100.0 <100 <100 -90.5 <100 -93.5 M 6 -40.1 -74.3 -81.2 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 -96.0 <100 -99.6 Rev. E | Page 25 of 40 7 8 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 <100 9 10 11 12 13 14 15 ADL5801 Data Sheet 2210 MHz Upconvert Performance VS = 5 V, VSET = 4.0 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 140 MHz, fLO = 2350 MHz, Z0 = 50 . M 0 N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -81.3 -66.0 <100 -74.4 <100 -90.9 -96.4 -75.8 -92.9 -66.5 -83.7 -64.8 -81.2 -64.5 -85.3 1 -21.0 0.0 -58.8 -56.7 -86.3 -75.3 -81.4 -71.2 -89.7 -86.2 <100 -98.4 <100 <100 <100 <100 2 -12.8 -70.1 -51.5 -78.2 -76.5 -88.0 -91.5 -85.9 -86.3 -92.2 -97.5 -97.9 -93.1 <100 -91.0 <100 3 4 5 6 7 <100 <100 <100 <100 <100 <100 <100 -95.4 Rev. E | Page 26 of 40 8 9 10 11 12 13 14 15 Data Sheet ADL5801 CIRCUIT DESCRIPTION LO AMPLIFIER AND SPLITTER The ADL5801 includes a double-balanced active mixer with a 50 input impedance and 250 output impedance. In addition, the ADL5801 integrates a local oscillator (LO) amplifier and an RF power detector that can be used to optimize the mixer dynamic range. The RF and LO are differential, providing maximum usable bandwidth at the input and output ports. The LO also operates with a 50 input impedance and can, optionally, be operated differentially or single ended. The input, output, and LO ports can be operated over an exceptionally wide frequency range. The ADL5801 can be configured as a downconvert mixer or as an upconvert mixer. The LO input is conditioned by a series of amplifiers to provide a well controlled and limited LO swing to the mixer core, resulting in excellent input IP3. The LO input is amplified using a broadband low noise amplifier (LNA) and is then followed by LO limiting amplifiers. The LNA input impedance is nominally 50 . The LO circuit exhibits low additive noise, resulting in an excellent mixer noise figure and output noise under RF blocking. For optimal performance, the LO inputs should be driven differentially but at lower frequencies; single-ended drive is acceptable. The ADL5801 can be divided into the following sections: the LO amplifier and splitter, the RF voltage-to-current (V-to-I) converter, the mixer core, the output loads, the RF detector, and the bias circuit. A simplified block diagram of the device is shown in Figure 87. The LO block generates a pair of differential LO signals to drive two mixer cores. The RF input power is converted into RF currents by the V-to-I converter that then feed into the two-mixer core. The internal differential load of the mixer provides a wideband 250 output impedance from the mixer. Reference currents to each section are generated by the bias circuit, which can be enabled or disabled using the ENBL pin. A detailed description of each section of the ADL5801 follows. The differential RF input signal is applied to a V-to-I converter that converts the differential input voltage to output currents. The V-to-I converter provides a 50 input impedance. The V-to-I section bias current can be adjusted up or down using the VSET pin. Adjusting the current up improves IP3 and P1dB input but degrades the SSB noise figure. Adjusting the current down improves the SSB noise figure but degrades IP3 and P1dB input. Conversion gain remains nearly constant over a wide range of VSET pin settings, allowing the part to be adjusted dynamically without affecting conversion gain. VPLO GND NC IFON IFOP GND 24 23 22 21 20 1 18 VPRF GND 2 17 GND LOIP 3 16 RFIP ADL5801 MIXER OUTPUT LOAD The mixer load uses a pair of 125 resistors connected to the positive supply. This provides a 250 differential output resistance. The mixer output should be pulled to the positive supply externally using a pair of RF chokes or using an output transformer with the center tap connected to the positive supply. It is possible to exclude these components when the mixer core current is low, but both P1dB input and IP3 input are then reduced. V2I LOIN 4 15 RFIN GND 5 14 GND GND 6 13 VPDT 7 8 9 DET 10 11 12 VPLO GND ENBL VSET DETO GND Figure 87. Block Diagram 08079-127 BIAS MIXER CORE The ADL5801 has a double-balanced mixer that uses high performance SiGe NPN transistors. This mixer is based on the Gilbert cell design of four cross-connected transistors. 19 GND RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER The mixer load output can operate from direct current (dc) up to approximately 600 MHz into a 200 load. For upconversion applications, the mixer load can be matched using off-chip matching components. Transmit operation up to 3 GHz is possible. See the Applications Information section for matching circuit details. Rev. E | Page 27 of 40 ADL5801 Data Sheet RF DETECTOR 5.0 An RF power detector is buffered from the V-to-I converter section. This detector has a power response range from approximately -25 dBm up to 0 dBm and provides a current output. The output current is designed to be connected to the VSET pin to boost the mixer core current when large RF signals are present at the mixer input. An external capacitor can be used to adjust the response time of this function. If not used, the DETO pin can be left open or connected to ground. 4.0 3.0 +85C +25C -40C GAIN (dB) 2.0 1.0 0 -1.0 -2.0 -3.0 The detector was characterized under the conditions specified in the Downconverter Mode with a Broadband Balun section. Pin 11 (DETO) was connected to Pin 10 (VSET), and the voltage on these pins was plotted vs. the RF input power level over temperature and a number of devices. -5.0 -35 -30 -25 -20 -15 -10 -5 0 5 0 5 RF INPUT (dBm) 08079-090 -4.0 Figure 90. Power Conversion Gain vs. RF Input 4.0 160 140 3.6 SUPPLY CURRENT (mA) 3.4 3.2 +85C +25C -40C 3.0 2.8 2.6 2.4 -25 -20 -15 -10 -5 0 5 08079-087 -30 RF INPUT (dBm) 35 +85C +25C -40C 20 15 10 5 0 -30 -25 -20 -15 -10 -5 RF INPUT (dBm) Figure 89. Input IP3 vs. RF Input 0 5 08079-088 INPUT IP3 (dBm) 60 40 -30 -25 -20 -15 -10 -5 RF INPUT (dBm) BIAS CIRCUIT 40 -5 -35 80 Figure 91. Supply Current vs. RF Input The input IP3, gain and supply current were also recorded under these conditions. The result can be seen in Figure 89 through Figure 91. 25 100 0 -35 Figure 88. Detector Output Voltage vs. RF Input 30 +85C +25C -40C 20 2.2 2.0 -35 120 08079-089 DETECTOR OUTPUT VOLTAGE (V) 3.8 A band gap reference circuit generates the reference currents used by mixers. The bias circuit and the internal detector can be enabled and disabled using the ENBL pin. Pulling the ENBL pin high shuts off the bias circuit and the internal detector. However, the ENBL pin does not alter the current in the LO section and, therefore, does not provide a true power-down feature. When the ENBL pin is pulled high, the device can be operated by applying an external voltage to the VSET pin or by connecting a resistor from the VSET pin to the positive supply. Internally, the VSET pin features a series resistance and diode to ground; therefore, a simple voltage divider driving the pin is not sufficient. Table 4 lists some typical values for this resistor and the resulting VSET value and supply current when the ENBL pin is set high. Use Table 4 to select the appropriate value of R10 (see Figure 110) to achieve the desired mixer bias level. In this mode of operation, the VSET pin must not be left floating, and placeholders R7 and R9 must remain open. Rev. E | Page 28 of 40 Data Sheet ADL5801 Table 4. Suggested Values of R10 (When ENBL Pin is High) Table 5. Suggested Values of R10 (When ENBL Pin is Low) R10 () 226 488 562 568 659 665 694 760 768 1000 1100 1150 1200 1300 1400 1500 1600 1700 1800 1900 2000 2300 5900 R10 () 226 562 568 659 665 694 760 768 1000 1100 1150 1200 1300 1400 1500 1600 1700 1800 1900 2000 2300 5900 Open IPOS is the mixer supply current. 1 VSET (V) 4.5 4.01 4 3.9 3.89 3.85 3.8 3.79 3.6 3.53 3.5 3.47 3.4 3.35 3.3 3.26 3.21 3.17 3.14 3.1 3 2.5 2.03 IPOS (mA)1 160 146 145 142 142 142 139 139 133 131 130 129 127 126 124 122 121 120 119 118 114 98 82 IPOS is the mixer supply current. If the ENBL pin is pulled low, the bias circuit and internal detector of the device are enabled. In this mode, the device can be operated by applying an external voltage to the VSET pin or by connecting a resistor from the VSET pin to the positive supply. Table 5 lists some typical values for this resistor and the resulting VSET value and supply current when the ENBL pin is set low. Use Table 5 to select the appropriate value of R10 (see Figure 110) to achieve the desired mixer bias level. In this mode of operation, R7 and R9 must remain open. Optionally, the VSET pin can be connected to the DETO pin to provide dynamic mixer bias control using the internal detector. Figure 92 is a comparison of the input IP3 performance vs. RF input power levels at 2 GHz, when the ENBL pin is pulled high and low. Pulling ENBL high results in improved linearity across input power levels, while pulling ENBL low results in enhanced IP3 performance at higher power levels. The device also exhibits improved spur performance when the ENBL pin is pulled high. Figure 95 is a comparison of the 4LO-5RF and 6LO-7RF spurs vs. RF input power levels at 900 MHz with ENBL high and low. Rev. E | Page 29 of 40 35 ENBL LOW 30 25 ENBL HIGH 20 fRF = 2000MHz fLO = 1797MHz fIF = 203MHz 15 10 5 0 -30 08079-192 IPOS (mA) 140 126 123 123 120 120 119 116 116 109 107 106 105 102 100 99 97 95 94 92 91 87 68 INPUT IP3 (dBm) 1 VSET (V) 4.14 4.00 3.90 3.89 3.78 3.77 3.74 3.67 3.66 3.44 3.36 3.33 3.29 3.22 3.16 3.10 3.05 3.00 2.95 2.91 2.87 2.76 2.18 1 -25 -20 -15 -10 -5 0 RF INPUT LEVEL (dBm) Figure 92. Input IP3 vs. RF Input Level at 2 GHz, VSET = 3.8 V, with ENBL High and Low ADL5801 Data Sheet Figure 93 is a plot of the input IP3 vs. RF input power levels for varying VSET levels at 2 GHz, when the ENBL pin is pulled high. The device exhibits the best linearity at a VSET level of 4.0 V in this mode of operation. As mentioned previously, the VSET level can be set using an external voltage or by placing a resistor from the VSET pin to the positive supply. Figure 94 is a plot of the input IP3 vs. RF input power levels for a VSET level of 4.0 V, when the ENBL is pulled high for varying temperature and frequency conditions. The device is well behaved across varying frequency levels and exhibits excellent temperature sensitivity. 35 INPUT IP3 (dBm) 30 25 20 08079-193 0 -5 -10 -15 -20 -25 RF INPUT LEVEL (dBm) Figure 93. Input IP3 vs. RF Input Level at 2 GHz for Varying VSET levels, ENBL High 08079-194 0 -5 -10 -15 20 0 -20 -40 -60 ADL5801 IF, ENBL LOW ADL5801 4LO-5RF SPUR, ENBL ADL5801 6LO-7RF SPUR, ENBL ADL5801 IF TONE, ENBL HIGH ADL5801 4LO-5RF SPUR, ENBL ADL5801 6LO-7RF SPUR, ENBL LOW LOW HIGH HIGH fRF = 900MHz fLO = 1077MHz fIF = 177MHz -80 -100 -120 -140 -20 08079-195 SPUR LEVEL, RELATIVE TO THE CARRIER (dBc) Figure 94. Input IP3 vs. RF Input Level for Across Varying Frequency and Temperature Conditions, VSET = 4.0 V, ENBL High 20 15 +85C AT 1.0GHz +85C AT 1.5GHz +85C AT 2.0GHz +85C AT 2.5GHz RF INPUT LEVEL (dBm) fRF = 2000MHz fLO = 1797MHz fIF = 203MHz 25 -30 INPUT IP3 (dBm) 30 = 3.40V = 3.60V = 3.80V = 4.05V = 4.20V = 4.40V = 4.65V +25C AT 1.0GHz +25C AT 1.5GHz +25C AT 2.0GHz +25C AT 2.5GHz -20 15 VSET VSET VSET VSET VSET VSET VSET -30 35 -25 -40C AT 1.0GHz -40C AT 1.5GHz -40C AT 2.0GHz -40C AT 2.5GHz -15 -10 -5 0 5 RF INPUT POWER LEVEL (dBm) Figure 95. 4LO-5RF and 6LO-7RF Spurs vs. RF Input Level at 900 MHz, with ENBL High and Low Rev. E | Page 30 of 40 Data Sheet ADL5801 APPLICATIONS INFORMATION BASIC CONNECTIONS RF AND LO PORTS The ADL5801 is designed to translate between radio frequencies (RF) and intermediate frequencies (IF). For both upconversion and downconversion applications, RFIP (Pin 16) and RFIN (Pin 15) must be configured as the input interfaces. IFOP (Pin 20) and IFON (Pin 21) must be configured as the output interfaces. Individual bypass capacitors are needed in close proximity to each supply pin (Pin 7, Pin 13, Pin 18, and Pin 24), the VSET control pin (Pin 10), and the DETO detector output pin (Pin 11). When the on-chip detector is chosen to form a closed loop, automatically controlling the VSET pin, R7 can be populated with a 0 resistor. Alternatively, simply use a jumper between the VSET and DETO test points for evaluation. Figure 96 illustrates the basic connections for ADL5801 operation. The RF and LO input ports are designed for a differential input impedance of approximately 50 . Figure 97 and Figure 98 illustrate the RF and LO interfaces, respectively. It is recommended that each of the RF and LO differential ports be driven through a balun for optimum performance. It is also necessary to ac couple both RF and LO ports. Using proper value capacitors may help improve the input return loss over desired frequencies. Table 6 and Table 9 list the recommended components for various RF and LO frequency bands in upconvert and downconvert modes. The characterization data is available in the Typical Performance Characteristics section. IFON IFOP T1 T5 T8 R11 C50 VPOS C20 R2 R3 R50 C2 L1 VPOS L2 L3 C19 C13 24 23 VPLO GND 22 21 20 19 C10 IFON IFOP GND NC 1 GND 2 GND GND 17 3 LOIP RFIP 16 VPRF VPOS 18 C8 C4 LOIN R8 L4 RFIP ADL5801 LOIP T2 R16 T4 T7 4 LOIN R4 RFIN 15 C9 C5 5 GND GND 14 6 GND VPDT 13 VPLO GND ENBL VSET DETO GND 7 8 9 10 11 C6 C18 C1 R7 C17 VSET R9 C12 Figure 96. Basic Connections Schematic Rev. E | Page 31 of 40 RFIN VPOS C7 DETO T3 T6 T9 R12 R10 12 ENBL VPOS L5 08079-128 C3 R14 R13 ADL5801 Data Sheet shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF frequency of operation not to load down the output current before it reaches the intended load. Additionally, the dc current handling capability of the selected choke inductors must be at least 45 mA. GND 17 C8 RFIP ADL5801 T3 08079-129 C9 GND 14 The self-resonant frequency of the selected choke inductors must be higher than the intended IF frequency. A variety of suitable choke inductors is commercially available from manufacturers such as Coilcraft(R) and Murata. An impedance transforming network may be required to transform the final load impedance to 200 at the IF outputs. Figure 97. RF Interface 1 GND 2 GND 3 LOIP 4 LOIN 5 GND Table 8 lists suggested components for the IF port in the upconvert and downconvert modes. C4 ADL5801 T2 IFOP T1 T5 T8 C5 6 VPOS GND 08079-130 LOIP C50 R3 R2 L3 Figure 98. LO Interface C13 Table 6. Suggested Components for the RF and LO Interfaces in Downconvert Mode RF and LO Frequency 10 MHz 900 MHz 1900 MHz 2500 MHz 3500 MHz 5500 MHz 10 MHz to 6000 MHz 23 22 GND NC 21 20 19 IFON IFOP GND ADL5801 T2, T3 Mini-Circuits TC1-1-13M+ Mini-Circuits TC1-1-13M+ Mini-Circuits TC1-1-13M+ Mini-Circuits TC1-1-43M+ 3600BL14M050 5400BL14B050 Mini-Circuits TCM1-63AX+ C8, C9 1 nF 5.6 pF 5.6 pF 2 pF 1.5 pF 3 pF 1 nF C4, C5 1 nF 100 pF 100 pF 8 pF 1.5 pF 3 pF 1 nF Figure 99. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer ZL IMPEDANCE TRANSFORMING NETWORK C3 T1 T5 T8 C2 VPOS Table 7. Suggested Components for the RF Interface in Upconvert Mode RF Frequency 153 MHz 08079-131 RFIN 15 T3 TC1-1-13M+ C20 VPOS L1 L2 L3 C19 C13 C8, C9 470 pF 23 22 GND NC IF PORT 21 20 ADL5801 The IF port features an open-collector, differential output interface. It is necessary to bias the open collector outputs using one of the schemes presented in Figure 99 and Figure 100. Figure 99 shows the use of center-tapped impedance transformers. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 load impedance, a 4:1 impedance ratio transformer should be used to transform the 50 load into a 200 differential load at the IF output pins. 19 IFON IFOP GND 08079-132 RFIP 16 Figure 100. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors Table 8. Suggested Components for the IF Port in Upconvert and Downconvert Modes IF Frequency 0 MHz to 500 MHz 900 MHz 2140 MHz Figure 100 shows a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The Rev. E | Page 32 of 40 Mode of Operation Downconvert Upconvert Upconvert T1 TC4-1W+ TC4-14+ 1850BL15B200 L3 Open 27 nH 3.3 nH Data Sheet ADL5801 ZL DOWNCONVERTING TO LOW FREQUENCIES IMPEDANCE TRANSFORMING NETWORK VPOS T1 T5 T8 10F 10F 50 50 VPOS C19 0.1F C20 0.1F 23 22 GND NC 21 20 19 IFON IFOP GND ADL5801 08079-136 For downconversion to lower frequencies, the device should be biased at the output with a resistor. The common-mode voltage at the IF output of the device should be 3.75 V to ensure optimal performance. Figure 101 provides a sample setup to downconvert a 900 MHz input signal down to 100 kHz. In the setup depicted in Figure 101, the output of the device is biased with 50 resistors. In this mode of operation, the device exhibits 2.0 dB of conversion gain when a signal at 500 MHz was downcoverted to a 100 kHz, 10 kHz or 1 kHz. Figure 101. Resistive Bias Network to Downconvert Signals to Low Frequencies Rev. E | Page 33 of 40 ADL5801 Data Sheet BROADBAND OPERATION The ADL5801 can support input frequencies from 10 MHz to 6 GHz. The device can be operated with a broadband balun such as the MiniCircuits TCM1-63AX+ for applications that need wideband frequency coverage. Figure 102 illustrates a sample setup configuration with the MiniCircuits TCM1-63AX+ balun populated on the RF and LO ports. This single setup solution provides the option to utilize the complete input frequency range of the device. IFOP IFON Mini-Circuits TC4-1W+ C50 0.1F VPOS R50 0 C20 100pF C2 0.1F C3 100pF 24 23 VPLO GND LOIN Mini-Circuits C4 TCM1-63AX+ 1nF 22 NC 21 20 19 IFON IFOP GND C10 0.1F 1 GND VPRF 18 2 GND GND 17 3 LOIP RFIP 16 VPOS C8 1nF R8 Mini-Circuits 0 TCM1-63AX+ RFIP ADL5801 4 LOIN LOIP R16 0 RFIN 15 RFIN C9 1nF C5 1nF 5 GND GND 14 6 GND VPDT 13 VPOS C11 0.1F VPLO GND ENBL VSET DETO GND 7 8 9 10 11 12 R10 VPOS C7 100pF C18 C17 0.1F 100pF ENBL VSET DETO C1 0.1F R9 C12 100pF Figure 102. Sample Setup Configuration with the MiniCircuits TCM1-63AX+ Broadband Balun Rev. E | Page 34 of 40 08079-137 C6 0.1F Data Sheet ADL5801 Figure 103 to Figure 105 demonstrate the performance of the mixer with the MiniCircuits TCM1-63AX+ populated on the RF and LO ports. 0 INPUT RETURN LOSS (dB) -5 70 CONVERSION GAIN (dB) IIP3 (dBm) IIP2 (dBm) 50 40 30 fIF = 153MHz, fLO: 163MHz TO 6153MHz (HIGH SIDE LO) -25 -30 -40 PRF = -10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS 10 0 08079-138 0 -10 0 1000 2000 3000 4000 5000 6000 RF FREQUENCY (MHz) Figure 103. Gain, IIP3, IIP2 vs. RF Frequency 16 14 12 10 8 fIF = 153MHz, fLO: 163MHz TO 6153MHz (HIGH SIDE LO) 6 PRF = -10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS 08079-139 4 2 0 1000 2000 3000 4000 5000 2000 3000 4000 RF FREQUENCY (MHz) 5000 6000 The device maintains an Input IP3 of 20 dBm or better and conversion gain of -2 dB or better across the 10 MHz to 6 GHz frequency band. VSET = 2.0V VSET = 3.6V 18 1000 Figure 105. Input Return Loss vs. RF Frequency 20 NOISE FIGURE (dB) -20 -35 20 0 -15 08079-140 GAIN, IIP3, IIP2 (dB, dBm) 60 -10 6000 RF FREQUENCY (MHz) Figure 104. Noise Figure vs. RF Frequency Rev. E | Page 35 of 40 ADL5801 Data Sheet SINGLE-ENDED DRIVE OF RF AND LO INPUTS The RF and LO ports of the active mixer can be driven single-ended without baluns for single-ended operation. In this configuration, the unused RF and LO ports should be ac grounded using a 1 nF capacitor. Figure 106 depicts setup configuration suggested to operate the device in the single-ended mode. IFOP IFON Mini-Circuits TC4-1W+ C50 0.1F VPOS R50 0 C2 0.1F C20 100pF C3 100pF 24 23 VPLO GND R14 0 22 NC 21 20 19 IFON IFOP GND C10 0.1F 1 GND VPRF 18 2 GND GND 17 3 LOIP RFIP 16 VPOS C8 1nF C4 1nF LOIN RFIP ADL5801 4 LOIN LOIP RFIN 15 RFIN C9 1nF C5 1nF 5 GND GND 14 6 GND VPDT 13 VPOS C11 0.1F VPLO GND ENBL VSET DETO GND 7 8 9 10 11 R1 0 12 R10 VPOS C7 100pF C18 C17 0.1F 100pF ENBL VSET DETO C1 0.1F R9 C12 100pF Figure 106. Single-Ended Configuration to Operate the ADL5801 Rev. E | Page 36 of 40 08079-141 C6 0.1F Data Sheet ADL5801 Figure 107 to Figure 109 demonstrate the performance of the mixer in the single ended mode. 0 -5 70 50 40 30 20 -20 -25 fIF = 153MHz fLO: 163MHz TO 6153MHz (HIGH SIDE LO) -30 PRF = -10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS PRF = -10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS -35 0 08079-142 0 -10 0 1000 2000 3000 4000 5000 RF FREQUENCY (MHz) 20 VSET = 2.0V VSET = 3.6V 15 10 fIF = 153MHz, fLO: 163MHz TO 6153MHz (HIGH SIDE LO) PRF = -10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS 08079-143 5 0 1000 2000 3000 4000 5000 1000 2000 3000 4000 RF FREQUENCY (MHz) 5000 Figure 109. Input Return Loss vs. RF Frequency 6000 Figure 107. Gain, IIP3, IIP2 vs. RF Frequency NOISE FIGURE (dB) -15 fIF = 153MHz, fLO: 163MHz TO 6153MHz (HIGH SIDE LO) 10 0 -10 6000 RF FREQUENCY (MHz) Figure 108. Noise Figure vs. RF Frequency Rev. E | Page 37 of 40 08079-144 GAIN, IIP3, IIP2 (dB, dBm) INPUT RETURN LOSS (dB) CONVERSION GAIN (dB) IIP3 (dBm) IIP2 (dBm) 60 6000 ADL5801 Data Sheet EVALUATION BOARD An evaluation board is available for the ADL5801. The standard evaluation board is fabricated using Rogers(R) RO3003 material. Each RF, LO, and IF port is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in Figure 110. Table 9 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 111 and Figure 112. IFOP T1 T5 T8 R11 R3 R50 C20 R2 L1 L2 L3 VPOS C19 C13 C3 24 23 VPLO GND R14 R13 C50 VPOS C2 IFON 22 21 NC 20 19 C10 IFON IFOP GND 1 GND VPRF 18 2 GND GND 17 3 LOIP RFIP 16 VPOS LOIN R8 L4 C8 C4 RFIP ADL5801 R16 T2 T4 T7 4 LOIN RFIN 15 5 GND GND 14 6 GND VPDT 13 8 9 10 11 VPOS 12 R10 C18 VPOS C6 C7 RFIN C11 VPLO GND ENBL VSET DETO GND 7 T3 T6 T9 R12 L5 C9 C5 C17 VSET ENBL R9 DETO C1 R7 C12 Figure 110. Evaluation Board Schematic Rev. E | Page 38 of 40 08079-133 LOIP Data Sheet ADL5801 Table 9. Evaluation Board Configuration C8, C9, L4, L5, R4, R8, R12, T3, T6, T9, RFIN, RFIP C13, C19, C20, C50, L1, L2, L3, R2, R3, R11, R13, R50, T1, T5, T8, IFON, IFOP C4, C5, R14, R16, T2, T4, T7, LOIN, LOIP C1, C12, R7, DETO LO interface. (Use LOIN for operation). C4 and C5 provide ac coupling for the local oscillator input. T2 is a 1:1 balun that allows single-ended interfacing to the differential 50 local oscillator input. T4 and T7 provide options when high frequency baluns are used and require smaller balun footprints. DETO interface. C1 and C12 provide decoupling for the DETO pin. R7 provides access to the VSET pin when automatic input IP3 control is needed. VSET bias control. C17 and C18 provide decoupling for the VSET pin. R9 and R10 form an optional resistor divider network between VPOS and GND, allowing for a fixed bias setting. Supply 3.8 V at the VSET pin when the DETO pin is not connected for automatic input IP3 control. Default Conditions C2, C6, C10, C11 = 0.1 F (size 0402) C3, C7 = 100 pF (size 0402) C8, C9 = 1 nF (size 0402) L4, L5 = 0 (size 0402) R12 = open (size 0402) R4, R8 = 0 (size 0402) T3 = TCM1-63AX+ (Mini-Circuits) C13 = open (size 0402) C19, C20 = 100 pF (size 0402) C50 = 0.1 F (size 0402) L1, L2 = open (size 0805) L3 = open (size 0402) R2, R3, R13, R50 = 0 (size 0402) R11 = open (size 0402) T1 = TC4-1W+ (Mini-Circuits) C4, C5 = 1 nF (size 0402) R14 = open (size 0402) R16 = 0 (size 0402) T2 = TCM1-63AX+ C1 = 0.1 F (size 0603) C12 = 100 pF (size 0402) R7 = open (size 0402) C17 = 100 pF (size 0402) C18 = 0.1 F (size 0603) R9, R10 = open (size 0402) 08079-134 C17, C18, R9, R10, VSET Function Power supply decoupling. Nominal supply decoupling consists of a 0.1 F capacitor to ground in parallel with 100 pF capacitors to ground, positioned as close to the device as possible. Series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. RF input interfaces. (Use RFIN for operation). Input channels are ac-coupled through C8 and C9. R8 and R12 provide options when additional matching is needed. T3 is a 1:1 balun used to interface to the 50 differential inputs. T6 and T9 provide options when high frequency baluns are used and require smaller balun footprints. IF output interfaces. The 200 open collector IF output interfaces are biased through the center tap of a 4:1 impedance transformer at T1. C50 provides local bypassing with R50 available for additional supply bypassing. L1 and L2 provide options when pull-up choke inductors are used to bias the open-collector outputs. C13, L3, R2, and R3 are provided for IF filtering and matching options. T5 and T8 provide options when high frequency baluns are used and require smaller balun footprints. 08079-135 Components C2, C3, C6, C7, C10, C11 Figure 111. Evaluation Board Top Layer Figure 112. Evaluation Board Bottom Layer Rev. E | Page 39 of 40 ADL5801 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 2.50 REF 0.60 MAX 18 3.75 BSC SQ 1 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD 6 13 TOP VIEW 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 7 12 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8 04-11-2012-A PIN 1 INDICATOR PIN 1 INDICATOR 24 19 Figure 113. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5801ACPZ-R7 ADL5801-EVALZ 1 Temperature Range -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. (c)2010-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08079-0-4/14(E) Rev. E | Page 40 of 40 Package Option CP-24-3 Ordering Quantity 1,500 per Reel 1