ST10F273Z4 Electrical characteristics
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IPD2
Power down supply current(10) (11)
(RTC on, main oscillator on,
main voltage regulator off)
TA = 25 °C – 8 mA
IPD3
Power down supply current (10)
(RTC on, 32 kHz oscillator on,
main voltage regulator off)
TA = 25 °C – 1.1 mA
ISB1
Stand-by supply current (10)
(RTC off, oscillators off, VDD off, VSTBY on)
VSTBY = 5.5 V
TA = TJ = 25 °C –250µA
VSTBY = 5.5 V
TA = TJ = 125 °C –500µA
ISB2
Stand-by supply current (10)
(RTC on, 32kHz oscillator on, main VDD off,
VSTBY on)
VSTBY = 5.5 V
TA = 25 °C –250µA
VSTBY = 5.5 V
TA = 125 °C –500µA
ISB3
Stand-by supply current (10)(8)
(VDD transient condition) ––2.5mA
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
2. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
3. Consult your vendor to know which version of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 35 for a scheme of the input
circuitry.
4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
5. The maximum current may be drawn while the respective signal line remains inactive.
6. The minimum current must be drawn in order to drive the respective signal line active.
7. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 36 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules (for ICC1)
Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM (for ICC2)
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
8. Not 100% tested, guaranteed by design characterization.
9. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 36 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at VIL or VIH, RSTIN pin at VIH1Min.
10. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD
– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
11. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range (i.e. VOV > VDD + 0.3 V or VOV < –0.3 V). The absolute sum of input overload currents on all port pins may
not exceed 50mA. The supply voltage must remain within the specified limits.
Table 65. DC characteristics (continued)
Symbol Parameter Test condition
Limit values
Unit
Min. Max.