8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer ADAR1000 Data Sheet FEATURES GENERAL DESCRIPTION 8 GHz to 16 GHz frequency range Half-duplex for transmit and receive modes Single-pin transmit and receive control 360 phase adjustment range 2.8 phase resolution 31 dB gain adjustment range 0.5 dB gain resolution Bias and control for external transmit and receive modules Memory for 121 prestored beam positions Four -20 dBm to +10 dBm power detectors Integrated temperature sensor Integrated 8-bit ADC for power detectors and temperature sensor Programmable bias modes 4-wire SPI interface The ADAR1000 is a 4-channel, X and Ku frequency band, beamforming core chip for phased arrays. This device operates in half-duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined in a common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a 31 dB gain adjustment range and a full 360 phase adjustment range in the radio frequency (RF) path, with 6-bit resolution (less than 0.5 dB and 2.8, respectively). A simple 4-wire serial port interface (SPI) controls all of the on-chip registers. In addition, two address pins allow SPI control of up to four devices on the same serial lines. Dedicated transmit and receive load pins also provide synchronization of all core chips in the same array, and a single pin controls fast switching between the transmit and receive modes. APPLICATIONS Phased array radar Satellite communications systems The ADAR1000 is available in a compact, 88-terminal, 7 mm x 7 mm, LGA package and is specified from -40C to +85C. REGULATORS LNA_BIAS PA_BIAS2 PA BIAS TO PA BIAS TR_POL TR_SW_NEG TR_SW_POS PA_ON CREG3 CREG4 CREG1 CREG2 AVDD3 AVDD1 FUNCTIONAL BLOCK DIAGRAM TRANSMIT/RECEIVE BIAS AND CONTROL ADAR1000 LNA BIAS PA BIAS ADC RX2 PA_BIAS3 DET3 TX3 TX2 RX3 DET2 ADC ADC DET4 RX1 TX4 TX1 RX4 ADC ADC TEMPERATURE SENSOR GND RF_IO RX_LOAD TR TX_LOAD CSB SDIO SCLK ADDR1 SPI PA_BIAS4 16790-001 SPI PA BIAS PA BIAS ADDR0 PA_BIAS1 ADC SDO DET1 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADAR1000 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Operation .......................................................................... 26 Applications ....................................................................................... 1 Chip Addressing ......................................................................... 27 General Description ......................................................................... 1 Memory Access........................................................................... 27 Functional Block Diagram .............................................................. 1 Calibration................................................................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 33 Specifications..................................................................................... 3 Gain Control Registers .............................................................. 33 Timing Specifications .................................................................. 6 Switched Attenuator Control .................................................... 33 Absolute Maximum Ratings ............................................................ 8 Phase Control Registers ............................................................. 34 Thermal Resistance ...................................................................... 8 Transmit and Receive Subcircuit Control ............................... 36 ESD Caution .................................................................................. 8 Transmit and Receive Switch Driver Control ......................... 36 Pin Configuration and Function Descriptions ............................. 9 PA Bias Output Control............................................................. 37 Typical Performance Characteristics ........................................... 12 LNA Bias Output Control ......................................................... 37 Theory of Operation ...................................................................... 24 Transmit/Receive Delay Control .............................................. 37 RF Path ......................................................................................... 24 SPI Programming Example ....................................................... 39 Phase and Gain Control ............................................................ 24 Powering the ADAR1000 .......................................................... 41 Power Detectors .......................................................................... 25 Register Map ................................................................................... 42 External Amplifier Bias DACs .................................................. 25 Register Descriptions ................................................................. 44 External Switch Control ............................................................ 25 Outline Dimensions ....................................................................... 65 Transmit and Receive Control .................................................. 26 Ordering Guide .......................................................................... 65 RF Subcircuit Bias Control and Enables.................................. 26 REVISION HISTORY 3/2019--Rev. 0 to Rev. A Change to Phase and Gain Switching Time Parameter, Table 1 ...... 5 Added SPI Write All Mode Section and Figure 6; Renumbered Sequentially ....................................................................................... 7 Added Figure 8.................................................................................. 9 Changes to Table 5 .......................................................................... 10 Reorganized Typical Performance Characteristics Section Layout ............................................................................................... 12 Changes to Figure 12 ...................................................................... 12 Added Figure 21.............................................................................. 14 Changes to Figure 26 ...................................................................... 14 Changes to Figure 31 ...................................................................... 15 Changes to Figure 33 ...................................................................... 16 Added Figure 40.............................................................................. 17 Added Figure 46 and Figure 49..................................................... 18 Changes to Figure 50 and Caption ............................................... 18 Changes to Figure 54, Figure 55, and Figure 56 ......................... 19 Changes to Figure 60 and Figure 61............................................. 20 Changes to Phase and Gain Control Section .............................. 24 Added Figure 86 ............................................................................. 24 Changes to External Switch Control Section .............................. 25 Changes to Table 6.......................................................................... 26 Added Chip Addressing Section .................................................. 27 Changes to Memory Access Section ............................................ 27 Added Table 7, Table 8, and Table 9, and Table 10; Renumbered Sequentially ...................................................................................... 27 Added Phase Control Registers Section, Table 13, and Table 14 ............................................................................................ 34 Added Table 15 and Table 16 ........................................................ 35 Added Transmit/Receive Delay Control Section ....................... 37 Changes to Figure 92...................................................................... 38 Changes to Table 20 ....................................................................... 39 Added Table 21 ............................................................................... 40 Added Powering the ADAR1000 Section, Figure 93 to Figure 97, and Table 22 .................................................................................... 41 6/2018--Revision 0: Initial Version Rev. A | Page 2 of 65 Data Sheet ADAR1000 SPECIFICATIONS AVDD1 = -5 V, AVDD3 = +3.3 V, TA = 25C, and the device is programmed to the maximum channel gain and the nominal bias conditions, unless otherwise noted. Nominal bias register settings: Register 0x034 = 0x08, Register 0x035 = 0x55, Register 0x036 = 0x2D, and Register 0x37 = 0x06. Low power bias register settings: Register 0x034 = 0x05, Register 0x035 = 0x1A, Register 0x036 = 0x2A, and Register 0x37 = 0x03. Table 1. Parameter OPERATING CONDITIONS RF Range Operating Temperature TRANSMIT SECTION Maximum Gain 9.5 GHz 11.5 GHz 14 GHz Gain Flatness vs. Frequency Gain Variation vs. Temperature Output 1 dB Compression (P1dB) Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Saturated Power (PSAT) Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Gain Resolution Root Mean Square (RMS) Gain Error Phase Adjustment Range Phase Resolution RMS Phase Error Noise Figure Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Channel to Channel Isolation 1 Transmit Output to RF_IO Test Conditions/Comments Min Typ 8 -40 Max Unit 16 +85 GHz C RF_IO, TX1, TX2, TX3, and TX4 pins 21 19 16 Across any 1 GHz bandwidth From 9 GHz to 14 GHz From 8 GHz to 15 GHz 11.5 GHz Maximum gain setting 1.0 1.7 2.5 dB dB dB dB dB dB dB 10 10 10 dBm dBm dBm 6 8 7 dBm dBm dBm 14 14 13 dBm dBm dBm 14 14 13 0.5 0.2 360 2.8 2 dBm dBm dBm dB dB Degrees Degrees Degrees 22 23 25 dB dB dB 22 23 25 -40 -60 dB dB dB dB dB Maximum gain setting Over phase settings and frequencies Over phase settings and frequencies Maximum gain setting Maximum gain setting, 9.5 GHz Rev. A | Page 3 of 65 ADAR1000 Parameter Output Return Loss Input Return Loss Output Third-Order Intercept (IP3) Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz RECEIVE SECTION Maximum Measured Gain 2 9.5 GHz 11.5 GHz 14 GHz Maximum Channel Gain 3 9.5 GHz 11.5 GHz 14 GHz Gain Flatness Gain Variation vs. Temperature Input P1dB Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Input IP3 Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Gain Adjustment Range Data Sheet Test Conditions/Comments TX1, TX2, TX3, or TX4 pin RF_IO pin Maximum gain setting, 1 MHz carrier spacing Min Typ -10 -12 Max Unit dB dB 20 21 22 dBm dBm dBm 15 16 16 dBm dBm dBm Nominal bias setting 10 9 7 dB dB dB Nominal bias setting 16 15 13 dB dB dB 1.0 1.7 3 dB dB dB -16 -16 -15 dBm dBm dBm -13 -12 -10 dBm dBm dBm -7 -7 -6 dBm dBm dBm -7 -6 -5 31 dBm dBm dBm dB 0.5 0.2 360 2.8 2 dB dB Degrees Degrees Degrees Across any 1 GHz bandwidth From 9 GHz to 14 GHz From 8 GHz to 15 GHz 11.5 GHz Maximum gain setting, carrier spacing 1 MHz Variable gain amplifier (VGA) and step attenuator Gain Resolution RMS Gain Error Phase Adjustment Range Phase Resolution RMS Phase Error Rev. A | Page 4 of 65 Data Sheet Parameter Noise Figure Nominal Bias Setting 9.5 GHz 11.5 GHz 14 GHz Low Bias Setting 9.5 GHz 11.5 GHz 14 GHz Channel to Channel Isolation 4 RF_IO to Receive Isolation Input Return Loss Output Return Loss TEMPERATURE SENSOR Range Slope Nominal Analog-to-Digital Converter (ADC) Output Resolution TRANSMIT AND RECEIVE SWITCHING Transmit and Receive Switching Time Phase and Gain Switching Time POWER DETECTOR RF Input Power Range Input Return Loss Nominal ADC Output Code Resolution POWER AMPLIFIER (PA) DIGITAL-TO-ANALOG CONVERTER (DAC) Resolution Voltage Range Source and Sink Current Off to On Switching Time On to Off Switching Time LOW NOISE AMPLIFIER (LNA) DAC Resolution Voltage Range Source and Sink Current Off to On Switching Time On to Off Switching Time TRANSMIT AND RECEIVE MODULE CONTROL Voltage Range Off to On Switching Time On to Off Switching Time ADAR1000 Test Conditions/Comments Maximum gain setting Min RF_IO pin Typ TX_LOAD, RX_LOAD, and TR pins From TR at 50% to RF at 90% From TX_LOAD or RX_LOAD at 50% to RF at 90% DET1, DET2, DET3, and DET4 pins 11.5 GHz Input power (PIN) = 0 dBm, 11.5 GHz Unit 8 8 9 dB dB dB 9 10 11 40 60 -10 -12 dB dB dB dB dB dB dB -40 Power-on reset (POR) mode (transmit and receive not enabled), TA = 25C Max 0.8 145 +85 C LSB/C Decimal 8 Bits 180 20 ns ns -20 +10 -10 60 8 dBm dB Decimal Bits PA_BIAS1, PA_BIAS2, PA_BIAS3, and PA_BIAS4 pins From TR or CSB at 50% to VOUT at 90%, VOUT from -1 V to -2 V, 1 nF CLOAD From TR or CSB at 50% to VOUT at 10%, VOUT from -1 V to -2 V, 1 nF CLOAD LNA_BIAS pin From TR or CSB at 50% to VOUT at 90%, VOUT from -2 V to -1 V, 1 nF CLOAD From TR or CSB at 50% to VOUT at 10%, VOUT from -1 V to -2 V, 1 nF CLOAD TR_SW_POS, TR_SW_NEG, TR_POL pins TR_SW_NEG, TR_POL TR_SW_POS From TR or CSB at 50% to VOUT at 90% From TR or CSB at 50% to VOUT at 10% Rev. A | Page 5 of 65 8 -4.8 to 0 -10 to +10 60 Bits V mA 60 ns 8 -4.8 to 0 -10 to+10 60 Bits V mA ns 60 ns -4.8 to 0 0 to 3.2 15 15 V V ns ns ns ADAR1000 Data Sheet Parameter LOGIC INPUTS Test Conditions/Comments TR, RX_LOAD, TX_LOAD, CSB, SCLK, and SDIO pins Input High Voltage (VIH) Input Low Voltage (VIL) High and Low Input Current, (IINH, IINL) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage, (VOH) Output Low Voltage, (VOL) POWER SUPPLIES AVDD1 AVDD3 IAVDD1 IAVDD1 IAVDD3 Reset Mode (Standby) Transmit Mode Receive Mode Min Typ Max 1.0 0.3 1 1 SDO and SDIO pins Output high current (IOH) = -10 mA Output low current (IOL) = 10 mA 1.4 0.4 -5.25 3.1 Quiescent (reset state) PA bias outputs fully loaded Four channels enabled, nominal bias Four channels enabled, low bias setting Four channels enabled, nominal bias Four channels enabled, low bias setting -5 3.3 -4 -50 -4.75 3.5 Unit V V A pF V V V V mA mA 23 350 240 mA mA mA 260 160 mA mA 1 From one transmit channel port to another, both channels must be set to the maximum gain. Measured gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports terminated in 50 . 3 Channel gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining, excluding the 6 dB combining gain. The channel gain is approximately 6 dB higher than the measured gain. 4 From one receive channel port to another, both channels must be set to the maximum gain. 2 TIMING SPECIFICATIONS AVDD1 = -5 V, AVDD3 = +3.3 V, TA = 25C, unless otherwise noted. Table 2. SPI Timing Parameter Maximum Clock Rate (tSCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWL) Setup Time, SDIO to SCLK (tDS) Hold Time, SDIO to SCLK (tDH) Data Valid, SDO to SCLK (tDV) Setup Time, CSB to SCLK (tDCS) SDIO, SDO Rise Time (tR) SDIO, SDO Fall Time (tF) Min Typ 25 10 10 5 5 5 10 20 20 Max Unit MHz ns ns ns ns ns ns ns ns Test Conditions/Comments Outputs loaded with 80 pF, 10% to 90% Outputs loaded with 80 pF, 10% to 90% Timing Diagrams INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE SDIO R/W A14 A13 A3 A2 A1 A0 D7N D6N D5N D30 Figure 2. Serial Port Interface Register Timing (MSB First) Rev. A | Page 6 of 65 D20 D10 D00 16790-002 SCLK Data Sheet ADAR1000 tSCLK tPWL tPWH SCLK tDCS CSB A_LSB A1 A2 A12 A13 A_MSB R/W SDIO D_MSB D6 D5 D1 D_LSB DON'T CARE DON'T CARE D1 D_LSB 16790-003 tDH tDS Figure 3. Timing Diagram for the Serial Port Interface Register Write SCLK CSB R/W SDIO A_MSB A_LSB A1 A2 A12 A13 DON'T CARE DON'T CARE DON'T CARE D_MSB D6 D5 SDO tF tR 16790-004 tDV Figure 4. Timing Diagram for Serial Port Interface Register Read SPI Block Write Mode Data can be written to the SPI registers in a block write mode, where the register address automatically increments, and data for consecutive registers can be written without sending new address bits. Data writing can be continued indefinitely until CSB is raised again, ending the write process. CSB SCLK R/W A14 A13 ... A1 A0 D7 ADDRESS OF FIRST REGISTER D6 ... D1 D0 D7 DATA OF FIRST REGISTER D6 ... D2 D1 D0 X 16790-005 SDIO DATA OF n + FIRIST REGISTER Figure 5. Timing Diagram for Block Write Mode SPI Write All Mode Data can be written to the SPI registers in a write all mode, where the data is written to all chips connected to the SPI bus with a single write command, regardless of the ADDR1 and ADDR0 values, by setting address Bits[A14:A11] = 0001. The write all mode allows the user to broadcast the same data, up to four ADAR1000 devices, with a single SPI write. CSB SCLK R/W 0 0 0 1 [A14:A11] = 0001 A10 ... A1 A0 ADDRESS OF FIRST REGISTER D7 D6 ... D1 D0 DATA OF FIRST REGISTER D7 ... D2 D1 D0 DATA OF n + FIRIST REGISTER Figure 6. SPI Write All Instruction and Timing Diagram Rev. A | Page 7 of 65 D6 X 16790-106 SDIO ADAR1000 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter AVDD1 to GND AVDD3 to GND Digital Input/Output Voltage to GND Maximum RF Input Power Operating Temperature Range Storage Temperature Range Reflow Soldering Peak Temperature Junction Temperature (TJ) Electrostatic Discharge (ESD) Charged Device Model (CDM) Human Body Model (HBM) Rating -5.5 V 3.6 V 2.0 V 20 dBm -40C to +85C -65C to +150C 260C 135C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. The PCB thermal design requires careful attention. JA is the junction to the ambient with the exposed pad soldered down, and JC is the junction to the exposed pad. Table 4. Thermal Resistance Package Type CC-88-11 1 500 V 2500 V JA 18.7 Simulated based on PCB specified in JESD-51. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 8 of 65 JC 10.1 Unit C/W Data Sheet ADAR1000 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N ADAR1000 NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD AND ALL GND CONNECTIONS TO A LOW IMPEDANCE GROUND PLANE ON THE PCB. 16790-006 TOP VIEW (Not to Scale) Figure 7. Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A DET3 GND TR_SW_NEG PA_BIAS4 PA_BIAS3 GND RF_IO GND PA_BIAS2 PA_BIAS1 LNA_BIAS GND GND B GND GND PA_ON TR_POL TR_SW_POS GND GND GND GND GND AVDD1 GND GND C TX3 GND GND RX2 D GND GND GND GND E RX3 GND GND TX2 F GND GND GND GND NO PINS EXPOSED PAD CONNECT TO LOW IMPEDANCE GROUND PLANE ON PCB G DET4 GND GND DET2 H GND GND GND GND J TX4 GND GND RX1 K GND GND GND GND L RX4 GND GND TX1 M GND GND N GND RX_LOAD NO PINS TX_LOAD SDO SDIO SCLK GND CREG1 CREG2 AVDD3 AVDD3 GND GND ADDR0 ADDR1 TR GND GND CREG4 CREG3 AVDD3 GND DET1 GROUND RF INPUT/OUTPUT BEAM CONTROL 3.3V ANALOG SUPPLY EXT BIAS OUTPUT REGULATOR DECOUPLING CHIP ADDRESS -5V ANALOG SUPPLY DETECTOR OUTPUT PA BIAS CONTROL EXPOSED PAD SPI Figure 8. Pin Configuration, Color Coded (Top View) Rev. A | Page 9 of 65 16790-108 CSB ADAR1000 Data Sheet Table 5. Pin Function Descriptions Pin No. A1 Mnemonic DET3 A2, A6, A8, A12, A13, B1, B2, B6 to B10, B12, B13, C2, C12, D1, D2, D12, D13, E2, E12, F1, F2, F12, F13, G2, G12, H1, H2, H12, H13, J2, J12, K1, K2, K12, K13, L2, L12, M1, M2, M7, M12, M13, N1, N7, N8, N12 A3 A4 GND A5 PA_BIAS3 A7 A9 RF_IO PA_BIAS2 A10 PA_BIAS1 A11 LNA_BIAS B3 PA_ON B4 B5 B11 TR_POL TR_SW_POS AVDD1 C1 C13 E1 E13 G1 TX3 RX2 RX3 TX2 DET4 G13 DET2 J1 J13 L1 L13 M3 TX4 RX1 RX4 TX1 CSB TR_SW_NEG PA_BIAS4 Description Channel 3 Power Detector Input. DET3 is internally ac-coupled and enabled by Register 0x030, Bit 1. The nominal operating input power range is -20 dBm to +10 dBm. RF Ground. Tie all ground pins together to a low impedance plane on the PCB board. Gate Control Output for External Transmit and Receive Switch (0 V or -5 V). Gate Bias Output for Channel 4 External PA. Output ranges from 0 to -4.8 V, controlled by a combination of the PA_ON pin, Register 0x02C (CH4_PA_BIAS_ON value), and Register 0x049 (CH4_PA_BIAS_OFF value). Output is set to the CH4_PA_BIAS_OFF value if the PA_ON pin is at logic low. Gate Bias Output for Channel 3 External PA. Output ranges from 0 to -4.8 V, controlled by a combination of the PA_ON pin, Register 0x02B (CH3_PA_BIAS_ON value), and Register 0x048 (CH3_PA_BIAS_OFF value). Output is set to the CH3_PA_BIAS_OFF value if the PA_ON pin is at logic low. Common RF Pin for Input in Transmit Mode and Output in Receive Mode. Gate Bias Output for Channel 2 External PA. Output ranges from 0 to -4.8 V, controlled by a combination of the PA_ON pin, Register 0x02A (CH2_PA_BIAS_ON value), and Register 0x047 (CH2_PA_BIAS_OFF value). Output is set to the CH2_PA_BIAS_OFF value if the PA_ON pin is at logic low. Gate Bias Output for Channel 1 External PA. Output ranges from 0 to -4.8 V, controlled by a combination of the PA_ON pin, Register 0x029 (CH1_PA_BIAS_ON value), and Register 0x046 (CH1_PA_BIAS_OFF value). Output is set to the CH1_PA_BIAS_OFF value if the PA_ON pin is at logic low. Gate Bias Output for External LNA. Output ranges from 0 to -4.8 V, controlled by a combination of Register 0x030 (Bit 4, LNA_BIAS_OUT_EN), Register 0x02D (LNA_BIAS_ON value), and Register 0x04A (LNA_BIAS_OFF value). Output floats if Register 0x030, Bit 4 is at logic low. PA Enable Input. Set this pin to logic high for PA bias voltages to assume the values set by the EXT_PAx_BIAS_ON and EXT_PAx_BIAS_OFF registers (x = 1 to 4). All PA_BIASx outputs take on the corresponding CHx_PA_BIAS_OFF value if the PA_ON pin is at logic low. This pin is internally pulled up to the 1.8 V low dropout (LDO) regulator bias voltage with a 100 k resistor. Gate Control Output for External Polarization Switch (0 V or -5 V). Gate Control Positive Output for External Transmit and Receive Switch (0 V or 3.3 V). -5 V Power Supply. AVDD1 provides the negative currents for sinking the PA_BIASx and LNA_BIAS outputs. If the PA_BIASx and LNA_BIAS pins are not used, the user can connect AVDD1 to ground to reduce power consumption and to use a single voltage supply. Channel 3 Output in Transmit Mode. Channel 2 Input in Receive Mode. Channel 3 Input in Receive Mode. Channel 2 Output in Transmit Mode. Channel 4 Power Detector Input. DET4 is internally ac-coupled and enabled by Register 0x030, Bit 0. The nominal operating input power range is -20 dBm to +10 dBm. Channel 2 Power Detector Input. DET2 is internally ac-coupled and enabled by Register 0x030, Bit 2. The nominal operating input power range is -20 dBm to +10 dBm. Channel 4 Output in Transmit Mode. Channel 1 Input in Receive Mode. Channel 4 Input in Receive Mode. Channel 1 Output in Transmit Mode. SPI Chip Select Input (1.8 V CMOS Logic). Serial communication is enabled when CSB goes low. When CSB goes high, serial data is loaded into the register corresponding to the address in the instruction cycle (see Figure 2) in write mode. Rev. A | Page 10 of 65 Data Sheet ADAR1000 Pin No. M4 M5 M6 Mnemonic SDO SDIO SCLK M8 CREG1 M9 CREG2 M10, M11, N11 N2 AVDD3 RX_LOAD N3 TX_LOAD N4 ADDR0 N5 ADDR1 N6 N9 TR CREG4 N10 CREG3 N13 DET1 EPAD Description SPI Serial Data Output (1.8 V CMOS Logic). SPI Serial Data Input and Output (1.8 V CMOS Logic). SPI Serial Clock Input (1.8 V CMOS Logic). In write mode, data is sampled on the rising edge of SCLK. During a read cycle, output data changes at the falling edge of SCLK. Decoupling Pin for 1.8 V LDO Reference. Connect a 1 F capacitor through a low impedance path from this pin to a ground plane. Decoupling Pin for 2.8 V LDO Output. Connect a 1 F capacitor through a low impedance path from this pin to a ground plane. 3.3 V Voltage Power Supply Inputs. Load Receive Registers Input (1.8 V CMOS Logic). A rising edge causes contents in the receive channel holding registers to transfer to the working registers. Load Transmit Registers Input (1.8 V CMOS Logic). A rising edge causes contents in the transmit channel holding registers to transfer to the working registers. Chip Select Address 0 Input (1.8 V CMOS Logic). ADDR1 and ADDR0 together select one of four core chips to accept the serial instructions and data. Chip select Address 1 Input (1.8 V CMOS Logic). ADDR1 and ADDR0 together select one of four core chips to accept the serial instructions and data. Transmit and Receive Mode Select Input (1.8 V CMOS Logic). Decoupling Pin for 1.8 V LDO Output. Connect a 1 F capacitor through a low impedance path from this pin to a ground plane. Decoupling Pin for 2.8 V LDO Reference. Connect a 1 F capacitor through a low impedance path from this pin to a ground plane. Channel 1 Power Detector Input. DET1 is internally ac-coupled and enabled by Register 0x030, Bit 3. The nominal operating input power range is -20 dBm to +10 dBm. Exposed Pad. Connect the exposed pad and all GND connections to a low impedance ground plane on the PCB. Rev. A | Page 11 of 65 ADAR1000 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = -5 V, ADVDD3 = +3.3 V, TA = 25C, nominal bias settings and reported gain is measured gain, unless otherwise stated. 10 NORMALIZED GAIN (dB) 5 GAIN (dB) 0 -5 -10 -15 -20 -25 -35 6 8 10 12 14 16 18 FREQUENCY (GHz) 16790-007 -30 Figure 9. Gain vs. Frequency for Gain Settings from 0 to 127, Single Receive Channel 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 9.5GHz, ATTENUATOR = 1 11.5GHz, ATTENUATOR = 1 14.0GHz, ATTENUATOR = 1 9.5GHz, ATTENUATOR = 0 11.5GHz, ATTENUATOR = 0 14.0GHz, ATTENUATOR = 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 7-BIT CONTROL CODE 16790-010 15 Figure 12. Normalized Gain vs. 7-Bit Gain Control Code, Single Receive Channel 12 6 5 11 10 3 2 9 3.3V, +85C 3.3V, +25C 3.3V, -40C 0 3.1V, +85C 3.1V, +25C 3.1V, -40C 3.5V, +85C 3.5V, +25C 3.5V, -40C -1 -2 -3 8 7 6 -4 5 9.5GHz 11.5GHz 14.0GHz -5 6 8 10 12 14 16 18 FREQUENCY (GHz) 4 16790-008 -6 0 40 80 120 160 200 240 280 320 360 PHASE SETTING (Degrees) 16790-011 1 GAIN (dB) NORMALIZED GAIN (dB) 4 Figure 13. Gain vs. Phase Setting over Frequency, Receive Channel Figure 10. Normalized Gain vs. Frequency over AVDD3 Supply and Temperature, Receive Channel 20 20 15 15 GAIN AND RETURN LOSS (dB) 10 10 0 -5 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C -15 8 10 12 -10 -15 -20 -25 -35 -20 6 CHANNEL GAIN MEASURED GAIN RETURN LOSS RF_IO RETURN LOSS RXx -30 14 FREQUENCY (GHz) 16 18 -40 16790-009 -10 0 -5 Figure 11. Gain vs. Frequency over Bias and Temperature, Receive Channel 6 8 10 12 14 FREQUENCY (GHz) 16 18 16790-012 GAIN (dB) 5 5 Figure 14. Gain and Return Loss vs. Frequency, at Maximum Gain, Receive Channel Rev. A | Page 12 of 65 Data Sheet ADAR1000 10 500 8 400 350 300 250 200 0 45 90 135 180 225 270 315 360 PHASE SETTING (Degrees) Figure 15. Phase Shift vs. Phase Setting over Temperature, Receive Channel -2 -4 -6 -8 -6 -4 6 5 6 4 2 0 0 9.5GHz 11.5GHz 14.0GHz 4 8 -2 Figure 18. Normalized Phase Shift vs. Normalized Gain over Frequency, Receive Channel 12 -2 3 2 1 0 -1 -2 -3 -4 PEAK AVERAGE RMS 7 8 9 10 11 12 13 14 15 16 17 18 FREQUENCY (GHz) 35 30 25 20 15 10 5 0 -5 7 8 9 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 18 16790-015 ATTENUATION BYPASS 6 0 45 90 135 180 225 270 315 360 PHASE SETTING (Degrees) Figure 19. Phase Error vs. Phase Setting over Frequency, Receive Channel Figure 16. Phase Error vs. Frequency, Receive Channel -10 -6 Figure 17. Phase Shift vs. Frequency for Step Attenuator in Attenuation Mode, Normalized to Bypass Mode, Receive Channel CHANNEL TO CHANNEL PHASE DIFFERENCE (Degrees) 6 -5 16790-014 -4 -15 9.5GHz 11.5GHz 14.0GHz -8 NORMALIZED GAIN (dB) PHASE ERROR (Degrees) PHASE ERROR (Degrees) 0 -10 -24 -22 -20 -18 -16 -14 -12 -10 10 PHASE SHIFT (Degrees) 2 14 -6 RECOMMENDED OPERATING RANGE 4 16790-017 100 16790-013 -40C +25C +85C 150 6 15 CH1 CH2 CH3 CH4 10 5 0 -5 -10 -15 6 8 10 12 14 FREQUENCY (GHz) 16 18 16790-018 PHASE SHIFT (Degrees) 450 16790-016 NORMALIZED PHASE SHIFT (Degrees) 550 Figure 20. Channel to Channel Phase Difference vs. Frequency, Receive Channel Rev. A | Page 13 of 65 Data Sheet 2 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C 0 1.5 CH1 CH2 CH3 CH4 -2 INPUT IP3 (dBm) 1.0 0.5 0 -0.5 -4 -6 -8 -1.0 -10 -1.5 -12 -2.0 6 7 8 9 10 11 12 13 14 15 16 17 -14 6 18 8 10 Figure 21. Channel to Channel Gain Difference vs. Frequency, Receive Channel 14 16 18 Figure 24. Input IP3 vs. Frequency over Bias and Temperature, Receive Channel -4 17 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C -8 GAIN = 15 GAIN = 29 GAIN = 43 GAIN = 57 GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 16 15 NOISE FIGURE (dB) -6 INPUT P1dB (dBm) 12 FREQUENCY (GHz) FREQUENCY (GHz) 16790-021 2.0 16790-120 CHANNEL TO CHANNEL GAIN DIFFERENCE (dB) ADAR1000 -10 -12 -14 14 13 12 11 10 -16 9 -18 6 8 10 12 14 16 18 FREQUENCY (GHz) 7 16790-019 -20 6 GAIN = 15 GAIN = 29 GAIN = 43 GAIN = 57 GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 -8 -10 -13 -14 14 16 18 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C 17 NOISE FIGURE (dB) -6 12 Figure 25. Noise Figure vs. Frequency over Gain, Receive Channel 19 -4 10 FREQUENCY (GHz) Figure 22. Input P1dB vs. Frequency over Bias and Temperature, Receive Channel -16 15 13 11 9 -20 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 23. Input P1dB vs. Frequency over Gain, Receive Channel 5 6 8 10 12 14 FREQUENCY (GHz) 16 18 16790-023 7 -18 16790-020 INPUT P1dB (dBm) 8 16790-022 8 Figure 26. Noise Figure vs. Frequency over Bias and Temperature, Receive Channel Rev. A | Page 14 of 65 Data Sheet ADAR1000 0 30 GAIN = 15 GAIN = 29 GAIN = 43 GAIN = 57 GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 -2 -4 20 15 -5 -6 10 5 0 -8 -5 -9 6 8 10 12 14 16 18 FREQUENCY (GHz) -10 16790-024 -10 Figure 27. Input IP3 vs. Frequency over Gain, Receive Channel 6 NORMALIZED GAIN (dB) GAIN (dB) 10 0 -10 10 12 14 16 18 FREQUENCY (GHz) 16790-025 -20 8 12 14 16 18 Figure 30. Gain vs. Frequency over Bias and Temperature, Single Transmit Channel 20 6 10 FREQUENCY (GHz) 30 -30 8 16790-027 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C -7 Figure 28. Gain vs. Frequency over Gain Settings from 0 to 127, Single Transmit Channel 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 9.5GHz, ATTENUATOR = 1 11.5GHz, ATTENUATOR = 1 14.0GHz, ATTENUATOR = 1 9.5GHz, ATTENUATOR = 0 11.5GHz, ATTENUATOR = 0 14.0GHz, ATTENUATOR = 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 7-BIT CONTROL CODE 16790-028 INPUT IP3 (dBm) -3 25 GAIN (dB) -1 Figure 31. Normalized Gain vs. 7-Bit Gain Control Code, Transmit Channel 5 12 4 11 10 2 9 0 GAIN (dB) 3.3V, +85C 3.3V, +25C 3.3V, -40C 1 3.1V, +85C 3.1V, +25C 3.1V, -40C 3.5V, +85C 3.5V, +25C 3.5V, -40C -1 -2 8 7 6 -3 5 -5 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 29. Normalized Gain vs. Frequency over AVDD3 Supply and Temperature, Transmit Channel 9.5GHz 11.5GHz 14.0GHz 4 0 40 80 120 160 200 240 PHASE SETTING (Degrees) 280 320 360 16790-029 -4 16790-026 NORMALIZED GAIN (dB) 3 Figure 32. Gain vs. Phase Setting over Frequency, Single Transmit Channel Rev. A | Page 15 of 65 ADAR1000 Data Sheet 35 25 20 30 25 10 PHASE SHIFT (Degrees) GAIN AND RETURN LOSS (dB) 15 5 0 GAIN RETURN LOSS TXx RETURN LOSS RF_IO -5 -10 -15 -20 -25 20 15 10 5 0 -5 -30 -10 6 8 10 12 14 16 18 FREQUENCY (GHz) -15 16790-030 9 10 11 12 13 14 15 16 17 18 400 300 200 -40C +25C +85C 0 45 90 135 180 225 270 315 360 PHASE SETTING (Degrees) Figure 34. Phase Shift vs. Phase Setting over Temperature, Transmit Channel 8 6 RECOMMENDED OPERATING RANGE 4 2 0 -2 -4 -6 9.5GHz 11.5GHz 14.0GHz -8 -10 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 6 12 5 PHASE ERROR (Degrees) 4 2 0 0 9.5GHz 11.5GHz 14.0GHz 4 10 6 -2 Figure 37. Normalized Phase Shift vs. Normalized Gain over Frequency, Transmit Channel 14 8 -4 NORMALIZED GAIN (dB) 16790-034 NORMALIZED PHASE SHIFT (Degrees) 500 16790-031 PHASE SHIFT (Degrees) 8 10 600 -2 3 2 1 0 -1 -2 -3 -4 PEAK AVERAGE RMS -4 6 7 8 9 10 11 12 13 14 15 16 17 FREQUENCY (GHz) Figure 35. Phase Error vs. Frequency, Transmit Channel -5 18 -6 16790-032 PHASE ERROR (Degrees) 7 FREQUENCY (GHz) 700 -6 6 Figure 36. Phase Shift vs. Frequency for Step Attenuator in Attenuation Mode, Normalized to Bypass Mode, Transmit Channel Figure 33. Gain and Return Loss vs. Frequency, Transmit Channel 100 ATTENUATION BYPASS 0 45 90 135 180 225 PHASE SETTING (Degrees) 270 315 360 16790-035 -40 16790-033 -35 Figure 38. Phase Error vs. Phase Setting over Frequency, Transmit Channel Rev. A | Page 16 of 65 ADAR1000 12 15 CH1 CH2 CH3 CH4 10 5 0 -5 6 4 2 GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 0 -10 -2 -15 6 8 10 12 14 16 18 FREQUENCY (GHz) 6 8 12 14 16 18 Figure 42. Output P1dB vs. Frequency over Gain, Transmit Channel 25 2.0 1.5 20 CH1 CH2 CH3 CH4 15 0.5 0 -0.5 10 5 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C 0 -1.0 16790-139 -5 -2.0 6 7 8 9 10 11 12 13 14 15 16 17 -10 6 18 8 10 12 14 16 18 FREQUENCY (GHz) FREQUENCY (GHz) Figure 40. Channel to Channel Gain Difference vs. Frequency, Transmit Channel 16790-039 OUTPUT IP3 (dBm) 1.0 -1.5 Figure 43. Output IP3 vs. Frequency over Bias and Temperature, Transmit Channel 14 50 GAIN = 15 GAIN = 29 GAIN = 43 GAIN = 57 GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 12 45 10 NOISE FIGURE (dB) 8 6 4 2 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C -2 -4 8 10 12 35 30 25 -6 6 40 14 FREQUENCY (GHz) 16 18 Figure 41. Output P1dB vs. Frequency over Bias and Temperature, Transmit Channel Rev. A | Page 17 of 65 20 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 44. Noise Figure vs. Frequency over Gain, Transmit Channel 16790-040 0 16790-037 OUTPUT P1dB (dBm) 10 FREQUENCY (GHz) Figure 39. Channel to Channel Phase Difference vs. Frequency, Transmit Channel GAIN DIFFERENCE (dB) 8 16790-038 OUTPUT P1dB (dBm) 10 16790-036 CHANNEL TO CHANNEL PHASE DIFFERENCE (Degrees) Data Sheet ADAR1000 Data Sheet 30 36 NOMINAL BIAS, -40C NOMINAL BIAS, +25C NOMINAL BIAS, +85C LOW BIAS, -40C LOW BIAS, +25C LOW BIAS, +85C 20 26 24 15 10 5 0 22 -5 20 6 8 10 12 14 16 18 FREQUENCY (GHz) -10 16790-041 18 18 16 16 14 14 PSAT (dBm) 8 8 6 4 4 2 2 8 9 10 11 12 13 14 15 16 17 18 FREQUENCY (GHz) Figure 46. PSAT vs. Frequency, Transmit Channel, Nominal Bias, Maximum Gain and Phase Set to 45, All Channels Enabled 6 7 8 9 10 16 18 11 -20 -10 0xFF 0xAB 0x8B 0 13 14 15 16 17 18 Figure 49. PSAT vs. Frequency, Transmit Channel, Low Bias, Maximum Gain and Phase Set to 45, All Channels Enabled -30 -20 -10 0 10 10 0x7F 0x2B 0x0B 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN 16790-043 -30 12 FREQUENCY (GHz) -40 -40 14 0 16790-146 0 7 12 -40C +25C +85C 10 6 6 10 12 -40C +25C +85C 10 8 Figure 48. Output IP3 vs. Frequency over Gain, Transmit Channel 18 12 6 FREQUENCY (GHz) Figure 45. Noise Figure vs. Frequency over Bias and Temperature, Transmit Channel PSAT (dBm) GAIN = 71 GAIN = 85 GAIN = 99 GAIN = 113 GAIN = 127 16790-042 28 16790-147 30 25 Figure 47. Gain Variation vs. Phase over Gain, 9.5 GHz, Receive Channel 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN 16790-046 NOISE FIGURE (dB) 32 OUTPUT IP3 (dBm) 34 Figure 50. Phase Variation vs. Gain over Phase, 9.5 GHz, Receive Channel Rev. A | Page 18 of 65 Data Sheet ADAR1000 -40 0 0xFF 0xAB 0x8B 0x7F 0x2B 0x0B -10 0 0xFF 0xAB 0x8B -30 -20 -10 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN 0xFF 0xB3 0x94 0 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN 10 0x7F 0x2B 0x0B 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, 10 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN Figure 55. Phase Variation vs. Gain over Phase, 14 GHz, Receive Channel -40 -30 -20 -10 0 10 10 Figure 52. Gain Variation vs. Phase over Gain, 14 GHz, Receive Channel -40 -30 -20 -10 0 Figure 54. Phase Variation vs. Gain over Phase, 11.5 GHz, Receive Channel 16790-045 -20 -10 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, -40 -30 -20 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN Figure 51. Gain Variation vs. Phase over Gain, 11.5 GHz, Receive Channel -40 -30 10 16790-047 -10 16790-048 -20 0 10 20 20 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN 0x7F 0x33 0x14 Figure 53. Gain Variation vs. Phase over Gain, 9.5 GHz, Transmit Channel 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN 16790-052 -30 16790-044 -40 Figure 56. Phase Variation vs. Gain over Phase, 9.5 GHz, Transmit Channel Rev. A | Page 19 of 65 Data Sheet 20 -40 -30 -20 -10 0x7F 0x33 0x14 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN Figure 57. Gain Variation vs. Phase over Gain, 11.5 GHz, Transmit Channel 0 Degrees 45 Degrees 90 Degrees 135 Degrees 0 Degrees, 10dB ATTEN 45 Degrees, 10dB ATTEN 90 Degrees, 10dB ATTEN 135 Degrees, 10dB ATTEN 0x7F 0x33 0x14 300 0 250 -1 200 -2 150 -3 100 -4 20 30 40 50 60 70 80 90 -5 250 20 TEMPERATURE (C) Figure 59. AVDD3 and AVDD1 Supply Current vs. Temperature, Four Transmit Channels Enabled, Normal Bias Mode and Low Bias Mode 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN 1 IAVDD3 , NOMINAL BIAS IAVDD3 , LOW BIAS IAVDD1 , NOMINAL BIAS IAVDD1 , LOW BIAS 0 200 -1 150 -2 100 -3 50 -4 0 -40 -30 -20 -10 16790-055 10 AVDD3 SUPPLY CURRENT (mA) 1 0 300 2 350 50 -40 -30 -20 -10 10 Figure 61. Phase Variation vs. Gain over Phase, 14 GHz, Transmit Channel 3 NOMINAL BIAS LOW BIAS NOMINAL BIAS LOW BIAS AVDD1 SUPPLY CURRENT (mA) AVDD3 SUPPLY CURRENT (mA) 400 IAVDD3 , IAVDD3 , IAVDD1 , IAVDD1 , 0 20 Figure 58. Gain Variation vs. Phase over Gain, 14 GHz, Transmit Channel 450 10dB ATTEN 10dB ATTEN 10dB ATTEN 10dB ATTEN 0 10 20 30 40 TEMPERATURE (C) 50 60 70 80 90 -5 16790-056 0xFF 0xB3 0x94 10 20 Figure 60. Phase Variation vs. Gain over Phase, 11.5 GHz, Transmit Channel 16790-051 0 10 180 Degrees 225 Degrees 270 Degrees 315 Degrees 180 Degrees, 225 Degrees, 270 Degrees, 315 Degrees, -40 -30 -20 -10 -40 -30 -20 -10 0 16790-054 0xFF 0xB3 0x94 10 AVDD1 SUPPLY CURRENT (mA) 0 16790-050 -40 -30 -20 -10 16790-053 ADAR1000 Figure 62. AVDD3 and AVDD1 Supply Current vs. Temperature, Four Receive Channels Enabled, Normal Bias Mode and Low Bias Mode Rev. A | Page 20 of 65 ADAR1000 -0.015 -0.020 0 -0.025 -0.5 -0.030 -1.0 -0.035 -1.5 -0.040 -2.0 -20 0 1 TIME (ns) -3 -4 -6 -10 -0.020 0 -0.025 -0.5 TR PA_BIAS1 DETECTED TRANSMIT OUTPUT DETECTED RECEIVE OUTPUT -1.0 -1.5 40 50 60 70 3.0 HIGH TO LOW GAIN LOW TO HIGH GAIN TX_LOAD -0.030 -0.035 2.0 0.3 1.5 0.2 1.0 0.1 0.5 0 TIME (ns) 0 -0.1 -10 16790-058 -0.045 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 -0.5 -5 0 5 10 15 20 25 30 35 40 TIME (ns) Figure 64. Transmit to Receive Switching Response to TR Falling Edge Figure 67. Gain Settling Response to TX_LOAD 0.6 4 3.0 MINIMUM TO MAXIMUM MAXIMUM TO MINIMUM TX_LOAD 3 0.5 DETECTED TX1 OUTPUT (V) 2 1 TR TR_SW_POS TR_SW_NEG 0 -1 -2 -3 2.5 0.4 -0.040 -2.0 -20 0 30 0.5 DETECTED TX1 OUTPUT (V) 0.5 20 0.6 DETECTED RECEIVE OUTPUT (V) -0.015 VOLTAGE (V) 2.5 0.4 2.0 0.3 1.5 0.2 1.0 0.1 0.5 -4 0 0 -6 -10 0 10 20 30 TIME (ns) 40 50 60 70 -0.1 -10 Figure 65. TR_SW_POS and TR_SW_NEG Response to TR Rising Edge Rev. A | Page 21 of 65 -0.5 -5 0 5 10 15 20 25 30 35 40 TIME (ns) Figure 68. Phase Settling Response (as TX1 Vector Modulator Inphase-Channel Output) to TX_LOAD 16790-062 -5 16790-059 TR, PA_BIAS1, DETECTED TRANSMIT OUTPUT (V) 1.0 10 Figure 66. TR_SW_POS and TR_SW_NEG Response to TR Falling Edge -0.005 -0.010 0 TIME (ns) Figure 63. Receive to Transmit Switching Response to TR Rising Edge 1.5 -2 -5 -0.045 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 2.0 0 -1 16790-060 0.5 2 TX_LOAD (V) TR PA_BIAS1 DETECTED TRANSMIT OUTPUT DETECTED RECEIVE OUTPUT 1.0 TR TR_SW_POS TR_SW_NEG 3 16790-061 -0.010 TX_LOAD (V) 1.5 4 VOLTAGE (V) -0.005 DETECTED RECEIVE OUTPUT (V) 2.0 16790-057 TR, PA_BIAS1, DETECTED TRANSMIT OUTPUT (V) Data Sheet ADAR1000 Data Sheet 0 TX1 TO DET1: TRANSMIT TX1 TO DET1: TRANSMIT DET1 TO TX1: TRANSMIT DET1 TO TX1: TRANSMIT -5 SCLK MODE, MODE, MODE, MODE, DET DET DET DET ON OFF ON OFF -10 ISOLATION (dB) 1 TX_LOAD 2 M MEM 3 MEM 2 MEM 1 TX1 DETECTED OUTPUT AMPLITUDE -15 -20 -25 -30 -35 M1.00s A CH2 1.25GS/s IT 80.0ps/pt T 20.00% 1.20V -45 16790-063 CH1 2.00V CH2 2.00V MATH 20.0mV 6 8 10 12 14 16 18 FREQUENCY (GHz) 16790-066 -40 Figure 72. Isolation vs. Frequency, Transmit to Detector and Detector to Transmit Figure 69. Beam Position Memory Advance vs. TX_LOAD 0 RX1 TO RX2 RX2 TO RX1 -10 TR INPUT -20 TRANSMIT POSITION 1 ISOLATION (dB) 1 TRANSMIT POSITION 2 TX1 DETECTED OUTPUT AMPLITUDE 2 RX_LOAD 4 3 RECEIVE POSITION 2 -40 -50 -60 EXTERNAL LNA BIAS RECEIVE POSITION 1 A CH1 1.20V -80 16790-064 M1.00s T 10.00% 6 -10 12 14 16 18 Figure 73. Isolation vs. Frequency, Receive Channel to Receive Channel 0 RX1 TO TX1: RECEIVE MODE RX1 TO TX1: TRANSMIT MODE TX1 TO RX1: RECEIVE MODE TX1 TO RX1: TRANSMIT MODE -5 10 FREQUENCY (GHz) Figure 70. Beam Position Memory Advance vs. RX_LOAD with Transmit and Receive Switching 0 8 16790-067 -70 CH2 50.0V CH4 1.00V CH1 2.00V CH3 2.00V -30 RX3 TO RX4 RX4 TO RX3 -10 -20 ISOLATION (dB) -20 -25 -30 -30 -40 -50 -35 -60 -40 -50 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 71. Isolation vs. Frequency, Transmit to Receive Channel -80 6 8 10 12 14 FREQUENCY (GHz) 16 18 16790-068 -70 -45 16790-065 ISOLATION (dB) -15 Figure 74. Isolation vs. Frequency, Receive Channel to Receive Channel Rev. A | Page 22 of 65 Data Sheet ADAR1000 300 RF DETECTOR OUTPUT CODE (Decimal) TX1 TO TX2 TX2 TO TX1 -10 -30 -40 -50 -60 -80 6 8 10 12 14 16 18 FREQUENCY (GHz) 100 50 -15 -5 -10 10 5 0 15 0 TX3 TO TX4 TX4 TO TX3 INPUT RETURN LOSS (dB) -5 -20 -30 -40 -50 -60 -10 -15 -20 -25 6 8 10 12 14 16 18 FREQUENCY (GHz) -35 16790-070 -80 6 8 10 12 14 16 18 FREQUENCY (GHz) 16790-073 -30 -70 Figure 79. Input Return Loss vs. Frequency, RF Detector Figure 76. Isolation vs. Frequency, Transmit Channel to Transmit Channel 210 0 RX1 TO DET2: TRANSMIT MODE, DET2 ON DET2 TO RX1: RECEIVE MODE, DET2 ON DET2 TO RX1: RECEIVE MODE, DET2 OFF DET2 TO RX1: TRANSMIT MODE, DET2 ON DET2 TO RX1: TRANSMIT MODE, DET2 OFF -10 200 190 ADC OUTPUT CODE (Decimal) -5 ISOLATION (dB) -40C +25C +85C Figure 78. RF Detector Output Code vs. Input Power and Temperature, 11.5 GHz -10 ISOLATION (dB) 150 INPUT POWER (dBm) Figure 75. Isolation vs. Frequency, Transmit Channel to Transmit Channel 0 200 0 -20 16790-069 -70 250 -15 -20 -25 -30 -35 180 170 160 150 140 130 120 110 100 -40 RESET RECEIVE NOMINAL BIAS TRANSMIT NOMINAL BIAS 90 6 8 10 12 14 FREQUENCY (GHz) 16 18 80 -40 -30 -20 -10 16790-071 -45 Figure 77. Input Isolation vs. Frequency, Receive to Detector and Detector to Receive 0 10 20 30 40 50 AMBIENT TEMPERATURE (C) 60 70 80 90 16790-074 ISOLATION (dB) -20 16790-072 0 Figure 80. ADC Output Code vs. Ambient Temperature, Temperature Sensor Rev. A | Page 23 of 65 ADAR1000 Data Sheet RF PATH The ADAR1000 contains four identical transmit and receive channels for time division duplex (TDD) operation. As shown in Figure 81, each receive channel includes an LNA followed by a phase shifter and a VGA. Each transmit channel includes a VGA followed by a phase shifter and a driver amplifier. A control switch selects between the transmit and receive paths, and a step attenuator stage of 0 dB or 15 dB is included in the common path and shared between the transmit and receive modes before connecting to the passive 4:1 combining and splitting network. The primary function of the chip is to accurately set the relative phase and gain of each channel so that the signals coherently add in the desired direction. The individual element gain control compensates for temperature and process effects and provides tapering for the beam to achieve low-side lobe levels. one bit for polarity control, for a total of 12 bits per phase shifter. The vector modulator output voltage amplitude (VOUT) and phase shift () are given by the following equations: V= OUT VI 2 + VQ 2 = arctan(VQ/VI) where: VI is output voltage of the I channel VGA. VQ is the output voltage of the Q channel VGA. I VGA IN 90 OUT BITS 16790-079 THEORY OF OPERATION Q VGA Figure 85. Active Vector Modulator Phase Shifter Block Diagram RX1 16790-075 Note that when evaluating the arctangent function, the proper phase quadrant must be selected. The signs of VQ and VI determine the phase quadrant according to the following: TX1 Figure 81. Transmit and Receive Channel Functional Diagram * TRANSMIT OUTPUT 16790-076 * Figure 82. Transmit Channel Output Interface Schematic * RECEIVE INPUT 16790-077 * If VQ and VI are both positive, the phase shift is between 0 and 90. If VQ is positive and VI is negative, the phase shift is between 90 and 180. If VQ and VI are both negative, the phase shift is between 180 and 270. If VQ is negative and VI is positive, the phase shift is between 270 and 360. Figure 83. Receive Channel Input Interface Schematic Q 90 As shown in Figure 82 and Figure 83, the receive input and transmit output of each channel is connected to a balun, which converts the single-ended signal to the differential signal required for the active RF circuit blocks. The balun networks also match the input and outputs to 50 over the operating bandwidth. Figure 84 shows the interface schematic for the common RF_IO port, which is single-ended, matched to 50 over the operating bandwidth, and connected to dc ground through a shunt matching inductor. VQ VOUT 180 VI I 0 Figure 84. Common RF_IO Interface Schematic 270 PHASE AND GAIN CONTROL Figure 86. Vector Gain Representation Phase control is implemented using the active vector modulator architecture shown in Figure 85. The incoming signal is split into equal amplitude, inphase and quadrature (I and Q) signals that are amplified independently by two identical biphase VGAs and summed at the output to generate the required phase shift. Six bits control each VGA, five bits for amplitude control and Rev. A | Page 24 of 65 16790-184 16790-078 RF_IO Data Sheet ADAR1000 Table 13 in the Phase Control Registers section details the values to set in Register 0x014 to Register 0x01B for the receiver and Register 0x020 to Register 0x027 for the transmitter, to sweep the phase while keeping the gain of the vector modulator constant. Keeping the vector modulator gain constant degrades the phase resolution to 2.8. SPI sets the DAC output, which is amplified and translated to a 0 V to -4.8 V range intended for the gate bias of the GaAs or GaN PAs. A push pull output stage allows sourcing or sinking of up to 10 mA for PAs that can draw significant gate current when pushed deep into compression. The LNA bias DAC also includes a disable mode with a high output impedance, which provides flexibility for self biased LNAs that also have an external gate voltage adjustment capability. The LNA_BIAS_ OUT_EN bit (Bit 4, Register 0x030) provides this control. 1.8V LDO If the values given Table 13 are used, the VGA exclusively executes the gain control in either the transmitter or receiver path. Register 0x010 to Register 0x013 and Register 0x01C to Register 0x01F control the receiver and transmitter VGAs, respectively. If using values not found in Table 13, be aware that both the vector modulator and the VGA affect the total gain. The total gain (in dB) (GAINTOTAL) is calculated by the following equation: 8 8-BIT DAC AMPLIFIER BIAS AVDD1 Figure 88. Simplified PA/LNA Bias DAC Schematic GAINTOTAL (dB) = GAINVM (dB) + GAINVGA (dB) where: GAINVM is the vector modulator gain. GAINVGA is the VGA gain from any of the transmitter and receiver paths. POWER DETECTORS Four power detectors (one per channel) are provided to sample peak power coupled from the outputs of off chip power amplifiers for power monitoring. The on-chip ADC selects from the four detectors and converts the output to an 8-bit digital word that is read back over the SPI. Figure 87 shows a simplified power detector schematic. Each detector input (detector input in Figure 87) is ac-coupled to a diode-based detector, and then amplified and routed to the ADC. A reference diode (not shown) provides temperature compensation to minimize variation in the output voltage vs. the input power response over the operating temperature range. The detector inputs are matched on chip to 50 . Register 0x030 contains an enable bit (CHx_DET_EN) for each detector so that the detectors can be powered down when not in use. 50 TO ADC 16790-080 DETECTOR INPUT FROM SPI 16790-081 In general, select the VQ and VI values to give the desired phase shift while minimizing the variation in VOUT (gain). However, allowing some amplitude variation can result in finer phase step resolution and/or lower phase errors. Figure 87. Simplified Power Detector Schematic EXTERNAL AMPLIFIER BIAS DACs Five on-chip DACs are provided for off chip biasing of gallium arsenide (GaAs) or gallium nitride (GaN) PAs. One DAC is intended for each of the four off chip Pas, and the fifth DAC is shared between the four off chip LNAs. Figure 88 shows a simplified schematic for the bias DACs. An 8-bit word from the Two SPI registers are associated with each bias DAC, an on register (Register 0x029 through Register 0x02D) for setting the bias voltage for the amplifier when active, and an off register (Register 0x046 through Register 0x04A) for setting the appropriate voltage for turning the amplifier bias off. The BIAS_CTRL bit (Bit 6, Register 0x030) determines whether the DAC outputs must be changed by loading the new settings over the SPI each time, whether the outputs switch between the on and off registers with the TX_EN or RX_EN signal (SPI transmit and receive mode) or with the state of the external transmit and receive pin. All 0s correspond to a 0 V output, and all 1s correspond to a -4.8 V output. EXTERNAL SWITCH CONTROL The chip provides two driver outputs for external GaAs switch control: one (TR_SW_NEG) for an external transmit and receive switch, and the other (TR_POL) for a polarization switch. Figure 89 shows a simplified schematic of the TR_SW_NEG and TR_POL switch driver. The switch driver outputs between 0 V and AVDD1 (nominally -5 V). A push pull output stage allows sourcing or sinking of up to 1 mA. The chip also provides a third driver output, TR_SW_POS (see Figure 90), to drive a transmit/receive switch requiring a positive control voltage. TR_SW_POS outputs between 0 V and AVDD3 (nominally 3.3 V). The external transmit and receive switch driver outputs change state along with the on-chip transmit and receive switches via the transmit and receive control signal (either through the SPI or the TR pin). Register 0x031 (SW_CTRL) contains all the control bits required for both switch drivers. The polarity of the transmit and receive switch driver output with respect to the transmit and receive control signal is set via the SW_DRV_ TR_STATE bit (Bit 7, Register 0x031) to provide flexibility for different GaAs switches. The external polarization switch changes with the state of the POL bit (Bit 0, Register 0x031). Write a high to the SW_DRV_EN_TR and SW_DRV_EN_POL bits (Bits[4:3], Register 0x031) to enable the switch drivers. Rev. A | Page 25 of 65 ADAR1000 Data Sheet 1.8V LDO switches, enabling the receive or transmit subcircuits, as well as turning on and off the gate bias for the external PAs and LNAs if the BIAS_CTRL bit (Bit 6, Register 0x030) is high. SWITCH DRIVER OUTPUT RF SUBCIRCUIT BIAS CONTROL AND ENABLES Use Register 0x034 through Register 0x037 to adjust the bias current setting of each of the active RF subcircuits to trade RF performance for lower dc power. Table 6 provides the recommended settings for the nominal and low operating power modes. The nominal power mode provides the highest performance. When reducing dc power for power sensitive applications, this power reduction is at the expense of lower gain, higher noise figure, and lower linearity. 16790-082 FROM SPI AVDD1 Figure 89. TR_SW_NEG and TR_POL Switch Driver AVDD3 TR_SW_POS 16790-083 FROM SPI Figure 90. TR_SW_POS Switch Driver TRANSMIT AND RECEIVE CONTROL Properly transitioning from transmit mode to receive mode, and vice versa, is key to operating a TDD or radar phased array system. The ADAR1000 performs the transmitter to receiver and receiver to transmitter functionality based on a transmit and receive control signal input to the chip. Mode transition can be accomplished through either a SPI register write or via the digital transmit and receive input pin of the chip. When using the SPI, all of the controls required to change the transmit and receive state are contained in Register 0x031, so that the transition is made using a single register write. First, the TR_SOURCE bit (Bit 2, Register 0x031) determines whether the SPI (low) or the TR pin (high) is used for transmit and receive control. When the SPI is used, the TR_SPI bit (Bit 1, Register 0x031) determines receive (low) or transmit (high) mode. The TX_EN and RX_EN bit (Bits[6:5], Register 0x031) must also be active to turn on the receive or transmit subcircuits for the applicable mode, as well as to turn on or off the gate bias for the external PAs and LNAs if the BIAS_CTRL bit (Bit 6, Register 0x030) is high. Register 0x031 also controls the external switch drivers as previously described in the External Switch Control section. When the TR_SOURCE bit (Bit 2, Register 0x031) is high, the transmit and receive pin controls all operation necessary to switch from receive to transmit and vice versa. This operation includes setting the on-chip and off chip transmit and receive The RF subcircuits are powered down when not in use. When using the SPI for transmit and receive control, RF subcircuits and/or channels can be individually enabled via Register 0x02E (receive channel enables) and Register 0x02F (transmit channel enables). The TX_EN and RX_EN bits (Bits[6:5], Register 0x031) must also be at logic high to enable the transmit or receive subcircuits, respectively. The transmit and receive subcircuits cannot be turned on simultaneously, and if both TX_EN and RX_EN are high, both the transmit and receive subcircuits power down. If using the transmit and receive pin for transmit and receive control, the functions of the TX_EN and RX_EN automatically follow the state of the transmit and receive input, allowing fast switching between transmit and receive modes. ADC OPERATION The chip contains an 8-bit ADC for sampling the outputs of the four power detectors and the temperature sensor. Register 0x032 controls the ADC. The ADC_CLKFREQ_SEL (Bit 7, Register 0x032) selects between a 2 MHz or a 250 kHz clock frequency. The ADC_EN and CLK_EN bits (Bits[6:5], Register 0x032) allow the ADC to be powered down when not in use. The ST_CONV bit (Bit 4, Register 0x032) initiates a conversion, which requires 16 clock cycles for a minimum conversion time of 8 s (2 MHz clock). The ADC_EOC (Bit 0, Register 0x032) read bit indicates when a conversion is complete and the 8-bit output is available for reading over the SPI. A mux selects between the five inputs based on the MUX_SEL bits (Bits[3:1], Register 0x032). The 8-bit output is read from Register 0x033 (ADC_OUTPUT). Table 6. SPI Settings for Different Power Modes Subcircuit Receive LNA Receive Vector Modulator Receive VGA Transmit Vector Modulator Transmit VGA Transmit Driver Register (Hexidecimal) 0x034 0x035 0x035 0x036 0x036 0x037 Bits Bits[3:0] Bits[2:0] Bits[6:3] Bits[2:0] Bits[6:3] Bits[2:0] Rev. A | Page 26 of 65 Bit Field LNA_BIAS RX_VM_BIAS RX_VGA_BIAS TX_VM_BIAS TX_VGA_BIAS TX_DRV_BIAS Bias Setting (Decimal) Nominal Low Power 8 5 5 2 10 3 5 2 5 5 6 3 Data Sheet ADAR1000 CHIP ADDRESSING Using the ADDR1 and ADDR0 pins to set the address of each individual chip, the user can connect the SCLK, CSB, SDIO, and SDO lines of up to four chips together. The ADDR1 and ADDR0 values correspond to the AD1 and AD0 bits (Bits[14:13] of the SPI address header) shown in Table 11, respectively. An example write to Chip 2 has the following address bit settings. For a group of four chips, indexed 0 to 3, ADDR1 is set to high and ADDR0 is set to low with the address header set to Bits[14:13] = 10. The user also has the option to write to all four chips with a single write by setting the address header Bits[14:11] = 0001. MEMORY ACCESS On-chip random access memory (RAM) is provided for storing phase and amplitude settings for up to 121 beam positions and seven bias settings for both transmit and receive modes, as shown in Table 11. A beam position consists of the gain, Vector Modulator I, and Vector Modulator Q settings for all four channels. Beam positions are stored in memory by writing to the 0x1000 through 0x1FFF locations. Beam positions are then loaded from memory by writing to Register 0x039 for the receive channels, and Register 0x03A for the transmit channels, which pulls the amplitude and phase setting for all four channels. Additionally, if the RX_CHX_RAM_BYPASS and TX_CHX_RAM_BYPASS bits (Bits[1:0], Register 0x038) are active, the amplitude and phase settings can be individually pulled for each receive or transmit channel, allowing even greater flexibility. In this case, the settings for each receive channel are loaded by writing to Register 0x03D through Register 0x040 and for each transmit channel by writing to Register 0x041 through Register 0x044. The BEAM_RAM_ BYPASS bit in Register 0x038 determines where the amplitude and phase settings are pulled from the memory (low) or written to over the SPI (high). Seven memory locations are also provided for storing bias settings for all the transmit and receive channel subcircuits, normally stored in Register 0x034 through Register 0x037. When the BIAS_RAM_BYPASS bit (Register 0x38, Bit 5) is at logic low, the bias setting can be recalled from memory instead of from the SPI. Using Table 7, Table 8, Table 9, and Table 10 in conjunction with Table 11, the user can decode the receive beam position bits, transmit beam position bits, receive bias setting bits, and transmit receive bias setting bits that are located in the RAM. An example of writing gain, phase, and bias values to the memory is provided in Table 21 in the SPI Programming Example section. Additionally, the beam can be stepped sequentially through the positions stored in memory. To use this function, first load Register 0x04D through Register 0x04E with the transmit channel start and stop memory addresses, and Register 0x04F through Register 0x050 with the receive channel start and stop memory addresses. Then, apply six serial clock pulses followed by a pulse to the TX_LOAD or RX_LOAD input for recalling memory for the transmit or receive channels, respectively. Channel settings are loaded sequentially from memory by repeatedly applying the serial clock pulses plus TX_LOAD or RX_LOAD. This mode eliminates the need for a SPI register write to load the next beam position, resulting in faster beam transitions. An example of this operation is shown in Figure 69. CALIBRATION There is no built in calibration or factory calibration for the magnitude and phase of each gain and phase of the RF channel. The rms phase error resulting from using the I and Q settings is determined from the equations previously provided in the Phase and Gain Control section. The rms phase error can be improved by running a full over the air active electronically scanned array (AESA) calibration of each channel at the desired frequency operation. Rev. A | Page 27 of 65 ADAR1000 Data Sheet Table 7. Beam Position Vector Modulator (VM) and VGA Decoding for Receiver and Transmitter Channel 1 to Channel 4 Bits[23:22] Don't care Bit 21 VM Q polarity Bits[20:16] VM Q gain Bits[15:14] Don't care Bit 13 VM I polarity Bits[12:8] VM I gain Bit 7 Attenuator Bits[6:0] VGA gain Table 8. Receiver Bias Setting Decoding Bits[31:28] Don't care Bits[27:23] LNA bias Bits[22:20] VM bias Bits[19:16] VGA bias Bits[15:8] External LNA bias on Bits[7:0] External LNA bias off Table 9. Transmitter Bias Setting Decoding for Bits[63:0] Bits[63:56] External PA 4 bias On Bits[55:48] External PA 4 bias off Bits[47:40] External PA 3 bias on Bits[39:32] External PA 2 bias on Bits[31:24] External PA 1 bias on Bits[23:16] External PA 3 bias off Bits[15:8] External PA 2 bias off Bits[7:0] External PA 1 bias off Table 10. Transmitter Bias Setting Decoding for Bits[74:64] Bits[79:75] Don't care Bits[74:72] Driver bias Bits[70:68] VM bias Bits[67:64] VGA bias Table 11. Control Register Address and SPI Beam Memory Address Map 14 AD1 13 AD0 12 0 11 0 10 0 SPI Address 9 8 7 6 0 0 0 0 AD1 ... AD0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 .... AD1 AD0 0 1 1 1 1 1 1 1 1 1 1 1 1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5 0 4 0 3 0 2 0 1 0 0 0 Rev. A | Page 28 of 65 Function Addresses with Bit 12 equal to 0 point to the control registers described in the Register Map section Control register locations Range of addresses pointing to additional control register locations Control register locations Addresses with Bit 12 equal to 1 point to the memory area for storing the beam settings at each location Receive Channel 1 Beam Position 0, Bits[7:0] Receive Channel 1 Beam Position 0, Bits[15:8] Receive Channel 1 Beam Position 0, Bits[23:16] Not applicable Receive Channel 2 Beam Position 0, Bits[7:0] Receive Channel 2 Beam Position 0, Bits[15:8] Receive Channel 2 Beam Position 0, Bits[23:16] Not applicable Receive Channel 3 Beam Position 0, Bits[7:0] Receive Channel 3 Beam Position 0, Bits[15:8] Receive Channel 3 Beam Position 0, Bits[23:16] Not applicable Receive Channel 4 Beam Position 0, Bits[7:0] Receive Channel 4 Beam Position 0, Bits[15:8] Receive Channel 4 Beam Position 0, Bits[23:16] Not applicable Receive Channel 1 Beam Position 1, Bits[7:0] Receive Channel 1 Beam Position 1, Bits[15:8] Receive Channel 1 Beam Position 1, Bits[23:16] Not applicable Receive Channel 2 Beam Position 1, Bits[7:0] Receive Channel 2 Beam Position 1, Bits[15:8] Receive Channel 2 Beam Position 1, Bits[23:16] Not applicable Receive Channel 3 Beam Position 1, Bits[7:0] Receive Channel 3 Beam Position 1, Bits[15:8] Receive Channel 3 Beam Position 1, Bits[23:16] Not applicable Data Sheet ADAR1000 14 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 ... 13 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 ... 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPI Address 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ... 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev. A | Page 29 of 65 Function Receive Channel 4 Beam Position 1, Bits[7:0] Receive Channel 4 Beam Position 1, Bits[15:8] Receive Channel 4 Beam Position 1, Bits[23:16] Not applicable Receive Channel 1 Beam Position 2, Bits[7:0] Receive Channel 1 Beam Position 2, Bits[15:8] Receive Channel 1 Beam Position 2, Bits[23:16] Not applicable Receive Channel 2 Beam Position 2, Bits[7:0] Receive Channel 2 Beam Position 2, Bits[15:8] Receive Channel 2 Beam Position 2, Bits[23:16] Not applicable Receive Channel 3 Beam Position 2, Bits[7:0] Receive Channel 3 Beam Position 2, Bits[15:8] Receive Channel 3 Beam Position 2, Bits[23:16] Not applicable Receive Channel 4 Beam Position 2, Bits[7:0] Receive Channel 4 Beam Position 2, Bits[15:8] Receive Channel 4 Beam Position 2, Bits[23:16] Not applicable Range of addresses pointing to additional receive beam positions Receive Channel 1 Beam Position 121, Bits[7:0] Receive Channel 1 Beam Position 121, Bits[15:8] Receive Channel 1 Beam Position 121, Bits[23:16] Not applicable Receive Channel 2 Beam Position 121, Bits[7:0] Receive Channel 2 Beam Position 121, Bits[15:8] Receive Channel 2 Beam Position 121, Bits[23:16] Not applicable Receive Channel 3 Beam Position 121, Bits[7:0] Receive Channel 3 Beam Position 121, Bits[15:8] Receive Channel 3 Beam Position 121, Bits[23:16] Not applicable Receive Channel 4 Beam Position 121, Bits[7:0] Receive Channel 4 Beam Position 121, Bits[15:8] Receive Channel 4 Beam Position 121, Bits[23:16] Not applicable Receive Bias Setting 1, Bits[7:0] Receive Bias Setting 1, Bits[15:8] Not applicable Not applicable Receive Bias Setting 1, Bits[23:16] Receive Bias Setting 1, Bits[31:24] Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable ADAR1000 Data Sheet 14 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 ... 13 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 ... 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI Address 8 7 6 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 ... ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ... 2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev. A | Page 30 of 65 Function Not applicable Not applicable Receive Bias Setting 2, Bits[7:0] Receive Bias Setting 2, Bits[15:8] Not applicable Not applicable Receive Bias Setting 2, Bits[23:16] Receive Bias Setting 2, Bits[31:24] Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Range of addresses pointing to additional receive bias settings Receive Bias Setting 7, Bits[7:0] Receive Bias Setting 7, Bits[15:8] Not applicable Not applicable Receive Bias Setting 7, Bits[23:16] Receive Bias Setting 7, Bits[31:24] Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Transmit Channel 1 Beam Position 0, Bits[7:0] Transmit Channel 1 Beam Position 0, Bits[15:8] Transmit Channel 1 Beam Position 0, Bits[23:16] Not applicable Transmit Channel 2 Beam Position 0, Bits[7:0] Transmit Channel 2 Beam Position 0, Bits[15:8] Transmit Channel 2 Beam Position 0, Bits[23:16] Not applicable Transmit Channel 3 Beam Position 0, Bits[7:0] Transmit Channel 3 Beam Position 0, Bits[15:8] Transmit Channel 3 Beam Position 0, Bits[23:16] Not applicable Transmit Channel 4 Beam Position 0, Bits[7:0] Transmit Channel 4 Beam Position 0, Bits[15:8] Transmit Channel 4 Beam Position 0, Bits[23:16] Not applicable Data Sheet ADAR1000 14 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 ... 13 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 ... 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPI Address 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ... 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev. A | Page 31 of 65 Function Transmit Channel 1 Beam Position 1, Bits[7:0] Transmit Channel 1 Beam Position 1, Bits[15:8] Transmit Channel 1 Beam Position 1, Bits[23:16] Not applicable Transmit Channel 2 Beam Position 1, Bits[7:0] Transmit Channel 2 Beam Position 1, Bits[15:8] Transmit Channel 2 Beam Position 1, Bits[23:16] Not applicable Transmit Channel 3 Beam Position 1, Bits[7:0] Transmit Channel 3 Beam Position 1, Bits[15:8] Transmit Channel 3 Beam Position 1, Bits[23:16] Not applicable Transmit Channel 4 Beam Position 1, Bits[7:0] Transmit Channel 4 Beam Position 1, Bits[15:8] Transmit Channel 4 Beam Position 1, Bits[23:16] Not applicable Range of addresses pointing to additional transmit beam positions Transmit Channel 1 Beam Position 121, Bits[7:0] Transmit Channel 1 Beam Position 121, Bits[15:8] Transmit Channel 1 Beam Position 121, Bits[23:16] Not applicable Transmit Channel 2 Beam Position 121, Bits[7:0] Transmit Channel 2 Beam Position 121, Bits[15:8] Transmit Channel 2 Beam Position 121, Bits[23:16] Not applicable Transmit Channel 3 Beam Position 121, Bits[7:0] Transmit Channel 3 Beam Position 121, Bits[15:8] Transmit Channel 3 Beam Position 121, Bits[23:16] Not applicable Transmit Channel 4 Beam Position 121, Bits[7:0] Transmit Channel 4 Beam Position 121, Bits[15:8] Transmit Channel 4 Beam Position 121, Bits[23:16] Not applicable Transmit Bias Setting 1, Bits[7:0] Transmit Bias Setting 1, Bits[15:8] Transmit Bias Setting 1, Bits[23:16] Not applicable Transmit Bias Setting 1, Bits[31:24] Transmit Bias Setting 1, Bits[39:32] Transmit Bias Setting 1, Bits[47:40] Not applicable Transmit Bias Setting 1, Bits[55:48] Transmit Bias Setting 1, Bits[63:56] Not applicable Not applicable Transmit Bias Setting 1, Bits[71:64] Transmit Bias Setting 1, Bits[79:72] Not applicable Not applicable Transmit Bias Setting 2, Bits[7:0] Transmit Bias Setting 2, Bits[15:8] ADAR1000 Data Sheet 14 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 ... 13 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 ... 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPI Address 8 7 6 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 ... ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ... 2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev. A | Page 32 of 65 Function Transmit Bias Setting 2, Bits[23:16] Not applicable Transmit Bias Setting 2, Bits[31:24] Transmit Bias Setting 2, Bits[39:32] Transmit Bias Setting 2, Bits[47:40] Not applicable Transmit Bias Setting 2, Bits[55:48] Transmit Bias Setting 2, Bits[63:56] Not applicable Not applicable Transmit Bias Setting 2, Bits[71:64] Transmit Bias Setting 2, Bits[79:72] Not applicable Not applicable Range of addresses pointing to additional receive bias settings Transmit Bias Setting 7, Bits[7:0] Transmit Bias Setting 7, Bits[15:8] Transmit Bias Setting 7, Bits[23:16] Not applicable Transmit Bias Setting 7, Bits[31:24] Transmit Bias Setting 7, Bits[39:32] Transmit Bias Setting 7, Bits[47:40] Not applicable Transmit Bias Setting 7, Bits[55:48] Transmit Bias Setting 7, Bits[63:56] Not applicable Not applicable Transmit Bias Setting 7, Bits[71:64] Transmit Bias Setting 7, Bits[79:72] Not applicable Not applicable Data Sheet ADAR1000 Gain control for each channel is provided through a combination of independent receive and transmit path VGAs, which provide over 16 dB of gain control range, and a switched 0 dB or 15 dB step attenuator that is shared between the transmit and receive channels. The resulting combined gain control range exceeds 31 dB. The gain of each receive or transmit channel is controlled by an 8-bit register. The VGAs require seven bits of control to ensure a 0.5 dB minimum step size with less than 0.25 dB error over all conditions, and the eighth bit controls the state of the switched attenuator. To update the amplitude and phase settings, load the new settings over the SPI or from the on-chip memory. When updating the amplitude and phase setting over the SPI, write the new values to Register 0x010 through Register 0x01B to set the receive channel gains and phases, and to Register 0x01C through Register 0x027 to set the transmit channel gains and phases. These gain and phase settings are initially written to holding registers, and do not take effect until a positive pulse occurs on either the LDRX_OVERRIDE bit for the receive channel, or the LDTX_OVERRIDE bit for the transmit channel (Bit 0 and Bit 1, respectively, of Register 0x028). This positive pulse transfers the new settings from the holding registers to the working registers, causing the new settings to take effect in the RF subcircuits. This transfer can also be done by sending positive pulses to the RX_LOAD or TX_LOAD pin for the receive and transmit channels, respectively. This arrangement allows the chip to actively receive or transmit using one amplitude and phase setting while loading the next setting in the background. The state of the switched attenuator also depends upon the transmit and receive control signal because the attenuator is shared between the transmit and the receive paths. Additionally, the BEAM_RAM_BYPASS bit (Bit 6 of Register 0x038) must be high for loading amplitude and phase settings over the SPI. Alternatively, up to 121 gain and amplitude settings for both the receive and the transmit modes can be stored in the on-chip memory and then recalled by writing to Register 0x039 for the receive mode, and Register 0x03A for the transmit mode. When loading new settings over the SPI, the new settings loaded from memory do not take effect until the appropriate load command is sent. The gain control registers for the receive channels are Register 0x010 through Register 0x013, and the gain control registers for the transmit channels are Register 0x01C through Register 0x01F. Bits[6:0] (RX_VGA_CHx and TX_VGA_CHx) of each register control the VGA gain approximately as shown in Figure 91. Limit the usage to the top 16 dB of the gain control range for optimal gain linearity and repeatability. Bit 7 (CHx_ATTN_RX and CHx_ATTN_TX) of each register controls the attenuator state (logic high means attenuator is bypassed). 2 0 -2 -4 -6 -8 -10 -12 INTENDED OPERATING RANGE -14 -16 -18 -20 -22 9.5GHz, ATTENUATION = 1 11.5GHz, ATTENUATION = 1 14.0GHz, ATTENUATION = 1 -24 -26 0 10 20 30 40 50 60 70 80 90 100 110 120 130 7-BIT GAIN CONTROL CODE 16790-084 GAIN CONTROL REGISTERS NORMALIZED GAIN (dB) APPLICATIONS INFORMATION Figure 91. Normalized Gain vs. 7-Bit Gain Control Code The TX_LOAD and RX_LOAD pins, or alternatively the LDTX_OVERRIDE and LDRX_OVERRIDE bits (Bits[1:0], Register 0x028, respectively), must be pulsed for new settings to take effect. New settings can be loaded in the background while transmitting and receiving using the current settings. SWITCHED ATTENUATOR CONTROL The CHx_ATTN_RX bit (Bit 7) of Register 0x010 through Register 0x013 control the receive step attenuators. The CHx_ATTN_TX bit (Bit 7) of Register 0x01C to Register 0x01F control the transmit step attenuators. A multiplexer (mux) determines whether the attenuator for each channel is set according to the receive or transmit working registers as shown in Table 12. Table 12. Step Attenuator Control Channel Transmit and Receive State Receive Receive Transmit Transmit 1 2 CHx_ATTN_RX 1 1 0 X2 X2 From SPI, x = 1, 2, 3, or 4. X means don't care. Rev. A | Page 33 of 65 CHx_ATTN_TX1 X2 X2 1 0 Channel x Attenuator State1 Bypass Attenuation Bypass Attenuation ADAR1000 Data Sheet Phase is determined by setting the I and Q VGA gains of the vector modulator(s). The phase control registers for the receiver channels are Register 0x14 through Register 0x1B. The phase control registers for the transmitter channels are Register 0x020 through Register 0x027. Each register controls the gain of I or Q VGA and the polarity bit to determine the quadrant of the resultant vector. See Figure 86 in the Phase and Gain Control section. Table 13 maps the user desired phase to data of several phase control registers. I Reg represents Register Bits[5:0], which includes the I polarity Bit 5 and the VM I Gain Bits[4:0]. Q Reg represents Bits[5:0], which includes the Q polarity Bit 5 and the VM Q Gain Bits[4:0]. Table 13. Quadrant 1 Phase Control--Mapping of I and Q VM VGA Register Settings to Phase Setting Table 14. Quadrant 2 Phase Control--Mapping of I and Q VM VGA Register Settings to Phase Setting Phase (Degrees) 0 2.8125 5.625 8.4375 11.25 14.0625 16.875 19.6875 22.5 25.3125 28.125 30.9375 33.75 36.5625 39.375 42.1875 45 47.8125 50.625 53.4375 56.25 59.0625 61.875 64.6875 67.5 70.3125 73.125 75.9375 78.75 81.5625 84.375 87.1875 Phase (Degrees) 90 92.8125 95.625 98.4375 101.25 104.0625 106.875 109.6875 112.5 115.3125 118.125 120.9375 123.75 126.5625 129.375 132.1875 135 137.8125 140.625 143.4375 146.25 149.0625 151.875 154.6875 157.5 160.3125 163.125 165.9375 168.75 171.5625 174.375 177.1875 PHASE CONTROL REGISTERS I Reg (Hex) 0x3F 0x3F 0x3F 0x3F 0x3F 0x3E 0x3E 0x3D 0x3D 0x3C 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x30 0x2F 0x2E 0x2C 0x2B 0x2A 0x28 0x27 0x25 0x24 0x22 Q Reg (Hex) 20 21 23 24 26 27 28 2A 2B 2D 2E 2F 30 31 33 34 35 36 37 38 38 39 3A 3A 3B 3C 3C 3C 3D 3D 3D 3D Rev. A | Page 34 of 65 I Reg (Hex) 21 01 03 04 06 07 08 0A 0B 0D 0E 0F 11 12 13 14 16 17 18 19 19 1A 1B 1C 1C 1D 1E 1E 1E 1F 1F 1F Q Reg (Hex) 3D 3D 3D 3D 3D 3C 3C 3C 3B 3A 3A 39 38 38 37 36 35 34 33 31 30 2F 2E 2D 2B 2A 28 27 26 24 23 21 Data Sheet ADAR1000 Table 15. Quadrant 3 Phase Control--Mapping of I and Q VM VGA Register Settings to Phase Setting Table 16. Quadrant 4 Phase Control--Mapping of I and Q VM VGA Register Settings to Phase Setting Phase (Degrees) 180 182.8125 185.625 188.4375 191.25 194.0625 196.875 199.6875 202.5 205.3125 208.125 210.9375 213.75 216.5625 219.375 222.1875 225 227.8125 230.625 233.4375 236.25 239.0625 241.875 244.6875 247.5 250.3125 253.125 255.9375 258.75 261.5625 264.375 267.1875 Phase (Degrees) 270 272.8125 275.625 278.4375 281.25 284.0625 286.875 289.6875 292.5 295.3125 298.125 300.9375 303.75 306.5625 309.375 312.1875 315 317.8125 320.625 323.4375 326.25 329.0625 331.875 334.6875 337.5 340.3125 343.125 345.9375 348.75 351.5625 354.375 357.1875 I Reg (Hex) 1F 1F 1F 1F 1F 1E 1E 1D 1D 1C 1C 1B 1A 19 18 17 16 15 14 13 12 10 0F 0E 0C 0B 0A 08 07 05 04 02 Q Reg (Hex) 20 01 03 04 06 07 08 0A 0B 0D 0E 0F 10 11 13 14 15 16 17 18 18 19 1A 1A 1B 1C 1C 1C 1D 1D 1D 1D Rev. A | Page 35 of 65 I Reg (Hex) 01 21 23 24 26 27 28 2A 2B 2D 2E 2F 31 32 33 34 36 37 38 39 39 3A 3B 3C 3C 3D 3E 3E 3E 3F 3F 3F Q Reg (Hex) 1D 1D 1D 1D 1D 1C 1C 1C 1B 1A 1A 19 18 18 17 16 15 14 13 11 10 0F 0E 0D 0B 0A 08 07 06 04 03 01 ADAR1000 Data Sheet TRANSMIT AND RECEIVE SUBCIRCUIT CONTROL The TR_SOURCE bit (Bit 2, Register 0x031) determines whether a dedicated input pin (TR pin) or the SPI registers controls the switching between transmit or receive modes for the ADAR1000. If the TR input is selected, the transmit and receive subcircuit enables are also controlled by the transmit and receive input. Any combination of receive subcircuits or transmit subcircuits can be turned on at a given time. Transmit and receive subcircuits cannot be turned on simultaneously. TR_SOURCE = 1 (TR Pin Control) When TR_SOURCE = 1, if the TR input is at logic low, the device goes into receive mode and all receive subcircuits are turned on. If the TR input is at logic high, the device goes into transmit mode, and all transmit subcircuits turn on. As a result, all transmit and receive switching functionality are completely controlled by a single pin. TR_SOURCE = 0 (SPI Control) Register 0x02E, Register 0x02F, and Register 0x031 of the SPI registers turn the transmit and receive subcircuits on and off together. Typical operating mode is to set all channel and subcircuit enables active (that is, set Register 0x02E to 0x7F and Register 0x02F to 0x7F), and then use TX_EN and RX_EN (Bits[6:5] of Register 0x31, respectively) to turn on either the transmit subcircuits or receive subcircuits. TRANSMIT AND RECEIVE SWITCH DRIVER CONTROL The TR_SW_NEG and TR_SW_POS pins are the output pins that control the external switches that determine the signal flow direction between the transmit and receive modes that the ADAR1000 operates in. Several register bits and the TR pin work together to provide different ways to control the state of the TR_SW_NEG and TR_SW_POS pins. To enable the switch drivers, set the SW_DRV_EN_TR bit (Bit 4, Register 0x031) to logic high. The TR_SOURCE bit (Bit 2, Register 0x031) determines whether transmit and receive control is done through the TR_SPI bit (Bit 1, Register 0x031) an SPI or the dedicated transmit, and receive input pin to the chip (if TR_SOURCE = 0, the TR_SPI bit is in control). The SW_DRV_TR_STATE bit (Bit 7, Register 0x031) determines the polarity of these switch driver outputs (TR_SW_POS and TR_SW_NEG) with respect to transmit and receive mode. Allowing the polarity to be programmable provides additional flexibility when using different transmit and receive switch control configurations (see Table 17). Table 17. Controlling TR_SW_POS and TR_SW_NEG Output SW_DRV_ EN_TR (Register 0x031, Bit 4) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TR_SOURCE (Register 0x031, Bit 2) 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TR (Chip Input)1 X X X X X 0 0 1 1 X X X X 0 0 1 1 TR_SPI (Register 0x031, Bit 1)1 X 0 0 1 1 X X X X 0 0 1 1 X X X X SW_DRV_TR_ MODE_SEL (Register 0x030, Bit 7)1 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X means don't care. Rev. A | Page 36 of 65 Device Transmit or Receive State1 X Receive Receive Transmit Transmit Receive Receive Transmit Transmit Receive Receive Transmit Transmit Receive Receive Transmit Transmit SW_DRV_ TR_STATE (Register 0x031, Bit 7)1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TR_SW_POS (Chip Output) Floating Floating Floating Floating Floating Floating Floating Floating Floating 0V 3.3 V 3.3 V 0V 0V 3.3 V 3.3 V 0V TR_SW_NEG (Chip Output) Floating 0V -5 V -5 V 0V 0V -5 V -5 V 0V Floating Floating Floating Floating Floating Floating Floating Floating Data Sheet ADAR1000 PA BIAS OUTPUT CONTROL The four PA bias output voltages are controlled by four separate DACs, which in turn are controlled by a combination of three bits from the SPI registers (BIAS_CTRL, TR_SOURCE, TX_EN), two input pins (TR and PA_ON), and the EXT_PAx_BIAS_ON (Register 0x029 to Register 0x02C) and EXT_PAx_BIAS_OFF (Register 0x046 to Register 0x049) bits (see Table 18). BIAS_CTRL determines if the bias DACs always use the CHx_PA_BIAS_ON value for each channel. TR_SOURCE determines whether switching between transmit and receive mode is controlled by the SPI register or the TR input. The PA_ON input determines whether to use the CHx_PA_BIAS_ON or CHx_PA_BIAS_OFF value when the ADAR1000 is in transmit mode and BIAS_CTRL is set to 1. LNA BIAS OUTPUT CONTROL The LNA_BIAS output voltage is controlled by a DAC which in turn is controlled by a combination of four bits in the SPI registers (LNA_BIAS_OUT_EN, BIAS_CTRL, TR_SOURCE, and RX_EN), the TR input pin, and the LNA_BIAS_ON and LNA_BIAS_OFF registers (Register 0x02D and Register 0x04A, respectively), as shown in Table 19. The LNA_BIAS output is only enabled if LNA_BIAS_OUT_EN = 1. Otherwise, the output is open. The output is set by the LNA_BIAS_ON register when the ADAR1000 is in receive mode and BIAS_CTRL is set to 1. TRANSMIT/RECEIVE DELAY CONTROL The delays between switching from transmitter-to-receiver and receiver-to-transmitter, Delay 1 and Delay 2, are controlled via Register 0x4B and Register 0x4C, respectively. The delay time is proportional to the SPI clock period. With a 50 ns clock period (20 MHz), the maximum value for either Delay 1 or Delay 2 is 750 ns. This delay value corresponds to a delay code of 15 or 0xF in either the top and/or bottom nibbles of Register 0x4B and Register 0x4C. A delay value of 0 corresponds to 0 ns delay, a delay value of 1 corresponds to 50 ns, a delay value of 2 corresponds to 100 ns, and so on. Table 18. Control of PA Bias Outputs BIAS_CTRL (Register 0x030, Bit 6) 0 1 1 1 1 1 1 TR_SOURCE (Register 0x031, Bit 2) X1 0 0 1 1 1 TX_EN (Register 0x031, Bit 6) X1 0 1 0 0 0 TR (Input to Chip) X1 X1 X1 0 1 1 PA_ON (Input to Chip) X1 X1 X1 X1 0 1 PA Bias Bits Used (x = 1, 2, 3, or 4) EXT_PAx_BIAS_ON EXT_PAx_BIAS_OFF EXT_PAx_BIAS_ON EXT_PAx_BIAS_OFF EXT_PAx_BIAS_OFF EXT_PAx_BIAS_ON X means don't care. Table 19. Control of LNA_BIAS Output LNA_BIAS_OUT_EN (Register 0x030, Bit 4) 0 1 1 1 1 1 1 1 1 1 BIAS_CTRL (Register 0x030, Bit 6) X1 0 0 1 1 0 0 1 1 TR_SOURCE (Register 0x031, Bit 2) X1 0 0 0 0 1 1 1 1 RX_EN (Register 0x031, Bit 5) X1 0 1 0 1 0 0 0 0 X means don't care. Rev. A | Page 37 of 65 TR (Input to Chip) X1 X1 X1 X1 X1 0 1 0 1 LNA Bias Bits Used Open circuit (floating) EXT_LNA_BIAS_ON EXT_LNA_BIAS_ON EXT_LNA_BIAS_OFF EXT_LNA_BIAS_ON EXT_LNA_BIAS_ON EXT_LNA_BIAS_ON EXT_LNA_BIAS_OFF EXT_LNA_BIAS_ON ADAR1000 Data Sheet Transmit and Receive Mode Switching Figure 92 shows the timing for transmit and receive mode switching. PA RAMP-DOWN LNA RAMP-UP LNA RAMP-DOWN PA RAMP-UP PA RAMP-DOWN PA PA TRANSMIT TRANSMIT RECEIVE LNA LNA TOGGLE TR INPUT RECEIVE DELAY 1 DELAY 2 REGISTER 0x04B TOGGLE TR INPUT DELAY 1 DELAY 2 REGISTER 0x04C PROGRAMMABLE DELAYS Figure 92. Timing for Transmit and Receive Mode Switching Rev. A | Page 38 of 65 TOGGLE TR INPUT DELAY 1 DELAY 2 REGISTER 0x04B 16790-085 INTERNAL DEVICE MODE Data Sheet ADAR1000 SPI PROGRAMMING EXAMPLE The SPI programming example in Table 20 sets up the bias of the different subcircuits, as well as the gain and phase settings of all channels. The device stays in the receive mode until the TR input is raised high, and the device switches into transmit mode. All the external amplifier bias and switches also change state accordingly. Table 20. Register Programing to Set Up the ADAR1000 Register Address 0x000 0x401 0x400 0x046 0x047 0x048 0x049 0x029 0x02A 0x02B 0x02C 0x02D 0x030 0x038 0x031 0x02F 0x036 0x037 0x01C 0x020 0x021 0x01D 0x020 0x 021 0x 01E 0x 020 0x 021 0x 01F 0x 020 0x 021 0x 02E 0x 034 0x 035 0x 010 0x 014 0x 015 0x 011 0x 016 0x 017 0x 012 0x 018 0x 019 0x 013 0x 01A 0x 01B Content (Hexadecimal) BD 10 55 60 60 60 60 28 28 28 28 28 1F 60 1C 7F 16 06 FF 36 35 FF 36 35 FF 36 35 FF 36 35 7F 08 16 FF 36 35 FF 36 35 FF 36 35 FF 36 35 Description Reset whole chip, use SDO line for readback, address auto incrementing in block write mode. Allow LDO adjustments from user settings. Adjust LDOs. Set PA_BIAS1 output to approximately -1.8 V in receive mode. Set PA_BIAS2 output to approximately -1.8 V in receive mode. Set PA_BIAS3 output to approximately -1.8 V in receive mode. Set PA_BIAS4 output to approximately -1.8 V in receive mode. Set PA_BIAS1 output to approximately -0.8 V in transmit mode. Set PA_BIAS2 output to approximately -0.8 V in transmit mode. Set PA_BIAS3 output to approximately -0.8 V in transmit mode. Set PA_BIAS4 output to approximately -0.8 V in transmit mode. Set LNA_BIAS to approximately -0.8 V. Enable LNA_BIAS, select fixed output. Select SPI instead of internal RAM for channel settings. Select TR input for transmit and receive switching control, enables switch outputs. Select all four transmit channel and enable transmit driver, vector modulator, and VGA. Set transmit VGA bias to 2, vector modulator bias to 6. Set transmit driver bias to 6. Set Channel 1 attenuator to 0 dB, VGA gain to maximum. Set Channel 1 vector modulator I input to positive, Magnitude 16. Set Channel 1 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45 Set Channel 2 attenuator to 0 dB, VGA gain to maximum. Set Channel 2 vector modulator I input to positive, Magnitude 16. Set Channel 2 vector modulator Q input to positive, magnitude 15; these two together set phase to 45. Set Channel 3 attenuator to 0 dB, VGA gain to maximum. Set Channel 3 vector modulator I input to positive, Magnitude 16. Set Channel 3 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45. Set Channel 4 attenuator to 0 dB, VGA gain to maximum. Set Channel 4 vector modulator I input to positive, Magnitude 16. Set Channel 4 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45. Select all four receive channel, enable receive LNA, vector modulator and VGA. Set receive LNA bias to 8. Set receive VGA bias to 2, vector modulator bias to 6. Set Channel 1 attenuator to 0 dB, VGA gain to maximum. Set Channel 1 vector modulator I input to positive, Magnitude 16. Set Channel 1 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45. Set Channel 2 attenuator to 0 dB, VGA gain to maximum. Set Channel 2 vector modulator I input to positive, Magnitude 16. Set Channel 2 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45. Set Channel 3 attenuator to 0 dB; VGA gain to maximum. Set Channel 3 vector modulator I input to positive, Magnitude 16. Set Channel 3 vector modulator Q input to positive, Magnitude 15; these two together set phase to 45. Set Channel 4 attenuator to 0 dB, VGA gain to maximum. Set Channel 4 vector modulator I input to positive, Magnitude 16. Set Channel 4 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45. Rev. A | Page 39 of 65 ADAR1000 Data Sheet Table 21. ADAR1000 Memory Register Programming Example for Beam Position 0 and Bias Setting 1 Register 1 0x038 0x1000 0x1001 0x1002 0x1004 0x1005 0x1006 0x1008 0x1009 0x100A 0x100C 0x100D 0x100E 0x1790 0x1791 0x1794 0x1795 0x1800 0x1801 0x1802 0x1804 0x1805 0x1806 0x1808 0x1809 0x180A 0x180C 0x180D 0x180E 0x1F90 0x1F91 0x1F92 0x1F94 0x1F95 0x1F96 0x1F98 0x1F99 0x1F9C 0x1F9D 0x39 Content 00 FF 36 35 FF 36 35 FF 36 35 FF 36 35 60 28 16 08 FF 36 35 FF 36 35 FF 36 35 FF 36 35 60 60 60 28 28 28 60 28 16 06 80 0x3A 80 0x51 0x52 08 08 1 Description Set beam ram bypass and bias ram bypass bits to load working registers from memory Set receiver VGA gain and attenuator values for Channel 1; VGA gain maximum, attenuator = 0 dB Set receiver I vector and polarity values for Channel 1; positive polarity, Magnitude = 16 Set receiver Q vector and polarity values for Channel 1; positive polarity, Magnitude = 15 Set receiver VGA gain and attenuator values for Channel 2; VGA gain maximum, attenuator = 0 dB Set receiver I vector and polarity values for Channel 2; positive polarity, Magnitude = 16 Set receiver Q vector and polarity values for Channel 2; positive polarity, Magnitude = 15 Set receiver VGA gain and attenuator values for Channel 3; VGA gain maximum, attenuator = 0 dB Set receiver I vector and polarity values for Channel 3; positive polarity, Magnitude = 16 Set receiver Q vector and polarity values for Channel 3; positive polarity, Magnitude = 15 Set receiver VGA gain and attenuator values for Channel 4; VGA gain maximum, attenuator = 0 dB Set receiver I vector and polarity values for Channel 4; positive polarity, Magnitude = 16 Set receiver Q vector and polarity values for Channel 4; positive polarity, Magnitude = 15 Set receiver EXT_LNA_BIAS_OFF value for receiver Bias Setting 1; -1.8 V output Set receiver EXT_LNA_BIAS_ON value for receiver Bias Setting 1; -0.8 V output Set receiver vector modulator and VGA bias values for receiver; VGA = 2, vector modulator = 6 Set receiver LNA bias value for receiver; LNA = 8 Set transmitter VGA gain and attenuator values for Channel 1 Set transmitter I vector and polarity values for Channel 1 Set transmitter Q vector and polarity values for Channel 1 Set transmitter VGA gain and attenuator values for Channel 2 Set transmitter I vector and polarity values for Channel 2 Set transmitter Q vector and polarity values for Channel 2 Set transmitter VGA gain and attenuator values for Channel 3 Set transmitter I vector and polarity values for Channel 3 Set transmitter Q vector and polarity values for Channel 3 Set transmitter VGA gain and attenuator values for Channel 4 Set transmitter I vector and polarity values for Channel 4 Set transmitter Q vector and polarity values for Channel 4 Set transmitter EXT_PA1_BIAS_OFF value for transmitter; -1.8 V output Set transmitter EXT_PA2_BIAS_OFF value for transmitter; -1.8 V output Set transmitter EXT_PA3_BIAS_OFF value for transmitter; -1.8 V output Set transmitter EXT_PA1_BIAS_ON value for transmitter; -0.8 V output Set transmitter EXT_PA2_BIAS_ON value for transmitter; -0.8 V output Set transmitter EXT_PA3_BIAS_ON value for transmitter; -0.8 V output Set transmitter EXT_PA4_BIAS_OFF value for transmitter; -1.8 V output Set transmitter EXT_PA4_BIAS_ON value for transmitter; -0.8 V output Set transmitter vector modulator and VGA bias values for transmitter; VGA bias = 2, vector modulator = 6 Set transmitter driver bias value for transmitter; driver = 6 Set all receiver channels to Beam Position 0 and set the fetch bit; the user can individually set the receiver channels using Register 0x03D through Register 0x040 Set all transmitter channels to Beam Position 0 and set the fetch bit; the user can individually set the transmitter channels using Register 0x041 through Register 0x044 Set receiver bias to Bias Setting 1 and set the fetch bit Set receiver bias to Bias Setting 1 and set the fetch bit Transmitter and receiver gain are set to maximum and the phase value is 45 for all channels. Refer to Table 7 through Table 11 for bit decoding and memory address values. Rev. A | Page 40 of 65 Data Sheet ADAR1000 POWERING THE ADAR1000 The ADAR1000 has two power supply domains, +3.3V and -5 V. These power supplies can be driven with the synchronous step down regulator LT8609S and the inverting dc to dc converter LT3462, respectively. With a single 5.5 V supply driving both the LT8609S and LT3462, the LT8609S generates the +3.3 V supply, while the LT3462 generates the -5 V supply. 2 3 4 16790-194 A single ADAR1000 is tested using the LT8609S and LT3462. Figure 93 and Figure 94 show the rise and fall times of the LNA_BIAS pin under a maximum load condition of -10 mA. Figure 95 and Figure 96 show the rise and fall times of all four PA_BIASx pins, each with a maximum load condition of -10 mA. A simplified block diagram of the test setup for the LT8609S and LT3462 is shown in Figure 97. 1 CH1 2.50V CH3 2.50V CH2 2.50V CH4 2.50V 0.0s A CH1 20.00ns/DIV -2.30V Figure 95. PA_BIAS1, PA_BIAS2, PA_BIAS3, or PA_BIAS 4 Rise Time; -10 mA load If more than two ADAR1000 devices must be powered, and if the user does not want multiple LT8609S and LT3462 devices, there are several solutions that power from four to 64 ADAR1000 devices by using a single chip per voltage supply. Table 22 shows these solutions by providing the quantity of ADAR1000 devices and the corresponding chips required to power multiple ADAR1000 devices. 1 2 3 16790-195 4 2 CH1 2.50V CH3 2.50V 1 CH2 2.50V CH4 2.50V 0.0s A CH1 20.00ns/DIV -2.30V Figure 96. PA_BIAS1, PA_BIAS2, PA_BIAS3, or PA_BIAS4 Fall Time; -10 mA Load 16790-192 POWER SUPPLY CH1 2.00V CH2 2.00V -20.00ns A CH1 20.00ns/DIV +5.5V +5.5V LT8609S LT3462 -2.30V Figure 93. LNA_BIAS Rise Time; -10 mA Load +3.3V -5V 16790-196 ADAR1000 Figure 97. Block Diagram of the LT8609S and the LT3462 Powering the ADAR1000 2 1 16790-193 Table 22. Power Solutions for Multiple ADAR1000 Devices CH1 2.00V CH2 2.00V -20.00ns A CH1 20.00ns/DIV ADAR1000 Quantity 4 16 32 64 -2.30V Figure 94. LNA_BIAS Fall Time; -10 mA load Rev. A | Page 41 of 65 Supplying +3.3 V LT8609S LT8642S LTC7151S LTM4636 Supplying -5 V LT1931 LT3580 LT3957A LT3757 ADAR1000 Data Sheet REGISTER MAP Table 23. Control Registers Summary Reg. (Hex) Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 000 INTERFACE_ CONFIG_A [7:0] SOFTRESET LSB_ FIRST ADDR_ ASCN SDO ACTIVE SDO ACTIVE_ ADDR_ ASCN_ LSB_FIRST_ SOFTRESET_ 0x00 R/W 001 INTERFACE_ CONFIG_B [7:0] SINGLE_ INSTRUCTION CSB_ STALL MASTER_ SLAVE_RB SLOW_ INTER FACE_ CTRL RESERVED RESERVED 0x00 R/W 002 DEV_CONFIG [7:0] 0x10 R/W 003 CHIP_TYPE [7:0] CHIP_TYPE 0x00 R 004 PRODUCT_ID_H [7:0] PRODUCT_ID[15:8] 0x00 R 005 PRODUCT_ID_L [7:0] PRODUCT_ID[7:0] 0x00 R 00A SCRATCH_PAD [7:0] SCRATCHPAD 0x00 R/W 00B SPI_REV [7:0] SPI_REV 0x00 R 00C VENDOR_ID_H [7:0] VENDOR_ID[15:8] 0x00 R 00D VENDOR_ID_L [7:0] VENDOR_ID[7:0] 0x00 R 00F TRANSFER_REG [7:0] 0x00 R/W 010 CH1_RX_GAIN [7:0] CH1_ATTN_RX RX_VGA_CH1 0x00 R/W 011 CH2_RX_GAIN [7:0] CH2_ATTN_RX RX_VGA_CH2 0x00 R/W 012 CH3_RX_GAIN [7:0] CH3_ATTN_RX RX_VGA_CH3 0x00 R/W 013 CH4_RX_GAIN [7:0] CH4_ATTN_RX RX_VGA_CH4 0x00 R/W 014 CH1_RX_PHASE_I [7:0] RESERVED RX_VM_ CH1_POL_I RX_VM_CH1_GAIN_I 0x00 R/W 015 CH1_RX_PHASE_Q [7:0] RESERVED RX_VM_ CH1_ POL_Q RX_VM_CH1_GAIN_Q 0x00 R/W 016 CH2_RX_PHASE_I [7:0] RESERVED RX_VM_ CH2_ POL_I RX_VM_CH2_GAIN_I 0x00 R/W 017 CH2_RX_PHASE_Q [7:0] RESERVED RX_VM_ CH2_ POL_Q RX_VM_CH2_GAIN_Q 0x00 R/W 018 CH3_RX_PHASE_I [7:0] RESERVED RX_VM_ CH3_ POL_I RX_VM_CH3_GAIN_I 0x00 R/W 019 CH3_RX_PHASE_Q [7:0] RESERVED RX_VM_ CH3_ POL_Q RX_VM_CH3_GAIN_Q 0x00 R/W 01A CH4_RX_PHASE_I [7:0] RESERVED RX_VM_ CH4_ POL_I RX_VM_CH4_GAIN_I 0x00 R/W 01B CH4_RX_PHASE_Q [7:0] RESERVED RX_VM_ CH4_ POL_Q RX_VM_CH4_GAIN_Q 0x00 R/W 01C CH1_TX_GAIN [7:0] CH1_ATTN_TX TX_VGA_CH1 0x00 R/W 01D CH2_TX_GAIN [7:0] CH2_ATTN_TX TX_VGA_CH2 0x00 R/W 01E CH3_TX_GAIN [7:0] CH3_ATTN_TX TX_VGA_CH3 0x00 R/W 01F CH4_TX_GAIN [7:0] CH4_ATTN_TX TX_VGA_CH4 0x00 R/W 020 CH1_TX_PHASE_I [7:0] RESERVED TX_VM_ CH1_POL_I TX_VM_CH1_GAIN_I 0x00 R/W 021 CH1_TX_PHASE_Q [7:0] RESERVED TX_VM_ CH1_ POL_Q TX_VM_CH1_GAIN_Q 0x00 R/W 022 CH2_TX_PHASE_I [7:0] RESERVED TX_VM_ CH2_ POL_I TX_VM_CH2_GAIN_I 0x00 R/W SOFT_RESET CUST_OPERATING_ MODE DEV_STATUS MASTER_ SLAVE_XFER RESERVED Rev. A | Page 42 of 65 NORM_ OPERATING_MODE Data Sheet ADAR1000 Reg. (Hex) Name Bits 023 CH2_TX_PHASE_Q [7:0] RESERVED TX_VM_ CH2_ POL_Q 024 CH3_TX_PHASE_I [7:0] RESERVED 025 CH3_TX_PHASE_Q [7:0] 026 CH4_TX_PHASE_I 027 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reset R/W TX_VM_CH2_GAIN_Q 0x00 R/W TX_VM_ CH3_ POL_I TX_VM_CH3_GAIN_I 0x00 R/W RESERVED TX_VM_ CH3_ POL_Q TX_VM_CH3_GAIN_Q 0x00 R/W [7:0] RESERVED TX_VM_ CH4_ POL_I TX_VM_CH4_GAIN_I 0x00 R/W CH4_TX_PHASE_Q [7:0] RESERVED TX_VM_ CH4_ POL_Q TX_VM_CH4_GAIN_Q 0x00 R/W 028 LD_WRK_REGS [7:0] 0x00 W 029 CH1_PA_BIAS_ON [7:0] EXT_PA1_BIAS_ON 0x00 R/W 02A CH2_PA_BIAS_ON [7:0] EXT_PA2_BIAS_ON 0x00 R/W 02B CH3_PA_BIAS_ON [7:0] EXT_PA3_BIAS_ON 0x00 R/W 02C CH4_PA_BIAS_ON [7:0] EXT_PA4_BIAS_ON 0x00 R/W 02D LNA_BIAS_ON [7:0] EXT_LNA_BIAS_ON 0x00 R/W 02E RX_ENABLES [7:0] RESERVED CH1_ RX_EN CH2_ RX_EN CH3_ RX_EN CH4_ RX_EN RX_ LNA_EN RX_ VM_EN RX_VGA_EN 0x00 R/W 02F TX_ENABLES [7:0] RESERVED CH1_ TX_EN CH2_ TX_EN CH3_ TX_EN CH4_ TX_EN TX_ DRV_EN TX_ VM_EN TX_VGA_EN 0x00 R/W 030 MISC_ENABLES [7:0] SW_DRV_ TR_MODE_SEL BIAS_ CTRL BIAS_EN LNA_ BIAS_ OUT_EN CH1_ DET_EN CH2_ DET_EN CH3_ DET_EN CH4_ DET_EN 0x00 R/W 031 SW_CTRL [7:0] SW_DRV_ TR_STATE TX_EN RX_EN SW_DRV_ EN_TR SW_DRV_ EN_POL TR_ SOURCE TR_SPI POL 0x00 R/W 032 ADC_CTRL [7:0] ADC_ CLKFREQ_SEL ADC_ EN CLK_EN ST_CONV ADC_EOC 0x00 R/W 033 ADC_OUTPUT [7:0] 034 BIAS_CURRENT_ RX_LNA [7:0] 035 BIAS_CURRENT_ RX [7:0] RESERVED RX_VGA_BIAS 036 BIAS_CURRENT_ TX [7:0] RESERVED TX_VGA_BIAS 037 BIAS_CURRENT_ TX_DRV [7:0] 038 MEM_CTRL [7:0] SCAN_ MODE_EN 039 RX_CHX_MEM [7:0] RX_CHX_ RAM_FETCH 03A TX_CHX_MEM [7:0] 03D RX_CH1_MEM 03E LDTX_ OVERRIDE RESERVED MUX_SEL Bit 0 LDRX_ OVERRIDE ADC 0x00 R 0x00 R/W RX_VM_BIAS 0x00 R/W TX_VM_BIAS 0x00 R/W TX_DRV_BIAS 0x00 R/W 0x00 R/W RX_CHX_RAM_INDEX 0x00 R/W TX_CHX_ RAM_FETCH TX_CHX_RAM_INDEX 0x00 R/W [7:0] RX_CH1_ RAM_FETCH RX_CH1_RAM_INDEX 0x00 R/W RX_CH2_MEM [7:0] RX_CH2_RAM_ FETCH RX_CH2_RAM_INDEX 0x00 R/W 03F RX_CH3_MEM [7:0] RX_CH3_RAM_ FETCH RX_CH3_RAM_INDEX 0x00 R/W 040 RX_CH4_MEM [7:0] RX_CH4_ RAM_FETCH RX_CH4_RAM_INDEX 0x00 R/W 041 TX_CH1_MEM [7:0] TX_CH1_ RAM_FETCH TX_CH1_RAM_INDEX 0x00 R/W 042 TX_CH2_MEM [7:0] TX_CH2_ RAM_FETCH TX_CH2_RAM_INDEX 0x00 R/W RESERVED LNA_BIAS RESERVED BEAM_ RAM_ BYPASS BIAS_ RAM_ BYPASS RESERVED Rev. A | Page 43 of 65 TX_BEAM_ STEP_EN RX_ BEAM_ STEP_ EN TX_CHX_ RAM_ BYPASS RX_CHX_ RAM_ BYPASS ADAR1000 Data Sheet Reg. (Hex) Name Bits Bit 7 043 TX_CH3_MEM [7:0] TX_CH3_ RAM_FETCH 044 TX_CH4_MEM [7:0] TX_CH4_ RAM_FETCH 045 REV_ID [7:0] 046 CH1_PA_BIAS_OFF [7:0] 047 CH2_PA_BIAS_OFF [7:0] 048 CH3_PA_BIAS_OFF [7:0] 049 CH4_PA_BIAS_OFF 04A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W TX_CH3_RAM_INDEX 0x00 R/W TX_CH4_RAM_INDEX 0x00 R/W REV_ID 0x00 R EXT_PA1_BIAS_OFF 0x00 R/W EXT_PA2_BIAS_OFF 0x00 R/W EXT_PA3_BIAS_OFF 0x00 R/W [7:0] EXT_PA4_BIAS_OFF 0x00 R/W LNA_BIAS_OFF [7:0] EXT_LNA_BIAS_OFF 0x00 R/W 04B TX_TO_RX_ DELAY_CTRL [7:0] TX_TO_RX_DELAY_1 TX_TO_RX_DELAY_2 0x00 R/W 04C RX_TO_ TX_DELAY_CTRL [7:0] RX_TO_TX_DELAY_1 RX_TO_TX_DELAY_2 0x00 R/W 04D TX_BEAM_ STEP_START [7:0] TX_BEAM_STEP_START 0x00 R/W 04E TX_BEAM_ STEP_STOP [7:0] TX_BEAM_STEP_STOP 0x00 R/W 04F RX_BEAM_ STEP_START [7:0] RX_BEAM_STEP_START 0x00 R/W 050 RX_BEAM_ STEP_STOP [7:0] RX_BEAM_STEP_STOP 0x00 R/W 051 RX_BIAS_RAM_CTL [7:0] RESERVED RX_BIAS_ RAM_FETCH RX_BIAS_RAM_INDEX 0x00 R/W 052 TX_BIAS_RAM_CTL [7:0] RESERVED TX_BIAS_ RAM_FETCH TX_BIAS_RAM_INDEX 0x00 R/W 400 LDO_TRIM_CTL_0 [7:0] 0x00 R/W 401 LDO_TRIM_CTL_1 [7:0] 0x00 R/W LDO_TRIM_REG RESERVED LDO_TRIM_SEL REGISTER DESCRIPTIONS Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Functions of the last four bits in this register are intentionally replicated from the first four bits in a reverse manner so that the bit pattern is the same, whether sent LSB first or MSB first. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] SO FT RESET ( R/W ) So ft Re se t [ 0 ] SO FT RESET _ ( R/W ) So ft Re se t (d up licate ) [ 6 ] LSB_FIRST ( R/W ) LSB First [ 1 ] LSB_FIRST _ ( R/W ) LSB First (d up licate ) [ 5 ] AD D R_ASCN ( R/W ) Ad d re ss Asce nsio n [ 2 ] AD D R_ASCN _ ( R/W ) Ad d re ss Asce nsio n (d up licate ) [ 4 ] SD O ACT IVE ( R/W ) SDO Active [ 3 ] SD O ACT IVE_ ( R/W ) SDO Active (d up licate ) Table 24. Bit Descriptions for INTERFACE_CONFIG_A Bit 7 6 5 4 3 2 1 0 Bit Name SOFTRESET LSB_FIRST ADDR_ASCN SDOACTIVE SDOACTIVE_ ADDR_ASCN_ LSB_FIRST_ SOFTRESET_ Settings Description Soft Reset LSB First Address Ascension SDO Active SDO Active (duplicate) Address Ascension (duplicate) LSB First (duplicate) Soft Reset (duplicate) Rev. A | Page 44 of 65 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet ADAR1000 Address: 0x001, Reset: 0x00, Name: INTERFACE_CONFIG_B 5 6 7 2 3 4 0 1 0 0 0 0 0 0 0 0 [ 7 ] SIN GLE_IN STRU CTION ( R/W ) Single Inst ruct ion [ 0 ] RESERV ED [ 2 :1 ] SOFT_RESET ( R/W ) Soft Reset [ 6 ] CSB_STALL ( R/W ) CSB St all [ 3 ] RESERV ED [ 5 ] M ASTER_SLAV E_RB ( R/W ) Mast er Slav e Readback [ 4 ] SLOW _IN TERFACE_CTRL ( R/W ) Slow Int erface Cont rol Table 25. Bit Descriptions for INTERFACE_CONFIG_B Bit(s) 7 6 5 4 3 [2:1] 0 Bit Name SINGLE_INSTRUCTION CSB_STALL MASTER_SLAVE_RB SLOW_INTERFACE_CTRL RESERVED SOFT_RESET RESERVED Settings Description Single Instruction CSB Stall Master Slave Readback Slow Interface Control Reserved Soft Reset Reserved Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R R/W R Address: 0x002, Reset: 0x10, Name: DEV_CONFIG 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [ 7 :4 ] D EV _STATU S ( R/W ) Dev ice St at us [ 1 :0 ] N ORM _OPERATIN G_M OD E ( R/W ) Norm al Operat ing Modes [ 3 :2 ] CU ST_OPERATIN G_M OD E ( R/W ) Cust om Operat ing Modes Table 26. Bit Descriptions for DEV_CONFIG Bit(s) [7:4] [3:2] [1:0] Bit Name DEV_STATUS CUST_OPERATING_MODE NORM_OPERATING_MODE Settings Description Device Status Custom Operating Modes Normal Operating Modes Reset 0x1 0x0 0x0 Access R/W R/W R/W Address: 0x003, Reset: 0x00, Name: CHIP_TYPE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] CH IP_TYPE ( R) Chip Ty pe Table 27. Bit Descriptions for CHIP_TYPE Bit(s) [7:0] Bit Name CHIP_TYPE Settings Description Chip Type Reset 0x0 Access R Address: 0x004, Reset: 0x00, Name: PRODUCT_ID_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] PRO D UCT _ID [ 1 5 :8 ] ( R) Pro d uct ID[ 15 :8 ] Table 28. Bit Descriptions for PRODUCT_ID_H Bit(s) [7:0] Bit Name PRODUCT_ID[15:8] Settings Rev. A | Page 45 of 65 Description Product ID[15:8] Reset 0x0 Access R ADAR1000 Data Sheet Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] PRO D UCT _ID [ 7 :0 ] ( R) Pro d uct ID[ 7 :0 ] Table 29. Bit Descriptions for PRODUCT_ID_L Bit(s) [7:0] Bit Name PRODUCT_ID[7:0] Settings Description Product ID[7:0] Reset 0x0 Access R Address: 0x00A, Reset: 0x00, Name: SCRATCH_PAD 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] SCRATCH PAD ( R/W ) Scrat ch Pad Table 30. Bit Descriptions for SCRATCH_PAD Bit(s) [7:0] Bit Name SCRATCHPAD Settings Description Scratch Pad Reset 0x0 Access R/W Address: 0x00B, Reset: 0x00, Name: SPI_REV 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] SPI_REV ( R) SPI Rev ision Table 31. Bit Descriptions for SPI_REV Bit(s) [7:0] Bit Name SPI_REV Settings Description SPI Revision Reset 0x0 Access R Address: 0x00C, Reset: 0x00, Name: VENDOR_ID_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] VEN D O R_ID [ 1 5 :8 ] ( R) Ve nd o r ID[ 15 :8 ] Table 32. Bit Descriptions for VENDOR_ID_H Bit(s) [7:0] Bit Name VENDOR_ID[15:8] Settings Description Vendor ID[15:8] Reset 0x0 Access R Reset 0x0 Access R Address: 0x00D, Reset: 0x00, Name: VENDOR_ID_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] VEN D O R_ID [ 7 :0 ] ( R) Ve nd o r ID[ 7 :0 ] Table 33. Bit Descriptions for VENDOR_ID_L Bit(s) [7:0] Bit Name VENDOR_ID[7:0] Settings Description Vendor ID[7:0] Rev. A | Page 46 of 65 Data Sheet ADAR1000 Address: 0x00F, Reset: 0x00, Name: TRANSFER_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :1 ] RESERV ED [ 0 ] M ASTER_SLAV E_X FER ( R/W ) Mast er Slav e Transfer Table 34. Bit Descriptions for TRANSFER_REG Bit(s) [7:1] 0 Bit Name RESERVED MASTER_SLAVE_XFER Settings Description Reserved Master Slave Transfer Reset 0x0 0x0 Access R R/W Address: 0x010, Reset: 0x00, Name: CH1_RX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 1 _AT T N _RX ( R/W ) Channe l 1 Atte nuato r Se tting fo r Re ce ive Mo d e [ 6 :0 ] RX_VGA_CH 1 ( R/W ) Channe l 1 Re ce ive VGA Gain Co ntro l Table 35. Bit Descriptions for CH1_RX_GAIN Bit(s) 7 [6:0] Bit Name CH1_ATTN_RX RX_VGA_CH1 Settings Description Channel 1 Attenuator Setting for Receive Mode Channel 1 Receive VGA Gain Control Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x011, Reset: 0x00, Name: CH2_RX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 2 _AT T N _RX ( R/W ) Channe l 2 Atte nuato r Se tting fo r Re ce ive Mo d e [ 6 :0 ] RX_VGA_CH 2 ( R/W ) Channe l 2 Re ce ive VGA Gain Co ntro l Table 36. Bit Descriptions for CH2_RX_GAIN Bit(s) 7 [6:0] Bit Name CH2_ATTN_RX RX_VGA_CH2 Settings Description Channel 2 Attenuator Setting for Receive Mode Channel 2 Receive VGA Gain Control Address: 0x012, Reset: 0x00, Name: CH3_RX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 3 _AT T N _RX ( R/W ) Channe l 3 Atte nuato r Se tting fo r Re ce ive Mo d e [ 6 :0 ] RX_VGA_CH 3 ( R/W ) Channe l 3 Re ce ive VGA Gain Co ntro l Table 37. Bit Descriptions for CH3_RX_GAIN Bit(s) 7 [6:0] Bit Name CH3_ATTN_RX RX_VGA_CH3 Settings Description Channel 3 Attenuator Setting for Receive Mode Channel 3 Receive VGA Gain Control Rev. A | Page 47 of 65 ADAR1000 Data Sheet Address: 0x013, Reset: 0x00, Name: CH4_RX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 4 _AT T N _RX ( R/W ) Channe l 4 Atte nuato r Se tting fo r Re ce ive Mo d e [ 6 :0 ] RX_VGA_CH 4 ( R/W ) Channe l 4 Re ce ive VGA Gain Co ntro l Table 38. Bit Descriptions for CH4_RX_GAIN Bit(s) 7 [6:0] Bit Name CH4_ATTN_RX RX_VGA_CH4 Settings Description Channel 4 Attenuator Setting for Receive Mode Channel 4 Receive VGA Gain Control Reset 0x0 0x0 Access R/W R/W Address: 0x014, Reset: 0x00, Name: CH1_RX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 1 _GAIN _I ( R/W ) Channe l 1 Re ce ive Ve cto r Mo d ulato r I Gain [ 5 ] RX_VM _CH 1 _PO L_I ( R/W ) Channe l 1 Re ce ive Ve cto r Mo d ulato r I Po larity Table 39. Bit Descriptions for CH1_RX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH1_POL_I RX_VM_CH1_GAIN_I Settings Description Reserved Channel 1 Receive Vector Modulator I Polarity Channel 1 Receive Vector Modulator I Gain Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x015, Reset: 0x00, Name: CH1_RX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 1 _GAIN _Q ( R/W ) Channe l 1 Re ce ive Ve cto r Mo d ulato r Q Gain [ 5 ] RX_VM _CH 1 _PO L_Q ( R/W ) Channe l 1 Re ce ive Ve cto r Mo d ulato r Q Po larity Table 40. Bit Descriptions for CH1_RX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH1_POL_Q RX_VM_CH1_GAIN_Q Settings Description Reserved Channel 1 Receive Vector Modulator Q Polarity Channel 1 Receive Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x016, Reset: 0x00, Name: CH2_RX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 5 ] RX_VM _CH 2 _PO L_I ( R/W ) Channe l 2 Re ce ive Ve cto r Mo d ulato r I Po larity [ 4 :0 ] RX_VM _CH 2 _GAIN _I ( R/W ) Channe l 2 Re ce ive Ve cto r Mo d ulato r I Gain Table 41. Bit Descriptions for CH2_RX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH2_POL_I RX_VM_CH2_GAIN_I Settings Description Reserved Channel 2 Receive Vector Modulator I Polarity Channel 2 Receive Vector Modulator I Gain Rev. A | Page 48 of 65 Data Sheet ADAR1000 Address: 0x017, Reset: 0x00, Name: CH2_RX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 2 _GAIN _Q ( R/W ) Channe l 2 Re ce ive Ve cto r Mo d ulato r Q Gain [ 5 ] RX_VM _CH 2 _PO L_Q ( R/W ) Channe l 2 Re ce ive Ve cto r Mo d ulato r Q Po larity Table 42. Bit Descriptions for CH2_RX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH2_POL_Q RX_VM_CH2_GAIN_Q Settings Description Reserved Channel 2 Receive Vector Modulator Q Polarity Channel 2 Receive Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x018, Reset: 0x00, Name: CH3_RX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 3 _GAIN _I ( R/W ) Channe l 3 Re ce ive Ve cto r Mo d ulato r I Gain [ 5 ] RX_VM _CH 3 _PO L_I ( R/W ) Channe l 3 Re ce ive Ve cto r Mo d ulato r I Po larity Table 43. Bit Descriptions for CH3_RX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH3_POL_I RX_VM_CH3_GAIN_I Settings Description Reserved. Channel 3 Receive Vector Modulator I Polarity Channel 3 Receive Vector Modulator I Gain Address: 0x019, Reset: 0x00, Name: CH3_RX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 3 _GAIN _Q ( R/W ) Channe l 3 Re ce ive Ve cto r Mo d ulato r Q Gain [ 5 ] RX_VM _CH 3 _PO L_Q ( R/W ) Channe l 3 Re ce ive Ve cto r Mo d ulato r Q Po larity Table 44. Bit Descriptions for CH3_RX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH3_POL_Q RX_VM_CH3_GAIN_Q Settings Description Reserved Channel 3 Receive Vector Modulator Q Polarity Channel 3 Receive Vector Modulator Q Gain Address: 0x01A, Reset: 0x00, Name: CH4_RX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 5 ] RX_VM _CH 4 _PO L_I ( R/W ) Channe l 4 Re ce ive Ve cto r Mo d ulato r I Po larity [ 4 :0 ] RX_VM _CH 4 _GAIN _I ( R/W ) Channe l 4 Re ce ive Ve cto r Mo d ulato r I Gain Table 45. Bit Descriptions for CH4_RX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH4_POL_I RX_VM_CH4_GAIN_I Settings Description Reserved Channel 4 Receive Vector Modulator I Polarity Channel 4 Receive Vector Modulator I Gain Rev. A | Page 49 of 65 ADAR1000 Data Sheet Address: 0x01B, Reset: 0x00, Name: CH4_RX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] RX_VM _CH 4 _GAIN _Q ( R/W ) Channe l 4 Re ce ive Ve cto r Mo d ulato r Q Gain [ 5 ] RX_VM _CH 4 _PO L_Q ( R/W ) Channe l 4 Re ce ive Ve cto r Mo d ulato r Q Po larity Table 46. Bit Descriptions for CH4_RX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED RX_VM_CH4_POL_Q RX_VM_CH4_GAIN_Q Settings Description Reserved Channel 4 Receive Vector Modulator Q Polarity Channel 4 Receive Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x01C, Reset: 0x00, Name: CH1_TX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 1 _AT T N _T X ( R/W ) Channe l 1 Atte nuato r Se tting fo r Transm it Mo d e [ 6 :0 ] T X_VGA_CH 1 ( R/W ) Channe l 1 Transm it VGA Gain Co ntro l Table 47. Bit Descriptions for CH1_TX_GAIN Bit(s) 7 [6:0] Bit Name CH1_ATTN_TX TX_VGA_CH1 Settings Description Channel 1 Attenuator Setting for Transmit Mode Channel 1 Transmit VGA Gain Control Address: 0x01D, Reset: 0x00, Name: CH2_TX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 2 _AT T N _T X ( R/W ) Channe l 2 Atte nuato r Se tting fo r Transm it Mo d e [ 6 :0 ] T X_VGA_CH 2 ( R/W ) Channe l 2 Transm it VGA Gain Co ntro l Table 48. Bit Descriptions for CH2_TX_GAIN Bit(s) 7 [6:0] Bit Name CH2_ATTN_TX TX_VGA_CH2 Settings Description Channel 2 Attenuator Setting for Transmit Mode Channel 2 Transmit VGA Gain Control Address: 0x01E, Reset: 0x00, Name: CH3_TX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 3 _AT T N _T X ( R/W ) Channe l 3 Atte nuato r Se tting fo r Transm it Mo d e [ 6 :0 ] T X_VGA_CH 3 ( R/W ) Channe l 3 Transm it VGA Gain Co ntro l Table 49. Bit Descriptions for CH3_TX_GAIN Bit(s) 7 [6:0] Bit Name CH3_ATTN_TX TX_VGA_CH3 Settings Description Channel 3 Attenuator Setting for Transmit Mode Channel 3 Transmit VGA Gain Control Rev. A | Page 50 of 65 Data Sheet ADAR1000 Address: 0x01F, Reset: 0x00, Name: CH4_TX_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] CH 4 _AT T N _T X ( R/W ) Channe l 4 Atte nuato r Se tting fo r Transm it Mo d e [ 6 :0 ] T X_VGA_CH 4 ( R/W ) Channe l 4 Transm it VGA Gain Co ntro l Table 50. Bit Descriptions for CH4_TX_GAIN Bit(s) 7 [6:0] Bit Name CH4_ATTN_TX TX_VGA_CH4 Settings Description Channel 4 Attenuator Setting for Transmit Mode Channel 4 Transmit VGA Gain Control Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x020, Reset: 0x00, Name: CH1_TX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] T X_VM _CH 1 _GAIN _I ( R/W ) Channe l 1 Transm it Ve cto r Mo d ulato r I Gain [ 5 ] T X_VM _CH 1 _PO L_I ( R/W ) Channe l 1 Transm it Ve cto r Mo d ulato r I Po larity Table 51. Bit Descriptions for CH1_TX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH1_POL_I TX_VM_CH1_GAIN_I Settings Description Reserved Channel 1 Transmit Vector Modulator I Polarity Channel 1 Transmit Vector Modulator I Gain Address: 0x021, Reset: 0x00, Name: CH1_TX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] T X_VM _CH 1 _GAIN _Q ( R/W ) Channe l 1 Transm it Ve cto r Mo d ulato r Q Gain [ 5 ] T X_VM _CH 1 _PO L_Q ( R/W ) Channe l 1 Transm it Ve cto r Mo d ulato r Q Po larity Table 52. Bit Descriptions for CH1_TX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH1_POL_Q TX_VM_CH1_GAIN_Q Settings Description Reserved Channel 1 Transmit Vector Modulator Q Polarity Channel 1 Transmit Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x022, Reset: 0x00, Name: CH2_TX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 5 ] T X_VM _CH 2 _PO L_I ( R/W ) Channe l 2 Transm it Ve cto r Mo d ulato r I Po larity [ 4 :0 ] T X_VM _CH 2 _GAIN _I ( R/W ) Channe l 2 Transm it Ve cto r Mo d ulato r I Gain Table 53. Bit Descriptions for CH2_TX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH2_POL_I TX_VM_CH2_GAIN_I Settings Description Reserved Channel 2 Transmit Vector Modulator I Polarity Channel 2 Transmit Vector Modulator I Gain Rev. A | Page 51 of 65 Reset 0x0 0x0 0x0 Access R R/W R/W ADAR1000 Data Sheet Address: 0x023, Reset: 0x00, Name: CH2_TX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] T X_VM _CH 2 _GAIN _Q ( R/W ) Channe l 2 Transm it Ve cto r Mo d ulato r Q Gain [ 5 ] T X_VM _CH 2 _PO L_Q ( R/W ) Channe l 2 Transm it Ve cto r Mo d ulato r Q Po larity Table 54. Bit Descriptions for CH2_TX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH2_POL_Q TX_VM_CH2_GAIN_Q Settings Description Reserved Channel 2 Transmit Vector Modulator Q Polarity Channel 2 Transmit Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x024, Reset: 0x00, Name: CH3_TX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 4 :0 ] T X_VM _CH 3 _GAIN _I ( R/W ) Channe l 3 Transm it Ve cto r Mo d ulato r I Gain [ 7 :6 ] RESERVED [ 5 ] T X_VM _CH 3 _PO L_I ( R/W ) Channe l 3 Transm it Ve cto r Mo d ulato r I Po larity Table 55. Bit Descriptions for CH3_TX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH3_POL_I TX_VM_CH3_GAIN_I Settings Description Reserved Channel 3 Transmit Vector Modulator I Polarity Channel 3 Transmit Vector Modulator I Gain Address: 0x025, Reset: 0x00, Name: CH3_TX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] T X_VM _CH 3 _GAIN _Q ( R/W ) Channe l 3 Transm it Ve cto r Mo d ulato r Q Gain [ 5 ] T X_VM _CH 3 _PO L_Q ( R/W ) Channe l 3 Transm it Ve cto r Mo d ulato r Q Po larity Table 56. Bit Descriptions for CH3_TX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH3_POL_Q TX_VM_CH3_GAIN_Q Settings Description Reserved Channel 3 Transmit Vector Modulator Q Polarity Channel 3 Transmit Vector Modulator Q Gain Address: 0x026, Reset: 0x00, Name: CH4_TX_PHASE_I 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 5 ] T X_VM _CH 4 _PO L_I ( R/W ) Channe l 4 Transm it Ve cto r Mo d ulato r I Po larity [ 4 :0 ] T X_VM _CH 4 _GAIN _I ( R/W ) Channe l 4 Transm it Ve cto r Mo d ulato r I Gain Table 57. Bit Descriptions for CH4_TX_PHASE_I Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH4_POL_I TX_VM_CH4_GAIN_I Settings Description Reserved Channel 4 Transmit Vector Modulator I Polarity Channel 4 Transmit Vector Modulator I Gain Rev. A | Page 52 of 65 Data Sheet ADAR1000 Address: 0x027, Reset: 0x00, Name: CH4_TX_PHASE_Q 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 4 :0 ] T X_VM _CH 4 _GAIN _Q ( R/W ) Channe l 4 TX Ve cto r Mo d Q Gain [ 5 ] T X_VM _CH 4 _PO L_Q ( R/W ) Channe l 4 Transm it Ve cto r Mo d ulato r Q Po larity Table 58. Bit Descriptions for CH4_TX_PHASE_Q Bit(s) [7:6] 5 [4:0] Bit Name RESERVED TX_VM_CH4_POL_Q TX_VM_CH4_GAIN_Q Settings Description Reserved Channel 4 Transmit Vector Modulator Q Polarity Channel 4 Transmit Vector Modulator Q Gain Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x028, Reset: 0x00, Name: LD_WRK_REGS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :2 ] RESERVED [ 1 ] LD T X_O VERRID E ( W ) Lo ad s Transm it Wo rking Re g iste rs fro m SPI [ 0 ] LD RX_O VERRID E ( W ) Lo ad s Re ce ive Wo rking Re g iste rs fro m SPI Table 59. Bit Descriptions for LD_WRK_REGS Bit(s) [7:2] 1 0 Bit Name RESERVED LDTX_OVERRIDE LDRX_OVERRIDE Settings Description Reserved Loads Transmit Working Registers from SPI Loads Receive Working Registers from SPI Reset 0x0 0x0 0x0 Access R W W Address: 0x029, Reset: 0x00, Name: CH1_PA_BIAS_ON 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA1 _BIAS_ON ( R/W ) Ex t ernal Bias for Ex t ernal PA 1 Table 60. Bit Descriptions for CH1_PA_BIAS_ON Bit(s) [7:0] Bit Name EXT_PA1_BIAS_ON Settings Description External Bias for External PA 1 Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x02A, Reset: 0x00, Name: CH2_PA_BIAS_ON 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA2 _BIAS_ON ( R/W ) Ex t ernal Bias for Ex t ernal PA 2 Table 61. Bit Descriptions for CH2_PA_BIAS_ON Bit(s) [7:0] Bit Name EXT_PA2_BIAS_ON Settings Description External Bias for External PA 2 Rev. A | Page 53 of 65 ADAR1000 Data Sheet Address: 0x02B, Reset: 0x00, Name: CH3_PA_BIAS_ON 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA3 _BIAS_ON ( R/W ) Ex t ernal Bias for Ex t ernal PA 3 Table 62. Bit Descriptions for CH3_PA_BIAS_ON Bit(s) [7:0] Bit Name EXT_PA3_BIAS_ON Settings Description External Bias for External PA 3 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x02C, Reset: 0x00, Name: CH4_PA_BIAS_ON 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA4 _BIAS_ON ( R/W ) Ex t ernal Bias for Ex t ernal PA 4 Table 63. Bit Descriptions for CH4_PA_BIAS_ON Bit(s) [7:0] Bit Name EXT_PA4_BIAS_ON Settings Description External Bias for External PA 4 Address: 0x02D, Reset: 0x00, Name: LNA_BIAS_ON 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_LN A_BIAS_ON ( R/W ) Ex t ernal Bias for Ex t ernal LNAs Table 64. Bit Descriptions for LNA_BIAS_ON Bit(s) [7:0] Bit Name EXT_LNA_BIAS_ON Settings Description External Bias for External LNAs Address: 0x02E, Reset: 0x00, Name: RX_ENABLES 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RESERVED [ 0 ] RX_VGA_EN ( R/W ) Enab le s the Re ce ive Channe l VGAs [ 6 ] CH 1 _RX_EN ( R/W ) Enab le s Re ce ive Channe l 1 Sub circuits [ 1 ] RX_VM _EN ( R/W ) Enab le s the Re ce ive Channe l Ve cto r Mo d ulato rs [ 5 ] CH 2 _RX_EN ( R/W ) Enab le s Re ce ive Channe l 2 Sub circuits [ 2 ] RX_LN A_EN ( R/W ) Enab le s the Re ce ive Channe l LNAs [ 4 ] CH 3 _RX_EN ( R/W ) Enab le s Re ce ive Channe l 3 Sub circuits [ 3 ] CH 4 _RX_EN ( R/W ) Enab le s Re ce ive Channe l 4 Sub circuits Table 65. Bit Descriptions for RX_ENABLES Bit 7 6 5 4 3 2 1 0 Bit Name RESERVED CH1_RX_EN CH2_RX_EN CH3_RX_EN CH4_RX_EN RX_LNA_EN RX_VM_EN RX_VGA_EN Settings Description Reserved Enables Receive Channel 1 Subcircuits Enables Receive Channel 2 Subcircuits Enables Receive Channel 3 Subcircuits Enables Receive Channel 4 Subcircuits Enables the Receive Channel LNAs Enables the Receive Channel Vector Modulators Enables the Receive Channel VGAs Rev. A | Page 54 of 65 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W R/W R/W R/W Data Sheet ADAR1000 Address: 0x02F, Reset: 0x00, Name: TX_ENABLES 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RESERVED [ 0 ] T X_VGA_EN ( R/W ) Enab le s the Transm it Channe l VGAs [ 6 ] CH 1 _T X_EN ( R/W ) Enab le s Transm it Channe l 1 Sub circuits [ 1 ] T X_VM _EN ( R/W ) Enab le s the Transm it Channe l Ve cto r Mo d ulato rs [ 5 ] CH 2 _T X_EN ( R/W ) Enab le s Transm it Channe l 2 Sub circuits [ 2 ] T X_D RV_EN ( R/W ) Enab le s the Transm it Channe l Drive rs [ 4 ] CH 3 _T X_EN ( R/W ) Enab le s Transm it Channe l 3 Sub circuits [ 3 ] CH 4 _T X_EN ( R/W ) Enab le s transm it Channe l 4 Sub circuits Table 66. Bit Descriptions for TX_ENABLES Bit 7 6 5 4 3 2 1 0 Bit Name RESERVED CH1_TX_EN CH2_TX_EN CH3_TX_EN CH4_TX_EN TX_DRV_EN TX_VM_EN TX_VGA_EN Settings Description Reserved Enables Transmit Channel 1 Subcircuits Enables Transmit Channel 2 Subcircuits Enables Transmit Channel 3 Subcircuits Enables Transmit Channel 4 Subcircuits Enables the Transmit Channel Drivers Enables the Transmit Channel Vector Modulators Enables the Transmit Channel VGAs Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W R/W Address: 0x030, Reset: 0x00, Name: MISC_ENABLES 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SW_DRV_TR_MODE_SEL (R/W) Transm it/Receive Output Driver Select. If 0, TR_SW_NEG is enabled, and if 1, TR_SW_POS is enabled. [0] CH4_DET_EN (R/W) Enables Channel 4 Power Detector. [1] CH3_DET_EN (R/W) Enables Channel 3 Power Detector. [6] BIAS_CTRL (R/W) External Am plifier Bias Control. If 0, DACs assum e the on register values. If 1, DACs vary with device m ode (transm it and receive) [2] CH2_DET_EN (R/W) Enables Channel 2 Power Detector. [3] CH1_DET_EN (R/W) Enables Channel 1 Power Detector. [5] BIAS_EN (R/W) Enables PA and LNA bias DACs. 0 = enabled. [4] LNA_BIAS_OUT_EN (R/W) Enables output of LNA bias DAC. 0= open and 1 = bias connected. Table 67. Bit Descriptions for MISC_ENABLES Bit 7 Bit Name SW_DRV_TR_MODE_SEL 6 BIAS_CTRL 5 4 3 2 1 0 BIAS_EN LNA_BIAS_OUT_EN CH1_DET_EN CH2_DET_EN CH3_DET_EN CH4_DET_EN Settings Description Transmit/Receive Output Driver Select. If 0, TR_SW_NEG is enabled, and if 1, TR_SW_POS is enabled. External Amplifier Bias Control. If 0, DACs assume the on register values. If 1, DACs vary with device mode (transmit and receive). Enables PA and LNA Bias DACs. 0 = enabled. Enables Output of LNA Bias DAC. 0 = open and 1 = bias connected. Enables Channel 1 Power Detector. Enables Channel 2 Power Detector. Enables Channel 3 Power Detector. Enables Channel 4 Power Detector. Rev. A | Page 55 of 65 ADAR1000 Data Sheet Address: 0x031, Reset: 0x00, Name: SW_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SW_DRV_TR_STATE (R/W) Controls Sense of Transm it/Receive Switch Driver Output. If 0, the driver outputs 0 V in receive m ode. [0] POL (R/W) Control for External Polarization Switch Drivers. 0 = outputs 0 V, and 1 = outputs -5 V, if switch is enabled. [6] TX_EN (R/W) Enables Transm it Channel Subcircuits when Under SPI Control. 1 = enabled. [1] TR_SPI (R/W) State of SPI Control. 0 = receive and 1 = transm it. [5] RX_EN (R/W) Enables Receive Channel Subcircuits when Under SPI Control. 1 = enabled. [2] TR_SOURCE (R/W) Source for Transm it/Receive Control. 0 = TR_SPI, 1 = TR input. [4] SW_DRV_EN_TR (R/W) Enables Switch Driver for External Transm it/Receive Switch. 1 = enabled. [3] SW_DRV_EN_POL (R/W) Enables Switch Driver for External Polarization Switch. 1 = enabled. Table 68. Bit Descriptions for SW_CTRL Bit 7 Bit Name SW_DRV_TR_STATE 6 5 4 3 2 1 0 TX_EN RX_EN SW_DRV_EN_TR SW_DRV_EN_POL TR_SOURCE TR_SPI POL Settings Description Controls Sense of Transmit/Receive Switch Driver Output. If 0, the driver outputs 0 V in receive mode. Enables Transmit Channel Subcircuits when Under SPI Control. 1 = enabled. Enables Receive Channel Subcircuits when Under SPI Control. 1 = enabled. Enables Switch Driver for External Transmit/Receive Switch. 1 = enabled. Enables Switch Driver for External Polarization Switch. 1 = enabled. Source for Transmit/Receive Control. 0 = TR_SPI, 1 = TR input. State of SPI Control. 0 = receive and 1 = transmit. Control for External Polarity Switch Drivers. 0 = outputs 0 V, and 1 = outputs -5 V, if switch is enabled. Reset 0x0 Access R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W R/W R/W Address: 0x032, Reset: 0x00, Name: ADC_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] AD C_CLKFREQ_SEL ( R/W ) ADC Clock Frequency Select ion [ 0 ] AD C_EOC ( R) ADC End of Conv ersion Signal [ 6 ] AD C_EN ( R/W ) Turns on Com parat or and Reset s St at e Machine [ 3 :1 ] M U X _SEL ( R/W ) ADC Input Signal Select [ 5 ] CLK_EN ( R/W ) Turns on Clock Oscillat or [ 4 ] ST_CON V ( R/W C) Pulse Triggers Conv ersion Cy cle Table 69. Bit Descriptions for ADC_CTRL Bit(s) 7 6 5 4 [3:1] 0 Bit Name ADC_CLKFREQ_SEL ADC_EN CLK_EN ST_CONV MUX_SEL ADC_EOC Settings Description ADC Clock Frequency Selection Turns on Comparator and Resets State Machine Turns on Clock Oscillator Pulse Triggers Conversion Cycle ADC Input Signal Select ADC End of Conversion Signal Rev. A | Page 56 of 65 Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/WC R/W R Data Sheet ADAR1000 Address: 0x033, Reset: 0x00, Name: ADC_OUTPUT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] AD C ( R) ADC Out put Word Table 70. Bit Descriptions for ADC_OUTPUT Bit(s) [7:0] Bit Name ADC Settings Description ADC Output Word Reset 0x0 Access R Address: 0x034, Reset: 0x00, Name: BIAS_CURRENT_RX_LNA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERV ED [ 3 :0 ] LN A_BIAS ( R/W ) LNA Bias Current Set t ing Table 71. Bit Descriptions for BIAS_CURRENT_RX_LNA Bit(s) [7:4] [3:0] Bit Name RESERVED LNA_BIAS Settings Description Reserved LNA Bias Current Setting Reset 0x0 0x0 Access R R/W Address: 0x035, Reset: 0x00, Name: BIAS_CURRENT_RX 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RESERVED [ 2 :0 ] RX_VM _BIAS ( R/W ) Re ce ive Channe l Ve cto r Mo d ulato r Bias Curre nt Se tting [ 6 :3 ] RX_VGA_BIAS ( R/W ) Re ce ive Channe l VGA Bias Curre nt Se tting Table 72. Bit Descriptions for BIAS_CURRENT_RX Bit(s) 7 [6:3] [2:0] Bit Name RESERVED RX_VGA_BIAS RX_VM_BIAS Settings Description Reserved Receive Channel VGA Bias Current Setting Receive Channel Vector Modulator Bias Current Setting Reset 0x0 0x0 0x0 Access R R/W R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x036, Reset: 0x00, Name: BIAS_CURRENT_TX 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RESERVED [ 6 :3 ] T X_VGA_BIAS ( R/W ) Transm it Channe l VGA Bias Curre nt Se tting [ 2 :0 ] T X_VM _BIAS ( R/W ) Transm it Channe l Ve cto r Mo d ulato r Bias Curre nt Se tting Table 73. Bit Descriptions for BIAS_CURRENT_TX Bit(s) 7 [6:3] [2:0] Bit Name RESERVED TX_VGA_BIAS TX_VM_BIAS Settings Description Reserved Transmit Channel VGA Bias Current Setting Transmit Channel Vector Modulator Bias Current Setting Rev. A | Page 57 of 65 ADAR1000 Data Sheet Address: 0x037, Reset: 0x00, Name: BIAS_CURRENT_TX_DRV 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 2 :0 ] T X_D RV_BIAS ( R/W ) Transm it Drive r Bias Curre nt Se tting [ 7 :3 ] RESERVED Table 74. Bit Descriptions for BIAS_CURRENT_TX_DRV Bit(s) [7:3] [2:0] Bit Name RESERVED TX_DRV_BIAS Settings Description Reserved Transmit Driver Bias Current Setting Reset 0x0 0x0 Access R R/W Address: 0x038, Reset: 0x00, Name: MEM_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] SCAN _M O D E_EN ( R/W ) Scan Mo d e Enab le [ 0 ] RX_CH X_RAM _BYPASS ( R/W ) Byp ass RAM fo r Re ce ive Channe ls [ 6 ] BEAM _RAM _BYPASS ( R/W ) Byp ass RAM and Lo ad Be am Po sitio n Se tting s fro m SPI [ 1 ] T X_CH X_RAM _BYPASS ( R/W ) Byp ass RAM fo r Transm it Channe ls [ 2 ] RX_BEAM _ST EP_EN ( R/W ) Se q ue ntially Ste p Thro ug h Sto re d Re ce ive Be am Po sitio ns [ 5 ] BIAS_RAM _BYPASS ( R/W ) Byp ass RAM and Lo ad Bias Po sitio n Se tting s fro m SPI [ 3 ] T X_BEAM _ST EP_EN ( R/W ) Se q ue ntially Ste p Thro ug h Sto re d Transm it Be am Po sitio ns [ 4 ] RESERVED Table 75. Bit Descriptions for MEM_CTRL Bit 7 6 5 4 3 2 1 0 Bit Name SCAN_MODE_EN BEAM_RAM_BYPASS BIAS_RAM_BYPASS RESERVED TX_BEAM_STEP_EN RX_BEAM_STEP_EN TX_CHX_RAM_BYPASS RX_CHX_RAM_BYPASS Settings Description Scan Mode Enable Bypass RAM and Load Beam Position Settings from SPI Bypass RAM and Load Bias Position Settings from SPI Reserved Sequentially Step Through Stored Transmit Beam Positions Sequentially Step Through Stored Receive Beam Positions Bypass RAM for Transmit Channels Bypass RAM for Receive Channels Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R R/W R/W R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x039, Reset: 0x00, Name: RX_CHX_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RX_CH X_RAM _FET CH ( R/W ) Ge t Re ce ive Channe l Be am Se tting s fro m RAM [ 6 :0 ] RX_CH X_RAM _IN D EX ( R/W ) RAM Ind e x fo r Re ce ive Channe ls Table 76. Bit Descriptions for RX_CHX_MEM Bit(s) 7 [6:0] Bit Name RX_CHX_RAM_FETCH RX_CHX_RAM_INDEX Settings Description Get Receive Channel Beam Settings from RAM RAM Index for Receive Channels Rev. A | Page 58 of 65 Data Sheet ADAR1000 Address: 0x03A, Reset: 0x00, Name: TX_CHX_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 6 :0 ] T X_CH X_RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe ls [ 7 ] T X_CH X_RAM _FET CH ( R/W ) Ge t Transm it Channe l Be am Se tting s fro m RAM Table 77. Bit Descriptions for TX_CHX_MEM Bit(s) 7 [6:0] Bit Name TX_CHX_RAM_FETCH TX_CHX_RAM_INDEX Settings Description Get Transmit Channel Beam Settings from RAM RAM Index for Transmit Channels Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x03D, Reset: 0x00, Name: RX_CH1_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RX_CH1_RAM_FETCH (R/W) Get Receive Channel 1 Beam Settings from RAM [6:0] RX_CH1_RAM_INDEX (R/W) RAM Index for Receive Channel 1 Table 78. Bit Descriptions for RX_CH1_MEM Bit(s) 7 [6:0] Bit Name RX_CH1_RAM_FETCH RX_CH1_RAM_INDEX Settings Description Get Receive Channel 1 Beam Settings from RAM RAM Index for Receive Channel 1 Address: 0x03E, Reset: 0x00, Name: RX_CH2_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RX_CH 2 _RAM _FET CH ( R/W ) Ge t Re ce ive Channe l 2 Be am Se tting s fro m RAM [ 6 :0 ] RX_CH 2 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Re ce ive Channe l 2 Table 79. Bit Descriptions for RX_CH2_MEM Bit(s) 7 [6:0] Bit Name RX_CH2_RAM_FETCH RX_CH2_RAM_INDEX Settings Description Get Receive Channel 2 Beam Settings from RAM RAM Index for Receive Channel 2 Address: 0x03F, Reset: 0x00, Name: RX_CH3_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RX_CH 3 _RAM _FET CH ( R/W ) Ge t Re ce ive Channe l 3 Be am Se tting s fro m RAM [ 6 :0 ] RX_CH 3 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Re ce ive Channe l 3 Table 80. Bit Descriptions for RX_CH3_MEM Bit(s) 7 [6:0] Bit Name RX_CH3_RAM_FETCH RX_CH3_RAM_INDEX Settings Description Get Receive Channel 3 Beam Settings from RAM RAM Index for Receive Channel 3 Rev. A | Page 59 of 65 ADAR1000 Data Sheet Address: 0x040, Reset: 0x00, Name: RX_CH4_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RX_CH 4 _RAM _FET CH ( R/W ) Ge t Re ce ive Channe l 4 Be am Se tting s fro m RAM [ 6 :0 ] RX_CH 4 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Re ce ive Channe l 4 Table 81. Bit Descriptions for RX_CH4_MEM Bit(s) 7 [6:0] Bit Name RX_CH4_RAM_FETCH RX_CH4_RAM_INDEX Settings Description Get Receive Channel 4 Beam Settings from RAM RAM Index for Receive Channel 4 Reset 0x0 0x0 Access R/W R/W Address: 0x041, Reset: 0x00, Name: TX_CH1_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] T X_CH 1 _RAM _FET CH ( R/W ) Ge t Transm it Channe l 1 Be am Se tting s fro m RAM [ 6 :0 ] T X_CH 1 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe l 1 Table 82. Bit Descriptions for TX_CH1_MEM Bit(s) 7 [6:0] Bit Name TX_CH1_RAM_FETCH TX_CH1_RAM_INDEX Settings Description Get Transmit Channel 1 Beam Settings from RAM RAM Index for Transmit Channel 1 Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x042, Reset: 0x00, Name: TX_CH2_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] T X_CH 2 _RAM _FET CH ( R/W ) Ge t Transm it Channe l 2 Be am Se tting s fro m RAM [ 6 :0 ] T X_CH 2 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe l 2 Table 83. Bit Descriptions for TX_CH2_MEM Bit(s) 7 [6:0] Bit Name TX_CH2_RAM_FETCH TX_CH2_RAM_INDEX Settings Description Get Transmit Channel 2 Beam Settings from RAM RAM Index for Transmit Channel 2 Address: 0x043, Reset: 0x00, Name: TX_CH3_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] T X_CH 3 _RAM _FET CH ( R/W ) Ge t Transm it Channe l 3 Be am Se tting s fro m RAM [ 6 :0 ] T X_CH 3 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe l 3 Table 84. Bit Descriptions for TX_CH3_MEM Bit(s) 7 [6:0] Bit Name TX_CH3_RAM_FETCH TX_CH3_RAM_INDEX Settings Description Get Transmit Channel 3 Beam Settings from RAM RAM Index for Transmit Channel 3 Rev. A | Page 60 of 65 Data Sheet ADAR1000 Address: 0x044, Reset: 0x00, Name: TX_CH4_MEM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] T X_CH 4 _RAM _FET CH ( R/W ) Ge t Transm it Channe l 4 Be am Se tting s fro m RAM [ 6 :0 ] T X_CH 4 _RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe l 4 Table 85. Bit Descriptions for TX_CH4_MEM Bit(s) 7 [6:0] Bit Name TX_CH4_RAM_FETCH TX_CH4_RAM_INDEX Settings Description Get Transmit Channel 4 Beam Settings from RAM RAM Index for Transmit Channel 4 Reset 0x0 0x0 Access R/W R/W Address: 0x045, Reset: 0x00, Name: REV_ID 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] REV _ID ( R) Chip Rev ision ID Table 86. Bit Descriptions for REV_ID Bit(s) [7:0] Bit Name REV_ID Settings Description Chip Revision ID Reset 0x0 Access R Address: 0x046, Reset: 0x00, Name: CH1_PA_BIAS_OFF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA1 _BIAS_OFF ( R/W ) Ex t ernal Bias for Ex t ernal PA 1 Table 87. Bit Descriptions for CH1_PA_BIAS_OFF Bit(s) [7:0] Bit Name EXT_PA1_BIAS_OFF Settings Description External Bias for External PA 1 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x047, Reset: 0x00, Name: CH2_PA_BIAS_OFF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA2 _BIAS_OFF ( R/W ) Ex t ernal Bias for Ex t ernal PA 2 Table 88. Bit Descriptions for CH2_PA_BIAS_OFF Bit(s) [7:0] Bit Name EXT_PA2_BIAS_OFF Settings Description External Bias for External PA 2 Address: 0x048, Reset: 0x00, Name: CH3_PA_BIAS_OFF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA3 _BIAS_OFF ( R/W ) Ex t ernal Bias for Ex t ernal PA 3 Table 89. Bit Descriptions for CH3_PA_BIAS_OFF Bit(s) [7:0] Bit Name EXT_PA3_BIAS_OFF Settings Description External Bias for External PA 3 Rev. A | Page 61 of 65 ADAR1000 Data Sheet Address: 0x049, Reset: 0x00, Name: CH4_PA_BIAS_OFF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_PA4 _BIAS_OFF ( R/W ) Ex t ernal Bias for Ex t ernal PA 4 Table 90. Bit Descriptions for CH4_PA_BIAS_OFF Bit(s) [7:0] Bit Name EXT_PA4_BIAS_OFF Settings Description External Bias for External PA 4 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 0x0 Access R/W R/W Reset 0x0 0x0 Access R/W R/W Address: 0x04A, Reset: 0x00, Name: LNA_BIAS_OFF 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] EX T_LN A_BIAS_OFF ( R/W ) Ex t ernal Bias for Ex t ernal LNAs Table 91. Bit Descriptions for LNA_BIAS_OFF Bit(s) [7:0] Bit Name EXT_LNA_BIAS_OFF Settings Description External Bias for External LNAs Address: 0x04B, Reset: 0x00, Name: TX_TO_RX_DELAY_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] TX _TO_RX _D ELAY_1 ( R/W ) PA Bias off t o TR Sw it ch Delay [ 3 :0 ] TX _TO_RX _D ELAY_2 ( R/W ) TR Sw it ch t o LNA Bias on Delay Table 92. Bit Descriptions for TX_TO_RX_DELAY_CTRL Bit(s) [7:4] [3:0] Bit Name TX_TO_RX_DELAY_1 TX_TO_RX_DELAY_2 Settings Description PA Bias off to TR Switch Delay TR Switch to LNA Bias on Delay Address: 0x04C, Reset: 0x00, Name: RX_TO_TX_DELAY_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RX _TO_TX _D ELAY_1 ( R/W ) LNA Bias off t o TR Sw it ch Delay [ 3 :0 ] RX _TO_TX _D ELAY_2 ( R/W ) TR Sw it ch t o PA Bias on Delay Table 93. Bit Descriptions for RX_TO_TX_DELAY_CTRL Bit(s) [7:4] [3:0] Bit Name RX_TO_TX_DELAY_1 RX_TO_TX_DELAY_2 Settings Description LNA Bias off to TR Switch Delay TR Switch to PA Bias on Delay Address: 0x04D, Reset: 0x00, Name: TX_BEAM_STEP_START 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] T X_BEAM _ST EP_ST ART ( R/W ) Start Me m o ry Ad d re ss fo r Transm it Channe l Be am Ste p p ing Table 94. Bit Descriptions for TX_BEAM_STEP_START Bit(s) [7:0] Bit Name TX_BEAM_STEP_START Settings Description Start Memory Address for Transmit Channel Beam Stepping Rev. A | Page 62 of 65 Reset 0x0 Access R/W Data Sheet ADAR1000 Address: 0x04E, Reset: 0x00, Name: TX_BEAM_STEP_STOP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] T X_BEAM _ST EP_ST O P ( R/W ) Sto p Me m o ry Ad d re ss fo r Transm it Channe l Be am Ste p p ing Table 95. Bit Descriptions for TX_BEAM_STEP_STOP Bit(s) [7:0] Bit Name TX_BEAM_STEP_STOP Settings Description Stop Memory Address for Transmit Channel Beam Stepping Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x04F, Reset: 0x00, Name: RX_BEAM_STEP_START 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] RX_BEAM _ST EP_ST ART ( R/W ) Start Me m o ry Ad d re ss fo r Re ce ive Channe l Be am Ste p p ing Table 96. Bit Descriptions for RX_BEAM_STEP_START Bit(s) [7:0] Bit Name RX_BEAM_STEP_START Settings Description Start Memory Address for Receive Channel Beam Stepping Address: 0x050, Reset: 0x00, Name: RX_BEAM_STEP_STOP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] RX_BEAM _ST EP_ST O P ( R/W ) Sto p Me m o ry Ad d re ss fo r Re ce ive Channe l Be am Ste p p ing Table 97. Bit Descriptions for RX_BEAM_STEP_STOP Bit(s) [7:0] Bit Name RX_BEAM_STEP_STOP Settings Description Stop Memory Address for Receive Channel Beam Stepping Address: 0x051, Reset: 0x00, Name: RX_BIAS_RAM_CTL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERVED [ 3 ] RX_BIAS_RAM _FET CH ( R/W ) Ge t Re ce ive Be am Se tting s fro m RAM [ 2 :0 ] RX_BIAS_RAM _IN D EX ( R/W ) RAM Ind e x fo r Re ce ive Channe ls Table 98. Bit Descriptions for RX_BIAS_RAM_CTL Bit(s) [7:4] 3 [2:0] Bit Name RESERVED RX_BIAS_RAM_FETCH RX_BIAS_RAM_INDEX Settings Description Reserved Get Receive Beam Settings from RAM RAM Index for Receive Channels Rev. A | Page 63 of 65 ADAR1000 Data Sheet Address: 0x052, Reset: 0x00, Name: TX_BIAS_RAM_CTL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERVED [ 2 :0 ] T X_BIAS_RAM _IN D EX ( R/W ) RAM Ind e x fo r Transm it Channe ls [ 3 ] T X_BIAS_RAM _FET CH ( R/W ) Ge t Transm it Channe l Be am Se tting s fro m RAM Table 99. Bit Descriptions for TX_BIAS_RAM_CTL Bit(s) [7:4] 3 [2:0] Bit Name RESERVED TX_BIAS_RAM_FETCH TX_BIAS_RAM_INDEX Settings Description Reserved Get Transmit Channel Beam Settings from RAM RAM Index for Transmit Channels Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x400, Reset: 0x00, Name: LDO_TRIM_CTL_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] LD O _T RIM _REG ( R/W ) Trim Value s fo r Ad justing LDO Outp uts Table 100. Bit Descriptions for LDO_TRIM_CTL_0 Bits [7:0] Bit Name LDO_TRIM_REG Settings Description Trim Values for Adjusting LDO Outputs Reset 0x0 Access R/W Address: 0x401, Reset: 0x00, Name: LDO_TRIM_CTL_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :2 ] RESERVED [ 1 :0 ] LD O _T RIM _SEL ( R/W ) Se t value to 2 (10 b inary) to e nab le use r ad justm e nts fo r LDO o utp uts. Othe r co m b inatio ns no t re co m m e nd e d . Table 101. Bit Descriptions for LDO_TRIM_CTL_1 Bits [7:2] [1:0] Bit Name RESERVED LDO_TRIM_SEL Settings Description Reserved. Set value to 2 (10 binary) to enable user adjustments for LDO outputs. Other combinations not recommended. Rev. A | Page 64 of 65 Reset 0x0 0x0 Access R R/W Data Sheet ADAR1000 OUTLINE DIMENSIONS PIN A1 CORNER AREA 7.10 7.00 6.90 0.30 0.25 SQ 0.20 4.25 BSC 13 12 11 10 9 8 7 6 5 4 3 2 CHAMFERED PIN 1 (0.1 x 45) 1 A B C D 6.00 REF SQ E F EXPOSED PAD G H 3.25 BSC J K L M N TOP VIEW 0.80 MAX SIDE VIEW 0.530 REF PKG-005340 0.220 0.180 0.140 BOTTOM VIEW 0.38 BSC FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-24-2017-A 0.50 BSC Figure 98. 88-Terminal Land Grid Array [LGA] (CC-88-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAR1000ACCZN ADAR1000ACCZN-R7 ADAR1000-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 88-Terminal Land Grid Array [LGA] 88-Terminal Land Grid Array [LGA], 7" Reel Evaluation Board Z = RoHS Compliant Part. (c)2018-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16790-0-3/19(A) Rev. A | Page 65 of 65 Package Option CC-88-1 CC-88-1