PCA2129T/Q900/2,518 - NXP SEMICONDUCTORS

1. General description

The PCA2129T is a CMOS1 Real Time Clock (RTC) and calendar with an integrated

Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz

crystal op timized for very high a ccuracy and very low power consump tion. The PCA2129T

has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a

programmable watchdog function, a timestamp function, and many other features.

2. Features and benefits

AEC-Q100 compliant for automotive applications

Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors

Typical accuracy: 3ppm from 30 C to +80 C

Integration of a 32.768 kHz quartz crystal and oscillator in the same package

Provides year, month, day, weekday, hours, minutes, seconds, and leap year

correction

Timestamp functio n

with interrupt capability

detection of two dif ferent event s on one multilevel input pin (for example, for tamper

detection)

Two line bidirectional 400 kHz Fast-mode I2C-bus interface

3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s)

Battery backup input pin and switch-over circuitry

Battery backed output voltage

Battery low detection function

Power-On Reset Override (PORO)

Oscillator stop detection function

Interrupt output (open-drain)

Programmable 1 second or 1 minute interrupt

Programmable watchdog timer with interrupt

Programmable alarm function with interrupt capability

Programmable square output

Clock operating voltage: 1.8 V to 4.2 V

Low supply current: typical 0.70 A at VDD =3.3V

PCA2129T

Accurate RTC with integrated quartz crystal for automotive

Rev. 4 — 11 July 2013 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.

Product data sheet Rev. 4 — 11 July 2013 2 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

3. Applications

Electronic metering for electricity, water, and gas

Precision timekeeping

Access to accurate time of the day

GPS equipment to reduce time to first fix

Applications that require an accurate process timing

Products with long automated unattended operation time

4. Ordering information

4.1 Ordering options

5. Marking

Ta ble 1. Ordering information

Type number Package

Name Description Version

PCA2129T/Q900/2 SO16 plastic small outline package; 16 leads;

body width 7.5 mm SOT162-1

Table 2. Ordering options

Product type number Sales item (12NC) Orderable part number IC

revision Delivery form

PCA2129T/Q900/2 935296923518 PCA2129T/Q900/2,51 2 tape and reel, 13 inch, dry pack

Ta ble 3. Marking codes

Product type number Marking code

PCA2129T/Q900/2 PCA2129T/Q

Product data sheet Rev. 4 — 11 July 2013 3 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

6. Block diagram

Fig 1. Block diagram of PCA2129T

013aaa124

TEMP

VDD

BBS

VBAT

VSS

internal

power

supply

CLKOUT

RPU

INT

OSCI

OSCO

TEMP 1 Hz

32.768 kHz

TCXO

BATTERY BACK UP

SWITCH-OVER

CIRCUITRY

OSCILLATOR

MONITOR

TEMPERATURE

SENSOR

RESET

LOGIC

CONTROL

DIVIDER

AND

TIMER

ADDRESS

Control_1

Control_2

Control_3

00h

01h

02h

Seconds 03h

Minutes 04h

Hours 05h

Days 06h

Weekdays 07h

Months 08h

Years 09h

Second_alarm 0Ah

Minute_alarm 0Bh

Hour_alarm 0Ch

Day_alarm 0Dh

Weekday_alarm 0Eh

CLKOUT_ctl 0Fh

Watchdg_tim_ctl 10h

Watchdg_tim_val 11h

Timestp_ctl 12h

Sec_timestp 13h

Min_timestp 14h

Hour_timestp 15h

Day_timestp 16h

Mon_timestp 17h

Year_timestp 18h

Aging_offset 19h

Internal_reg 1Ah

Internal_reg 1Bh

PCA2129

SCL

SDI

SDO SERIAL BUS

INTERFACE

SELECTOR

SPI-BUS

INTERFACE

I2C-BUS

INTERFACE

SDA/CE

IFS

Product data sheet Rev. 4 — 11 July 2013 4 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

7. Pinning information

7.1 Pinning

7.2 Pin description

Top view. For mechanical details, see Figure 44.

Fig 2. Pin configuration for PCA2129T (SO16)

PCA2129T

SCL V

SDI V

BAT

SDO BBS

SDA/CE INT

IFS n.c.

TS n.c.

CLKOUT n.c.

n.c.

013aaa125

Ta ble 4. Pin description of PCA2129T

Symbol Pin Description

SCL 1 combined serial clock input for both I2C-bus and SPI-bus

SDI 2 serial data input for SPI-bus

connect to pin VSS if I2C-bus is selected

SDO 3 serial data output for SPI-bus, push-pull

SDA/CE 4 combined serial data input and output for the I2C-bus and chip

enable input (active LOW) for the SPI-bus

IFS 5 interface selector input

connect to pin VSS to select the SPI-bus

connect to pin BBS to select the I2C-bus

TS 6 timestamp input (active LOW) with 200 k internal pull-up resistor

(RPU)

CLKOUT 7 clock output (open-drain)

VSS 8 ground supply voltage

n.c. 9 to 12 not connected; do not conn ect; do not use as feed through

INT 13 interrupt output (open-drain; active LOW)

BBS 14 output voltage (battery backed)

VBAT 15 battery supply voltage (backup)

connect to VSS if battery switch over is not used

VDD 16 supply voltage

Product data sheet Rev. 4 — 11 July 2013 5 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8. Functional description

The PCA2129T is a Real Time Clock (RTC) and calendar with an on-chip Temperature

Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated

into the same package (s ee Section 8.3.2).

Address and data are transferred by a selectable 400 kHz Fast-mode I2C-bus or a 3 line

SPI-bus with separate data input and output (see Section 9). The maximum speed of the

SPI-bus is 6.5 Mbit/s.

The PCA2129T has a backup battery input pin and backup battery switch-over circuit

which monitors the main power supply. The backup battery switch-over circuit

automatically switches to the backup battery when a power failure condition is detected

(see Section 8.5.1). Accura te time ke ep in g is ma intained even when the main power

supply is interrupted.

A battery low detection circuit monitors the st atus of the battery (see Section 8.5.3). When

the battery voltage drops below a certain threshold value, a flag is set to indicate that the

battery must be replaced soon. This ensures the integrity of the data during periods of

battery backup.

8.1 Register overview

The PCA2129T contains an auto-incrementing address register: the built-in address

(see Figure 3).

•The first three registers (memory address 00h, 01h, and 02h) are used as control

registers (see Section 8.2).

•The memory addresses 03h through to 09h are used as co unters for the clock

function (seconds up to years). The date is automatically adjusted for months with

fewer than 31 days, including corrections for leap years. The clock can operate in

12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.8).

•The registers at addresses 0Ah through 0Eh define the alarm function. It can be

selected that an interrupt is generated when an alarm event occurs (see Section 8.9).

Fig 3. Handlin g address registers

001aaj398

address register

00h

auto-increment

wrap around

01h

02h

03h

...

19h

1Ah

1Bh

Product data sheet Rev. 4 — 11 July 2013 6 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

•The register at address 0Fh defines the temperature measurement period and the

clock out mode. The temperature measurement can be selected from every 4 minutes

(default) down to every 30 seconds (see Table 10). CLKOUT frequencies of

32.768 kHz (default) down to 1 Hz for use as system clock, microcontroller clock, and

so on, can be chosen (see Table 11).

•The registers at addresses 10h and 11h are used for the watchdog timer functions.

The watchdog timer has four selectable source clocks allowing for timer periods from

less than 1 ms to greater than 4 hours (see Table 33). An interrupt will be generated

when the watchdog times out.

•The registers at addresses 12h to 18h ar e used for the timest a mp function. When the

trigger event happens, the actual time is saved in the timestamp registers (s ee

Section 8.11).

•The register at address 19h is used for the correction of the crystal aging effect (see

Section 8.4.1).

•The registers at addresses 1Ah and 1Bh are for internal use only.

•The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in

Binary Coded Decimal (BCD) format to simplify application use. Other registers are

either bit-wise or standard binary.

When one of the RTC registers is written or read, the content of all counters is temporarily

frozen. This prevents a faulty writing or reading of the clock and calendar during a carry

condition (see Section 8.8.8).

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Product data sheet Rev. 4 — 11 July 2013 7 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

Table 5. Register overview

Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with logic 0. Bits labeled as X are undefined at

power-on and unchanged by subsequent resets.

Address Register name Bit Reset value Reference

76543210

Control registers

00h Control_1 EXT_

TEST TSTOPTSF1POR_

OVRD 12_24 MI SI 0000 0000 Table 6 on page 9

01h Control_2 MSF WDTF TSF2 AF T TSIE AIE T 0000 0000 Table 7 on page 10

02h Control_3 PWRMNG[2:0] BTSE BF BLF BIE BLIE 0000 0000 Table 8 on page 11

Time and date registers

03h Seconds OSF SECONDS (0 to 59) 1XXX XXXX Table 16 on page 23

04h Minutes - MINUTES (0 to 59) - XXX XXXX Table 18 on page 23

05h Hours - - AMPM HOURS (1 to 12) in 12 h mode - - XX XXXX Table 19 on page 24

HOURS (0 to 23) in 24 h mode - - XX XXXX

06h Days - - DAYS (1 to 31) - - XX XXXX Table 20 on page 24

07hWeekdays-----WEEKDAYS (0 to 6) -----XXXTable 21 on page 24

08h Months - - - MONTHS (1 to 12) - - - X XXXX Table 23 on page 25

09h Years YEARS (0 to 99) XXXX XXXX Table 25 on page 25

Alarm registers

0Ah Second_alarm AE_S SECOND_ALARM (0 to 59) 1XXX XXXX Table 26 on page 27

0Bh Minute_alarm AE_M MINUTE_ALARM (0 to 59) 1XXX XXXX Table 27 on page 28

0Ch Hour_alarm AE_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode 1 - XX XXXX Table 28 on page 28

HOUR_ALARM (0 to 23) in 24 h mode 1 - XX XXXX

0Dh Day_alarm AE_D - DAY_ALARM (1 to 31) 1 - XX XXXX Table 29 on page 28

0EhWeekday_alarmAE_W----WEEKDAY_ALARM (0 to 6)1----XXXTable 30 on page 29

CLKOUT control register

0FhCLKOUT_ctlTCR[1:0] ---COF[2:0] 00---000Table 9 on page 12

Watchdog registers

10hWatchdg_tim_ctlWD_CDTTI_TP---TF[1:0] 000---11Table 31 on page 30

11h Watchdg_tim_val WATCHDG_TIM_VAL[7:0] XXXX XXXX Table 32 on page 30

Timestamp registers

12h Timestp_ctl TSM TSOFF - 1_O_16_TIMESTP[4:0] 00 - X XXXX Table 38 on page 35

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Product data sheet Rev. 4 — 11 July 2013 8 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

13h Sec_timestp - SECOND_TIMESTP (0 to 59) - XXX XXXX Table 39 on page 35

14h Min_timestp - MINUTE_TIMESTP (0 to 59) - XXX XXXX Table 40 on page 35

15h Hour_timestp - - AMPM HOUR_TIMESTP (1 to 12) in 12 h mode - - XX XXXX Tab le 41 on page 36

HOUR_TIMESTP (0 to 23) in 24 h mode - - XX XXXX

16h Day_timestp - - DAY_TIMESTP (1 to 31) - - XX XXXX Table 42 on page 36

17h Mon_timestp - - - MONTH_TIMESTP (1 to 12) - - - X XXXX Table 43 on page 36

18h Year_timestp YEAR_TIME STP (0 to 99) XXXX XXXX Table 44 on page 36

Aging offset register

19h Aging_offset - - - - AO[3:0] - - - - 1000 Table 12 on page 14

Internal registers

1AhInternal_reg-----------------

1BhInternal_reg-----------------

Table 5. Register overview …continued

Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with logic 0 . Bits labeled as X are undefined at

power-on and unchanged by subsequent resets.

Address Register name Bit Reset value Reference

76543210

Product data sheet Rev. 4 — 11 July 2013 9 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.2 Control registers

The first 3 registers of the PCA2129T, with the addresses 00h, 01 h, and 02 h, are used as

control registers.

8.2.1 Register Control_1

[1] Default value.

[2] When writing to the register this bit always has to be set logic 0.

Table 6. Control_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 EXT_TEST 0 [1] normal mode Section 8.13

1 external clock test mode

6T 0[2] unused -

5STOP 0[1] RTC source clock runs Section 8.14

1 RTC clock is stopped;

RTC divider chain flip-flops a re

asynchronously set logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz, or

8.192 kHz is still available

4TSF1 0[1] no timestamp interrupt generated Section 8.11.1

1 flag set when TS input is driven to an

intermediate level between power supply and

ground;

flag must be cleared to clear interrupt

3POR_OVRD0[1] Power-On Reset Override (PORO) facility

disabled;

set logic 0 for normal operation

Section 8.7.2

1 Power-On Reset Override (PORO) sequence

reception enabled

2 12_24 0 [1] 24 hour mode selected Table 19

1 12 hour mode selected

1 MI 0 [1] minute interrupt disabled Section 8.12.1

1 minute interrupt enabled

0SI 0[1] second interrupt disabled

1 second interrupt enabled

Product data sheet Rev. 4 — 11 July 2013 10 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.2.2 Register Control_2

[1] Default value.

[2] When writing to the register this bit always has to be set logic 0.

Table 7. Control_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7MSF 0[1] no minute or second interrupt generated Section 8.12

1 flag set when minute or second interrupt

generated;

flag must be cleared to clear interrupt

6WDTF 0[1] no watchdog timer interrupt or reset

generated Section 8.12.3

1 flag set when watchdog timer interrupt or

reset generated;

flag cannot be cleared by command

(read-only)

5TSF2 0[1] no timestamp interrupt generated Section 8.11.1

1 flag set when TS input is driven to ground;

flag must be cleared to clear interrupt

4AF 0[1] no alarm interrupt generated Section 8.9.6

1 flag set when alarm triggered;

flag must be cleared to clear interrupt

3T 0[2] unused -

2TSIE 0[1] no interru pt generated from timestamp flag Section 8.12.5

1 interrupt generated when timestamp flag set

1AIE 0[1] no interrupt generated from the alarm flag Section 8.12.4

1 interrupt generated when alarm flag set

0T 0[2] unused -

Product data sheet Rev. 4 — 11 July 2013 11 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.2.3 Register Control_3

[1] Values see Table 14.

[2] Default value.

Table 8. Control_3 - control and status register 3 (address 02h) bit description

Bit Symbol Value Description Reference

7 to 5 PWRMNG[2:0] [1] control of the battery switch-over, battery low

detection, and extra power fail detection

functions

Section 8.5

4BTSE 0[2] no timestamp when battery switch-over

occurs Section 8.11.4

1 time-stamped when battery switch-over

occurs

3BF 0[2] no battery switch-over interrupt generated Section 8.5.1

and

Section 8.11.4

1 flag set when battery switch-over occurs;

flag must be cleared to clear interrupt

2BLF 0[2] battery status ok;

no battery low interrupt generated Section 8.5.3

1 battery st atus low;

flag cannot be cleared by command

1BIE 0[2] no interrupt generated from the battery

flag (BF) Section 8.12.6

1 interrupt generated when BF is set

0BLIE 0[2] no interrupt ge nerated from battery low

flag (BLF) Section 8.12.7

1 interrupt generated when BLF is set

Product data sheet Rev. 4 — 11 July 2013 12 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.3 Register CLKOUT_ctl

8.3.1 Temperature compensated crystal oscillator

The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the

PCA2129T, the frequency deviation caused by temperat ur e va ria tio n is cor rec te d by

adjusting the load capacitance of the crystal oscillator.

The load cap acitance is changed by switching between two load capacitance values using

a modulation signal with a p rogrammable duty cycle. In order to compensate the spread of

the quartz parameters every chip is fac tory calibrated.

The frequency accuracy can be evaluated by measuring the frequency of the square

wave signal available at the output pin CLKOUT. However, the selection of

fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. Accurate

frequency measurement occurs when fCLKOUT = 16.384 kHz or lower is selected (see

Table 11).

8.3.1.1 Temperature measurement

The PCA2129T has a temperature sensor circuit used to perform the temperature

compensation of the frequency. The temperature is me asured immediately af ter power-on

and then periodica lly with a period set by the temperatur e conversion rate TCR[1:0] in the

[1] Default value.

8.3.2 Clock output

A programmable square wave is available at pin CLKOUT. Operation is contro lled by the

COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down

to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump

input, or for calibrating the oscillator.

CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is

high-impedance.

The duty cycle of the selected clock is not controlled, however, due to the nature of the

clock generation all but the 32.768 kHz frequencies will be 50 : 50.

Table 9. CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description

Bit Symbol Value Description

7 to 6 TCR[1:0] see Table 10 temperature measurement period

5 to 3 - - unused

2 to 0 COF[2:0] see Table 11 CLKOUT frequency selection

Ta ble 10. Te mperature measurement period

TCR[1:0] Temperature measure ment period

00 [1] 4min

01 2 min

10 1 min

11 30 seconds

Product data sheet Rev. 4 — 11 July 2013 13 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default value.

[3] The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to

32.768 kHz or if CLKOUT is disabled.

Ta ble 11. CLKOUT frequency selection

COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1]

000[2][3] 32768 60 : 40 to 40 : 60

001 16384 50 : 50

010 8192 50 : 50

011 4096 50 : 50

100 2048 50 : 50

101 1024 50 : 50

110 1 50 : 50

111 CLKOUT = high-Z -

Product data sheet Rev. 4 — 11 July 2013 14 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.4 Register Aging_offset

8.4.1 Crystal aging correction

The PCA2129T has an offset register Aging_offset to correct the crystal aging effects2.

The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset

adds an adjustment, positive or negative, in the temperature compensation circuit which

allows correcting the aging effect.

At 25 C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0]

value, from 7 ppm to +8 ppm.

[1] Default value.

Ta ble 12. Aging_offset - crystal aging offset register (address 19h ) b it de scription

Bit Symbol Value Description

7 to 4 - - unused

3 to 0 AO[3:0] see Table 13 aging offset value

2. For further information, refer to the application note Ref. 3 “AN11120”.

Ta ble 13. Frequency correction at 25C, typical

AO[3:0] ppm

Decimal Binary

00000+8

10001+7

20010+6

30011+5

40100+4

50101+3

60110+2

70111+1

81000

[1] 0

910011

10 1010 2

11 1011 3

12 1100 4

13 1101 5

14 1110 6

15 1111 7

Product data sheet Rev. 4 — 11 July 2013 15 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.5 Power management functions

The PCA2129T has two power supply pins and one power output pin:

•VDD - the main power supply input pin

•VBAT - the battery backup input pin

•BBS - battery backed output voltage pin (equal to the internal power supply)

The PCA2129T has two power management functions imp lemented:

•Battery switch-over function

•Battery low detection function

The power management functions are controlled by the contr ol bits PWRMNG[2:0] in

[1] Default value.

[2] When the battery switch-over function is disabled, the PCA2129T works only with the power supply VDD.

VBAT must be put to ground and the battery low detection function is disabled.

8.5.1 Battery switch-over function

The PCA2129T has a backup battery switch-over circuit which monitors the main power

supply VDD. When a power failure condition is detected, it automatically switches to the

backup battery.

One of two operation modes can be selected:

•Standard mode: the power failure condition happens when:

VDD < VBAT AND VDD <V

th(sw)bat

Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. The battery

switch-over in standard mode works only for VDD > 2.5 V.

•Direct switching mode: the power failure condition happe ns when V DD < VBAT.

Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat

Ta ble 14. Power management control bit description

PWRMNG[2:0] Function

000 [1] battery switch-over function is enabled in standard mode;

battery low detection function is enabled

001 battery switch-over function is enabled in standard mode;

battery low detection function is disabled

010 battery switch-over function is enabled in standard mode;

battery low detection function is disabled

011 battery switch-over function is enabled in direct switching mode ;

battery low detection function is enabled

100 battery switch-over function is enabled in direct switching mode;

battery low detection function is disabled

101 battery switch-over function is enabled in direct switching mode;

battery low detection function is disabled

111 [2] battery switch-over function is disabled, only one power supply (VDD);

battery low detection function is disabled

Product data sheet Rev. 4 — 11 July 2013 16 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

When a power failure condition occurs and the power supply switche s to th e ba tt er y, the

following sequence occurs:

1. The battery switch flag BF (register Control_3) is set logic 1.

2. An interrupt is generated if the control bit BIE (register Control_3) is enabled

(see Section 8.12.6).

3. If the control bit BTSE (register Control_3) is logic 1, the timest amp register s store the

time and date when the battery switch occurred (see Section 8.11.4).

4. The battery switch flag BF is cleared by command; it must be cleared to clear the

interrupt.

The interface is disabled in battery backup operation:

•Interface inputs are not recognized, preventing extraneous data being written to the

device

•Interface outputs are high-impedance

8.5.1.1 Standard mode

If VDD > VBAT OR VDD >V

th(sw)bat, the internal power supply is VDD.

If VDD < VBAT AND VDD <V

th(sw)bat, the internal power supply is VBAT.

8.5.1.2 Direct switching mode

If VDD > VBAT the internal power supply is VDD.

If VDD < VBAT the internal power supply is VBAT.

Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the

battery switch-over works only for VDD > 2.5 V.

VDD may be lower than VBAT (for example VDD =3V, V

BAT =4.1V).

Fig 4. Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled)

001aaj311

internal power supply (= V

BBS

)

cleared via interface

backup battery operation

th(sw)bat

(= 2.5 V)

(= 0 V)

BAT

BBS

INT

Product data sheet Rev. 4 — 11 July 2013 17 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The direct switching mode is useful in systems where VDD is higher th an VBAT at all times.

This mode is not recommended if the VDD and VBAT values are similar (for example,

VDD = 3.3 V, VBAT 3.0 V). In direct switching mode, the power consumption is reduced

compared to the standard mode beca use the monitori ng of V DD and Vth(sw)bat is not

performed.

8.5.1.3 Battery switch-over disabled: only one power supply (VDD)

When the battery switch-over function is disabled:

•The power supply is applied on the VDD pin

•The VBAT pin must be conn ected to groun d

•The internal power supply, available at the output pin BBS, is equal to VDD

•The battery flag (BF) is always logic 0

8.5.1.4 Battery switch-over architecture

The architecture of the battery switch-over circuit is shown in Figure 6.

Fig 5. Battery switch-over behavior in direct switching mode with bit BIE set logic 1

(enabled)

001aaj312

internal power supply (= V

BBS

)

cleared via interface

backup battery operation

th(sw)bat

(= 2.5 V)

(= 0 V)

BAT

BBS

INT

Product data sheet Rev. 4 — 11 July 2013 18 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The internal power supply (available on pin BBS) is equal to VDD or VBAT. It has to be

assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS.

8.5.2 Battery backup supply

The VBBS voltage on the output pin BBS is equal to the internal power supply, depending

on the selected battery switch-over function mode:

Fig 6. Battery switch-over circuit, simplified block diagram

001aag061

th(sw)bat

BBS

(internal

power supply)

DD(int)

BAT

LOGIC

comparators logic switches

th(sw)bat

BAT

Ta ble 15. Output pin BBS

Battery switch-over function mode Conditions VBBS equals

standard VDD > VBAT OR VDD > Vth(sw)bat VDD

VDD < VBAT AND VDD < Vth(sw)bat VBAT

direct switching VDD > VBAT VDD

VDD < VBAT VBAT

disabled only VDD available,

VBAT must be put to ground VDD

Fig 7. Typical driving capability of VBBS: (VBBS  VDD) with respect to the output load

current IBBS

IBBS (mA)

0 8642

001aaj327

−400

−600

−200

VBBS − VDD

(mV)

−800

VDD = 4.2 V

VDD = 3 V

VDD = 2 V

Product data sheet Rev. 4 — 11 July 2013 19 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The output pin BBS can be used as a supply for external devices with battery backup

needs, such as SRAM (see Ref. 3 “AN11120”). For this case, Figure 7 shows the typical

driving capability when VBBS is driven from VDD.

8.5.3 Battery low detection function

The PCA2129T has a batter y low detection circui t which monitors the st atus of the batte ry

VBAT.

When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag

(register Control_3) is set to indicate that the battery is low and that it must be replaced.

Monitoring of the battery voltage also occurs during battery operation.

An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical

1.2 V) and with that the data integrity gets lost.

When VBAT drop s below the threshold value Vth(bat)low, the following sequence occurs (see

Figure 8):

1. The battery low flag BLF is set logic 1.

2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled

(see Section 8.12.7).

3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by

command. It is cleared automatically by the battery low detection circuit when the

battery is replaced.

Fig 8. Battery low detection behavior with bit BLIE set logic 1 (enabled)

001aaj322

internal power supply (= V

BBS

)

BAT

BLF

th(bat)low

(= 2.5 V)

BAT

= V

BBS

INT

Product data sheet Rev. 4 — 11 July 2013 20 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.6 Oscillator stop detection function

The PCA2129T has an on-chip oscillator detection circuit which monitors the status of the

oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF

(in register Seconds) is set logic 1.

•Power-on:

a. The oscillator is not running, the chip is in reset (OSF is logic 1).

b. When the oscillator starts running and is stable after power-on, the chip exits from

reset.

c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

•Power supply failure:

a. When the power su pply of the chip (VBBS, see Section 8.5.2) drops belo w a certain

value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs.

b. When the power supply returns to normal operation, the oscillator starts running

again, the chip exits from reset.

c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

(1) Theoretical state of the signals since there is no power.

(2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has

occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock

information is not guaranteed. The OSF flag is cleared by command.

Fig 9. Power failure event due to battery discharge: reset occurs

001aaj409

internal power supply

(1)

Vth(sw)bat

(= 2.5 V)

VSS

VBAT

Vlow

(= 1.2 V)

VDD

VBBS

VDD

VBAT

VSS

(2)

OSF

battery discharge

Product data sheet Rev. 4 — 11 July 2013 21 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.7 Reset function

The PCA2129T has a Power-On Reset (POR) and a Power-On Reset Override (PORO)

function implemented.

8.7.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is also considered to

be stopped during the time between power-on and stable cryst al resonance (see

Figure 10). This time may be in the range of 20 0 ms to 2 s depending on temperatur e and

supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set

logic 1).

After POR, the following mode is entered:

•32.768 kHz CLKOUT active

•Power-On Reset Override (PORO) available to be set

•24 hour mode is selected

•Battery switch-over is enabled

•Battery low detection is enabled

The register values after power-on are shown in Table 5.

8.7.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and therefore speed up the on-board te st of th e de vice .

Fig 10. Depend e nc y between POR and oscillator

001aaf897

chip in reset chip not in reset

VDD

oscillation

internal

reset

Fig 11. Power-On Reset (POR) system

001aaj324

OSCILLATOR

0 = override inactive

1 = override active

0 = clear override mode

1 = override possible

POR_OVRD

SDA/CE

SCL RESET

OVERRIDE

CLEAR

osc stopped

0 = stopped, 1 = running reset

Product data sheet Rev. 4 — 11 July 2013 22 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The setting of the PORO mode requires that POR_OVRD in register Control_1 is set

logic 1 and that the signals at the inte r fa ce pin s SDA/CE and SCL are toggled as

illustrated in Figure 12. All timings shown are re quired minimum.

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be

logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0

during normal operation has no effect except to prevent accidental entry into the PORO

mode.

Fig 12. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus

001aaj326

minimum 2000 nsminimum 500 ns8 ms

power up

SCL

reset override

SDA/CE

Product data sheet Rev. 4 — 11 July 2013 23 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.8 T ime and date function

Most of these registers are coded in the Binary Coded Decimal (BCD) format.

8.8.1 Register Seconds

[1] Start-up value.

8.8.2 Register Minutes

Ta ble 16. Seconds - seconds and clock integrity register (address 03h) bit description

Bit Symbol Value Place value Description

7 OSF 0 - clock integrity is guaranteed

1[1] - clock integrity is not guaranteed:

oscillator has stopped and chip reset

has occurred since flag was last cleared

6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format

3to0 0to9 unit place

Ta ble 17. Seconds code d in BCD format

Seconds val ue in

decimal Upper-digit (ten’s place) Digit (unit place)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 0000000

01 0000001

02 0000010

: :::::::

09 0001001

10 0010000

: :::::::

58 1011000

59 1011001

Table 18. Minutes - minutes register (address 04h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 MINUTES 0 to 5 ten’ s place actual minutes coded in BCD format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 24 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.8.3 Register Hours

[1] Hour mode is set by the bit 12_24 in register Control_1.

8.8.4 Register Days

[1] If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC

compensates for leap years by adding a 29th day to February.

8.8.5 Register Weekdays

Although the association of the weekdays counter to the actual weekday is arbitrary, the

PCA2129T will assume that Sunday is 000 and Monday is 001 for the purposes of

determining the increment for calendar weeks.

[1] Definition may be reassigned by the user.

Ta ble 19. Hours - hours register (address 05h) bit descriptio n

Bit Symbol Value Place value Description

7to6 - - - unused

12 hour mode[1]

5 AMPM 0 - indicates AM

1 - indicates PM

4 HOURS 0 to 1 ten’s place actual hours coded in BCD format when in

12 hour mode

3to0 0to9 unit place

24 hour mode[1]

5 to 4 HOURS 0 to 2 ten’ s place actual hours coded in BCD format when in

24 hour mode

3to0 0to9 unit place

Ta ble 20. Days - days register (address 06h) bit description

Bit Symbol Value Place value Description

7to6 - - - unused

5to4 DAYS

[1] 0 to 3 ten’s place actual day coded in BCD format

3to0 0to9 unit place

Ta ble 21. Weekdays - weekdays register (address 07h ) bit de scription

Bit Symbol Value Description

7to3 - - unused

2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 22

Ta ble 22. Weekday assignments

Day[1] Bit

210

Sunday 0 0 0

Monday 0 0 1

Tuesday 0 1 0

Wednesday 0 1 1

Thursday 1 0 0

Friday 1 0 1

Saturday110

Product data sheet Rev. 4 — 11 July 2013 25 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.8.6 Register Months

8.8.7 Register Years

8.8.8 Setting and reading the time

Figure 13 shows the data flow and data dependencies starting from the 1 Hz clock tick.

During read/write operations, the time counting circuits (memory locations 03h through

09h) are blocked.

This prevents

•Faulty reading of the clock and calenda r dur ing a carr y con d itio n

•Incrementing the time registers during the read cycle

Ta ble 23. Months - months register (address 08h) bit des cription

Bit Symbol Value Place value Description

7to5 - - - unused

4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see

Table 24

3to0 0to9 unit place

Table 24. Month assignments in BCD format

Month Upper-digit

(ten’s place) Digit (unit place)

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January 0 0 0 0 1

February 0 0 0 1 0

March 0 0 0 1 1

April00100

May00101

June00110

July00111

August01000

September 0 1 0 0 1

October10000

November10001

December10010

Table 25. Years - years register (address 09h) bit desc ription

Bit Symbol Value Place value Description

7 to 4 YEARS 0 to 9 ten’s place actual year coded in BCD format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 26 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

After this read/write access is completed, the time circuit is released again. Any pending

request to increment the time counters that occurred during the read/write access is

serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed withi n 1 se con d (s ee Figure 14).

As a consequence of this method, it is very important to make a read or write access in

one go, that is, setting or reading seconds th ro ugh to ye ar s should be mad e in one single

access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time may increment between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next. Therefore it is

advised to read all time and date registers in one access.

Fig 13. Data flow of the time function

Fig 14. Access time for read/write operations

001aaf901

1 Hz tick

12_24 hour mode

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR

CALCULATION

MONTHS

YEARS

t < 1 s

013aaa215

SLAVE ADDRESS DATA STOPDATA

START

Product data sheet Rev. 4 — 11 July 2013 27 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.9 Alarm function

When one or mor e of the alarm bit fields ar e loaded with a valid second, minute, h our , day,

or weekday and it s corresp onding alarm enable bit (AE_x) is log ic 0, then that informatio n

is compared with the actual second, minute, hour, day, and weekday (see Figure 15).

The generation of interrupts from the alarm function is described in Section 8.12.4.

8.9.1 Register Second_alarm

[1] Default value.

(1) Only when all enabled alarm settings are matching.

Fig 15. Alarm functio n blo c k dia g ram

013aaa236

WEEKDAY ALARM

AE_W

WEEKD AY TIME

DAY ALARM

AE_D

D AY TIME

HOUR ALARM

AE_H

HOUR TIME

MINUTE ALARM

check now signal

set alarm flag AF (1)

AE_S = 1

example

AE_M

MINUTE TIME

SECOND TIME

SECOND ALARM

AE_S

Ta ble 26. Second_alarm - se cond alarm register (addres s 0Ah) bit description

Bit Symbol Value Place value Description

7 AE_S 0 - second alarm is enabled

1[1] - second alarm is disabled

6 to 4 SECOND_ALARM 0 to 5 ten’s place second alarm information coded in BCD

format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 28 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.9.2 Register Minute_alarm

[1] Default value.

8.9.3 Register Hour_alarm

[1] Default value.

[2] Hour mode is set by the bit 12_24 in register Control_1.

8.9.4 Register Day_alarm

[1] Default value.

Ta ble 27. Minute_alarm - minute alarm reg ister (address 0Bh) bit descr iption

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

1[1] - minute alarm is disabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute al arm information coded in BCD

format

3to0 0to9 unit place

Table 28. Hour_alarm - hour alarm register (address 0Ch) bit description

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

1[1] - hour alarm is disabled

6 - - - unused

12 hour mode[2]

5 AMPM 0 - indicates AM

1 - indicates PM

4 HOUR_ALARM 0 to 1 ten’s place hour alarm information coded in BCD

format when in 12 hour mode

3to0 0to9 unit place

24 hour mode[2]

5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD

format when in 24 hour mode

3to0 0to9 unit place

Ta ble 29. Day_alarm - day alarm register (address 0Dh) bit description

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

1[1] - day alarm is disabled

6 - - - unused

5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm info rmation coded in BCD

format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 29 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.9.5 Register Weekday_alarm

[1] Default value.

8.9.6 Alarm flag

When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.

AF will remain set until cleared by command. Once AF has been cleared, it will only be set

again when the time incr ement s to match the alarm con dition once more . For clearin g the

flags. see Section 8.10.5

Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.

Ta ble 30. Weekday_alarm - weekday alarm register (address 0Eh) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1[1] weekday alarm is disabled

6to3 - - unused

2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 16. Alarm flag timing diagram

001aaf903

44 45

45minute alarm

minutes counter

INT when AIE = 1

Product data sheet Rev. 4 — 11 July 2013 30 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.10 T imer functions

The PCA2129T has a watchdog timer function. The timer can be switched on and off by

using the control bit WD_CD in the register Watchdg_tim_ctl.

The watchdog timer has four selectable source clocks. It can, for example, be used to

detect a microcontroller with interrupt and reset capability which is out of control (see

Section 8.10.3)

To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl,

and Wa tch d g_t im _v al ar e us ed .

8.10.1 Register Watchdg_tim_ctl

[1] Default value.

[2] When writing to the register this bit always has to be set logic 0.

8.10.2 Register Watchdg_tim_val

Table 31. Watchdg_tim_ctl - watchdog time r control register (address 10h) bit description

Bit Symbol Value Description

7 WD_CD 0[1] watchdog timer di sabled

1 watchdog timer enabled;

the interrupt pin INT is activated when timed out

6T 0

[2] unused

5TI_TP 0

[1] the interrupt pin INT is configured to gene rate a

permanent active signal when MSF (register Con trol _2)

is set

1 the interrupt pin INT is configured to generate a pulsed

signal when MSF flag is set (see Figure 19)

4to2 - - unused

1 to 0 TF[1:0] timer source clock for watchdog timer

00 4.096 kHz

01 64 Hz

10 1 Hz

11[1] 1⁄60 Hz

Ta ble 32. Watchdg _tim_val - watchdog timer value register (address 11h) bit descriptio n

Bit Symbol Value Description

7 to 0 WATCHDG_TIM_VAL[7:0] 00 to FF timer period in seconds:

where n is the time r val u e

TimerPeriod n

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 4 — 11 July 2013 31 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.10.3 Watchdog timer function

The watchdog timer function is enabled or disabled by the WD_CD bit of the register

Watchdg_tim_ctl (see Table 31).

The two bits TF[1:0] in register Watchdg_ tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz (see Table 33).

When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val

determines the watchdog timer period (see Table 33).

The watchdog timer counts down from the software programmed 8-bit binary value n in

(register Control_2) is set logic 1 and an interrupt will be generated.

The counter does not automatically reload.

When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)

loads a watchdog timer value n, then:

•the flag WDTF is reset

•INT is cleared

•the watchdog timer starts again

Loading the counter with 0 will:

•reset the flag WDTF

•clear INT

•stop the watchdog timer

Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared

by:

•loading a value in register W atchdg_tim_val

•reading of the register Control_2

Writing a logic 0 or logic 1 to WDTF has no effect.

Table 33. Programmabl e wa tc hd og time r

TF[1:0] Timer source

clock frequenc y Units Minimum timer

period (n = 1) Units Maximum timer

period (n = 255) Units

00 4.096 kHz 244 s 62.256 ms

01 64 Hz 15.625 ms 3.984 s

10 1 Hz 1 s 255 s

11 1⁄60 Hz 60 s 15300 s

Product data sheet Rev. 4 — 11 July 2013 32 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

•When the watchdog tim er counter reaches 1, the watchdog timer flag WDTF (register

Control_2) is set logic 1

•When a minute or second interrupt occurs, the minute/second flag MSF (register

Control_2) is set logic 1 (see Section 8.12.1).

8.10.4 Pre-defined timers: second and minute interrupt

PCA2129T has two pre-defined timers which are used to generate an interrupt either once

per second or once per minute. The pulse generator for the minute or second interrupt

operates from an internal 64 Hz clock. It is independent of the watchdog timer. Each of

these timers can be enabled by the bits SI (second interrupt) and MI ( minute interrupt) in

8.10.5 Clearing flags

The flags MSF, AF, and TSFx can be cleared by command. To prevent one flag being

overwritten while clearing another, a logic AND is performed during the write access. A

flag is cleared by writing logic 0 while a flag is not cleared by writing logic 1. Writing logic 1

will result in the flag value remaining unchanged.

Two examples ar e giv en for cleari ng the flag s. Cle ar ing a flag is mad e by a writ e

command:

•Bits labeled with - must be written with their previous values

•Bits labeled with T have to be written with logic 0

•WDTF is read only and has to be written with logic 0

Repeatedly rewriting these bits has no influence on the functional behavior.

Counter reached 1, WDTF is logic 1, and an interrupt is generated.

Fig 17. WD_CD set logic 1: watchdog activates an interrupt when timed out

001aag062

watchdog

timer value

WDTF

n = 1 n

MCU

INT

Table 34. Flag location in register Control_2

76543210

Control_2 MSF WDTF TSF2 AF T - - T

Product data sheet Rev. 4 — 11 July 2013 33 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The following tables show what instruction must be sent to clear the appropriate flag.

[1] The bits labeled as - have to be rewritten with the previous values.

Ta ble 35. Example values in register Control_2

76543210

Control_210110000

Table 36. Example to clear only AF (bit 4)

76543210

Control_2 1 0 1 0 0 0[1] 0[1] 0

Table 37. Example to clear only MSF (bit 7)

76543210

Control_2 0 0 1 1 0 0[1] 0[1] 0

Product data sheet Rev. 4 — 11 July 2013 34 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.11 Timestamp function

The PCA2129T has an active LOW timestamp input pin TS, internally pulled with an

on-chip pull-up resistor to the internal powe r supply of the de vice. It a lso ha s a time stamp

detection circuit which can detect two different events:

1. Input on pin TS is driven to an intermediate level between power supply and ground.

2. Input on pin TS is driven to ground.

The timestamp function is enabled by defa ult af ter powe r-on and it can be switched off by

setting the control bit TSOFF (reg iste r Timestp_ctl).

A most common application of the timestamp function is described in Ref. 3 “AN11120”.

See Section 8.12.5 for a description of interrupt generation from the timestamp function.

8.11.1 Timestamp flag

1. When the TS input pin is driven to an intermediate level between the power supply

and ground, then the following sequence occurs:

a. The actual date and time are stored in the timestamp registers.

b. The timestamp flag TSF1 (register Control_1) is set.

c. If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is

generated.

The TSF1 flag can be cleared by command. Clearing the flag will clear the interrupt.

Once TSF1 is cleared, it will only be set again when a new negative edge on pin TS is

detected.

2. When the TS input pin is driven to ground, the following sequence occurs:

a. The actual date and time are stored in the timestamp registers.

b. In addition to the TSF1 flag, the TSF2 flag (register Control_2) is set.

c. If the TSIE bit is active, an interrupt on the INT pin is generated.

Fig 18. Timestamp detection with two push-buttons on the TS pin (for example, for

tamper detection)

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Product data sheet Rev. 4 — 11 July 2013 35 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The TSF1 and TSF2 flags can be cleared by command; clearing both flags will clear

the interrupt. Once TSF2 is cleared, it will only be set again when TS pin is driven to

ground once again.

8.11.2 Timestamp mode

The timestamp function has two different modes selected by the control bit TSM

(timestamp mode) in register Timestp_ctl:

•If TSM is logic 0 (default) : in subsequent trigger event s without clearing the timest amp

flags, the last timestamp event is stored

•If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags,

the first timestamp event is stored

The timestamp function also depends on the control bit BTSE in register Control_3, see

Section 8.11.4.

8.11.3 Timestamp registers

8.11.3.1 Register Timestp_ctl

[1] Default value.

8.11.3.2 Register Sec_timestp

8.11.3.3 Register Min_timestp

Ta ble 38. Timestp_ctl - timestamp con t rol register (address 12h) bit description

Bit Symbol Value Description

7TSM 0

[1] in subsequent events without clearing the timestamp

flags, the last event is stored

1 in subsequent events without clearing the timestamp

flags, the first event is stored

6TSOFF 0

[1] timestamp function active

1 timestamp function disable d

5 - - unused

4 to 0 1_O_16_TIMESTP[4:0] 1⁄16 second timestamp information coded in BCD format

Ta ble 39. Sec_timestp - second time stamp register (address 13h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 SECOND_TIMESTP 0 to 5 ten’s place second timestamp information coded in

BCD format

3to0 0to9 unit place

Table 40. Min_timestp - minute timestamp register (address 14h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 MINUTE_TIMESTP 0 to 5 ten’s place minute timestamp information coded in

BCD format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 36 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.11.3.4 Register Hour_timestp

[1] Hour mode is set by the bit 12_24 in register Control_1.

8.11.3.5 Register Day_timestp

8.11.3.6 Register Mon_timestp

8.11.3.7 Register Year_timestp

Table 41. Hour_timestp - hour timestamp register (address 15h) bit descriptio n

Bit Symbol Value Place value Description

7to6 - - - unused

12 hour mode[1]

5 AMPM 0 - indicates AM

1 - indicates PM

4 HOUR_TIMESTP 0 to 1 ten’ s place hour timestamp information coded in BCD

format when in 12 hour mode

3to0 0to9 unit place

24 hour mode[1]

5 to 4 HOUR_TIMESTP 0 to 2 ten’ s place hour timestamp information coded in BCD

format when in 24 hour mode

3to0 0to9 unit place

Ta ble 42. Day_timestp - day timestamp register (address 16h) bit description

Bit Symbol Value Place value Description

7to6 - - - unused

5 to 4 DAY_TIMESTP 0 to 3 ten’s place day timestamp information coded in BCD

format

3to0 0to9 unit place

Ta ble 43. Mon_timestp - month timestamp register (address 17h) bit description

Bit Symbol Value Place value Description

7to5 - - - unused

4 MONTH_T IMESTP 0 to 1 ten’s place month timestamp informa ti on coded in

BCD format

3to0 0to9 unit place

Ta ble 44. Year_timestp - year timestamp register (address 18h) bit description

Bit Symbol Value Place value Description

7 to 4 YEAR_TIMESTP 0 to 9 ten’s place year timestamp information coded in BCD

format

3to0 0to9 unit place

Product data sheet Rev. 4 — 11 July 2013 37 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.11.4 Dependency between Battery switch-over and timestamp

The timestamp function depends on the control bit BTSE in register Control_3:

[1] Default value.

Ta ble 45. Battery switch-over and timestamp

BTSE BF Description

0- [1] the battery switch-over does not affect the timestamp registers

1 If a battery switch-over event occurs:

0[1] the timestamp registers store the time and date when the switch-over occurs;

after this event occurred BF is set logic 1

1 the timestamp registers are not modified;

in this condition subsequent battery switch-over events or falling edges on pin

TS are not re gi st ere d

Product data sheet Rev. 4 — 11 July 2013 38 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.12 Interrupt output, INT

PCA2129T has an interrupt output pin INT which is open-drain, active LOW (requir ing a

pull-up resistor if used). Interrupts may be sourced from differen t places:

•second or minute timer

•watchdog timer

•alarm

•timestamp

•battery switch-over

•battery low detection

When SI, MI, WD_CD, AIE, TSIE, BIE, BLIE are all disabled, INT will remain high-impedance (output HIGH).

Fig 19. Interrupt block diagr am

BLF: BATTERY

LOW FLAG

SET

set battery

low flag, BLF

to interface:

read BLF BLIE

001aaj399

from battery

low detection

circuit: clear BF

CLEAR

BF: BATTERY

FLAG

SET

set battery

flag, BF

to interface:

read BF BIE

from interface:

clear BF

CLEAR

TSFx: TIMESTAMP

FLAG

SET

set timestamp

flag, TSFx

to interface:

read TSFx TSIE

from interface:

clear TSF

CLEAR

AF: ALARM

FLAG

SET

set alarm

flag, AF

to interface:

read AF AIE

from interface:

clear AF

CLEAR

WDTF:

WATCHDOG

TIMER FLAG

SET

WATCHDOG

COUNTER

to interface:

read WD_CD WD_CD = 0

WD_CD = 1

MCU loading

watchdog counter

CLEAR

INT pin

MSF:

MINUTE

SECOND FLAG

SET

MINUTES COUNTER

SECONDS COUNTER to interface:

read MSF SI/MI

TI_TP

from interface:

clear MSF

CLEAR

PULSE

GENERATOR 1

TRIGGER

CLEAR

Product data sheet Rev. 4 — 11 July 2013 39 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the

interrupts generated from the second/minute timer (flag MSF in register Control_2) are

pulsed signals or a permanently active signal. All the other interrupt sources generate a

permanently active interrupt signal which follows the status of the corresponding flags.

When the interrupt sources are all disabled, INT remains high-impedance.

•The flags MSF, AF, TSFx, and BF can be cleared by command.

•The flag WDTF is read only. How it can be cleared is explained in Section 8.10.5.

•The flag BLF is read only. It is cleared automatically from the battery low detection

circuit when the battery is replaced.

8.12.1 Minute and second interrupts

Minute and second interrupts are generated by predefined timers. The timers can be

enabled independently from one another by the bits MI and SI in register Control_1.

However, a minute interrupt enabled on top of a second interrupt will not be

distinguishable since it will occur at the same time.

The minute/second flag MSF (re gister Control_2) is set lo gic 1 when either the seco nds or

the minutes counter increments according to the enabled interrupt (see Table 46). The

MSF flag can be cleared by command.

When MSF is set logic 1:

•If TI_TP is logic 1, the interrupt is generated as a pulsed signal.

•If TI_TP is logic 0, the interrupt is permanently active signal that remains until MSF is

cleared.

Table 46. Effect of bits MI and SI on pin INT and bit MSF

MI SI Result on INT Result on MSF

0 0 no interrupt generated MSF never set

1 0 an interrupt once per minute MSF set when minutes counter increments

0 1 an interrupt once per second MSF set when seconds counter increments

1 1 an interrupt once per second MSF set when seconds counter increments

In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt.

Fig 20. INT example for SI and MI when TI_TP is logic 1

001aaf905

58 59 59 00

seconds counter

minutes counter

INT when SI enabled

MSF when SI enabled

INT when only MI enabled

MSF when only MI enabled

00 01

Product data sheet Rev. 4 — 11 July 2013 40 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The pulse generator for the minute /second interrupt operates from an internal 64 Hz clock

and generates a pulse of 1⁄64 seconds in duration.

8.12.2 INT pulse shortening

If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the

INT pulse is shortened. This allows the source of a system interrupt to be cleared

immediately when it is serviced, that is, the system does not have to wait for the

completion of the pu lse bef ore co nt inu i ng; se e Figure 22. Instructions for clearing the bit

MSF can be found in Section 8.10.5.

8.12.3 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD bit

(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows

the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is

possible for watchdog timer interrupts.

In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.

Fig 21. INT example for SI and MI when TI_TP is logic 0

001aag072

58seconds counter

minutes counter

INT when SI enable

MSF when SI enable

INT when only MI enabled

MSF when only MI enabled

59 59

00 00 01

(1) Indicates normal duration of INT pulse.

The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is,

when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic

Fig 22. Example of shortening the INT pulse by clearing th e MSF flag

001aaf908

58seconds counter

MSF

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

(1)

Product data sheet Rev. 4 — 11 July 2013 41 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot

be cleared by command. Instructions for clearing it can be found in Section 8.10.5.

8.12.4 Alarm interrupts

Generation of interrupts from the alarm function is controlled by the bit AIE (register

Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register

Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for

alarm interrupts.

8.12.5 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE bit (register

Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing

the flags TSFx immediately clears INT. No pulse generation is possible for timestamp

interrupts.

8.12.6 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled by the BIE bit (register

Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3

(see Table 45). Clearing BF immediately clears INT. No pulse generation is possible for

battery switch-over interrupts.

8.12.7 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled by the BLIE bit

(register Control_3). If BLIE is enabled, the INT pin will follow the status of bit BLF

(register Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0)

or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be

cleared by command.

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 23. AF timing diag ram

001aaf910

minute counter

minute alarm

INT

SCL

instruction

CLEAR INSTRUCTION

8th clock

Product data sheet Rev. 4 — 11 July 2013 42 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.13 External clock test mode

A test mode is available which allows on-board testing. In this mode, it is possible to set

up test condition s an d co nt ro l the op e ratio n of th e RTC.

The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)

with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down by a 26divider chain called prescaler (see Table 47). The prescaler can be set into a

known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0.

STOP must be cleared before the pres caler can operate again.

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operating ex am p le:

1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

2. Set bit STOP (register Control_1, STOP is logic 1).

3. Set time registers to desired value.

4. Clear STOP (register Control_1, STOP is logic 0).

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Product data sheet Rev. 4 — 11 July 2013 43 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

8.14 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuit s. ST OP will

cause the upper part of the prescaler (F9 to F14) to be held in r eset and thu s no 1 Hz ticks

are generated. The time circuits can then be set and will not increment until the STOP bit

is released. STOP will not affect the CLKOUT signal but the output of the prescaler in the

range of 32 Hz to 1 Hz (see Figure 24).

The lower st ages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the

SPI-bus are asynchronous to the crystal oscillator, the accuracy of restarting the time

circuits is b etween 0 and one 64 Hz cycle (0.48 43 75 s and 0.500000 s), see Table 47 and

Figure 25.

[1] F0 is clocked at 32.768 kHz.

Table 47. First increment of time circuits after stop release

Bit

STOP Prescaler bits[1]

F0 to F8 - F9 to F14

1Hz tick Time

hh:mm:ss Comment

Clock is running normally

010000111-010100

12:45:12 prescaler counting normally

STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally

xxxxxxxxx-000000

12:45:12 prescaler is reset; ti me circuits are frozen

New time is set by user

xxxxxxxxx-000000

08:00:00 prescaler is reset; ti me circuits are frozen

STOP bit is released by user

xxxxxxxxx-000000

08:00:00 prescaler is now running

xxxxxxxxx-100000

08:00:00

xxxxxxxxx-100000

08:00:00

xxxxxxxxx-110000

08:00:00

:: :

111111111-111110

08:00:00

000000000-000001

08:00:01 0 to 1 transition of F14 increments the time circuits

100000000-000001

08:00:01

:: :

111111111-111111

08:00:01

000000000-000000

08:00:01

100000000-000000

:: :

111111111-111110

08:00:01

000000000-000001

08:00:02 0 to 1 transition of F14 increments the time circuits

001aaj479

0.484375 - 0.500000 s

1 s

Product data sheet Rev. 4 — 11 July 2013 44 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

Fig 24. STOP bit functional diagram

001aaj342

OSC

32768 Hz

16384 Hz

8192 Hz

4096 Hz

128 Hz

RES

64 Hz

RES

F10

LOWER PRESCALER UPPER PRESCALER

RES

F13

RES

stop

1 Hz tick

F14

Fig 25. STOP bit release timing

001aaj343

0 ms - 15.625 ms

64 Hz

stop released

Product data sheet Rev. 4 — 11 July 2013 45 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

9. Interfaces

The PCA2129T has an I2C- bus or SPI-bus interface using the same pins. The selection is

done using the interface selection pin IFS (see Table 48).

Table 48. Interface selection input pin IFS

Pin Connection Bus interface Reference

IFS VSS SPI-bus Section 9.1

BBS I2C-bus Section 9.2

To select the SPI-bus interface, pin IFS has to be

connected to pin VSS. To select the I2C-bus interface, pin IFS has to be

connected to pin BBS.

a. SPI-bus interface selection b. I2C-bus interface selection

Fig 26. Interface selection

013aaa127

BBS

SCL

PCA2129

SDI 15

SDO 14

SDA/CE 13

IFS 12

611

710

SDO

SDI

SCL

013aaa128

BBS

SCL 16

PCA2129

SDI 15

SDO 14

SDA/CE 13

IFS 12

611

710

SDA

SCL

RPU

Product data sheet Rev. 4 — 11 July 2013 46 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

9.1 SPI-bus interface

Data tr ansfer to an d from the device is made by a 3 line SPI-bus (see Table 49). The dat a

lines for input and output are split. The data input and output line can be connected

together to facilitate a bidirectional data bus (see Figure 27). The SPI-bus is initialized

whenever the chip enable line pin SDA/CE is inactive.

[1] The chip enable must not be wired permanently LOW.

9.1.1 Data transmiss ion

The chip enable signal is used to identify the transmitted data. Each data transfer is a

whole byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable sign al SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes will be either data to be w ritten

or data to be read (see Figure 28).

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

reset to zero after the last valid register is accessed. The R/W bit defines if the following

bytes will be read or write information.

Fig 27. SDI, SDO co nfigurations

Table 49. Serial interface

Symbol Function Description

SDA/CE chip enable input;

active LOW [1] when HIGH, the interface is rese t;

input may be higher than VDD

SCL s erial clock input when SDA/CE is HIGH, input may float;

input may be higher than VDD

SDI serial data input when SDA/CE is HIGH, input may fl oat;

input may be higher than VDD;

input data is sampled on the rising edge of SCL

SDO serial data output push-pull output;

drives from VSS to VBBS;

output data is changed on the falling edge of SCL

001aai560

SDI

two wire mode

SDO

SDI

single wire mode

SDO

Fig 28. Data transfer overview

013aaa311

data bus

SDA/CE

COMMAND DATA DATA DATA

Product data sheet Rev. 4 — 11 July 2013 47 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

Ta ble 50. Command byte definition

Bit Symbol Value Description

7R/W data read or write selection

0 write data

1 read data

6 to 5 SA 01 subaddress;

other codes will cause the device to ignore da ta

transfer

4 to 0 RA 00h to 1Bh register address

In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.

Fig 29. SPI-bus write examp le

001aaj348

seconds data 45BCD minutes data 10BCD

addr 03hR/W SA

03xx 04 05

SCL

SDI

SDA/CE

address

counter

0b6

0b5

1b4

0b3

0b2

0b1

1b0

1b7

0b6

1b5

0b4

0b3

0b2

1b1

0b0

1b7

0b6

0b5

0b4

1b3

0b2

0b1

0b0

In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this

configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left

open, high IDD currents may result.

Fig 30. SPI-bus re a d ex a mp le

001aaj349

months data 11BCD years data 06BCD

addr 08hR/W SA

08xx 09 0A

SCL

SDI

SDA/CE

address

counter

1b6

0b5

1b4

0b3

1b2

0b1

0b0

0b7

0b6

0b5

0b4

1b3

0b2

0b1

0b0

1b7

0b6

0b5

0b4

0b3

0b2

1b1

1b0

SDO

Product data sheet Rev. 4 — 11 July 2013 48 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

9.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are

connected to a positive supply by a pull-up resistor. Data tr ansfer is initiated only when the

bus is not busy.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line remains

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as control signals (see Figure 31).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition P (see Figure 32).

Remark: For the PCA21 29T, a repeated START is not allowed. Therefore a ST OP ha s to

be released before the next START.

9.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCA2129T can act as a slave transmitter and a slave receiver.

Fig 31. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 32. Definition of START and STOP conditions

mbc622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 4 — 11 July 2013 49 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

9.2.4 Acknowledge

The number of data bytes tran sf er re d be tween the START and STOP co nd itio ns from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

•A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

•Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is illustrated in Figure 34.

9.2.5 I2C-bus protocol

After a start condition, a valid hardware address has to be sent to a PCA2129T device.

The appropri ate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte

is shown in Table 51.

Fig 33. System confi gurat io n

mba605

MASTER

TRANSMITTER

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER

RECEIVER

SDA

SCL

Fig 34. Ackno wledgement on the I2C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 4 — 11 July 2013 50 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

The R/W bit defines the direction of the following single or multiple byte data tra nsfer (read

is logic 1, write is logic 0).

For the format and the timin g of the START cond ition (S), the ST OP condition (P), an d the

acknowledge (A ) re fe r to th e I 2C-bus specification Ref. 11 “ UM10204” and the

characteristics table (Table 56). In the write mode, a dat a transfer is terminated b y sending

either a STOP condition or the STA RT condition of the next data transfer.

Ta ble 51. I2C slave address byte

Slave address

Bit 7 6 5 4 3 2 1 0

MSB LSB

1010001R/W

Fig 35. Bus protocol, writing to registers

013aaa129

S 1 0 1

slave address register address

00h to 1Bh 0 to n

data bytes

write bit START/

STOP

acknowledge

from PCA2129T acknowledge

from PCA2129T

0 0 0 1 0 A A A P/S

Fig 36. Bus proto co l, rea ding from registers

013aaa130

S 1 0 1

slave address 0 to n data bytes

DATA BYTE LAST DATA BYTE

read bit

acknowledge

from PCA2129T acknowledge

from master no acknowledge

0 0 0 1 1 A A

S 1 0 1

slave address register address

00h to 1Bh

set register

address

read register

data

write bit STOP

acknowledge

from PCA2129T acknowledge

from PCA2129T

0 0 0 1 0 A A P

A P

Product data sheet Rev. 4 — 11 July 2013 51 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

10. Internal circuitry

11. Safety notes

Fig 37. Device diode protection diagram of PCA2129T

013aaa126

SCL

SDI

SDO

SDA/CE

IFS

CLKOUT

VSS

PCA2129T

INT

BBS

VBAT

VDD

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

Product data sheet Rev. 4 — 11 July 2013 52 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

12. Limiting values

[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.

[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).

[4] According to the store and transport requirements (see Ref. 12 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

Table 52. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.5 V

IDD supply current 50 +50 mA

Viinput voltage 0.5 +6.5 V

IIinput current 10 +10 mA

VOoutput voltage 0.5 +6.5 V

IOoutput current 10 +10 mA

at pin SDA/CE 10 +20 mA

VBAT battery supply voltage 0.5 +6.5 V

Ptot total power dissipation - 300 m W

VESD electrostatic discharge

voltage HBM [1] -4000 V

CDM [2] -1250 V

Ilu latch-up current [3] -200mA

Tstg storage temperature [4] 55 +85 C

Tamb ambient temperature operating device 40 +85 C

Product data sheet Rev. 4 — 11 July 2013 53 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

13. Static characteristics

Table 53. Static chara cteristics

VDD = 1.8 V to 4.2 V; VSS =0V; T

amb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage [1] 1.8 - 4.2 V

VBAT battery supply voltage 1.8 - 4.2 V

VDD(cal) calibration supply voltage - 3.3 - V

Vlow low voltage - 1.2 - V

IDD supply current interface active;

supplied by VDD

SPI-bus (fSCL = 6.5 MHz) - - 800 A

I2C-bus (fSCL = 400 kHz) - - 200 A

interface inactive (fSCL =0Hz)

[2];

TCR[1:0] = 00 (see Table 9 on page 12)

PWRMNG[2:0] = 111 (see Table 14 on pa g e 15);

TSOFF = 1 (see Table 38 on page 35);

COF[2:0] = 111 (see Table 11 on page 13)

VDD =2.0V - 500 - nA

VDD = 3.3 V - 700 1500 nA

VDD =4.2V - 800 - nA

PWRMNG[2:0] = 111 (see Table 14 on pa g e 15);

TSOFF = 1 (see Table 38 on page 35);

COF[2:0] = 000 (see Table 11 on page 13)

VDD =2.0V - 600 - nA

VDD =3.3V - 850 - nA

VDD =4.2V - 1050 - nA

PWRMNG[2:0] = 000 (see Table 14 on page 15);

TSOFF = 0 (see Table 38 on page 35);

COF[2:0] = 111 (see Table 11 on page 13)

VDD or VBAT =2.0V [3] - 1800 - nA

VDD or VBAT =3.3V [3] - 2150 - nA

VDD or VBAT =4.2V [3] -23503500nA

PWRMNG[2:0] = 000 (see Table 14 on page 15);

TSOFF = 0 (see Table 38 on page 35);

COF[2:0] = 000 (see Table 11 on page 13)

VDD or VBAT =2.0V [3] - 1900 - nA

VDD or VBAT =3.3V [3] - 2300 - nA

VDD or VBAT =4.2V [3] - 2600 - nA

IL(bat) battery leakage current VDD is acti ve supply;

VBAT = 3.0 V - 50 100 nA

Power management

Vth(sw)bat battery switch threshold

voltage -2.5-V

Vth(bat)low low battery threshold voltage - 2.5 - V

Product data sheet Rev. 4 — 11 July 2013 54 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

[1] For reliable oscillator start-up at power-on: VDD(po)min =V

DD(min) +0.3V.

[2] Timer source clock = 1⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS.

[3] When the device is supplied by the VBAT pin instead of the VDD pin, the current values for IBAT will be as specified for IDD under the same

conditions.

[4] The I2C-bus and SPI-bus interf aces of PCA2129T are 5 V tolerant.

[5] Tested on sample basis.

[6] For further information, see Figure 38.

Inputs[4]

VIinput voltage 0.5 - VDD +0.5 V

VIL LOW-level input voltage - - 0.25VDD V

Tamb =20 C to +85 C;

VDD > 2.0 V --0.3V

DD V

VIH HIGH-level input voltage 0.7VDD --V

ILI input leakage current VI=V

DD or VSS -0-A

post ESD event 1- +1A

Ciinput capacitance [5] --7pF

Outputs

VOoutput voltage on pins CLKOUT, INT,

referring to external pull-up 0.5 - 5.5 V

on pin SDO 0.5 - VBBS + 0.5 V

IOL LOW-level output current outpu t sink curren t;

VOL = 0.4 V

on pin SDA/CE [6] 317- mA

on all other outputs 1.0 - - mA

IOH HIGH-level output current output source current;

on pin SDO; VOH = 3.8 V;

VDD = 4.2 V

1.0--mA

ILO output leakage current VO = VDD or VSS -0-A

post ESD event 1- +1A

Table 53. Static chara cteristics …continued

VDD = 1.8 V to 4.2 V; VSS =0V; T

amb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 4 — 11 July 2013 55 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

13.1 Current consumption characteristics, typical

Typical value; VOL =0.4V.

Fig 38. IOL on pin SDA/CE

CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating.

Fig 39. IDD as a function of temperature

001aal763

VDD (V)

1.5 4.53.52.5

IOL

(mA)

Temperature (°C)

−40 1008060020−20 40

001aaj432

0.8

1.2

0.4

1.6

2.0

IDD

(μA)

VDD = 3 V

VDD = 2 V

Product data sheet Rev. 4 — 11 July 2013 56 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb =25C; TS input floating

b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb =25C; TS input floating

Fig 40. IDD as a function of VDD

VDD (V)

1.8 4.23.42.62.2 3.83.0

001aaj433

0.8

1.2

0.4

1.6

2.0

IDD

(μA)

CLKOUT OFF

CLKOUT enabled at

32 kHz

VDD (V)

1.8 4.23.42.62.2 3.83.0

001aaj434

1.6

2.4

0.8

3.2

4.0

IDD

(μA)

CLKOUT OFF

CLKOUT enabled at

32 kHz

Product data sheet Rev. 4 — 11 July 2013 57 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

13.2 Frequency characteristics

[1] 1 ppm corresponds to a time deviation of 0.0864 seconds per day.

[2] Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled.

[3] Not production tested. Effects of reflow soldering are included (see Ref. 3 “AN11120”).

Table 54. Frequency characteristics

VDD = 1.8 V to 4.2 V; VSS =0V; T

amb =+25



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fooutput frequency on pin CLKOUT;

VDD or VBAT = 3.3 V;

COF[2:0] = 000;

AO[3:0] = 1000

- 32.768 - kHz

f/f frequency stability VDD or VBAT = 3.3 V

Tamb =40 Cto30 C [1][2] -515 ppm

Tamb =30 C to +80 C[1][2] -38ppm

Tamb =+23C (2C) [1][2] -35.8 ppm

Tamb =+80Cto+85C[1][2] -515 ppm

fxtal/fxtal relative crystal frequency variation crystal aging

first year [3] --3ppm

ten years - - 8ppm

f/V frequency variation with voltage on pin CLKOUT - 1- ppm/V

(1) Typical temperature compensated frequency response.

(2) Uncompensated typical tuning-fork crystal frequency.

Fig 41. Typical characteristic of frequency with resp ect to temperature

Temperature (°C)

-40 1006008040-20 20

013aaa345

-40

Frequency

stability

(ppm)

-80

± 5 ppm ± 3 ppm ± 5 ppm

(1)

(2)

Product data sheet Rev. 4 — 11 July 2013 58 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

14. Dynamic characteristics

14.1 SPI-bus timing characteristics

[1] No load value; bus will be held up by bus capacitance; use RC time constant with application values.

Table 55. SPI-bus characteristics

VDD = 1.8 V to 4.2 V; VSS =0V; T

amb =





C to +85



C, unless otherwise specified. All timing values are valid with in the

operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see

Figure 42).

Symbol Parameter Conditions VDD =1.8V VDD =4.2V Unit

Min Max Min Max

Pin SCL

fclk(SCL) SCL clock frequency - 2.0 - 6.5 MHz

tSCL SCL time 800 - 140 - ns

tclk(H) clock HIGH time 100 - 70 - ns

tclk(L) clock LOW time 400 - 70 - ns

trrise time for SCL signal - 100 - 10 0 ns

tffall time for SCL signal - 100 - 100 ns

Pin SDA/CE

tsu(CE_N) CE_N set-up time 60 - 30 - ns

th(CE_N) CE_N hold time 40 - 25 - ns

trec(CE_N) CE_N recovery time 100 - 30 - ns

tw(CE_N) CE_N pulse width - 0.99 - 0.99 s

Pin SDI

tsu set-up time set-up time for SDI data 70 - 20 - ns

thhold time hold time for SDI data 70 - 20 - ns

Pin SDO

td(R)SDO SDO read delay time CL = 50 pF - 225 - 55 ns

tdis(SDO) SDO disable time [1] - 90 - 25 ns

tt(SDI-SDO) transition time from SDI to

SDO to avoid bus conflict 0 - 0 - ns

Product data sheet Rev. 4 — 11 July 2013 59 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

Fig 42. SPI-bus timing

013aaa152

R/W SA2 RA0 b7 b6 b0

b7 b6 b0

b0b6b7SDI

SDO

high-Z

SDI

SCL

WRITE

READ

w(CE_N)

80%

20%

clk(L)

h(CE_N)

rec(CE_N)

dis(SDO)

d(R)SDO

clk(H)

su(CE_N)

clk(SCL)

t(SDI-SDO)

Product data sheet Rev. 4 — 11 July 2013 60 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

14.2 I2C-bus timing characteristics

[1] The minimum SCL clock frequency is limited by the b us time-out feature which resets the serial bus

interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be

disabled for DC operation.

[2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of

the SCL signal) in order to bridge the undefined region of the falling edge of SCL.

[3] Cb is the total capacitance of one bus line in pF.

[4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage,

tf is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin,

and the SDA/SCL bus lines without exceeding the maximum tf.

[5] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.

[6] tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.

[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

Ta ble 56. I2C-bus characteristics

All timing characteristics are vali d within the operating supply voltage and ambient temperature

range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 43).

Symbol Parameter Standard mode Fast-mode (Fm) Unit

Min Max Min Max

Pin SCL

fSCL SCL clock frequency [1] 0 100 0 400 kHz

tLOW LOW period of the SCL

clock 4.7 - 1.3 - s

tHIGH HIGH period of the SCL

clock 4.0 - 0.6 - s

Pin SDA/CE

tSU;DAT data set-up time 250 - 100 - ns

tHD;DAT data hold time 0 - 0 - ns

Pins SCL and SDA/CE

tBUF bus free time between a

STOP and START

condition

4.7 - 1.3 - s

tSU;STO set-up time for STOP

condition 4.0 - 0.6 - s

tHD;STA hold time (repeated)

START condition 4.0 - 0.6 - s

tSU;STA set-up time for a

repeated START

condition

4.7 - 0.6 - s

trrise time of both SDA

and SCL signals [2][3][4] - 1000 20 + 0.1Cb300 ns

tffall time of bo th SDA and

SCL signals [2][3][4] - 300 20 + 0.1Cb300 ns

tVD;ACK data valid acknowledge

time [5] 0.1 3.45 0.1 0.9 s

tVD;DAT data valid time [6] 300 - 75 - ns

tSP pulse width of spikes

that must be suppressed

by the input filter

[7] - 50 - 50 ns

Product data sheet Rev. 4 — 11 July 2013 61 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

15. Application information

For information about application configuration see Ref. 3 “AN11120”.

16. Test information

16.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

Fig 43. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %

PROTOCOL

SCL

SDA

mbd820

BIT 0

LSB

(R/W)

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6) ACKNOWLEDGE

(A) STOP

CONDITION

(P)

SU;STA

HD;STA

SU;DAT

HD;DAT

VD;DAT

SU;STO

LOW

HIGH

1 / f

SCL

BUF

Product data sheet Rev. 4 — 11 July 2013 62 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

17. Package outline

Fig 44. Package outline SOT162-1 (SO16) of PCA2129T

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 10.5

10.1 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT162-1

detail X

0.25

075E03 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.41

0.40 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

vMA

(A )

0 5 10 mm

scale

SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

99-12-27

03-02-19

Product data sheet Rev. 4 — 11 July 2013 63 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

18. Packing information

18.1 Carrier tape information

19. Soldering

For information about soldering, see Ref. 3 “AN11120”.

Fig 45. Carrier tape details

Ta ble 57. Carrier tape dimensions

Symbol Description Value Unit

A0 pocket width in x direction 10.6 mm

B0 pocket width in y direction 10.7 mm

K0 pocket height 3.3 mm

P1 sprocket hole pitch 12 mm

W tape width in y direction 16 mm

013aaa697

pin 1

direction of feed

TOP VIEW

4.0

Ø 1.5

Figure not drawn to scale

Product data sheet Rev. 4 — 11 July 2013 64 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

19.1 Footprint information

Fig 46. Footprint information for reflow soldering of SO16 package

DIMENSIONS in mm

Ay By D1 D2 Gy HyP1

11.200 6.400 2.400 0.700

0.800 10.040 8.600

11.450

sot162-1_fr

11.9001.270

SOT162-1

solder land

occupied area

Footprint information for reflow soldering of SO16 package

AyByGy

Generic footprint pattern

Refer to the package outline drawing for actual layout

(0.125) (0.125)

D2 (4x)

1.320

Product data sheet Rev. 4 — 11 July 2013 65 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

20. Abbreviations

Ta ble 58. Abbreviations

Acronym Description

AEC Automotive Electronics Council

AM A nte Meridiem

BCD Binary Coded Decimal

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DC Direct Current

GPS Glo bal Positioning System

HBM Human Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LSB Least Significant Bit

MCU Microcontroller Unit

MM Machine Model

MSB Most Significant Bit

PM Post Meridiem

POR Power-On Reset

PORO Power-On Reset Override

PPM Parts Per Million

RC Resistance-Capacitance

RTC Real Time Clock

SCL Serial CLock line

SDA Serial DAta line

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

TCXO Temperature Compensated Xtal Oscillator

Xtal crystal

Product data sheet Rev. 4 — 11 July 2013 66 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

21. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — Handling precautions of ESD sensitive devices

[3] AN11120 — Application and soldering information for the PCA2129 autom otive

TCXO RTC

[4] IEC 60 13 4 — Rating syst ems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/R eflow Sensitivity Classific ation for

Nonhermetic Solid State Surface Mount Devices

[7] JESD 22 -A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD 22-C 10 1 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] UM10204 — I2C-bus specification and user manual

[12] UM10569 — Store and transport requirements

22. Revision history

Table 59. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA2129T v.4 20130711 Product data sheet - PCA2129T v. 3

Modifications: •Adjusted raise and fall time values in Table 55

•Enhance frequency stability specification in Table 54

PCA2129T v.3 20130124 Product data sheet - PCA2129T v.2.1

PCA2129T v.2.1 20121114 Product data sheet - PCA2129T v.2

PCA2129T v.2 20121113 Product data sheet - PCA2129T v.1

PCA2129T v.1 20111027 Objective data sheet - -

Product data sheet Rev. 4 — 11 July 2013 67 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

23. Legal information

23.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

23.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

23.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indire ct, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer pr oduct

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does no t accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data fro m the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 11 July 2013 68 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated ) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

23.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

24. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 4 — 11 July 2013 69 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

25. Tables

Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description of PCA2129T . . . . . . . . . . . . . .4

Table 5. Register overview . . . . . . . . . . . . . . . . . . . . . . .7

Table 6. Control_1 - control and status register 1

(address 00h) bit description . . . . . . . . . . . . . . .9

Table 7. Control_2 - control and status register 2

(address 01h) bit description . . . . . . . . . . . . . .10

Table 8. Control_3 - control and status register 3

(address 02h) bit description . . . . . . . . . . . . . .11

Table 9. CLKOUT_ctl - CLKOUT control register

(address 0Fh) bit description . . . . . . . . . . . . . .12

Table 10. Temperature measurement period . . . . . . . . . .12

Table 11. CLKOUT frequency selection. . . . . . . . . . . . . .1 3

Table 12. Aging_offset - crystal aging offset register

(address 19h) bit description . . . . . . . . . . . . . .14

Table 13. F r equency correction at 25 °C, typical . . . . . . .14

Table 14. Power management control bit description. . . .15

Table 15. Output pin BBS. . . . . . . . . . . . . . . . . . . . . . . . .18

Table 16. Seconds - seconds and clock integrity

Table 17. Seco nds coded in BCD format . . . . . . . . . . . .23

Table 18. Min ute s - minutes register (address 04h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 19. Ho urs - hours reg ister (address 05h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4

Table 20. Days - days register (address 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 21. Weekdays - weekdays register (addre ss 07h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 22. Weekday assignments . . . . . . . . . . . . . . . . . . .24

Table 23. Months - months register (address 08h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 24. Mon th assig nments in BCD format. . . . . . . . . .25

Table 25. Years - years register (address 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 26. Second_alarm - second alarm register

(address 0Ah) bit description . . . . . . . . . . . . . .27

Table 27. Minute_alarm - minute alarm register

(address 0Bh) bit description . . . . . . . . . . . . . .28

Table 28. Hour_alarm - hour alarm register

(address 0Ch) bit description . . . . . . . . . . . . . .28

Table 29. Day_alarm - day alarm register

(address 0Dh) bit description . . . . . . . . . . . . . .28

Table 30. Weekday_alarm - weekday alarm register

(address 0Eh) bit description . . . . . . . . . . . . . .29

Table 31. Watchdg_tim_ctl - watchdog timer control

Table 32. Watchdg_tim_val - watchdog timer value

Table 33. Programmable watchdog timer. . . . . . . . . . . . .31

Table 34. Flag location in register Control_2 . . . . . . . . . .32

Table 35. Example values in register Control_2. . . . . . . .33

Table 36. Example to clear only AF (bit 4) . . . . . . . . . . . .33

Table 37. Example to clear only MSF (bit 7). . . . . . . . . . .3 3

Table 38 . Timestp_ctl - timestamp control register

(address 12h) bit description . . . . . . . . . . . . . . 35

Table 39. Sec_time stp - second timestamp register

(address 13h) bit description . . . . . . . . . . . . . . 35

Table 40. Min_timestp - minute timestamp register

(address 14h) bit description . . . . . . . . . . . . . . 35

Table 41. Hour_timestp - hour timestamp register

(address 15h) bit description . . . . . . . . . . . . . . 36

Table 42. Day_timestp - day timestamp register

(address 16h) bit description . . . . . . . . . . . . . . 36

Table 43. Mon_timestp - month timestamp register

(address 17h) bit description . . . . . . . . . . . . . . 36

Table 44. Year_timestp - year timestamp register

(address 18h) bit description . . . . . . . . . . . . . . 36

Table 45. Battery switch-over and timestamp . . . . . . . . . 37

Table 46. Effect of bits MI and SI on pin INT and

bit MSF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 47. First increment of time circuits after stop

release. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 48. Interface selection input pin IFS. . . . . . . . . . . . 45

Table 49. Serial interface. . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 50. Command byte definition. . . . . . . . . . . . . . . . . 47

Table 51. I2C slave address byte. . . . . . . . . . . . . . . . . . . 50

Table 52. Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 53. Static characteristics . . . . . . . . . . . . . . . . . . . . 53

Table 54. Frequency characteristics . . . . . . . . . . . . . . . . 57

Table 55. SPI-bus characteristics . . . . . . . . . . . . . . . . . . 58

Table 56. I2C-bus characteristics. . . . . . . . . . . . . . . . . . . 60

Table 57. Carrier tape dimensions . . . . . . . . . . . . . . . . . 63

Table 58. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 59. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 66

Product data sheet Rev. 4 — 11 July 2013 70 of 72

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

26. Figures

Fig 1. Block diagram of PCA2129T . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for PCA2129T (SO16) . . . . . . . .4

Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .5

Fig 4. Battery switch-over behavior in standard mode

with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .16

Fig 5. Battery switch-over behavior in direct switching

mode with bit BIE set logic 1 (enabled) . . . . . . . .17

Fig 6. Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 7. Typical driving capability of VBBS: (VBBS - VDD)

with respect to the output load current IBBS . . . . .18

Fig 8. Battery low detection behavior with bit BLIE set

logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 9. Power failure event due to battery discharge:

reset occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 10. Dependency between POR and oscillator. . . . . .21

Fig 11. Power-On Reset (POR) system. . . . . . . . . . . . . .21

Fig 12. Power-On Reset Override (PORO) sequence,

valid for both I2C-bus and SPI-bus . . . . . . . . . . .22

Fig 13. Data flow of the time function. . . . . . . . . . . . . . . .26

Fig 14. Access time for read/write operations . . . . . . . . .26

Fig 15. Alarm function block diagram. . . . . . . . . . . . . . . .27

Fig 16. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .29

Fig 17. WD_CD set logic 1: watchdog activates an

interrupt when timed out . . . . . . . . . . . . . . . . . . .32

Fig 18. Timestamp detection with two push-buttons on

the TS pin (for example, for tamper detection) . .3 4

Fig 19. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .38

Fig 20. INT example for SI and MI when TI_TP is

logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 21. INT example for SI and MI when TI_TP is

logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 22. Example of shortening the INT pulse by

clearing the MSF flag. . . . . . . . . . . . . . . . . . . . . .4 0

Fig 23. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 24. STOP bit functional diagram . . . . . . . . . . . . . . . .44

Fig 25. STOP bit release timing. . . . . . . . . . . . . . . . . . . .44

Fig 26. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 27. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .46

Fig 28. Data transfer overview. . . . . . . . . . . . . . . . . . . . .46

Fig 29. SPI-bus write example. . . . . . . . . . . . . . . . . . . . .47

Fig 30. SPI-bus read example. . . . . . . . . . . . . . . . . . . . .47

Fig 31. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8

Fig 32. Definition of START and STOP conditions. . . . . .48

Fig 33. System configuration. . . . . . . . . . . . . . . . . . . . . .49

Fig 34. Acknowledgement on the I2C-bus . . . . . . . . . . . .49

Fig 35. Bus protocol, writing to registers . . . . . . . . . . . . .50

Fig 36. Bus protocol, reading from registers . . . . . . . . . .50

Fig 37. Device diode protection diagram of PCA2129T. .51

Fig 38. IOL on pin SDA/CE. . . . . . . . . . . . . . . . . . . . . . . .55

Fig 39. IDD as a function of temperature . . . . . . . . . . . . .5 5

Fig 40. IDD as a functi on of VDD . . . . . . . . . . . . . . . . . . . .56

Fig 41. Typical characteristic of frequency with re spect

to temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 42. SPI-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Fig 43. I2C-bus timing diagram; rise and fall times refer

to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . 61

Fig 44. Package outline SOT162-1 (SO16) of

PCA2129T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig 45. Carrier tape details . . . . . . . . . . . . . . . . . . . . . . . 63

Fig 46. Footprint information for reflow soldering of

SO16 package . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Product data sheet Rev. 4 — 11 July 2013 71 of 72

continued >>

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

27. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 Register overview. . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9

8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9

8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10

8.2.3 Register Control_3 . . . . . . . . . . . . . . . . . . . . . 11

8.3 Register CLKOUT_ctl. . . . . . . . . . . . . . . . . . . 12

8.3.1 Temperature compensated crystal oscillator . 12

8.3.1.1 Temperature measurement . . . . . . . . . . . . . . 12

8.3.2 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.4 Register Aging_offset . . . . . . . . . . . . . . . . . . . 14

8.4.1 Crystal aging correction . . . . . . . . . . . . . . . . . 14

8.5 Power management functions . . . . . . . . . . . . 15

8.5.1 Battery switch-over function . . . . . . . . . . . . . . 15

8.5.1.1 Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 16

8.5.1.2 Direct switching mode . . . . . . . . . . . . . . . . . . 16

8.5.1.3 Battery switch-over disabled: only one power

supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.5.1.4 Battery switch-over architecture . . . . . . . . . . . 17

8.5.2 Battery backup supply . . . . . . . . . . . . . . . . . . 18

8.5.3 Battery low detection function. . . . . . . . . . . . . 19

8.6 Oscillator stop detection function . . . . . . . . . . 20

8.7 Reset function . . . . . . . . . . . . . . . . . . . . . . . . 21

8.7.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 21

8.7.2 Power-On Reset Override (PORO) . . . . . . . . 21

8.8 Time and date function . . . . . . . . . . . . . . . . . . 23

8.8.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 23

8.8.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 23

8.8.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 24

8.8.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 24

8.8.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 24

8.8.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 25

8.8.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 25

8.8.8 Setting and reading the time. . . . . . . . . . . . . . 25

8.9 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 27

8.9.1 Register Second_alarm . . . . . . . . . . . . . . . . . 27

8.9.2 Register Minute_alarm. . . . . . . . . . . . . . . . . . 28

8.9.3 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 28

8.9.4 Register Day_alarm. . . . . . . . . . . . . . . . . . . . 28

8.9.5 Register Weekday_alarm. . . . . . . . . . . . . . . . 29

8.9.6 Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.10 Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 30

8.10.1 Register Watchdg_tim_ctl . . . . . . . . . . . . . . . 30

8.10.2 Register Watchdg_tim_val. . . . . . . . . . . . . . . 30

8.10.3 Watchdog ti mer function . . . . . . . . . . . . . . . . 31

8.10.4 Pre-defined timers: second and minute

interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.10.5 Clearing flags. . . . . . . . . . . . . . . . . . . . . . . . . 32

8.11 Timestamp function . . . . . . . . . . . . . . . . . . . . 34

8.11.1 Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 34

8.11.2 Timestamp mode . . . . . . . . . . . . . . . . . . . . . . 35

8.11.3 Timestamp registers. . . . . . . . . . . . . . . . . . . . 35

8.11.3.1 Register Timestp_ctl . . . . . . . . . . . . . . . . . . . 35

8.11.3.2 Register Sec_timestp. . . . . . . . . . . . . . . . . . . 35

8.11.3.3 Register Min_timestp . . . . . . . . . . . . . . . . . . . 35

8.11.3.4 Register Hour_timestp. . . . . . . . . . . . . . . . . . 36

8.11.3.5 Register Day_timestp. . . . . . . . . . . . . . . . . . . 36

8.11.3.6 Register Mon_timestp . . . . . . . . . . . . . . . . . . 36

8.11.3.7 Register Year_timestp . . . . . . . . . . . . . . . . . . 36

8.11 .4 Dependency between Battery switch-over

and timestamp . . . . . . . . . . . . . . . . . . . . . . . . 37

8.12 Interrupt output, INT. . . . . . . . . . . . . . . . . . . . 38

8.12.1 Minute and second interrupts. . . . . . . . . . . . . 39

8.12.2 INT pulse shortening . . . . . . . . . . . . . . . . . . . 40

8.12.3 Watchdog timer interrupts . . . . . . . . . . . . . . . 40

8.12.4 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 41

8.12.5 Timestamp interrupts . . . . . . . . . . . . . . . . . . . 41

8.12.6 Battery switch-over interrupts . . . . . . . . . . . . 41

8.12.7 Battery low detection interrupts . . . . . . . . . . . 41

8.13 External clock test mode . . . . . . . . . . . . . . . . 42

8.14 STOP bit function. . . . . . . . . . . . . . . . . . . . . . 43

9 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 46

9.1.1 Data transmission . . . . . . . . . . . . . . . . . . . . . 46

9.2 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 48

9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.2.2 START and STOP conditions. . . . . . . . . . . . . 48

9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 48

9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.2.5 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 49

10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 51

11 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 52

NXP Semiconductors PCA2129T

Accurate RTC with integrated quartz crystal for automotive

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 July 2013

Document identifier: PCA2129T

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

13 Static characteristics. . . . . . . . . . . . . . . . . . . . 53

13.1 Current consumption characteristics, typical . 55

13.2 Frequency characteristics. . . . . . . . . . . . . . . . 57

14 Dynamic characteristics . . . . . . . . . . . . . . . . . 58

14.1 SPI-bus timing characteristics . . . . . . . . . . . . 58

14.2 I2C-bus timing characteristics. . . . . . . . . . . . . 60

15 Application information. . . . . . . . . . . . . . . . . . 61

16 Test information. . . . . . . . . . . . . . . . . . . . . . . . 61

16.1 Quality information . . . . . . . . . . . . . . . . . . . . . 61

17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62

18 Packing information . . . . . . . . . . . . . . . . . . . . 63

18.1 Carrier ta pe information . . . . . . . . . . . . . . . . . 63

19 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

19.1 Footprint information. . . . . . . . . . . . . . . . . . . . 64

20 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 65

21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

22 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 66

23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 67

23.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 67

23.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

23.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 67

23.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 68

24 Contact information. . . . . . . . . . . . . . . . . . . . . 68

25 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

26 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71