PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853210 is a low skew, high performance dual 1-to- 5 Differential-to-2.5V/3.3V HiPerClockSTM LVPECL/ECL Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS853210 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853210 ideal for those clock distribution applications demanding well defined performance and repeatability. * 2 differential 2.5V/3.3V LVPECL / ECL bank outputs ,&6 * 2 differential clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLKx input * Output skew: 20ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: TBD * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V * -40C to 85C ambient operating temperature * Pin compatible with MC100EP210 and MC100LVEP210 nQB1 QB1 nQB0 QB0 24 23 22 21 20 19 18 17 VCCO 26 15 QB2 QA2 27 14 nQB2 nQA1 28 13 QB3 QA1 29 12 nQB3 nQA0 30 11 QB4 QA0 31 10 nQB4 VCCO 32 9 VCCO 2 3 4 5 6 7 8 nPCLKB VEE QB2 nQB2 1 PCLKB QB1 nQB1 ICS853210 VBB QB0 nQB0 16 nQA2 nPCLKA QA4 nQA4 25 PCLKA QA3 nQA3 VCCO nc QA2 nQA2 PCLKB nPCLKB nQA4 QA1 nQA1 QA4 QA3 QA0 nQA0 VCC PCLKA nPCLKA PIN ASSIGNMENT nQA3 BLOCK DIAGRAM 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View V BB QB3 nQB3 QB4 nQB4 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853210BY www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type Description Core supply pin. 2 nc Unused 3 PCLKA Input No connect. 4 nPCLKA Input 5 VBB Output 6 PCLKB Input 7 nPCLKB Input Clock input. VCC/2 default when left floating. Pulldown Non-inver ting differential clock input. Clock input. VCC/2 default when left floating. Bias voltage. Pulldown Non-inver ting differential clock input. 8 VEE Power Negative supply pin. 9, 25, 32 VCCO Power Output supply pins. 10, 11 nQB4, QB4 Output Differential output pair. LVPECL interface levels. 12, 13 nQB3, QB3 Output Differential output pair. LVPECL interface levels. 14, 15 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 17, 18 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 19, 20 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 21, 22 nQA4, QA4 Output Differential output pair. LVPECL interface levels. 23, 24 nQA3, QA3 Output Differential output pair. LVPECL interface levels. 26, 27 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 28, 29 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 30, 31 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor Minimum Typical Maximum Units 4 pF 37.5 K 75 K TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs PCLKA or PCLKB 0 nPCLKA or nPCLKB 1 1 0 0 1 Outputs QA0:QA4, nQA0:nQA4, QB0:QB4 nQB0:nQB4 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting HIGH LOW Differential to Differential Non Inver ting Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853210BY www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V NOTE: Stresses beyond those listed under Absolute Negative Supply Voltage, VEE -4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO 0.5V to VEE - 0.5V VBB Sink/Source, IBB 0.5mA Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40C to +85C Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 47.9C/W (0 lfpm) (Junction-to-Ambient) Package Thermal Impedance, JC 12C/W to 17C/W (Junction-to-Case) Wave Solder, TSOL 265C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum 3.3 3.8 2.375 TBD Units V mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V -40C 25C 85C Symbol Parameter VOH Output High Voltage; NOTE 1 2280 mV VOL Output Low Voltage; NOTE 1 1480 mV VSWING Peak-to-Peak Output Voltage Swing TBD mV VBB Output Voltage Reference; NOTE 2 TBD mV VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 PCLKA, PCLKB Input High Current nPCLKA, nPCLKB VCMR IIH Min Typ Max Min Typ Max Min Typ 853210BY TBD mV 1.2 3.3 V 150 A Input Low Current www.icst.com/products/hiperclocks.html 3 Units 150 PCLKA, PCLKB -10 nPCLKA, nPCLKB -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VCC + 0.3V. IIL Max A REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter -40C Min Typ 25C Max Min Typ 85C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 1480 mV VOL Output Low Voltage; NOTE 1 680 mV VSWING Peak-to-Peak Output Voltage Swing VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLKA, PCLKB Input High Current nPCLKA, nPCLKB VCMR IIH TBD 150 mV TBD mV V 150 A PCLKA, PCLKB -10 nPCLKA, nPCLKB -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.125V to 1.3V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VCC + 0.3V. IIL Input Low Current A TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V -40C 25C 85C Symbol Parameter VOH Output High Voltage; NOTE 1 -1020 mV Min Typ Max Min Typ Max Min Typ Max Units VOL Output Low Voltage; NOTE 1 -1820 mV VSWING Peak-to-Peak Output Voltage Swing TBD mV VBB Output Voltage Reference; NOTE 2 TBD mV Peak-to-Peak Input Voltage 150 TBD Input High Voltage VEE + 1.2 0.0 VCMR Common Mode Range; NOTE 3, 4 PCLKA, PCLKB IIH Input High Current 150 nPCLKA, nPCLKB PCLKA, PCLKB -10 IIL Input Low Current nPCLKA, -150 nPCLKB Input and output parameters var y 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VEE -3V in ECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VCC + 0.3V. VPP 853210BY www.icst.com/products/hiperclocks.html 4 mV V A A REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V Symbol ICS853210 OR VCC = 2.375 TO 3.8V; VEE = 0V -40C Parameter Min fMAX Output Frequency tPD Propagation Delay; NOTE 1 Typ 25C Max Min Typ 85C Max Min Typ Max Units >3 GHz TBD ps tsk(o) Output Skew; NOTE 2, 4 20 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 85 ps tR/tF Output Rise/Fall Time TBD ps 20% to 80% NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853210BY www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC, VCCO = 2V VCC SCOPE Qx nPCLKA, nPCLKB LVPECL V Cross Points PP V CMR PCLKA, PCLKB nQx V EE VEE = -0.375V to -1.8V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW 80% nPCLKA, nPCLKB 80% PCLKA, PCLKB V SW I N G 20% 20% nQA0:nQA4, nQB0:nQB4, Clock Outputs t R t F QA0:QA4, QB0:QB4, OUTPUT RISE/FALL TIME 853210BY tPD PROPAGATION DELAY www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VDD(or VCC) CLK_IN + VBB - C1 0.1uF FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50 5 2 Zo FIN FOUT 5 2 Zo Zo = 50 Zo = 50 FOUT RTT = 1 (VOH + VOL / VCC -2) -2 Zo = 50 VCC - 2V RTT 3 2 Zo Zo FIGURE 2A. LVPECL OUTPUT TERMINATION 853210BY FIN 50 50 3 2 Zo FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853210 is: 437 853210BY www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 q 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 853210BY www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853210 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS853210BY ICS853102BY 32 lead LQFP 250 per tray -40C to 85C ICS853210BYT ICS853210BY 32 lead LQFP on Tape and Reel 1000 -40C to 85C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853210BY www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 30, 2003