Functional Details
Functionally the GD16360 consists of
two identical blocks, each containing:
uA transmit channel
uA receive channel
Transmit Channel
Each transmit channel comprises:
uOne differential LVPECL signal input
(shaper)
uTwo cable drivers, providing G.703
interface signals.
The cable drivers can be adjusted indi-
vidually, allowing optimum performance,
with minimum power consumption.
The shaper takes the distorted LVPECL
CMI signals and restores them to a near
square waveform internally. This signal is
sent out through the cable drivers. Both
of which are differential open collector
outputs. Both cable drivers are adjust-
able by use of a current control pin (cur-
rent mirroring).
Receive Channel
Each receive channel comprises:
uA cable equaliser and a LOS (ITU-T
G.775 compliant Loss Of Signal de-
tector)
uA selector and an LVPECL output
buffer.
The Equaliser takes the differential ana-
logue input signals, which have been
Öf-attenuated through the coax,
equalises the signal, and send it to a se-
lector. From the selector the signal goes
to the output LVPECL buffer. This buffer
drives the signal outputs from circuit in-
tended for interconnection to the system
ASIC.
The LOS function monitors the input sig-
nal amplitude and generates a signal ac-
cording to ITU-T G.775.
Loopback Mode
The selector can be used to take the sig-
nal from the transmit channel and send it
out through RXOxx to the system ASIC
by setting the LOOPx high.
Build in Test
The build in test is a monitoring circuit,
which looks at the two input signals as
well as both output signals.
For the input signals for the receiver the
detection is determined by the use of the
ITU-T G.775 LOS function.
For the remaining three I/O signals
(BITA/B/C), the criteria for signal detec-
tion is set by the presence of transitions.
If there are no transitions for more than
100 bit periods this signal will go high in-
ternally. Otherwise it will stay low.
The determination of the output open col-
lector signal BITxP/N, will be generated
according to the logic table below.
BITA/B/C/G.775
Receive Channel
CMI Digital Output CMI Analog Input
OK Signal ON Signal ON
FAIL Signal ON NO Signal
FAIL NO Signal Signal ON
OK NO Signal NO Signal
Transmit Channel
CMI Analog Output CMI Digital Input
OK Signal ON Signal ON
FAIL Signal ON NO Signal
FAIL NO Signal Signal ON
OK NO Signal NO Signal
Hence if there is one or more FAIL condi-
tions, then the overall (-external BITxP/N
monitoring signals) will be low (voltage).
The internal signals BITA, BITB, BITC,
G.775 are OR’ed together.
Data Sheet Rev.: 6 GD16360 Page 3 of 9