140/155 Mbit/s CMI Shaper and Equaliser for E4/STM-1/OC-3 GD16360 an Intel company Preliminary General Description The GD16360 is a dual transceiver for transmitting and receiving CMI-signals, according to the ITU-T G.703 standard. Basically the chip is used as an interface between the internal system signals and the outside world. The internal system signals are CMI coded, though distorted and attenuated. The outside world signals should fully meet ITU-T G.703. On the receive side the GD16360 receives an attenuated signal after passing through a 75 W coax cable with a 12.7 dB attenuation at 78 MHz. Features This signal is fed into an equalizer circuit, which compensates for the frequency dependant attenuation and reshapes the signal levels into digital, differential LVPECL levels. The transmit path receives a distorted signal usually improperly terminated and with high reflections. This signal is originally a differential LVPECL signal from the system ASIC. l Fully dual transmit/receive IC for E4/STM-1/OC-3 operations. l Meet G.703 for 140 and 155 Mbit/s CMI interface: - Return loss - Receive sensitivity - Transmit power l Meet G.775 for LOS detection. l 3.3 V LVPECL High speed I/O's. l CMOS configuration signals. l Power consumption: 500 mW <target>. l Supply voltage: 3.3 V (5 V for external cabledriver connection.) l Package: 48 pin TQFP (7x7x1.4 mm). l Designed for low cost and volume production. Applications l STM-1 or E4 CMI electrical line interfaces Data Sheet Rev.: 6 Block Diagram TXIN1P TXIN1N Shaper TXOM1P TXOM1N TD MCIP1 LOS BITA TXO1P TXO1N TD Line G.703 CIP1 LOS BITB LOS BITC RXO1P RXO1N PECL RXIN1P RXIN1N Equaliser RXOEN1 LOOP1 LOS1 BIT1P BIT1N TXIN2P TXIN2N Logic Shaper LOS G.775 TXOM2P TXOM2N TD MCIP2 LOS BITA TXO2P TXO2N TD Line G.703 CIP2 LOS BITB LOS BITC RXO2P RXO2N PECL Equaliser RXIN2P RXIN2N RXOEN2 LOOP2 LOS2 BIT2P BIT2N Data Sheet Rev.: 6 Logic LOS G.775 GD16360 Page 2 of 9 Functional Details Functionally the GD16360 consists of two identical blocks, each containing: u A transmit channel u A receive channel Transmit Channel Each transmit channel comprises: u One differential LVPECL signal input (shaper) u Two cable drivers, providing G.703 interface signals. The cable drivers can be adjusted individually, allowing optimum performance, with minimum power consumption. For the remaining three I/O signals (BITA/B/C), the criteria for signal detection is set by the presence of transitions. If there are no transitions for more than 100 bit periods this signal will go high internally. Otherwise it will stay low. The determination of the output open collector signal BITxP/N, will be generated according to the logic table below. BITA/B/C/G.775 Receive Channel CMI Digital Output CMI Analog Input OK Signal ON Signal ON The shaper takes the distorted LVPECL CMI signals and restores them to a near square waveform internally. This signal is sent out through the cable drivers. Both of which are differential open collector outputs. Both cable drivers are adjustable by use of a current control pin (current mirroring). FAIL Signal ON NO Signal FAIL NO Signal Signal ON OK NO Signal NO Signal Receive Channel Each receive channel comprises: u A cable equaliser and a LOS (ITU-T G.775 compliant Loss Of Signal detector) u A selector and an LVPECL output buffer. The Equaliser takes the differential analogue input signals, which have been Of-attenuated through the coax, equalises the signal, and send it to a selector. From the selector the signal goes to the output LVPECL buffer. This buffer drives the signal outputs from circuit intended for interconnection to the system ASIC. Transmit Channel CMI Analog Output CMI Digital Input OK Signal ON Signal ON FAIL Signal ON NO Signal FAIL NO Signal Signal ON OK NO Signal NO Signal Hence if there is one or more FAIL conditions, then the overall (-external BITxP/N monitoring signals) will be low (voltage). The internal signals BITA, BITB, BITC, G.775 are OR'ed together. The LOS function monitors the input signal amplitude and generates a signal according to ITU-T G.775. Loopback Mode The selector can be used to take the signal from the transmit channel and send it out through RXOxx to the system ASIC by setting the LOOPx high. Build in Test The build in test is a monitoring circuit, which looks at the two input signals as well as both output signals. For the input signals for the receiver the detection is determined by the use of the ITU-T G.775 LOS function. Data Sheet Rev.: 6 GD16360 Page 3 of 9 Pin List Mnemonic: Pin Number: Pin Type: TXIN1P, TXIN1N 13, 14 LVPECL-IN Distorted, LVPECL signal input, 100 - 1000 mVPP TXIN2P, TXIN2N 24, 23 LVPECL-IN Distorted, LVPECL signal input, 100 - 1000 mVPP TXO1P, TXO1N 2, 3 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally TXO2P, TXO2N 35, 34 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally TXOM1P, TXOM1N 6, 7 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally. Monitor cable driver. TXOM2P, TXOM2N 31, 30 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally. Monitor cable driver. CIP1, CIP2 1, 36 ANL CML open collector current control input. Connect resistor TBD W to VDD + 1.7 V. MCIP1, MCIP2 5, 32 ANL CML open collector current control input for Monitor cabledrivers. Connect resistor TBD W to VDD + 1.7 V RXIN1P, RXIN1N 44, 45 ANL-IN ITU-T G.703 input. f - Attenuated from coax. RXIN2P, RXIN2N 42, 41 ANL-IN ITU-T G.703 input. f - Attenuated from coax. RXO1P, RXO1N 17, 16 LVPECL-OUT LVPECL output to system ASIC. RXO2P, RXO2N 20, 21 LVPECL-OUT LVPECL output to system ASIC. RXOEN1 8 CMOS-IN When LOW, RXO1P is forced LOW. RXOEN2 29 CMOS-IN When LOW, RXO2P is forced LOW. LOS1 18 CMOS-OUT ITU-T G.775 LOS detected from RXIN1P/N input. When LOS flagged, output is LOW. LOS2 19 CMOS-OUT ITU-T G.775 LOS detected from RXIN2P/N input. When LOS flagged, output is LOW. LOOP1 9 CMOS-IN Loop-back selector. When HIGH loop-back in transceiver 1 is enabled. LOOP2 28 CMOS-IN Loop-back selector. When HIGH loop-back in transceiver 2 is enabled. BIT1P, BIT1N 10, 11 OPENCOLLECTOR Build in test for transceiver 1. Determines status of GD16360 and I/O signals determined from logic table above. If one or more fails the positive output is low (voltage). BIT2P, BIT2N 27, 26 OPENCOLLECTOR Build in test for transceiver 2. Determines status of GD16360 and I/O signals determined from logic table above. If one or more fails the positive output is low (voltage). VDD 4, 12, 15, 22, 33 PWR Positive power supply 3.3 V for transceiver 1. VDD 39, 40, 43, 46, 47 PWR Positive power supply 3.3 V for transceiver 2. VEE 25, 37 PWR 0 V power, GND. VEE 38, 48 PWR 0 V power, GND. Heat sink Data Sheet Rev.: 6 Description: Connected to VEE. GD16360 Page 4 of 9 Package Pinout VEE VDD VDD RXIN1N RXIN1P VDD RXIN2P RXIN2N VDD VDD VEE VEE 48 47 46 45 44 43 42 41 40 39 38 37 CIP1 1 36 CIP2 TXO1P 2 35 TXO2P TXO1N 3 34 TXO2N VDD 4 33 VDD MCIP1 5 32 MCIP2 TXOM1P 6 31 TXOM2P TXOM1N 7 30 TXOM2N RXOEN1 8 29 RXOEN2 LOOP1 9 28 LOOP2 BIT1P 10 27 BIT2P BIT1N 11 26 BIT2N VDD 12 25 VEE 13 14 15 16 17 18 19 20 21 22 23 24 TXIN1P TXIN1N VDD RXO1N RXO1P LOS1 LOS2 RXO2P RXO2N VDD TXIN2N TXIN2P Figure 1. Package 48 pin, Top View Data Sheet Rev.: 6 GD16360 Page 5 of 9 Maximum Ratings These are the limits beyond which the component may be damaged. All voltages are referenced to VEE unless otherwise noted. Symbol: Characteristic: Conditions: VDD Supply Voltage VO max Output Voltage LVPECL/CMOS IO,PECL max Output Current LVPECL IO,CMOS max Output Current CMOS VI max Input Voltage II max MAX.: UNIT: 0 5 V -0.5 VDD + 0.5 V 40 mA -10 10 mA LVPECL/CMOS -0.5 VDD + 0.5 V Input Current LVPECL/CMOS -1.0 1.0 mA TO Operating Temperature Junction -55 +150 EC Ts Storage Temperature Junction -65 +175 EC VESD ESD Voltage Note 1 500 FIT Note 1: MIN.: TYP.: V TBD Human body model (100 pF, 1500 W) MIL 883 std. Thermal Characteristics TAMBIENT = -5 C to 85 C. Thermal resistance qJ-C = TBD Thermal resistance qJ-A = TBD Note: Heat sink will be used, see package outline. Data Sheet Rev.: 6 GD16360 Page 6 of 9 DC Characteristics All voltages in table are referred to VEE unless otherwise noted. All input signal and power currents in the table are defined positive into the pin. All output signal currents are defined positive out of the pin. Symbol: Characteristic: VDD Supply Voltage IDD Supply Current Note 3 VIC,LVPECL LVPECL Input Common Mode Voltage Shaper Input VIDIFF,LVPECL LVPECL Differential Input Voltage Shaper Input, Note 2 IIH,LVPECL LVPECL Input HI Current VIH LVPECL, max IIL,LVPECL LVPECL Input LO Current VIL LVPECL, min VOH,LVPECL LVPECL Output HI Voltage Note 1 VDD -1.1 VDD -0.70 V VOL,LVPECL LVPECL Output LO Voltage Note 1 VDD -2.00 VDD -1.62 V VODIFF,LVPECL LVPECL Output Differential Voltage Note 1 600 1300 mV VIH,CMOS CMOS Input HI Voltage VDD x0.8 VDD V VIL,CMOS CMOS Input LO Voltage 0 VDD x0.2 V IIH ,CMOS CMOS Input HI Current VIH CMOS, max 100 mA IIL ,CMOS CMOS Input LO Current VIL CMOS, min VOH ,CMOS CMOS Output HI Voltage IOH = 1mA VDD - 0.1 VDD V VOL ,CMOS CMOS Output LO Voltage IOL = -1mA 0 0.1 V MAX.: UNIT: Note 1: Note 2: Conditions: MIN.: TYP.: MAX.: UNIT: 3.15 3.30 3.45 V TBD mA VDD -1.5 VDD -1.1 V 0.100 1.000 V 100 mA -100 mA -100 mA 50 W termination to VDD -2.0 V. Although VIDIFF,PECL may vary within VIH,MAX and VIL,MIN, it must not exceed VIDIFF,MAX. Analog Characteristics All specifications according to the CMI ITU-T interface are to be kept according to this standard. The `shaper' block is to be considered as a LVPECL input, with an external biasing according to note 1 above. Symbol: Characteristic: Conditions: MIN.: OVLDIN Input Overload G.703 interface 1000 SENSIN Input Sensitivity G.703 interface -15 dB RLIN Input Return Loss Note 1 -17 dB RLOUT Output Return Loss Note 1 -17 dB VOH G.703 G.703 Output Voltage HI Note 2 0.45 0.55 V VOL G.703 G.703 Output Voltage LO Note 2 -0.55 -0.45 V Note 1: Note 2: TYP.: mVPP G.703 interface open collector type. Actual value depends on discrete external circuitry. Measured in 75 W load via AC- or pulse transformer coupling Data Sheet Rev.: 6 GD16360 Page 7 of 9 AC Characteristics All voltages in table are referred to VEE unless otherwise noted. All input signal and power currents in the table are defined positive into the pin. All output signal currents are defined positive out of the pin. Symbol: Characteristic: Conditions: TR-PECL PECL Rise Time TF-PECL MAX.: UNIT: Note 1 800 ps PECL Fall Time Note 1 800 ps TR-CMOS CMOS Rise Time Note 2 4 ns TF-CMOS CMOS Fall Time Note 2 4 ns Note 1: Note 2: MIN.: TYP.: 20 - 80 %, 50 W to VDD - 2.0 V. 20 - 80 %, 10 pF and 100 mA load. Package Outline Figure 2. Package 48 pin TQFP, EDQUAD Data Sheet Rev.: 6 GD16360 Page 8 of 9 Device Marking GD16360 <Wafer ID> <YY WW> Figure 3. Device Marking, Top View External References ITU-T G.703 (04/91): ITU-T G.775 (11/94): General Aspects of Digital transmissionsystems, terminal equipments. LOS and AIS defect detection criteria. Ordering Information To order, please specify as shown below: Product Name: Intel Order number: Package Type: Ambient Temperature Range: GD16360-48BA FAGD1636048BA 48 Lead TQFP, EDQUAD -5..85 EC MM#: 836046 GD16360, Data Sheet Rev.: 6 - Date: 24 July 2001 an Intel company Mileparken 22, DK-2740 Skovlunde Denmark Phone : +45 7010 1062 Fax : +45 7010 1063 E-mail : sales@giga.dk Web site : http://www.intel.com/ixa Please check our Internet web site for latest version of this data sheet. The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems. Distributor: Copyright (c) 2001 GIGA ApS An Intel company All rights reserved