FAGD1636048BA - Intel - Datasheet.Live

General Description

The GD16360 is a dual transceiver for

transmitting and receiving CMI–signals,

according to the ITU-T G.703 standard.

Basically the chip is used as an interface

between the internal system signals and

the outside world.

The internal system signals are CMI

coded, though distorted and attenuated.

The outside world signals should fully

meet ITU-T G.703.

On the receive side the GD16360 re-

ceives an attenuated signal after passing

through a 75 Wcoax cable with a 12.7 dB

attenuation at 78 MHz.

This signal is fed into an equalizer circuit,

which compensates for the frequency de-

pendant attenuation and reshapes the

signal levels into digital, differential

LVPECL levels.

The transmit path receives a distorted

signal usually improperly terminated and

with high reflections. This signal is origi-

nally a differential LVPECL signal from

the system ASIC.

an Intel company

Data Sheet Rev.: 6

Preliminary

Features

lFully dual transmit/receive IC for

E4/STM-1/OC-3 operations.

lMeet G.703 for 140 and 155 Mbit/s

CMI interface:

–Return loss

–Receive sensitivity

–Transmit power

lMeet G.775 for LOS detection.

l3.3 V LVPECL High speed I/O’s.

lCMOS configuration signals.

lPower consumption: 500 mW

<target>.

lSupply voltage: 3.3 V

(5 V for external cabledriver

connection.)

lPackage: 48 pin TQFP

(7×7×1.4 mm).

lDesigned for low cost and volume

production.

Applications

lSTM-1 or E4 CMI electrical line inter-

faces

140/155 Mbit/s

CMI Shaper and

Equaliser for

E4/STM-1/OC-3

GD16360

Block Diagram

Data Sheet Rev.: 6 GD16360 Page 2 of 9

LOS

BITB

LOS

BITB

Line

G.703

Line

G.703

LOS

BITA

LOS

BITA

Shaper

TXIN1P

TXIN2P

TXOM1P

TXOM2P

TXO1P

TXO2P

RXIN1P

RXIN2P

TXOM1N

TXOM2N

MCIP1

MCIP2

TXO1N

TXO2N

CIP1

CIP2

RXIN1N

RXIN2N

TXIN1N

TXIN2N

RXO1N

RXO2N

LOOP1

LOOP2

LOS1

LOS2

BIT1N

BIT1P

BIT2N

BIT2P

RXO1P

RXOEN1

RXOEN2

RXO2P

PECL

Equaliser

Logic

LOS

G.775

LOS

G.775

LOS

BITC

LOS

BITC

Functional Details

Functionally the GD16360 consists of

two identical blocks, each containing:

uA transmit channel

uA receive channel

Transmit Channel

Each transmit channel comprises:

uOne differential LVPECL signal input

(shaper)

uTwo cable drivers, providing G.703

interface signals.

The cable drivers can be adjusted indi-

vidually, allowing optimum performance,

with minimum power consumption.

The shaper takes the distorted LVPECL

CMI signals and restores them to a near

square waveform internally. This signal is

sent out through the cable drivers. Both

of which are differential open collector

outputs. Both cable drivers are adjust-

able by use of a current control pin (cur-

rent mirroring).

Receive Channel

Each receive channel comprises:

uA cable equaliser and a LOS (ITU-T

G.775 compliant Loss Of Signal de-

tector)

uA selector and an LVPECL output

buffer.

The Equaliser takes the differential ana-

logue input signals, which have been

Öf-attenuated through the coax,

equalises the signal, and send it to a se-

lector. From the selector the signal goes

to the output LVPECL buffer. This buffer

drives the signal outputs from circuit in-

tended for interconnection to the system

ASIC.

The LOS function monitors the input sig-

nal amplitude and generates a signal ac-

cording to ITU-T G.775.

Loopback Mode

The selector can be used to take the sig-

nal from the transmit channel and send it

out through RXOxx to the system ASIC

by setting the LOOPx high.

Build in Test

The build in test is a monitoring circuit,

which looks at the two input signals as

well as both output signals.

For the input signals for the receiver the

detection is determined by the use of the

ITU-T G.775 LOS function.

For the remaining three I/O signals

(BITA/B/C), the criteria for signal detec-

tion is set by the presence of transitions.

If there are no transitions for more than

100 bit periods this signal will go high in-

ternally. Otherwise it will stay low.

The determination of the output open col-

lector signal BITxP/N, will be generated

according to the logic table below.

BITA/B/C/G.775

Receive Channel

CMI Digital Output CMI Analog Input

OK Signal ON Signal ON

FAIL Signal ON NO Signal

FAIL NO Signal Signal ON

OK NO Signal NO Signal

Transmit Channel

CMI Analog Output CMI Digital Input

OK Signal ON Signal ON

FAIL Signal ON NO Signal

FAIL NO Signal Signal ON

OK NO Signal NO Signal

Hence if there is one or more FAIL condi-

tions, then the overall (-external BITxP/N

monitoring signals) will be low (voltage).

The internal signals BITA, BITB, BITC,

G.775 are OR’ed together.

Data Sheet Rev.: 6 GD16360 Page 3 of 9

Pin List

Mnemonic: Pin Number: Pin Type: Description:

TXIN1P, TXIN1N 13, 14 LVPECL-IN Distorted, LVPECL signal input, 100 - 1000 mVPP

TXIN2P, TXIN2N 24, 23 LVPECL-IN Distorted, LVPECL signal input, 100 –1000 mVPP

TXO1P, TXO1N 2, 3 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally

TXO2P, TXO2N 35, 34 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally

TXOM1P, TXOM1N 6, 7 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally.

Monitor cable driver.

TXOM2P, TXOM2N 31, 30 ANL-OUT ITU-T G.703 interface, open collector output 26.7 mA nominally.

Monitor cable driver.

CIP1, CIP2 1, 36 ANL CML open collector current control input. Connect resistor TBD W

to VDD + 1.7 V.

MCIP1, MCIP2 5, 32 ANL CML open collector current control input for Monitor cabledrivers.

Connect resistor TBD Wto VDD + 1.7 V

RXIN1P, RXIN1N 44, 45 ANL-IN ITU-T G.703 input. f- Attenuated from coax.

RXIN2P, RXIN2N 42, 41 ANL-IN ITU-T G.703 input. f- Attenuated from coax.

RXO1P, RXO1N 17, 16 LVPECL-OUT LVPECL output to system ASIC.

RXO2P, RXO2N 20, 21 LVPECL-OUT LVPECL output to system ASIC.

RXOEN1 8 CMOS-IN When LOW, RXO1P is forced LOW.

RXOEN2 29 CMOS-IN When LOW, RXO2P is forced LOW.

LOS1 18 CMOS-OUT ITU-T G.775 LOS detected from RXIN1P/N input. When LOS

flagged, output is LOW.

LOS2 19 CMOS-OUT ITU-T G.775 LOS detected from RXIN2P/N input. When LOS

flagged, output is LOW.

LOOP1 9 CMOS-IN Loop-back selector. When HIGH loop-back in transceiver 1 is

enabled.

LOOP2 28 CMOS-IN Loop-back selector. When HIGH loop-back in transceiver 2 is

enabled.

BIT1P, BIT1N 10, 11 OPEN-

COLLECTOR

Build in test for transceiver 1. Determines status of GD16360 and

I/O signals determined from logic table above. If one or more fails

the positive output is low (voltage).

BIT2P, BIT2N 27, 26 OPEN-

COLLECTOR

Build in test for transceiver 2. Determines status of GD16360 and

I/O signals determined from logic table above. If one or more fails

the positive output is low (voltage).

VDD 4, 12, 15, 22,

PWR Positive power supply 3.3 V for transceiver 1.

VDD 39, 40, 43, 46,

PWR Positive power supply 3.3 V for transceiver 2.

VEE 25, 37 PWR 0 V power, GND.

VEE 38, 48 PWR 0 V power, GND.

Heat sink Connected to VEE.

Data Sheet Rev.: 6 GD16360 Page 4 of 9

Package Pinout

Figure 1. Package 48 pin, Top View

Data Sheet Rev.: 6 GD16360 Page 5 of 9

VEE

VDD

RXIN1N

RXIN1P

VDD

RXIN2P

RXIN2N

VDD

VEE

CIP2

TXO2P

TXO2N

VDD

MCIP2

TXOM2P

TXOM2N

RXOEN2

LOOP2

BIT2P

BIT2N

VEE

TXIN2N

TXIN2P

VDD

RXO2N

RXO2P

LOS2

LOS1

RXO1P

RXO1N

VDD

TXIN1N

TXIN1P

VDD

BIT1N

BIT1P

LOOP1

RXOEN1

TXOM1N

TXOM1P

MCIP1

VDD

TXO1N

TXO1P

CIP1

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages are referenced to VEE unless otherwise noted.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

VDD Supply Voltage 0 5 V

VOmax Output Voltage LVPECL/CMOS -0.5 VDD + 0.5 V

IO,PECL max Output Current LVPECL 40 mA

IO,CMOS max Output Current CMOS -10 10 mA

VImax Input Voltage LVPECL/CMOS -0.5 VDD + 0.5 V

IImax Input Current LVPECL/CMOS -1.0 1.0 mA

TOOperating Temperature Junction -55 +150 EC

TsStorage Temperature Junction -65 +175 EC

VESD ESD Voltage Note 1 500 V

FIT TBD

Note 1: Human body model (100 pF, 1500 W) MIL 883 std.

Thermal Characteristics

TAMBIENT =-5°Cto85°C.

Thermal resistance qJ-C = TBD

Thermal resistance qJ-A = TBD

Note: Heat sink will be used, see package outline.

Data Sheet Rev.: 6 GD16360 Page 6 of 9

DC Characteristics

All voltages in table are referred to VEE unless otherwise noted.

All input signal and power currents in the table are defined positive into the pin.

All output signal currents are defined positive out of the pin.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

VDD Supply Voltage 3.15 3.30 3.45 V

IDD Supply Current Note 3 TBD mA

VIC,LVPECL LVPECL Input Common Mode Voltage Shaper Input VDD -1.5 VDD -1.1 V

VIDIFF,LVPECL LVPECL Differential Input Voltage Shaper Input,

Note 2

0.100 1.000 V

IIH,LVPECL LVPECL Input HI Current VIH LVPECL, max 100 mA

IIL,LVPECL LVPECL Input LO Current VIL LVPECL, min -100 mA

VOH,LVPECL LVPECL Output HI Voltage Note 1 VDD -1.1 VDD -0.70 V

VOL,LVPECL LVPECL Output LO Voltage Note 1 VDD -2.00 VDD -1.62 V

VODIFF,LVPECL LVPECL Output Differential Voltage Note 1 600 1300 mV

VIH,CMOS CMOS Input HI Voltage VDD x0.8 VDD V

VIL,CMOS CMOS Input LO Voltage 0 VDD x0.2 V

IIH ,CMOS CMOS Input HI Current VIH CMOS, max 100 mA

IIL ,CMOS CMOS Input LO Current VIL CMOS, min -100 mA

VOH ,CMOS CMOS Output HI Voltage IOH = 1mA VDD - 0.1 VDD V

VOL ,CMOS CMOS Output LO Voltage IOL = -1mA 0 0.1 V

Note 1: 50 Wtermination to VDD -2.0 V.

Note 2: Although VIDIFF,PECL may vary within VIH,MAX and VIL,MIN, it must not exceed VIDIFF,MAX.

Analog Characteristics

All specifications according to the CMI ITU-T interface are to be kept according to this standard.

The ‘shaper’block is to be considered as a LVPECL input, with an external biasing according to note 1 above.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

OVLDIN Input Overload G.703 interface 1000 mVPP

SENSIN Input Sensitivity G.703 interface -15 dB

RLIN Input Return Loss Note 1 -17 dB

RLOUT Output Return Loss Note 1 -17 dB

VOH G.703 G.703 Output Voltage HI Note 2 0.45 0.55 V

VOL G.703 G.703 Output Voltage LO Note 2 -0.55 -0.45 V

Note 1: G.703 interface open collector type. Actual value depends on discrete external circuitry.

Note 2: Measured in 75 Wload via AC- or pulse transformer coupling

Data Sheet Rev.: 6 GD16360 Page 7 of 9

AC Characteristics

All voltages in table are referred to VEE unless otherwise noted.

All input signal and power currents in the table are defined positive into the pin.

All output signal currents are defined positive out of the pin.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

TR-PECL PECL Rise Time Note 1 800 ps

TF-PECL PECL Fall Time Note 1 800 ps

TR-CMOS CMOS Rise Time Note 2 4 ns

TF-CMOS CMOS Fall Time Note 2 4 ns

Note 1: 20-80%,50Wto VDD - 2.0 V.

Note 2: 20-80%,10pFand100mA load.

Package Outline

Figure 2. Package 48 pin TQFP, EDQUAD

Data Sheet Rev.: 6 GD16360 Page 8 of 9

Device Marking

Figure 3. Device Marking, Top View

External References

ITU-T G.703 (04/91): General Aspects of Digital transmissionsystems, terminal equipments.

ITU-T G.775 (11/94): LOS and AIS defect detection criteria.

Ordering Information

To order, please specify as shown below:

Product Name: Intel Order number:Package Type: Ambient Temperature Range:

GD16360-48BA FAGD1636048BA

MM#: 836046

48 Lead TQFP, EDQUAD -5..85 EC

GD16360, Data Sheet Rev.: 6 - Date: 24 July 2001

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

Mileparken 22, DK-2740 Skovlunde

Denmark

Phone : +45 7010 1062

Fax : +45 7010 1063

E-mail : sales@giga.dk

Web site : http://www.intel.com/ixa

Please check our Internet web site

for latest version of this data sheet.

Distributor:

An Intel company

an Intel company

GD16360

<YY WW>