Semiconductor MSC23V47257TD
Notes: 1. A start - up delay of 200µs is required after power-up, fol lowed by a mini mum of eight initializat ion cycles
(/RA S only r efresh or /CAS before / RA S r efr esh) befor e pr oper device operati on is achi eved.
2. The AC c har ac teristi c s assume tT = 2ns.
3. VIH(Min.) and VIL(M ax.) ar e r eference level s for measuring i nput ti ming signals. Transi ti on times (tT) are
m easured bet ween VIH and VIL.
4. This param eter is measured wit h a load circ uit equival ent to 1 TTL load and 100pF.
The out put timing refer enc e level s are VOH = 2.0V and VOL = 0.8V.
5. Operati on withi n the tRCD(M ax.) li mit ensures that t RAC(Max . ) can be met.
tRCD(Max.) is specified as a reference point only . If tRCD is greater than the specified tRCD(Max.) limit, then
the acc ess ti me is contr olled by tCAC.
6. Operati on withi n the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the acc ess ti me is contr olled by tAA.
7. tCEZ(Max. ), t REZ(Max. ), tWEZ( M ax.) and tOEZ(Max . ) def i ne the ti m e at whi ch the out put achi ev es the open
ci r c uit c ondit ion and are not refer enc ed to output volt age level s.
8. tCEZ or tREZ must be satisf ied for open c irc uit c ondit ion.
9. tRCH or tRRH must be satisfi ed for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not r est rict iv e operating param eters. They are i ncluded in t he data
sheet as elect r ical char ac teristi c s onl y. If tWCS ≥ tWCS(Mi n.), t hen the cycle is an early writ e cycle and the
data out will remain open circuit (high i mpedance) throughout t he entir e cycle. If tCWD ≥ tCWD(Min.), t RWD
≥ tRWD(Min.), t AWD ≥ tAWD(Mi n. ) and tCPWD ≥ tCPWD(Mi n.), then the cycl e is a read m odif y write cycl e and
da ta ou t w ill c on ta in d a ta r ead from the selected cell; if neither of the above sets of conditions is s atisfied,
then t he c ondit ion of the data out (at ac c ess ti me) is indetermi nate.
11. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE
leading edge in an /O E control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bi t parallel test funct ion. CA0, CA1 and CA10 are not used. In a read cycl e, if al l i nternal bit s are
equal, the DQ pin will in dic ate a hig h le ve l. If an y in te rn al b its a re no t equal, the DQ pin will in dic at e a low
levels. The test mode is cleared and the memory device returned to its normal operating state by
perform ing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specif ied in test mode cycle by adding the above v alue to the specified
value in this data sheet.