Semiconductor
MSC23V47257TD-xxBS18
4,194,304-Wo rd x 72-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
This version: Apr. 22. 1999
Prev i ous v ersion: Apr. 1. 1999
DESCRIPTION
The MSC23V47257TD-xxBS18 is a 4,194,304-word x 72-bit CMOS dynamic random access memory module w hich
is composed of eighteen 16Mb(4Mx4) DRAMs in TSOP packages mounted with eighteen decoupling capacitors.
This is an 168-pi n dual i n- line memory module. Thi s module supports any appli c ati on where high densi ty and large
capacity of storage memory ar e r equired.
FEATURES
· 4, 194,304-word x 72- bit or ganizati on
· 168-pin Dual In- line Memory M odule
· Gold tab
· Single 3.3V power supply, ±0.3V tolerance
· I nput : LVTTL c ompat ible
· Output : LVTTL compatible, 3-state
· Refresh : 2048cycles/ 32m s
· / CA S before / RA S r efr esh, hidden refresh, /RA S only r efresh capability
· F ast page mode with EDO , read modify wri te capability
· Mult i-bit test mode capability
· Ser ial Presence Det ec t
PRODUCT FAMILY
Access Tim e (Max. ) Power Di ssi pati on (Max. )
Family tRAC tAA tCAC tOEA
Cycle
Time
(Min.) Operating Standby
MSC23V47257TD-50BS18 50ns 25ns 13ns 13ns 84ns 6480mW
MSC23V47257TD-60BS18 60ns 30ns 15ns 15ns 104ns 5832mW
MSC23V47257TD-70BS18 70ns 35ns 20ns 20ns 124ns 5184mW
32.4mW
Semiconductor MSC23V47257TD
MODULE OUTLINE
1
84
36.83±0.05
127.35±0.1
133.35±0.7
*1
4.0Min.
4.00Max.
(U ni t : mm)
2 - R2.0
2 -
φ
3.0±0.1
1.27±0.1
54.61±0.05
17.78±0.1
3.0±0.1
A
B
C
131.35 TYP
133.35±0.12
R1.0
2.0±0.1
3.12±0.1
1.27±0.03
1.0±0.03
0.25 MAX
6.35±0.05
Detail A
2.0±0.1
6.35±0.05
Detail B
3.12±0.1
Detail C
4.175±0.13
3.175±0.13
R1.0
2.54 MIN
11.43±0.05
25.40±0.12
Note:
1. Tolerance over 19.78mm from bottom edge is ±0.7.
Semiconductor MSC23V47257TD
PIN CONF IGUR ATION
Front Side Back Side Front Side Back Si de
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1V
SS 85 VSS 43 VSS 127 VSS
2 DQ0 86 DQ32 44 /OE2 128 NC
3 DQ1 87 DQ33 45 /RAS2 129 NC
4 DQ2 88 DQ34 46 /CAS2 130 /CAS6
5 DQ3 89 DQ35 47 /CAS3 131 /CAS7
6V
CC 90 VCC 48 /WE2 132 NC
7 DQ4 91 DQ36 49 VCC 133 VCC
8 DQ5 92 DQ37 50 NC 134 NC
9 DQ6 93 DQ38 51 NC 135 NC
10 DQ7 94 DQ39 52 CB2 136 CB6
11 DQ8 95DQ4053 CB3137CB7
12 VSS 96 VSS 54 VSS 138 VSS
13 DQ9 97 DQ41 55 DQ16 139 DQ48
14 DQ10 98 DQ42 56 DQ17 140 DQ49
15 DQ11 99 DQ43 57 DQ18 141 DQ50
16 DQ12 100 DQ44 58 DQ19 142 DQ51
17 DQ13 101 DQ45 59 VCC 143 VCC
18 VCC 102 VCC 60 DQ20 144 DQ52
19 DQ14 103 DQ46 61 NC 145 NC
20 DQ15 104 DQ47 62 NC 146 NC
21 CB0 105 CB4 63 NC 147 NC
22 CB1 106 CB5 64 VSS 148 VSS
23 VSS 107 VSS 65 DQ21 149 DQ53
24 NC 108 NC 66 DQ22 150 DQ54
25 NC 109 NC 67 DQ23 151 DQ55
26 VCC 110 VCC 68 VSS 152 VSS
27 /WE0 111 NC 69 DQ24 153 DQ56
28 /CAS0 112 /CAS4 70 DQ25 154 DQ57
29 /CAS1 113 /CAS5 71 DQ26 155 DQ58
30 /RAS0 114 NC 72 DQ27 156 DQ59
31 /OE0 115 NC 73 VCC 157 VCC
32 VSS 116 VSS 74 DQ28 158 DQ60
33 A0 117 A1 75 DQ29 159 DQ61
34 A2 118 A3 76 DQ30 160 DQ62
35 A4 119 A5 77 DQ31 161 DQ63
36 A6 120 A7 78 VSS 162 VSS
37 A8 121 A9 79 NC 163 NC
38 A10 122 NC 80 NC 164 NC
39 NC 123 NC 81 NC 165 SA0
40 VCC 124 VCC 82 SDA 166 SA1
41 VCC 125 NC 83 SCL 167 SA2
42 NC 126 NC 84 VCC 168 VCC
Semiconductor MSC23V47257TD
Serial PD Matrix
Byte No. Function descri bed SPD Value
(Hex) Note
0 Number of Byte used 80 128 Bytes
1 Total SPD M em ory size 08 256 Bytes
2 Memory type 02 EDO
3 Number of Rows 0B 11
4 Number of Columns 0B 11
5 Number of Banks 01 1
6 Module Data Widt h 48 72
7 Module Data Widt h C ont inued 00 0
8 Supply Vol t age 01 LVTTL
-50 32 50ns
-60 3C 60ns9
-70
/RA S A ccess Ti m e
46 70ns
-50 0D 13ns
-60 0F 15ns10
-70
/CA S A ccess Ti m e
14 20ns
11 D I M M C onf i gurat i on t ype 02 ECC
12 R ef resh Rat e/Type 00 Normal R ef resh
13 Prim ary DR AM W idth 04 x4
14 Error Checking DR A M W idth 04 x4
15-61 Superset Informati on 00 Reserved
62 SPD D at a R evi si on Code 01 1
-50 34
-60 4063
-70
Checksum f or Byt e 0-62
4F
64-127 Reserved 00
128-255 Unused Storage Locat i on (Reserved) FF
Semiconductor MSC23V47257TD
BLOCK DIAGRAM
V
CC
V
SS
C1-C18
/RAS0
/WE0
/OE0
DQ0
DQ1
DQ2
DQ3
/CAS0
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D0
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D1
DQ8
DQ9
DQ10
DQ11
/CAS1
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D2
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D3
CB0
CB1
CB2
CB3
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D4
DQ16
DQ17
DQ18
DQ19
/CAS2
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D5
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D6
DQ24
DQ25
DQ26
DQ27
/CAS3
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D7
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D8
/RAS2
/WE2
/OE2
DQ32
DQ33
DQ34
DQ35
/CAS4
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D9
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D10
DQ40
DQ41
DQ42
DQ43
/CAS5
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D11
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D12
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D13
DQ48
DQ49
DQ50
DQ51
/CAS6
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D14
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D15
DQ56
DQ57
DQ58
DQ59
/CAS7
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D16
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
/CAS /RAS /WE /OE
D17
A0-A10
A0-A10 : D0-D17
D0-D17
D0-D17
SCL
SDA
A0 A1 A2
SCL
SDA
SA 0 SA 1 SA 2
Ser i al PD
Semiconductor MSC23V47257TD
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Vol t age on Any Pi n R el at i ve t o V SS VIN, VOUT -0.5 to 4.6 V
Vol t age on V CC Suppl y R el at ive to V SS VCC -0.5 to 4.6 V
Short Ci rcuit O utput C urrent IOS 50 mA
Power Dissipation PD *18W
Operating Temperature TOPR 0 t o 70 °C
Storage Temperature TSTG -40 to 125 °C
* Ta = 25°C
Recommen ded Operat ing Conditions ( Ta = 0°C t o 70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 3.0 3.3 3.6 V
Power Supply Vol tage VSS 000V
Input H i gh Volt age VIH 2.0 - VCC+0.3 V
Input Low Volt age VIL -0.3 - 0.8 V
Capacitance ( V CC = 3.3V ±0.3V, Ta = 25°C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input C apaci t ance (A0 - A10) CIN1 - 122 pF
Input Capaci tance (/RAS0, / R AS2, / WE0, / WE2, / O E0, / O E2) CIN2 -73pF
Input Capaci tance (/CAS0 - /C AS7) CIN3 -28pF
I/ O Capacitance (DQ 0 - DQ 63, C B0 - CB 7) CI/O -16pF
Semiconductor MSC23V47257TD
DC Characteristi cs (VCC = 3.3V ±0.3V, Ta = 0°C to 70°C )
-50 -60 -70
Parameter Symbol Condition Min. Max. Min. Max. Min. Max. Unit Note
Output High Voltage VOH IOH = -2.0mA 2.4 VCC 2.4 VCC 2.4 VCC V
Output Low Volt age VOL IOL = 2.0m A 0 0.4 0 0.4 0 0.4 V
Input Leakage C urrent ILI
0V ≤ VIN ≤ VCC+0.3V;
All other pins not
under test = 0V -180 180 -180 180 -180 180 µA
Output Leakage Current ILO DQ di sabl e
0V ≤ VOUT ≤ VCC -10 10 -10 10 -10 10 µA
Average Power
Supply Current
(Operating) ICC1 / R AS, / CAS cycli ng,
tRC = Min. - 1800 - 1620 - 1440 mA 1, 2
/RAS, / C AS = VIH -36-36-36mA
Power Supply Current
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -9-9-9mA
1
Average Power
Supply Current
(/RAS only ref resh) ICC3
/RAS cycli ng,
/CAS = VIH,
tRC = Min. - 1800 - 1620 - 1440 mA 1, 2
Average Power
Supply Current
(/CAS before /R AS refresh) ICC6 /RAS cycli ng,
/CAS bef ore /R AS - 1800 - 1620 - 1440 m A 1, 2
Average Power
Supply Current
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cycli ng,
tHPC = Mi n. - 1800 - 1620 - 1440 mA 1, 3
Notes: 1. ICC Max. i s specified as ICC for output open c ondit ion.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
Semiconductor MSC23V47257TD
AC Characteristics (1/ 2) (VCC = 3. 3V ±0.3V, Ta = 0°C t o 70°C ) Not e: 1, 2, 3, 12, 13
-50 -60 -70
Parameter Symbol Min. Max. Min. Max. Min. Max. Unit Note
Random R ead or Write C ycl e Time tRC 84 - 104 - 124 - ns
Read Modi f y Writ e C ycl e Tim e tRWC 110 - 135 - 160 - ns
Fast Page M ode Cycl e Tim e tHPC 20 - 25 - 30 - ns
Fast Page M ode Read M odify Writ e Cycle Time tHPRWC 58 - 68 - 78 - ns
Access Time f rom /RAS tRAC -50-60-70ns4, 5, 6
Access Time f rom /CAS tCAC -13-15-20ns4, 5
Access Time from C ol um n Address tAA -25-30-35ns4, 6
Access Time from / CAS Precharge tCPA -30-35-40ns4
Access Time f rom /OE tOEA -13-15-20ns4
Output Low I m pedance Time f rom / C AS t CLZ 0-0-0-ns4
Data Output Hold After /CAS Low tDOH 5-5-5-ns
/CAS to Data Output Buffer Turn-off Delay Time tCEZ 013015020ns7, 8
/RAS to Data Output Buffer Turn-off Delay Time tREZ 013015020ns7, 8
/OE to Data Output Buff er Turn-off Delay Time tOEZ 013015020ns7
/WE to Data Output Buff er Turn-off Delay Time tWEZ 013015020ns7
Transit i on Tim e tT150150150ns3
Refresh Period tREF -32-32-32ms
/RAS Precharge Time tRP 30 - 40 - 50 - ns
/RAS Pul se W i dt h tRAS 50 10K 60 10K 70 10K ns
/RAS Pul se W i dth (Fast Page Mode w i t h ED O) tRASP 50 100K 60 100K 70 100K ns
/RAS Hold Time tRSH 7 - 10 - 13 - ns
/RAS Hold Time referenced to /OE tROH 7 - 10 - 13 - ns
/CAS Precharge Time (Fast Page Mode with EDO ) tCP 7 - 10 - 10 - ns
/CAS Pul se W i dt h tCAS 7 10K 10 10K 13 10K ns
/CAS Hold Time tCSH 35 - 40 - 45 - ns
/CAS t o / RAS Precharge Time tCRP 5-5-5-ns
/RAS Hold Time from /CAS Precharge tRHCP 30 - 35 - 40 - ns
/OE Hold Time from /CAS (DQ Disable) tCHO 5-5-5-ns
/RAS to /CAS Delay Time tRCD 11 37 14 45 14 50 ns 5
/RAS to Column Address Delay Time tRAD 9 2512301235 ns6
Row Address Set-up Time tASR 0-0-0-ns
Row Address Hold Time tRAH 7 - 10 - 10 - ns
Colum n Address Set-up Time tASC 0-0-0-ns
Colum n Address Hol d Time tCAH 7 - 10 - 13 - ns
Colum n Address to / R AS Lead Time tRAL 25 - 30 - 35 - ns
Semiconductor MSC23V47257TD
AC Characteristics (2/ 2) (VCC = 3. 3V ±0.3V, Ta = 0°C t o 70°C ) Not e: 1, 2, 3, 12, 13
-50 -60 -70
Parameter Symbol Min. Max. Min. Max. Min. Max. Unit Note
Read Com m and Set -up Time t RCS 0-0-0-ns
Read Com m and Hold Time tRCH 0-0-0-ns9
Read Comm and H ol d Time referenced to / R AS tRRH 0-0-0-ns9
Write Com m and Set -up Time tWCS 0-0-0-ns10
Write Com m and H ol d Time tWCH 7 - 10 - 13 - ns
Write Com m and Pul se Widt h tWP 7 - 10 - 10 - ns
/W E Pul se W i dth (DQ Di sabl e) tWPE 7 - 10 - 10 - ns
/OE Com m and H old Time tOEH 7 - 10 - 13 - ns
/OE Precharge Time tOEP 7 - 10 - 10 - ns
/OE Com m and H old Time tOCH 7 - 10 - 10 - ns
Write Comm and to /RAS Lead Time tRWL 7 - 10 - 13 - ns
Write Comm and to /CAS Lead Time tCWL 7 - 10 - 13 - ns
Data-in Set -up Time tDS 0-0-0-ns11
Data-in Hold Time tDH 7 - 10 - 13 - ns 11
/OE to Data-in Delay Time tOED 13 - 15 - 20 - ns
/CAS to /WE Delay Time tCWD 30 - 34 - 44 - ns 10
Column Address to /WE Delay Time t AWD 42 - 49 - 59 - ns 10
/RAS to /WE Delay Time tRWD 67 - 79 - 94 - ns 10
/CAS Precharge /W E Del ay Time tCPWD 47 - 54 - 64 - ns 10
/CAS Active Delay Time from /RAS Precharge tRPC 5-5-5-ns
/RAS t o /C AS Set -up Time (/CAS before /RAS) tCSR 5-5-5-ns
/RAS t o /C AS Hol d Time (/CAS before /RAS) tCHR 10 - 10 - 10 - ns
/W E t o / R AS Precharge Time (/CAS before /RAS) tWRP 10 - 10 - 10 - ns
/WE Hold Time from /RAS (/CAS before /RAS) tWRH 10 - 10 - 10 - ns
/RAS t o / W E Set-up Time (Test Mode) tWTS 10 - 10 - 10 - ns
/RAS t o / W E H ol d Time (Test M ode) tWTH 10 - 10 - 10 - ns
Semiconductor MSC23V47257TD
Notes: 1. A start - up delay of 200µs is required after power-up, fol lowed by a mini mum of eight initializat ion cycles
(/RA S only r efresh or /CAS before / RA S r efr esh) befor e pr oper device operati on is achi eved.
2. The AC c har ac teristi c s assume tT = 2ns.
3. VIH(Min.) and VIL(M ax.) ar e r eference level s for measuring i nput ti ming signals. Transi ti on times (tT) are
m easured bet ween VIH and VIL.
4. This param eter is measured wit h a load circ uit equival ent to 1 TTL load and 100pF.
The out put timing refer enc e level s are VOH = 2.0V and VOL = 0.8V.
5. Operati on withi n the tRCD(M ax.) li mit ensures that t RAC(Max . ) can be met.
tRCD(Max.) is specified as a reference point only . If tRCD is greater than the specified tRCD(Max.) limit, then
the acc ess ti me is contr olled by tCAC.
6. Operati on withi n the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the acc ess ti me is contr olled by tAA.
7. tCEZ(Max. ), t REZ(Max. ), tWEZ( M ax.) and tOEZ(Max . ) def i ne the ti m e at whi ch the out put achi ev es the open
ci r c uit c ondit ion and are not refer enc ed to output volt age level s.
8. tCEZ or tREZ must be satisf ied for open c irc uit c ondit ion.
9. tRCH or tRRH must be satisfi ed for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not r est rict iv e operating param eters. They are i ncluded in t he data
sheet as elect r ical char ac teristi c s onl y. If tWCS ≥ tWCS(Mi n.), t hen the cycle is an early writ e cycle and the
data out will remain open circuit (high i mpedance) throughout t he entir e cycle. If tCWD ≥ tCWD(Min.), t RWD
≥ tRWD(Min.), t AWD ≥ tAWD(Mi n. ) and tCPWD ≥ tCPWD(Mi n.), then the cycl e is a read m odif y write cycl e and
da ta ou t w ill c on ta in d a ta r ead from the selected cell; if neither of the above sets of conditions is s atisfied,
then t he c ondit ion of the data out (at ac c ess ti me) is indetermi nate.
11. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE
leading edge in an /O E control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bi t parallel test funct ion. CA0, CA1 and CA10 are not used. In a read cycl e, if al l i nternal bit s are
equal, the DQ pin will in dic ate a hig h le ve l. If an y in te rn al b its a re no t equal, the DQ pin will in dic at e a low
levels. The test mode is cleared and the memory device returned to its normal operating state by
perform ing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specif ied in test mode cycle by adding the above v alue to the specified
value in this data sheet.