1 www.altera.com/enpirion
Enpirion® Power Datasheet
EP5388QI 800mA PowerSoC
Synchronous Buck Regulator
With Integrated Inductor
Product Overview
The EP5388QI is a synchronous buck converter
with integrated Inductor, PWM controller,
MOSFETS, and Compensation providing the
smallest possible solution size. The EP5388QI
requires only two small MLCC capacitors to make a
complete solution. Integration of the inductor
greatly simplifies design, contains noise, reduces
part count, and reduces solution footprint. Low
output ripple ensures compatibility with RF
systems.
The EP5388QI operates at a switching frequency of
4 MHz, enabling this unprecedented level of
integration and small external components. Type III
voltage mode control is used to provide high noise
immunity and wide control loop bandwidth.
The small footprint makes this part ideal for space
constrained portable applications. Shutdown
current of <1uA extends battery life Output voltage
level is programmed via a 3-pin VID selector
providing seven pre-programmed output voltages
along with an option for external resistor divider.
Applications
• Noise sensitive RF applications
• Area constrained applications
• Wireless data applications
• Portable gaming devices
• Personal Media Players
• Advanced Mobile Processors, DSP, IO,
Memory, Video, Multimedia Engines
Features
• 3mm x 3mm x 1 .1mm QFN package
• Only two low cost MLCC caps required
• 4 MHz switching frequency
• High efficiency, up to 94%
• Up to 800mA continuous output current
• Wide 2.4V to 5.5V input range
• VOUT Range: 0.6V to VIN – 0.5V
• 3-Pin VID output voltage programming
• 100% duty cycle capable
• Less than 1 µA standby current
• Low VOUT ripple for RF compatibility
• Short circuit and over current protection
• UVLO and thermal protection
• RoHS compliant; MSL 3 260°C reflow
Figure 1. Integrated Inductor Technology
VIN VSense
Vin
V
S1
V
S2
V
S0
EP5388QI 47µF
1206
4.7µF
0603
VOUT
Vout
GND
ENABLE
VFB
Voltage
Select
Figure 2. Typical application circuit
02377 Decemeber 11, 2017 Rev G
EP5388QI
2 www.altera.com/enpirion
Orderin g Information
Part Number
TAMBIENT Rating (° C)
Package Description
EP5388QI
-40 to +85
16 pin (3mm x 3mm x 1.1mm) QFN T&R
EP5388QI-E
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
Figure 3. EP5388QI Package Pin-out
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they m ust be soldered to the PCB. Fai l ure to follow this guideli ne may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
FUNCTION
1, 15, 16 NC(SW)
NO CONNECT – These pins are internally connected to the common drain output of
the internal MOSFE T s. NC(SW) pins are not to be electrically connected to any
external signal, ground, or voltage. How ever, they must be soldered to the PCB.
Failure to follow this guideline may result in part malfunction or damage.
2,3
PGND
Power Ground
4 VFB
Feedback pin for external divider option. When using the external divider option
(VS0=VS1=VS2= high) connect t hi s pin to the center of the external divider. Set the
divider such that V FB = 0.6V. The “ground” side of the external divider should be
connected to AGND. This pin may be le ft unconnected when using Voltage Sel ect
pins (VS0-VS2) to set the output voltage.
5 VSENSE
Sense pin for output voltage regulation. Refer to application section for prop er
configuration.
6
AGND
Analog ground. T hi s is t he quiet ground for the internal control circuitry
7,8 VOUT
Regulated Output Voltage. Refer to application section for proper layout and
decoupling.
9 NC
NO CONNECT – This pin should not be el ect rically conne cted t o any external signal,
voltage, or ground. This pin may be connected internally. Howev er, this pin must be
soldered to the PCB.
NC(SW)
PGND
VFB
VSENSE
AGND
1
2
3
4
5
6
VIN
ENABLE
VS0
VS1
NC
14
13
12
11
10
9
NC(SW)
NC(SW)
16
15
PGND
VOUT
VS2
7
8
VOUT
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PIN
NAME
FUNCTION
10, 11, 12 VS0,VS1,VS2
Output voltage select. VS2=pin10 V S1=pin11, VS0=pin12. Selects one of seven
preset output vol tages or choose extern al di vider by connecting pins to logic high or
low. Refer to section on output voltage select for more detail.
13
ENABLE
Output enable. Enable = logic high, disable = logic low.
14
VIN
Input voltage pin. Refer to application section for proper layout and decoupling.
Functional Block Diagram
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
VSENSE
VFB
VOUT
VS0 VS1 VS2
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
VIN
ENABLE
GND
Logic
Compensation
Network
NC(SW)
Figure 4. Function al bl ock diagram
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Absolut e Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute m aximum rated c ondi tions for ext ended periods may affect device reliabili ty.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Volt age
VIN
-0.3
7.0
V
Voltages on: ENABLE, VSENSE, VS0-VS2
-0.3
VIN + 0.3
V
Voltage on: VFB
-0.3
2.7
V
Storage Temperature Ran ge
TSTG
-65
150
°C
Reflow Temp, 10 S ec, M S L3 JEDEC J-STD-020C
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
VIN
2.4
5.5
V
Output Voltage Range
VOUT
0.603
VIN – 0.5
V
Output Current
IOUT
0
800
mA
Operating Ambi ent Temperature
TA
-40
+85
°C
Operating Junction T emperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Am bi ent (0 LFM)
θJA
100
°C/W
Thermal Overload Trip Point
TJ-TP
+150
°C
Thermal Overload Trip Point Hyster esis
15
°C
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at T A = 25°C, VIN = 3.6V. CIN =4.7µF 0603 MLCC,
COUT = 47µF 1206 MLCC.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOUT Initial Accuracy
∆VOUT_Initl
TA = 25C, 2.4V ≤ VIN ≤ 5.5V
-2%
+2%
Line Regulation
∆VOUT_linel
2.4V ≤ VIN ≤ 5.5V
0.0566
%/V
Load Regulation
∆VOUT_load
0A ≤ ILOAD ≤ 800mA
0.0003
%/mA
Temperature Variati on
∆VOUT_templ
-40°C ≤ TA ≤ +85°C
0.0078
%/°C
Overall V
OUT
Accuracy
(Line, Load, and
Temperature combined )
∆VOUT_All
2.4V ≤ V
IN
≤ 5.5V
-40°C ≤ TA ≤ +85°C
0A ≤ ILOAD ≤ 800mA
-3% +3%
Dropout Resistance
RDROPOUT
400
500
mΩ
Dynamic Voltage Slew
Rate
Vslew 0.975 1.5 2.025 V/ms
Continuous Output
Current
IOUT
-20°C ≤ T
A
≤ +85°C
-40°C ≤ TA ≤ +85°C
800
750
mA
Shut-Down Current
ISD
Enable = Low
0.75
µA
PFET OCP Threshold
ILIM
1000
mA
Feedback Pin Vol tage
VFB
0.603
V
Feedback Pin Input
Current
IFB 100 nA
VS0-VS1, Enable Voltage
Threshold
VTH
Pin = Low
Pin = High
0.0
1.4
0.4
VIN
VS0-VS2 Pin Input
Current
IVSX 1 nA
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
FOSC
4
MHz
PFET On Resistance
RDS(ON)
340
mΩ
NFET On Resistance
RDS(ON)
270
mΩ
Soft-Start Operation
Soft-Start Slew Rate VSS VID programming mode 0.975 1.5 2.025 V/ms
VOUT Rise Time TSS VFB programming m ode 0.784 1.2 1.628 ms
Typical P erformance Cha racteristics
Efficiency, VIN = 3.3V, VOUT = 1.2V, 1.5V,1.8V, 2.5V. Efficiency, VIN = 3.7V, VOUT = 1.2V, 1.5V,1.8V, 2.5V.
Efficiency, VIN = 5V, VOUT = 1.2V, 1.5V,1.8V, 2.5V, 3.3V. Output Ripple, VIN = 5V, VOUT = 1.2V; Load = 500mA.
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency (%)
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Output Ripple, VIN = 5V, VOUT = 1.8V; Load = 500mA. Output Ripple, VIN = 5V, VOUT = 2.5V; Load = 500mA.
Output Ripple, VIN = 5V, VOUT = 3.3V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 1.2V; Load = 500mA.
Output Ripple, VIN = 3.3V, VOUT = 1.8V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 2.5V; Load = 500mA.
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Transient, VIN = 5.0V, VOUT = 1.2V, Load = 0-800mA. Transient, VIN = 5.0V, VOUT = 3.3V, Load = 0-800mA.
Transient, VIN =3.3V, VOUT = 1.2V, Load = 0-800mA. Transient, VIN = 3.3V, VOUT = 1.8V, Load = 0-800mA.
Startup, VIN = 3.6V, VOUT = 1.5V, Load = 500mA. Shutdown, VIN = 3.6V, VOUT = 1.5V, Load = 500mA.
Enable in light blue; Vout in Dark blue. Enable in light blue; Vout in Dark blue.
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Detailed Description
Functional Overview
The EP5388QI is a complete DCDC converter
solution requiring only two low cost MLCC
capacitors. MOSFET switches, PWM controller,
Gate-drive, compensation, and inductor are
integrated into the tiny 3mm x 3mm x 1.1mm
package to provide the smallest footprint possible
while maintaining high efficiency, low ripple, and
high performance. The converter uses voltage
mode control to provide the simplest
implementation and high noise immunity. The
device operates at a 4MHz switching frequency.
The high switching frequency allows for a wide
control loop bandwidth providing excellent transient
performance. The high switching frequency further
enables the use of very small components making
possible this unprecedented level of integration.
Altera’s proprietary power MOSFET technology
provides very low switching loss at frequencies of 4
MHz and higher, allowing for the use of very small
internal components, and high performance.
Integration of the magnetics virtually eliminates the
design/layout issues normally associated with
switch-mode DCDC converters. All of this enables
much easier and faster incorporation into various
applications to meet demanding EMI requirements.
Output voltage is chosen from seven preset values
via a three pin VID voltage select scheme. An
external divider option enables the selection of any
voltage in VIN to 0.6V range. This reduces the
number of components that must be qualified and
reduces inventory burden. The VID pins can be
toggled on the fly to implement glitch free dynamic
voltage scaling.
Protection features include under-voltage lock-out
(UVLO), over-current protection (OCP), short circuit
protection, and thermal overload protection.
Integrated Inductor
Altera has introduced the world’s first product family
featuring integrated inductors. The EP5388QI
utilizes a proprietary low loss integrated inductor.
The use of an internal inductor localizes the noises
associated with the output loop currents. The
inherent shielding and compact construction of the
integrated inductor reduces the radiated noise that
couples into the traces of the circuit board. Further,
the package layout is optimized to reduce the
electrical path length for the AC ripple currents that
are a major source of radiated emissions from
DCDC converters. The integrated inductor
significantly reduces parasitic effects that can harm
loop stability, and makes layout very simple.
Stable Over Wide Range of Operating
Conditions
The EP5388QI utilizes an internal type III
compensation network and is designed to provide a
high degree of stability over a wide range of
operating conditions. The device operates over the
entire input and output voltage range with no
external modifications required. The very high
switching frequency allows for a very wide control
loop bandwidth.
Soft Start
Internal soft start circuits limit in-rush current when
the device starts up from a power down condition or
when the “ENABLE” pin is asserted “high”. Digital
control circuitry limits the VOUT ramp rate to levels
that are safe for the Power MOSFETS and the
integrated inductor.
The EP5388QI has two soft start operating modes.
When VOUT is programmed using a preset voltage
in VID mode, the device has a constant slew rate.
When the EP5388QI is configured in external
resistor divider mode, the device has a constant
VOUT ramp time. Output voltage slew rate and
ramp time is given in the Electrical Characteristics
Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. Maximum allowable output capacitance
depends on the device’s minimum current limit, the
output current at startup, the minimum soft-start
time and the output voltage (all are listed in the
Electrical Characteristics Table). The total
maximum capacitance on the output rail is
estimated by the equation below:
COUT_MAX = 0.7 * (ILIMIT - IOUT) * tSS / VOUT
COUT_MAX = maximum allowable output capacitance
ILIMIT = minimum current limit = 0.8A
IOUT = output current at startup
VOUT = output voltage
0.7 = margin factor
tSS(VFB) = min soft-start time
= 0.784ms External feedback setting
tSS(VID) = VOUT [V] / 2.025 [V/ms] VID setting
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The soft-start time in VID setting is different than
External Feedback (VFB) setting, so be sure to use
the correct value when calculating the maximum
allowable output capacitance.
NOTE: Do not use excessive output capacitance
since it may affect device stability. The EP5388QI
has high loop bandwidth and 80µF is all that is
needed for transient response optimization.
Over Current/Sh ort Circuit Prote ction
The current limit function is achieved by sensing
the current flowing through a sense P-MOSFET
which is compared to a reference current. When
this level is exceeded the P-FET is turned off and
the N-FET is turned on, pulling VOUT low. This
condition is maintained for a period of 1ms and
then a normal soft start is initiated. If the over
current condition still persists, this cycle will repeat
in a “hiccup” mode.
Under Voltage Lockout
During initial power up an under voltage lockout
circuit will hold-off the switching circuitry until the
input voltage reaches a sufficient level to insure
proper operation. If the voltage drops below the
UVLO threshold the lockout circuitry will again
disable the switching. Hysteresis is included to
prevent chattering between states.
Enable
The ENABLE pin provides a means to shut down
the converter or enable normal operation. A logic
low will disable the converter and cause it to shut
down. A logic high will enable the converter into
normal operation. In shutdown mode, the device
quiescent current will be less than 1 uA. At
extremely cold conditions below -30°C, the
controller may not be properly powered if ENABLE
is tied directly to AVIN during startup. It is
recommended to use an external RC circuit to
delay the ENABLE voltage rise so that the internal
controller has time to startup into regulation (see
circuit below). The RC circuit may be adjusted so
that AVIN and PVIN are above UVLO before
ENABLE is high. The startup time will be delayed
by the extra time it takes for the capacitor voltage to
reach the ENABLE threshold.
NOTE: This pin must not be left floating.
Figure 5. ENABLE Delay Circuit
Thermal Shut d o wn
When excessive power is dissipated in the chip, the
junction temperature rises. Once the junction
temperature exceeds the thermal shutdown
temperature the thermal shutdown circuit turns off
the converter output voltage thus allowing the
device to cool. When the junction temperature
decreases to a safe operating level, the device will
go through the normal startup process. The specific
thermal shutdown junction temperature and
hysteresis values can be found in the thermal
characteristics table.
Application Information
Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP5388QI uses a 3
pin VID, or Voltage ID, output voltage select
arrangement. This allows the designer to choose
one of seven preset voltages, or to use an external
voltage divider. Internally, the output of the VID
multiplexer sets the value for the voltage reference
DAC, which in turn is connected to the non-
inverting input of the error amplifier. This allows the
use of a single feedback divider with constant loop
gain and optimum compensation, independent of
the output voltage selected.
Table 1 shows the various VS0-VS2 pin logic states
and the associated output voltage levels. A logic “1”
indicates a connection to VIN or to a “high” logic
voltage level. A logic “0” indicates a connection to
ground or to a “low” logic voltage level. These pins
can be either hardwired to VIN or GND or
alternatively can be driven by standard logic levels.
Logic low is defined as VLOW ≤ 0.4V. Logic high is
defined as VHIGH ≥ 1.4V. Any level between these
02377 Decemeber 11, 2017 Rev G
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two values is indeterminate. These pins must not
be left floating.
VS2
VS1
VS0
VOUT
0
0
0
3.3V
0
0
1
2.5V
0
1
0
1.8V
0
1
1
1.5V
1
0
0
1.25V
1
0
1
1.2V
1
1
0
0.8V
1 1 1
User
Selectable
Table 1. VID voltage sel ect settings
External Vol ta ge D ivi der
As described above, the external voltage divider
option is chosen by connecting the VS0, VS1, and
VS2 pins to VIN or logic “high”. The EP5388QI
uses a separate feedback pin, VFB, when using the
external divider. VSENSE must be connected to
VOUT as indicated in Figure 6.
VIN
V
Sense
V
in
V
S1
V
S2
V
S0
EP5388QI 47µF
1206
4.7µF
0603
V
OUT
V
out
GND
ENABLE
Ra
Rb
V
FB
Figure 6. External Divider application circuit
The output voltage is selected by the following
formula:
( )
Rb
Ra
OUT
VV += 1603.0
Ra must be chosen as 200KΩ to maintain loop
gain. Then Rb is given as:
Ω
−
=603.
0
10
206.1 5
OUT
bVx
R
VOUT can be programmed over the range of 0.6V to
VIN-0.5V.
Dynamic all y Adjus t able O ut put
The EP5388QI is designed to allow for dynamic
switching between the predefined VID voltage
levels. The inter-voltage slew rate is optimized to
prevent excess undershoot or overshoot as the
output voltage levels transition. The slew rate is
identical to the soft-start slew rate of 1.5V/mS.
Dynamic transitioning between internal VID settings
and the external divider is not allowed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted
before VIN. During power down, the VIN should not
be powered down before the ENABLE. Tying PVIN
and ENABLE together during power-up or power-
down meets this requirement.
Pre-Bias Start-up
The EP5388QI does not support startup into a pre-
biased condition. Be sure the output capacitors are
not charged or the output of the EP5388QI is not
pre-biased when the EP5388QI is first enabled.
Input and Output Capacitors
The input capacitance requirement is 4.7uF 0603
MLCC. Altera recommends that a low ESR MLCC
capacitor be used. The input capacitor must use a
X5R or X7R or equivalent dielectric formulation.
Y5V or equivalent dielectric formulations lose
capacitance with frequency, bias, and with
temperature, and are not suitable for switch-mode
DC-DC converter input filter applications.
A variety of output capacitor configurations are
possible depending on footprint and ripple
requirements. For applications where VIN range is
up to 5.5V, it is recommended to use a single 47uF
1206 MLCC capacitor. Ripple performance can be
improved by using 2 x 22uF 0805 MLCC
capacitors.
A single 10uF 0805 MLCC can be used if VOUT
programming is accomplished using an external
divider, with the addition of a 10pF phase lead
capacitor as shown in Figure 7. Note that in this
configuration, VSENSE should NOT be connected to
VOUT. This modification is necessary to ensure
proper operation of the compensation network over
the range of operating conditions.
As described in the Soft Start section, there is a
limitation on the maximum bulk capacitance that
can be placed on the output of this device. Please
refer to the section on Soft Start for more details.
The output capacitor must use a X5R or X7R or
equivalent dielectric formulation. Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and temperature and are not
suitable for switch-mode DC-DC converter output
filter applications.
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X
VIN
V
Sense
V
in
V
S1
V
S2
V
S0
EP5388QI 10µF
0805
4.7µF
0603
V
OUT
V
out
GND
ENABLE
Ra
Rb
V
FB
10pF
Figure 7. Applications circuit for COUT = 1 x 10uF 0805
Layout Consider ations*
*Optimized PCB layout file is downloadable from
the Altera website to assure first pass design
success.
Refer to Figure 8 for the following layout
recommendations.
Recommendation 1: The input and output filter
capacitors should be placed as close to the
EP5388QI as possible to reduce EMI from input
and output loop AC currents. This reduces the
physical area of these AC current loops.
Recommendation 2: The system ground plane
should be the first layer immediately below the
surface layer (PCB layer 2). If it is not possible to
make PCB layer 2 the system ground plane, a local
ground island should be created on PCB layer 2
under the Altera Enpirion device and including the
area under the input and output filter capacitors.
This ground plane, or ground island, should be
continuous and uninterrupted underneath the Altera
Enpirion device and the input and output filter
capacitors.
Recommendation 3: The surface layer ground
pour should include a “slit” as shown in Figure 8 to
separate the input and output AC loop currents.
This will help reduce noise coupling from the input
current loop to the output current loop.
Recommendation 4: Multiple small vias
(approximately 0.25mm finished diameter) should
be used to connect the ground terminals of the
input and output capacitors, and the surface ground
pour under the device, to the system ground plane.
If a local ground island is used on PCB layer 2, the
vias should connect to the ground island and
continue down to the PCB system ground plane.
Recommendation 5: The AGND pin should be
connected to the system ground plane using a via
as described in recommendation 4. AGND must
NOT be connected to the surface layer ground
pour.
Recommendation 6: As with any switch-mode DC-
DC converter, do not run any sensitive signal or
control lines under the converter package.
Figure 8. PCB layout recommendation
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Revision History
Rev
Date
Change(s)
F June, 2017 Max Bulk Cap (COUT_MAX) equation updated to reflect loading an d s t artup
time (with margin added)
G Dec, 2017 Revision Histor y added
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights res erved. ALTERA, ARRIA, CYCLO NE , ENPI RION, HARDCOPY, MAX, MEGACORE, NIO S , Q UA RTUS and STRATIX
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trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
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notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
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02377 Decemeber 11, 2017 Rev G
