Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www . exa r .c om
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XRT75R06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
DECEMBER 2004 REV. 1.0.0
GENERAL DESCRIPTION
The XRT75R06 is a six channel fully integrated Line
Interface Unit (LIU) featuring EXAR’s R3 Technology
(Reconfigurable, Relayless, Redundancy) for E3/
DS3/STS-1 applications. The LIU incorporates 6
independent Receivers, Transmitters and Jitter
Attenuators in a single 217 Lead BGA package.
Each channel of the XRT75R06 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75R06’s differential receiver provides high
noise in terference margi n and is able to rece ive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75R06 incorporates an advanced crystal-
less j it ter a tten uator per c hann el th at ca n be se lec te d
either in the transmit or receive path. The jitter
attenuator performan ce meets the ETSI TBR-24 an d
Bellcore GR-499 specifications.
The XRT75R06 provides a Parallel Microprocessor
Interface for programming and control.
The XRT75R06 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bi t
error for diagnostic purposes.
APPLICATIONS
•E3/DS3 Access Equipment
•DSLAMs
•Digital Cross Connect Sys tems
•CSU/DSU Equipment
•Routers
•Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R06
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT75R06IB 217 Lead BGA -40°C to +85°C
XRT75R06
XRT75R06
Channel 5
Channel 0
Channel n...
Device
Monitor
MTIP_n
MRing_n
DMO_n
Timing
Control
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
Tx
Control
Jitter
Attenuator MUX
Line
Driver
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer Jitter
Attenuator
µProcessor Interface
Local
LoopBack
Clock & Da ta
Recovery
Clock
Synthesizer
RD
WR
Addr[7:0]
CS
INT
D[7:0]
TxON
TxClk_n
TxPOS_n
TxNEG_n
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
RLOL_n
RTIP_n
RRing_n
TTIP_n
TRing_n
CLKOUT_n
SFM_en
E3Clk
DS3Clk
STS-Clk/12M
ICT
Pmode
RDY
PCLK
RESET
XRT75R06
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FEATURES
RECEIVER
•R3 Technology (Reconfigurable, Relayless,
Redundancy)
•On chip Clock and Data Recovery circuit for high
input jitter tolerance
•Meets E3/DS3/STS-1 Jitter Tolerance Requirement
•Detects and Clears LOS as per G.775
•Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
•On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
•On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
•Provides low jitter output clock
TRANSMITTER
•R3 Technology (Reconfigurable, Relayless,
Redundancy)
•Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
•Tri-state Transmit output capability for redundancy
applications
•Each Transmitter can be independently turned on
or off
•Transmitters provide Voltage Output Drive
JITTER ATTENUATOR
•On chip advanced crystal-less Jitter Attenuator for
each channe l
•Jitter Attenuator can be selected in Receive,
Transmit path, or disabled
•Meets ETSI TBR 24 Jitter Transfer Requirements
•Compliant with jitter transfer template outlined in
ITU G.751, G. 752 , G .75 5 a nd G R- 49 9-C OR E, 199 5
standards
•16 or 32 bits selectable FIFO size
CONTROL AND DIAGNOSTICS
•Parallel Microprocessor Interface for control and
configuration
•Supports optional internal Transmit driver
monitoring
•Each ch ann el su ppo rts A nal og, Rem ote and Digi tal
Loop-backs
•Single 3.3 V ± 5% power supply
•5 V Tolerant digital inputs
•Available in 217 pin BGA Package
•- 40°C to 85°C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
•Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and gen erates a bipol ar signal
to the line
•Integrated Pulse Shaping Circuit
•Built-in B3ZS/HDB3 Encoder (which can be
disabled)
•Accepts Transmit Clock with duty cycle of 30%-
70%
•Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
•Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
•Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
•Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
•Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
•Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
•Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
•Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
•Declares Loss of Lock (LOL) Alarm
•Built-in B3ZS/HDB3 Decoder (which can be
disabled)
•Recovered Data can be muted while the LOS
Condition is declared
•Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
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XRT75R06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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FIGURE 2. XRT75R06 IN BGA PACKAGE (BOTTOM
VIEW)
117 16 15 14 12 12 32765411 10 9 8
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
(See pin list for pin names and function)
XRT75R06
XRT75R06
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TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS ......................................................................................................................................... ..... 1
Figure 1. Block Diagram of the XRT 75R06 ................................................................................................. ..... 1
ORDERING INFORMATION ........................................................................................................... ...... .. 1
FEATURES .................................................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 2. XRT75R06 in BGA package (Bottom View) ....................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ............... ................... .................... ................... ................... .................... .............. .......... 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
ANALOG POWER AND GROUND ................................................................................................................... 12
DIGITAL POWER AND GROUND ................. .................... ................... ................... .................... ................... ... 14
FUNCTIONAL DESCRIPTION ......................................................................................... 16
1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16
1.1 NETWORK ARCHITECTURE ................................................................................................................................ 16
Figure 3. Network Redundancy Architecture ................................................................................................. 16
2.0 clock Synthesizer ............................................................................................................................. 17
2.1 CLOCK DISTRIBUTION ....................................................................................................................................... 17
Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 17
Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 17
3.0 The Receiver Section ....................................................................................................................... 18
Figure 6. Receive Path Block Diagram ........................................................................................................... 18
3.1 RECEIVE LINE INTERFACE ................................................................................................................................. 18
Figure 7. Receive Line Interfac eCo nne ction ...... ................... ....... ...... ...... ....... ...... ....... ...... ............................. 18
3.2 ADAPTIVE GAIN CONTROL (AGC) ..................................................................................................................... 19
3.3 RECEIVE EQUALIZER ........................................................................................................................................ 19
Figure 8. ACG/Equali ze r Bloc k Diag ram .................. ....... ...... ....... ...... ................... ....... ...... ....... ...... ................ 19
3.3.1 Recommendations for Equalizer Settings ....................................................................................... 19
3.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 19
3.4.1 Data/Clock Recovery Mode ............................................................................................................... 19
3.4.2 Training Mode ..................................................................................................................................... 19
3.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 20
3.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 20
3.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 20
TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 20
3.5.3 E3 LOS Condition: ............................................................................................................................. 21
Figure 9. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 21
Figure 10. Loss of Signal Definition for E3 as per ITU-T G.775. ..................................................................... 21
3.5.4 Interference Tolerance ....................................................................................................................... 22
Figure 11. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 22
Figure 12. Interference Margin Test Set up for E3. ......................................................................................... 22
TABLE 2: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 23
3.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 24
3.6 B3ZS/HDB3 DECODER .................................................................................................................................... 24
Figure 13. Receiver Data output and code violation timing ............................................................................ 24
4.0 The Transmitter Section .................................................................................................................. 25
Figure 14. Transmit Path Block Diagram ........................................................................................................ 25
4.1 TRANSMIT DIGITAL INPUT INTERFACE ................................................................................................................ 25
Figure 15. Typical interface between terminal equipment and the XRT75R06 (dual-rail data) ....................... 25
Figure 16. Transmitter Terminal Input Timing ................................................................................................. 26
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Figure 17. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 26
4.2 TRANSMIT CLOCK ............................................................................................................................................ 27
4.3 B3ZS/HDB3 ENCODER ................................................................................................................................... 27
4.3.1 B3ZS Encoding .................................................................................................................................. 27
4.3.2 HDB3 Encoding .................................................................................................................................. 27
Figure 18. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 27
Figure 19. B3ZS Encoding Format ................................................................................................................. 27
4.4 TRANSMIT PULSE SHAPER ............................................................................................................................... 28
Figure 21. Transmit Pulse Shape Test Circuit ................................................................................................ 28
4.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 28
Figure 20. HDB3 Encoding Format ................................................................................................................ 28
4.5 E3 LINE SIDE PARAMETERS .............................................................................................................................. 29
Figure 22. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 29
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .......................... 30
Figure 23. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 31
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 31
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 32
Figure 24. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 32
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) .... 33
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 33
4.6 TRANSMIT DRIVE MONITOR .............................................................................................................................. 34
4.7 TRANSMITTER SECTION ON/OFF ....................................................................................................................... 34
Figure 25. Transmit Driver Monitor set-up. ..................................................................................................... 34
5.0 Jitter .................................................................................................................................................. 35
5.1 JITTER TOLERANCE .......................................................................................................................................... 35
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 35
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 35
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 36
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 36
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 36
5.2 JITTER TRANSFER ............................................................................................................................................ 37
5.3 JITTER ATTENUATOR ........................................................................................................................................ 37
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 37
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 37
5.3.1 Jitter Generation ................................................................................................................................ 38
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 38
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 38
6.0 Diagnostic Features ......................................................................................................................... 39
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 39
Figure 30. PRBS MODE ................................................................................................................................. 39
6.2 LOOPBACKS ................................................................................................................................................ 40
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 40
Figure 31. Analog Loopback ........................................................................................................................... 40
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 41
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 41
Figure 32. Digital Loopback ............................................................................................................................ 41
Figure 33. Remote Loopback ......................................................................................................................... 41
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 42
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 42
7.0 Microprocessor interface Block ..................................................................................................... 43
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 43
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 43
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 44
TABLE 12: XRT75R06 MICROPROCESSOR INTERFACE SIGNALS ........................................................................ 44
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION ......................................................................................... 45
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 46
Figure 37. Synchronous µP Interface Signals During Programmed I/O Read and Write Operations ............ 46
XRT75R06
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Figure 36. Asynchronous µP Interface Signals During Programmed I/O Read and Write Operations ........... 46
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................... 47
Figure 38. Interrupt process ............................................................................................................................ 48
7.2.1 Hardware Reset: ................................................................................................................................. 49
TABLE 15: REGISTER MAP AND BIT NAMES ................. .......................... .......................... .......................... ......... 49
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 50
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ...................................... 50
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ....................................... ................................ ................ 52
8.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 57
TABLE 19: ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 57
TABLE 20: DC ELECTRICAL CHARACTERISTICS: ................................................................................................. 57
APPENDIX - A ...... ..... ..... .............. .... ..... .............. ..... .... ..... .............. ..... .... ..... .............. ..... 58
TABLE 21: TRANSFORMER RECOMMENDATIONS ..................................................................................... 58
TABLE 22: TRANSFORMER DETAILS ................................................................................................................... 58
ORDERING INFORMATION ................................................................................................................. 59
PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE .................................................................. 59
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PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
LEAD #S
IGNAL NAME TYPE DESCRIPTION
T15
R16
R15
N14
P14
P13
TxON_0
TxON_1
TxON_2
TxON_3
TxON_4
TxON_5
ITransmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
Transmitter ON Input - Channel 3:
Transmitter ON Input - Channel 4:
Transmitter ON Input - Channel 5:
These pins are active only when the corresponding TxON bits are set.
Table below shows the status of the transmitter based on theTxON bit and TxON
pin settings.
N
OTES
:
1. These pins will be active and can control the TTIP and TRING outputs
only when the TxON_n bits in the channel register are set .
2. When Transmitters are turned off the TTIP and TRING outputs are Tri-
stated.
3. These pins are inter nally pulled up.
E3
M3
F15
P16
G3
H15
TxCLK_0
TxCLK_1
TxCLK_2
TxCLK_3
TxCLK_4
TxCLK_5
ITransmit Clock Input for TPOS and TNEG - Channel 0:
Transmit Clock Input for TPOS and TNEG - Channel 1:
Transmit Clock Input for TPOS and TNEG - Channel 2:
Transmit Clock Input for TPOS and TNEG - Channel 3:
Transmit Clock Input for TPOS and TNEG - Channel 4:
Transmit Clock Input for TPOS and TNEG - Channel 5:
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
By default, input data is sampled on the falling edge of TxCLK.
Bit
0
0
Transmitter Status
OFF
OFF
Pin
0
1
1
1
OFF
ON
0
1
XRT75R06
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F2
P2
G15
R17
H3
K15
TNEG_0
TNEG_1
TNEG_2
TNEG_3
TNEG_4
TNEG_5
ITransmit Negative Data Input - Channel 0:
Transmit Negative Data Input - Channel 1:
Transmit Negative Data Input - Channel 2:
Transmit Negative Data Input - Channel 3:
Transmit Negative Data Input - Channel 4:
Transmit Negative Data Input - Channel 5:
In D ual-rail mode, these p ins ar e sampled on the falling or risi ng edge of TxCLK_n
.
N
OTES
:
1. These input pins are ignored and must be grounded if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
F3
N3
F16
P15
G2
J15
TPOS_0
TPOS_1
TPOS_2
TPOS_3
TPOS_4
TPOS_5
ITransmit Positive Data Input - Channel 0:
Transmit Positive Data Input - Channel 1:
Transmit Positive Data Input - Channel 2:
Transmit Positive Data Input - Channel 3:
Transmit Positive Data Input - Channel 4:
Transmit Positive Data Input - Channel 5:
By default sampled on the falling edge of TxCLK.
D1
N1
D17
N17
H1
H17
TTIP_0
TTIP_1
TTIP_2
TTIP_3
TTIP_4
TTIP_5
OTransmit TTIP Output - Channel 0:
Transmit TTIP Output - Channel 1:
Transmit TTIP Output - Channel 2:
Transmit TTIP Output - Channel 3:
Transmit TTIP Output - Channel 4:
Transmit TTIP Output - Channel 5:
These pins along with TRING transmit bipolar signals to the line using a 1:1 trans-
former.
E1
M1
E17
M17
J1
J17
TRING_0
TRING_1
TRING_2
TRING_3
TRING_4
TRING_5
OTransmit Ring Output - Channel 0:
Transmit Ring Output - Channel 1:
Transmit Ring Output - Channel 2:
Transmit Ring Output - Channel 3:
Transmit Ring Output - Channel 4:
Transmit Ring Output - Channel 5:
These pins along with TTIP transmit bipolar signals to the line using a 1:1 trans-
fo r mer.
TRANSMIT INTERFACE
LEAD #S
IGNAL NAME TYPE DESCRIPTION
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RECEIVE INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
A2
U2
A17
U17
D8
P8
RxCLK_0
RXCLK_1
RxCLK_2
RxCLK_3
RxCLK_4
RxCLK_5
OReceive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
Receive Clock Output - Channel 2:
Receive Clock Output - Channel 3:
Receive Clock Output - Channel 4:
Receive Clock Output - Channel 5:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of RxCLK
A1
U1
A16
U16
D9
P9
RPOS_0
RPOS_1
RPOS_2
RPOS_3
RPOS_4
RPOS_5
OReceive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
Receive Positive Data Output - Channel 2:
Receive Positive Data Output - Channel 3:
Receive Positive Data Output - Channel 4:
Receive Positive Data Output - Channel 5:
N
OTE
: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V", "000V",
"B0V", "B00V") are removed and replaced with ‘0’.
B2
T2
B16
T16
D10
P10
RNEG_0/
LCV_0
RNEG_1/
LCV_1
RNEG_2/
LCV_2
RNEG_3/
LCV_3
RNEG_4/
LCV_4
RNEG_5/
LCV_5
OReceive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 0:
Receive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 1:
Receive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 2:
Receive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 3:
Receive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 4:
Receive Negative Da ta Output/Line Code Viola tion Indicator - Chan-
nel 5:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
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A5
U5
A14
U14
A9
U9
RRING_0
RRING_1
RRING_2
RRING_3
RRING_4
RRING_5
IReceive Input - Channel 0:
Receive Input - Channel 1:
Receive Input - Channel 2:
Receive Input - Channel 3:
Receive Input - Channel 4:
Receive Input - Channel 5:
These pins along with RTIP receive the bipolar line signal from the remote DS3/
E3/STS-1 Terminal.
A6
U6
A13
U13
A10
U10
RTIP_0
RTIP_1
RTIP_2
RTIP_3
RTIP_4
RTIP_5
IReceive Input - Channel 0:
Receive Input - Channel 1:
Receive Input - Channel 2:
Receive Input - Channel 3:
Receive Input - Channel 4:
Receive Input - Channel 5:
These pins along with RRING receive the bipolar line signal from the Remote
DS3/E3/STS-1 Terminal.
RECEIVE INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
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CLOCK INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
E15 E3CLK I E3 Clock Input (34.368 MHz ± 20 ppm):
If any of the channels is configured in E3 mode, a reference clock 34.368 MHz
is applied on this pin.
N
OTE
: In single f requency mode, this r efer ence clock is not required.
G16 DS3CLK I DS3 Clock Input (44.736 MHz ± 20 ppm):
If any of the channels is configured in DS3 mode, a reference clock 44.736
MHz. is applied on this pi n.
N
OTE
: In single f requency mode, this r efer ence clock is not required.
C16 STS-1CLK/
12M ISTS-1 Clock Input (51.84 MHz ± 20 ppm):
If any of the channels is configured in STS-1 mode, a reference clock 51.84
MHz is applied on this pin..
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is con-
nected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the channels in E3, DS3 or
STS-1 modes .
L15 SFM_EN I Single Frequency Mode Enable:
Tie this pin “High” to enable the Single Frequency Mode. A reference clock of
12.288 MHz ± 20 ppm is applied.
In the Single Frequency Mode (SFM) a low jitter output clock is provided for
each channel if the CLK_EN bit is set thus eliminating the need for a separate
clock source for the framer.
Tie this pin “Low” if single frequency mode is not selected. In this case, the
appropriate reference clocks must be provided.
N
OTE
: This pin is internally pulled down
B1
T1
B17
T17
D11
P11
CLKOUT_0
CLKOUT_1
CLKOUT_2
CLKOUT_3
CLKOUT_4
CLKOUT_5
OClock output for channel 0
Clock output for channel 1
Clock output for channel 2
Clock output for channel 3
Clock output for channel 4
Clock output for channel 5
Low jitter clock output for each channel based on the mode selection (E3,DS3
or STS-1) if the CLKOUTEN_n bit is set in the control register.
This eliminates the need for a separate clock source for the framer.
N
OTES
:
1. The maximum drive capability for the clockouts is 16 mA.
2. This clock out is available both in SFM and non-SFM modes.
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CONTROL AND ALARM INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
B7
R6
C14
R14
C6
D14
MRING_0
MRING_1
MRING_2
MRING_3
MRING_4
MRING_5
IMonitor Ring Input - Channel 0:
Monitor Ring Input - Channel 1:
Monitor Ring Input - Channel 2:
Monitor Ring Input - Channel 3:
Monitor Ring Input - Channel 4:
Monitor Ring Input - Channel 5:
The bipolar line output signal from TRING_n is connected to this pin via a 270 Ω
resistor to check for line driver failure.
N
OTE
: This pin is internally pulled up.
B8
R7
C13
R13
C7
D13
MTIP_0
MTIP_1
MTIP_2
MTIP_3
MTIP_4
MTIP_5
IMonitor Tip Input - Channel 0:
Monitor Tip Input - Channel 1:
Monitor Tip Input - Channel 2:
Monitor Tip Input - Channel 3:
Monitor Tip Input - Channel 4:
Monitor Tip Input - Channel 5:
The bipolar line output signal from TTIP_n is connected to this pin via a 270-
ohm resistor t o check for line driver failure.
N
OTE
: This pin is internally pulled up.
C5
T4
B12
T12
D5
B15
DMO_0
DMO_1
DMO_2
DMO_3
DMO_4
DMO_5
ODrive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
Drive Monitor Output - Channel 2:
Drive Monitor Output - Channel 3:
Drive Monitor Output - Channel 4:
Drive Monitor Output - Channel 5:
If MTIP_n and MRING_n has no transition pulse for 128 ± 32 TxCLK_n cycles,
DMO_n goes “High” to indicate the driver failure. DMO_n output stays “High”
until the next AMI signal is detected.
C8
T7
C12
T11
B11
R8
RLOS_0
RLOS_1
RLOS_2
RLOS_3
RLOS_4
RLOS_5
OReceive Loss of Signal - Channel 0:
Receive Loss of Signal - Channel 1:
Receive Loss of Signal - Channel 2:
Receive Loss of Signal - Channel 3:
Receive Loss of Signal - Channel 4:
Receive Loss of Signal - Channel 5:
This output pin toggles "High" if the receiver has detected a Loss of Signal Con-
dition.
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C9
T8
D12
R11
C11
R9
RLOL_0
RLOL_1
RLOL_2
RLOL_3
RLOL_4
RLOL_5
OReceive Loss of Lock - Channel 0:
Receive Loss of Lock - Channel 1:
Receive Loss of Lock - Channel 2:
Receive Loss of Lock - Channel 3:
Receive Loss of Lock - Channel 4:
Receive Loss of Lock - Channel 5:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL
(Loss of Lock) condition occurs if the recovered clock frequency deviates from
the Reference Clock frequency (available at either E3CLK or DS3CLK or STS-
1CLK input pins) by more than 0.5%.
L16 RXA **** External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
K16 RXB **** External Resistor of 3.01K Ω ±1%.
Should be connected between RxA and RxB for internal bias.
P12 ICT IIn-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For nor mal operation, tie this pin
"High".
N
OTE
: This pin is internally pulled up.
R12 TEST **** Factory Test Pin
N
OTE
: This pin must be connected to GND for normal operation.
MICROPROCESSOR INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
K3 CS I Chip Select
Tie this “Low” to enable the communication with the Microprocessor Interface.
R1 PCLK I Processor Clock Input
To operate the Microprocessor Interface, appropriate clock frequency is pro-
vided through this pin. Maximum frequency is 66 Mhz.
K2 WR IWrite Data :
To write data into the registers, this active low signal is asserted.
L2 RD IRead Data:
To read data from the registers, this active low pin is asserted.
J3 RESET IRegister Reset:
Setting this input pin "Low" resets the contents of the Command Registers to
their default settings and default operating configuration
N
OTE
: This pin is internally pulled up.
L3 PMODE I Processor Mode Select:
When this pin is tied “High”, the microprocessor is operating in synchronous
mode which means that clock must be applied to the PCLK (pin 55).
Tie this pin “Low” to select the Asynchronous mode. An internal clock is pro-
vided for the microprocessor interface.
CONTROL AND ALARM INTERFACE
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T3 RDY OReady Acknowledge:
N
OTE
: This pin must be connected to VDD via 3 k
Ω
± 1% resistor.
U3 INT OINTERRUPT Output:
A transition to “Low” indicates that an interrupt has been generated. The inter-
rup t f unc t io n ca n be d isa bled by cl ea ring t h e int er rup t e na ble b i t in t h e Cha n ne l
Control Register.
N
OTES
:
1. This pin will re main a sserted “Low” until the interrupt is serviced.
2. This pin must be conneced to VDD via 3 k
Ω
± 1% resistor.
B4
A3
B3
C4
C3
C2
D3
D4
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
IADDRESS BUS:
8 bit address bus fo r the microprocessor interface
N4
P3
P4
P5
R5
R4
R3
R2
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O DATA BUS:
8 bit Data Bus for the microprocessor interface
MICROPROCESSOR INTERFACE
LEAD # SIGNAL NAME TYPE DESCRIPTION
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ANALOG POWER AND GROUND
LEAD # SIGNAL NAME TYPE D
ESCRIPTION
E2 TxAVDD_0 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 0
N2 TxAVDD_1 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 1
E16 TxAVDD_2 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 2
N16 TxAVDD_3 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 3
J2 TxAVDD_4 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 4
J16 TxAVDD_5 **** Transmitter Analog 3.3 V ± 5% VDD - Channel 5
D2 TxAGND_0 **** Transmitter Analog GND - Chan nel 0
M2 TxAGND_1 **** Transmitter Analog GND - Chan nel 1
D16 TxAGND_2 **** Transmitter Analog GND - Channel 2
M16 TxAGND_3 **** Tran smitter Analog GND - C hannel 3
H2 TxAGND_4 **** Transmitter Analog GND - Chan nel 4
H16 TxAGND_5 **** Transmitter Analog GND - Channel 5
A4 RxAVDD_0 **** Receiver Analog 3.3 V ± 5% VDD - Channel 0
U4 RxAVDD_1 **** Receiver Analog 3.3 V ± 5% VDD - Channel 1
A15 RxAVDD_2 **** Receiver Analog 3.3 V ± 5% VDD - Channel 2
U15 RxAVDD_3 **** Receiver Analog 3.3 V ± 5% VDD - Channel 3
A8 RxAVDD_4 **** Receiver Analog 3.3 V ± 5% VDD - Channel 4
U8 RxAVDD_5 **** Receiver Analog 3.3 V ± 5% VDD - Channel 5
A7 RxAGND_0 **** Receiver Analog GND - Channel_0
U7 RxAGND_1 **** Receive Analog GND - Channel 1
A12 RxAGND_2 **** Receive Analog GND - Channel 2
U12 RxAGND_3 **** Receive Analog GND - Channel 3
A11 RxAGND_4 **** Receive Analog GND - Channel 4
U11 RxAGND_5 **** Receive Analog GND - Channel 5
E4 JaAVDD_0 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 0
K4 JaAVDD_1 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 1
E14 JaAVDD_2 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 2
K14 JaAVDD_3 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 3
G4 JaAVDD_4 **** Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 4
G14 JaAVDD_5 **** Analog 3.3 V ± 5% VDD - Jitter attenuator Channel 5
F4 JaAGND_0 **** Analog GND - Jitter Attenuator Channel 0
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J4 JaAGND_1 **** Analog GND - Jitter Attenuator Channel 1
F14 JaAGND_2 **** Analog GND - Jitter Attenuator Channel 2
J14 JaAGND_3 **** Analog GND - Jitter Attenuator Channel 3
H4 JaAGND_4 **** Analog GND - Jitter Attenuator Channel 4
H14 JaAGND_5 **** Analog GND - Jitter Attenuator Channel 5
C10 AGND **** Analog GND
R10 AGND **** Analog GND
H9 AGND **** Analog GND
J9 AGND **** Analog GND
K9 AGND **** Analog GND
N15 REFAVDD **** Analog 3.3 V ± 5% VDD - Reference
M15 REFGND **** Reference GND
ANALOG POWER AND GROUND
LEAD # SIGNAL NAME TYPE D
ESCRIPTION
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DIGITAL POWER AND GRO UND
LEAD # SIGNAL NAME TYPE D
ESCRIPTION
F1 TxVDD_0 **** Transmitter 3.3 V ± 5% VDD Channel 0
L1 TxVDD_1 **** Transmitter 3.3 V ± 5% VDD Channel 1
F17 TxVDD_2 **** Transmitter 3.3 V ± 5% VDD Channel 2
L17 TxVDD_3 **** Transmitter 3.3 V ± 5% VDD Channel 3
K1 TxVDD_4 **** Transmitter 3.3 V ± 5% VDD Channel 4
K17 TxVDD_5 **** Transmitter 3.3 V ± 5% VDD Channel 5
C1 TxGND_0 **** Transmitter GND - Channel 0
P1 TxGND_1 **** Transmitter GND - Channel 1
C17 TxGND_2 **** Transmitter GND - Channel 2
P17 TxGND_3 **** Transmitter GND - Channel 3
G1 TxGND_4 **** Transmitter GND - Channel 4
G17 TxGND_5 **** Transmitter GND - Channel 5
B5 RxDVDD_0 **** Receiver 3.3 V ± 5% VDD - Channel 0
T5 RxDVDD_1 **** Receiver 3.3 V ± 5% VDD - Channel 1
B14 RxDVDD_2 **** Receiver 3.3 V ± 5% VDD - Channel 2
T14 RxDVDD_3 **** Receiver 3.3 V ± 5% VDD - Channel 3
B9 RxDVDD_4 **** Receiver 3.3 V ± 5% VDD - Channel 4
T9 RxDVDD_5 **** Receiver 3.3 V ± 5% VDD - Channel 5
B6 RxDGND_0 **** Receiver Digital GND - Channel 0
T6 RxDGND_1 **** Receiver Digital GND - Channel 1
B13 RxDGND_2 **** Receiver Digital GND - Channel 2
T13 RxDGND_3 **** Receiver Digital GND - Channel 3
B10 RxDGND_4 **** Receiver Digital GND - Channel 4
T10 RxDGND_5 **** Receiver Digital GND - Channel 5
P6 DVDD_1 **** VDD 3.3 V ± 5%
C15 DVDD_2 **** VDD 3.3 V ± 5%
L4 JaDVDD_1 **** VDD 3.3 V ± 5%
D6 DVDD(uP) **** VDD 3.3 V ± 5%
L14 JaDVDD_2 **** VDD 3.3 V ± 5%
D15 DGND_1 **** Digital GND
D7 DGND(uP) **** Digital GND
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M14 JaDGND_2 **** Digital GND
M4 JaDGND_1 **** Digital GND
P7 DGND **** Digital GND
H8 DGND **** Digital GND
J8 DGND **** Digital GND
K8 DGND **** Digital GND
H10 DGND **** Digital GND
J10 DGND **** Digital GND
K10 DGND **** Digital GND
DIGITAL POWER AND GRO UND
LEAD # SIGNAL NAME TYPE D
ESCRIPTION
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FUNCTIONAL DESCRIPTION
The XRT75R06 is a six channel fully integrated Line Interface Unit featuring EXAR’s R3 Technology
(Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent
Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel can be
independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of
12.288MHz in Single Frequency Mode (SFM). The LIU is responsible for providing the physical connection
between a line interface and an aggregate mapper or framing device. Along with the analog-to-digital
processing, the LIU offers monitoring and diagnostic features to help optimize network design implementation.
A key characteristic within the network topology is Automatic Protection Switching (APS).
EXAR’s proven expertise in providing redundany solutions has paved the way for R3 Technology.
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY)
Redundancy is used to introduce reliability and protection into network card design. The redundant card in
many ca ses is an exact replicate of the primary card, such that when a failure occurs the network processor
can automatically switch to the backup card. EXAR’s R 3 technology has re-defined E3/DS-3/STS-1 LIU design
for 1:1 and 1+1 redundancy applications. Without relays and one Bill of Materials, EXAR offers multi-port,
integrat ed LI U so lutions to as si st hig h de ns ity aggregat e app li ca tio ns and f ra min g requ ir em ents wi th rel iab il ity.
The followin g sectio n can be used as a reference fo r implementi ng R3 Technology with EXAR’s world leading
line interface units.
1.1 Network Architec t ure
A common network design that supports 1:1 or 1+1 redundancy consists of N primary cards along with N
backup cards that connect into a mid-plane or back-plane architecture without transformers installed on the
network cards. In addition to the network cards, the design has a line interface card with one source of
transformers, connectors, and protection components that are common to both network cards. With this
design, the bill of materials is reduced to the fewest amount of components. See Figure 3. for a simplified
block diagram of a typical redundancy design.
FIGURE 3. NETWORK REDUNDANCY ARCHITECTURE
Line Interf ace Card
Primary Line Card
Framer/
Mapper LIU
Back
Plane
or
Mid
Plane
Tx
Rx
31.6Ω
31.6Ω
0.01µF
0.01µF
1:1
1:1
Red undant Line Card
Framer/
Mapper LIU
Tx
Rx
31.6Ω
31.6Ω
0.01µF
0.01µF
37.5Ω 37.5Ω
GND
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2.0 CLOCK SYNTHESIZER
The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks
used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS-
3 or SFM clock input. Therefore, if the chip is configured for STS-1 onl y or E3 only, then the DS-3 input pin
must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1
and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is
the only clo ck reference nec essary to genera te DS-3, E3, or STS -1 line rates and the microprocess or timing.
A simplified block diagram of the clock synthesizer is shown in Figure 4
2.1 Clock Distribution
Network cards that are designed to support multiple line rates which are not configured for single frequency
mode should ensure that a clock is applied to the DS3Clk input pin. For example: If the network card being
supplie d to an ISP r equ ir es E 3 on ly, the DS-3 in put cl oc k refer en ce is s til l n ec es sa ry to pr ov id e read an d wr it e
access to the internal microprocessor. Therefore, the E3 mode requires two input clock references. If
however, multiple line rates will not be supported, i.e. E3 only, then the DS3Clk input pin may be hard wire
connected to the E3Clk input pin.
FIGURE 5. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM
N
OTE
: For one input clock reference, the single frequency mode should be used.
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR
Clock Synthesizer
µProcessor
LOL_n
DS3ClkSFM_EN STS-1Clk/12M E3Clk
CLKOUT_n
0
1
Clock Synthesizer
µProcessor
LOL_n
DS3Clk E3Clk
CLKOUT_n
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3.0 THE RECEIVER SECTION
The rece iver i s desig ned so that th e L IU can r ecover clock and d ata from a n atten uated l ine s ignal c aused by
cable loss or flat loss according to industry specifications. Once data is recovered, it is processed and
present ed at the receiver output s according to the for mat chosen to inter face with a Framer/Map per or ASIC.
This section describes the detailed operation of various blocks within the receive path. A simplified block
diagram of the receive path is shown in Figure 6.
FIGURE 6. RECEIVE PATH BLOCK DIAGRAM
3.1 Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides
isolation and a level shift by blocking the DC offset of the incoming data strea m. The typical medium for the
line interface is a 75Ω coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of
materials, see Figure 7.
FIGURE 7. RECEIVE LINE INTERFACECONNECTION
Channel n
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer Jitter
Attenuator
Clock & Data
Recovery
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
RTIP_n
RRing_n
DS-3/E3/STS-1
1:1
Receiver 75Ω
RLOS_n
RTIP_n
RRing_n
37.5Ω
0.01µF
37.5Ω
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3.2 Adaptive Gain Control (AGC)
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak
detector provides feedback to the equalizer before slicing occurs.
3.3 Receive Equalizer
The Equali ze r re sto re s th e integ ri ty of th e sign al and co mpe nsa tes for th e frequ enc y dep end ent a tten uati on o f
up to 900 fee t of coax ial ca ble (1 300 feet for E3 ). The Equ aliz er also boo st s the hig h frequenc y conte nt of the
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.
FIGURE 8. ACG/EQUALIZER BLOCK DIAGRAM
3.3.1 Recommendations for Equalizer Settings
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Eq ualizer can b e enabl ed. Howeve r, for square- shaped pu lses such as E3 or for DS3/ STS-1 hig h pulses
(that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for
cable l ength less than 300 feet. This would help t o prevent over- equalization of the signal an d thus optimi ze
the perfo rmance in terms of be tter jit ter transfe r charac teristics. The Equal izer also c ontains an additiona l 20
dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have
20dB flat loss. The equalizer gain mode can be enabled by programming the appropriate register.
N
OTE
: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length,
the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
3.4 Clock and Data Recovery
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the
following two modes:
3.4.1 Data/C lock Recove ry Mode
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
3.4.2 Training Mode
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recove red lin e clock signal and the referen ce cl ock appli ed on th e ExClk _n input pi ns ex ceed 0.5 %, a L oss of
Lock con diti on i s de cl ared by t ogg ling RLOL_ n output pin “H i gh” or setti ng th e RLOL_n b it to “ 1” i n the c ontr ol
register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock.
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
RTIP_n
RRing_n
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3.5 LOS (Loss of Signal) Detector
3.5.1 DS3/STS-1 LOS Condition
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLO S con di tio n oc cu rs, the DLO S_ n bi t is se t to “ 1” in th e s tatus control r egi ste r. DLOS co ndi tio n is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses. Analog Loss of
Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown
in the Table 1.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the
logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled
“High” and the RLOS_n bit is set to “1” in the status control register.
3.5.2 Disabling ALOS/DLOS Detection
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both
ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING SIGNAL LEVEL TO DECLARE ALOS
DEFECT SIGNAL LEVEL TO CLEAR ALOS
DEFECT
DS3 0 0 < 75mVpk > 130mVpk
1 0 < 45mVpk > 60mVpk
0 1 < 120mVpk > 45mVpk
1 1 < 55mVpk > 180mVpk
STS-1 0 0 < 120mVpk > 170mVpk
1 0 < 50mVpk > 75mVpk
0 1 < 125mVpk > 205mVpk
1 1 < 55mVpk > 90mVpk
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3.5.3 E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No
transit ions i s defined as a signa l leve l between 15 an d 35 dB below the normal . This is illus trate d in Figure 9.
The LOS condi tion is cle ared within 10 to 255 UI after restor ation of the in comin g line si gnal. Figu re 10 shows
the LOS declaration and clearance conditions.
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
FIGURE 10. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
0 dB
-12 dB
-15dB
-35dB
Maximum Cable Loss for E3
LOS Sign al Must be Declared
LOS Sign al Mus t be Cleared
LOS Signal may be Cleared or Declared
Actual Occurrence
of LOS Condition Line Signal
is Restored
Time Range for
LOS Declaration
Time Range for
LOS Clearance
G.775
Compliance G.775
Compliance
0 UI
10 UI
0 UI
10 UI 255 UI255 UI
RTIP/
RRing
RLOS Output Pin
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3.5.4 Interference Tolerance
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
recommendation is being used. Figure 11 shows the configuration to test the interference margin for DS3/
STS1. Figure 12 shows the set up for E3.
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
FIGURE 12. INTERFERENCE MARGIN TEST SET UP FOR E3.
Sine Wave
Generator
Pattern Generator
223 -1 PRBS
N
S
Attenuator
∑
Test
Equipment
DUT
XRT75R06
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
Cable Simulator
Attenuator 1
N
S
Sine Wave
Generator
17.184mHz
Signal Source
223-1 PRBS
Attenuator 2
∑Test
Equipment
DUT
XRT75R06
Cable Simulator
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TABLE 2: INTERFERENCE MARGIN TEST RESULTS
MODE CABLE LENGTH (ATTENUATION)I
NTERFERENCE TOLERANCE
E3 0 dB
Equalizer “IN”
-17 dB
12 dB -14 dB
DS3
0 feet -15 dB
225 feet -15 dB
450 feet -14 dB
STS-1
0 feet -15 dB
225 feet -14 dB
450 feet -14 dB
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3.5.5 Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n
pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “1”.
N
OTE
: When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
3.6 B3ZS/HDB3 Decoder
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or
contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on
the RLCV_n output pins to indicate line code violation.
FIGURE 13. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
SYMBOL PARAMETER MIN TYP MAX UNITS
RxClk Duty Cycle 45 50 55 %
RxClk Frequency
E3
DS-3
STS-1
34.368
44.736
51.84
MHz
MHz
MHz
tRRX RxClk rise time (10% o 90%) 2 4 ns
tFRX RxClk falling time (10% to 90%) 2 4 ns
tCO RxClk to RPOS/RNEG delay time 4 ns
tLCVO RxClk to rising edge of LCV output delay 2.5 ns
RxClk
tRRX tFRX
RPOS or
RNEG
LCV
tLCVO
tCO
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4.0 THE TRANS MITTER SECTION
The transmitter is designed so that the LIU can accept serial data from a local device, encode the data
properly, and then output an analog pulse according to the pulse shape chosen in the appropriate registers.
This section describes the detailed operation of various blocks within the transmit path. A simplified block
diagram of the transmit path is shown in Figure 14.
FIGURE 14. TRANSMIT PATH BLOCK DIAGRAM
4.1 Transmit Digital Input Interface
The method for ap pl yi ng da ta to the tran sm it in puts of the LIU is a seria l int erfac e co ns is tin g of TxCl k, TxPO S ,
and TxNEG. For single rail mode, only TxClk and TxPOS are necessary for providing the local data from a
Framer device or ASIC. Data can be sampled on either edge of the input clock signal by programming the
appropriate register. A typical interface is shown in Figure 15.
FIGURE 15. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R06 (DUAL-RAIL DATA)
Channel n
Device
Monitor
MTIP_n
MRing_n
DMO_n
Timing
Control
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
Tx
Control
Jitter
Attenuator MUX
Line
Driver
TxON
TxClk_n
TxPOS_n
TxNEG_n
TTIP_n
TRing_n
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Transmit
Logic
Block
TxPOS
TxNEG
TxLineClk
TPData
TNData
TxClk
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FIGURE 16. TRANSMITTER TERMINAL INPUT TIMING
SYMBOL PARAMETER MIN TYP MAX UNITS
TxClk Duty Cycle 30 50 70 %
TxClk Frequency
E3
DS-3
STS-1
34.368
44.736
51.84
MHz
MHz
MHz
tRTX TxClk Rise Time (10% to 90%) 4 ns
tFTX TxClk Fall Time (10% to 90%) 4 ns
tTSU TPData/TNData to TxClk falling set up time 3 ns
tTHO TPData/TNData to TxClk falling hold time 3 ns
FIGURE 17. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
TPData or
TNData
TTIP or
TRing
TxClk tTSU tTHO
tRTX tFTX
TxClk
TPData
Data 1 1 0
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4.2 Transmit Clock
The Transmit Clock app lied via TxClk_n pin s, for the selected data r ate (for E3 = 34.368 MHz, DS3 = 44.736
MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle
clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied.
4.3 B3ZS/HDB3 ENCODER
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS
format (for either DS3 or STS-1) or HDB3 format (for E3).
4.3.1 B3ZS Encoding
An example of B3ZS encoding is shown in Figure 19. If the encoder detects an occurrence of three
consecutive zeros in the data stream, it is replaced with either B0V or 00V, where ‘B’ refers to Bipolar pulse
that is comp liant with the Alternati ng polarity requ irement of the AMI (Alter nate Mark Inver sion) line code and
‘V’ refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or
00V is made so that an odd num ber of bipol ar pulses ex ist between any two cons ecutive vio lation (V ) pulses.
This avoids the introduction of a DC component into the line signal.
4.3.2 HDB3 Encoding
An exam ple of th e HDB3 encodin g is show n in Figu re 20. If the HDB3 encoder detects an occurre nce of four
consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The
substitution code is made in such a way that an odd number of pulses exist between any consecutive V pulses.
This avoids the introduction of DC component into the analog signal.
FIGURE 18. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
FIGURE 19. B3ZS ENCODING FORMAT
TxClk
TPData
TNData
Data 1 1 0
0001
1
1
1
111
VB
V
1
00000 0
0000
0
0000V
BV
000
TClk
Line
Signal
TPDATA
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4.4 TRANSMIT PULSE SHAPER
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that mee ts the industry standa rd mask template r equirements for STS-1 an d DS3. For
E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can
either be disabled or enabled by setting the TxLEV_n bit to “1” or “0” in the control register. For DS3/STS-1
rates, the Transmit Build Out Circuit is used to shape the transmit waveform tha t ensures that transm it pulse
template requirements are met at the Cross-Connect system. The distance between the transmitter output and
the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is
measured at the secondary of the transformer and since there is no Cross-Connect system pulse template
requirements, the Transmit Build Out Circuit is always disabled. The differential line driver increases the
transmit waveform to appropriate level and drives into the 75Ω load as shown in Figure 21.
FIGURE 21. TRANSMIT PULSE SHAPE TEST CIRCUIT
4.4.1 Guidelines for using Transmit Build Out Circuit
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet,
enable the Transmit Build Out Circuit by setting the TxLEV_n control bit to “0”. If the distance between the
transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit.
FIGURE 20. HDB3 ENCODING FORMAT
00
0001
1
1
1
111
VB
V
1
0000 0
0000
0
0
000
V
000
TClk
Line
Signal
TPDATA
TTIP(n)
TRing(n) 1:1
R3
75Ω
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TPData(n)
TNData(n)
TxClk(n)
31.6Ω + 1%
31.6Ω +1%
R1
R2
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4.5 E3 line side p arameters
The XRT75R06 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for
34.368 Mbi ts/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure
22.
FIGURE 22. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.70 3
0%
50%
V = 100%
14.55ns
Nominal Pulse
12.1ns
(14.55 - 2.45)
17 ns
(14.55 + 2.45)
8.65 ns
10%
10%
20%
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N
OTE
: The above values are at TA = 25
0
C and V
DD
= 3.3 V± 5%.
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(Measured at secondary of the transformer) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Amplitude Ratio 0.95 1.00 1.05
Transmit Output Pulse Width 12.5 14.55 16.5 ns
Transmit Intrinsic Jitter 0.02 0.05 UIPP
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) 900 1200 feet
Interference Margin -20 -14 dB
Jitter Tolerance @ Jitter Frequency 800KHz 0.15 0.28 UIPP
Signal level to Declare Loss of Signal -35 dB
Signal Level to Clear Loss of Signal -15 dB
Occurence of LOS to LOS Declaration Time 10 255 UI
Termination of LOS to LOS Clearance Time 10 255 UI
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FIGURE 23. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS NORMALIZED AMPLITUDE
LOWER CURVE
-0.85
<
T < -0.38 - 0.03
-0.38 < T < 0.36
0.36 < T < 1.4 - 0.03
UPPER CURVE
-0.85 < T < -0.68 0.03
-0.68 < T < 0.26
0.26 < T < 1.4 0.1 + 0.61 x e-2.4[T-0.26]
STS-1 Pulse Tem plate
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 1
1.1
1.2
1.3
1.4
Tim e, in UI
Norm alized Am p litud e
Lower Curve
Upper Curve
0.5 1 π
2
---1
T
0.18
-----------+
sin+
·
0.03
–
0.5 1 π
2
---1
T
0.34
-----------+
sin+
·
0.03+
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N
OTE
: The above values are at TA = 25
0
C and V
DD
= 3.3 V ± 5%.
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0) 0.65 0.75 0.90 Vpk
Transmit Output Pulse Amplitude
(measured with TxLEV = 1) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Width 8.6 9.65 10.6 ns
Transmit Output Pulse Amplitude Ratio 0.90 1 .00 1.10
Transmit Intrinsic Jitter 0.02 0.05 UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) 900 1100 feet
Jitter Tolerance @ Jitter Frequency 400 KHz 0.15 UIpp
Signal Level to Declare Loss of Signal Refer to Table 10
Signal Level to Clear Loss of Signal Refer to Table 10
FIGURE 24. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
DS 3 P uls e Te m p late
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Tim e , in UI
Norm a lized Am plitude
Lower Curve
Upper Curve
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TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
N
OTE
: The above values are at TA = 25
0
C and V
DD
= 3.3V ± 5%.
TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS NORMALIZED AMPLITUDE
LOWER CURVE
-0.85
<
T < -0.36 - 0.03
-0.36 < T < 0.36
0.36 < T < 1.4 - 0.03
UPPER CURVE
-0.85 < T < -0.68 0.03
-0.68 < T < 0.36
0.36 < T < 1.4 0.08 + 0.407 x e-1.84[T-0.36]
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0) 0.65 0.75 0.85 Vpk
Transmit Output Pulse Amplitude
(measured with TxLEV = 1) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Width 10.10 11.18 12.28 ns
Transmit Outp ut Puls e Amplitu de R atio 0.90 1.00 1.10
Transmit Intrinsic Jitter 0.02 0.05 UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) 900 1100 feet
Jitter Tolerance @ 400 KHz (Cat II) 0.15 UIpp
Signal Level to Declare Loss of Signal Refer to Table 10
Signal Level to Clear Loss of Signal Refer to Table 10
0.5 1 π
2
---1
T
0.18
-----------+
sin+
·
0.03
–
0.5 1 π
2
---1
T
0.34
-----------+
sin+
·
0.03+
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4.6 Transmit Drive Monitor
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on
the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270Ω
resistor and MRing_n pins to TRing_n lines via 270Ω resistor as shown in Figure 25.
When the MTIP_n and MRing_n are connected to the TTIP_n and TRing_n lines, the drive monitor circuit
monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted “Low” as long as the
transitions on the line are detected via MTIP_n and MRing_n. If no transitions on the line are detected for 128
± 32 Tx Clk_n p er io ds, th e DMO _n ou tpu t to ggl es “H igh” and wh en the tr an si ti ons are detec te d agai n, DM O_ n
toggles “Low”.
N
OTE
: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
4.7 Transmitter Section On/Off
The transm itter sec tion of e ach ch annel c an either b e turned on or off. To turn on the tran smitte r, set the input
pin TxON to “High” and writ e a “1” to the TxON_n con trol bi t. When the trans mitter is turned off, TTIP_n and
TRing_n are tri-stated.
N
OTES
:
1. This feature provides support for Redundancy.
2. To perm it a syst em d esi gn ed for redun dan cy t o q uickly s hut -off the defe cti ve l ine c ard and tu rn on the back-u p line
card, writing a “1” to the TxON_n control bits transfers the control to TxON pin.
FIGURE 25. TRANSMIT DRIVER MONITOR SET-UP.
TTIP(n)
TRing(n) 1:1
R3
75Ω
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TPData(n)
TNData(n)
TxClk(n)
31.6Ω + 1%
31.6Ω +1%
R1
R2
MTIP(n)
MRing(n)
270Ω
270Ω
R1
R2
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5.0 JITTER
There are three fundamental parameters that describe circuit performance relative to jitter
•Jitter Tole ranc e
•Jitter Transfer
•Jitter Ge n era tio n
5.1 JITTER TOLERANCE
Jitter to leran ce is a mea su re of how well a Clo ck an d Data Rec over y unit c an succ essfu lly r ecover data in th e
presence of various fo rms of ji tter. It is char ac teri zed by the amount of ji tter req ui re d to pr od uc e a s pecified bi t
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter am plitude over a jit ter spectrum fo r which the clo ck and data rec overy unit ach ieves a specifi ed bit error
rate (BER). To measure the jitter tolerance as shown in Figure 26, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of
compliance with jitter mask which is represented as a combination of points. Each point corresponds to a
minimum amplitude of sinusoidal jitter at a given jitter frequency.
5.1.1 DS3/STS-1 Jitter Tolerance Requirements
Bellcore GR-499 CORE specifies the minimum requireme nt of jitter tolerance for Category I and C ategory II.
The jitter tolerance requirement for Category II is the most stringent. Figure 27 shows the jitter tolerance curve
as per GR-499 specification.
FIGURE 26. JITTER TOLERANCE MEASUREMENTS
FREQ
Synthesizer
Pattern
Generator DUT
XRT75R06 Error
Detector
Modulation
Freq.
Data
Clock
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5.1.2 E3 Jitter Tolerance Requirements
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to tolerate jitter up to certain
specified limits. Figure 28 shows the tolerance curve.
As shown in the Fi gures above, in the jitter toleranc e measure ment, the dark li ne indicates the mi nimum level
of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude
versus the modulation frequency for various standards.
FIGURE 27. INPUT JITTER TOLERANCE FOR DS3/STS-1
FIGURE 28. INPUT JITTER TOLERANCE FOR E3
0.01 0.03
15
1.5
0.3 220
0.15
JITTER AMPLITUDE (UI
pp)
JITTER FREQUENCY (kHz)
10
5
0.3
100
0.1
GR-253 STS-1
G R -4 99 C a t II
G R -4 99 C a t I
64
41
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0.1
1.5
110
JITTER AMPLITUDE (UI
pp)
JITTER FREQUENCY (kHz) 800
ITU-T G.8 2 3
64
10
0.3
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5.2 JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as
the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a
low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO).
The jitter tran sfer function is a ratio between the ji tter output and ji tter input for a compon ent, or system ofte n
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter . A zero dB jitter transfer indicates the element had no ef fect on jitter . Table 9
shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
N
OTE
: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
5.3 Jitter Attenuator
An advanced crystal-less jitter attenuator per channel is included in the XRT75R06. The jitter attenuator
requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in
the chan nel c ontro l r eg is ters s el ect s the ji tter atte nuat or ei the r in the Re ce iv e o r Transmit pa th o n p er c ha nnel
basis. The FIFO size can be either 16-bit or 32-bit. The bits JA0_n and JA1_n can be set to appropriate
combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel basis. Data is
clocked i nto the FIFO with t he associated c lock signal (TxCl k or RxClk) an d clocked out of the FIFO with th e
dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL_n
is set to “1” in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
N
OTE
: It is recomme nded to sele ct the 16 -bit FIFO for dela y-sensit ive ap plica tions as wel l as for remov ing smal ler amo unts
of jitter. Table 10 specifies the jitter transfer mask requirements for various data rates:
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE
(KB/S)STANDARD INPUT JITTER AMPLITUDE (UI P-P)MODULATION FREQUENCY
A1 A2 A3 F1(HZ)F2(HZ)F3(KHZ)F4(KHZ)F5(KHZ)
34368 ITU-T G.823 1.5 0.15 - 100 1000 10 800 -
44736 GR-499
CORE Cat I 5 0.1 - 10 2.3k 60 300 -
44736 GR-499
CORE Cat II 10 0.3 - 10 669 22.3 300 -
51840 GR-253
CORE Cat II 15 1.5 0.15 10 30 300 2 20
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES
E3 DS3 STS-1
ETSI TBR-24 GR-499 CORE section 7.3.2
Category I and Category II GR-253 CORE section 5.6.2.1
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The jitter atten uator wi thin th e XRT75R06 meets the late st jitter attenuat ion sp ecifi catio ns and/o r jitter tra nsfer
characteristics as shown in the Figure 29.
5.3.1 JITTER GENERATION
Jitter Ge neration is define d as the process whe reby jitte r appears at the output port of the digital equ ipmen t in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data rec overy circui t and measu ring the amou nt of jitter on the outp ut clock or th e re-timed d ata. Sinc e this is
essenti ally a no ise mea suremen t, it requ ires a de finition of bandw idth t o be mea ningful. The bandwi dth is se t
according to the data rate. In general, the jitter is measured over a band of frequencies.
TABLE 10: JITTER TRANSFER PASS MASKS
RATE
(KBITS)MASK F1
(HZ)F2
(HZ)F3
(HZ)F4
(KHZ)A1(dB) A2(dB)
34368 G.823
ETSI-TBR-24 100 300 3K800K0.5 -19.5
44736 GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
-
-
15k
300k
15k
0.1
0.1
0.1
-
-
-
51840 GR-253 CORE 10 4 0k - 400k 0.1 -
FIGURE 29. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
F1
A1
F2
JITTER AMPLITUDE
JITTER FREQU ENCY (kHz)
A2
F3 F4
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6.0 DIAGNOSTIC FEATURES
6.1 PRBS Generator and Detector
The XRT75R06 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. With the PRBSEN_n bit = “1”, the transmitter will send out PRBS of 223-1 in E3 rate or
215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct
PRBS pat tern is detecte d by the recei ver, the RNE G/LCV pin w ill go “Low” to i ndicate PRB S synchroniza tion
has been ac hieved. When the PRBS detec tor is not in sy nc the PRBSLS bi t will be set to “1” and RNE G/LCV
pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “ 1” to INSPR BS bit. The re ceiver at RN EG/LCV pin will pu lse “High ” for one Rx Clk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
Figure 30 shows the status of RNEG/LCV pin when the XRT75R06 is configured in PRBS mode.
N
OTE
: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 30. PRBS MODE
RxClk
RxNEG/LCV
SYNC LOSS
PRBS SYNC Single Bit Error
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6.2 LOOPBACKS
The XRT75R06 offers three loopback modes for diagnostic purposes. The loopback mo des are selected via
the RLB_n and LLB_n bits n the Channel control registers select the loopback modes.
6.2.1 ANALOG LOOPBACK
In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs
RTIP_n and RRing_n as shown in Figure 31. Data and clock are output at RxClk_n, RxPOS_n and RxNEG_n
pins for the cor respond ing trans ceiver. Analog loopbac k exer cises most o f the fun ctional blo cks of th e devic e
including the jitter attenuator which can be selected in either the transmit or receive path.
N
OTES
:
1. In the Analog loopback mode, data is also output via TTIP_n and TRing_n pins.
2. Signals on the RTIP_n and RRing_n pins are ignored during analog loopback.
FIGURE 31. ANALOG LOOPBACK
TRing
TTIP
RRing
RTIP
RxPOS
RxNEG
RxClk
TxNEG
TxClk
TxPOS HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JITTER
ATTENUATOR
JITTER
ATTENUATOR
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
Tx
Rx
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6.2.2 DIGITAL LOOPBACK
When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n &
TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 32.
6.2.3 REMOTE LOOPBACK
With Remote loopback activated as shown in Figure 33, the receive data on RTIP and RRing is looped back
after the jitter at tenuator (if se lected in rece ive or transmit path) to the transmit path using RxC lk as transmit
timing. The receive data is also output via the RxPOS and RxNEG pins.
N
OTE
: Input signals on TxClk, TxPOS and TxNEG are ignored during Remote loopback.
FIGURE 32. DIGITAL LOOPBACK
FIGURE 33. REMOTE LOOPBACK
TRing
TTIP
RRing
RTIP
RxPOS
RxNEG
RxCLK
TxNEG
TxCLK
TxPOS HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JITTER
ATTENUATOR
JITTER
ATTENUATOR
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
Tx
Rx
TRing
TTIP
RRing
RTIP
RxPOS
RxNEG
RxCLK
TxNEG
TxCLK
TxPOS HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JITTER
ATTENUATOR
JITTER
ATTENUATOR
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
Tx
Rx
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6.3 TRANSMIT ALL ONES (TAOS)
T ransmit All Ones (TAOS) can be set by setting the TAOS_n control bits to “1” in the Channel control registers.
When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all “1’s” pattern on
TTIP_n and TRing_ n pins . The frequenc y of this ones pa ttern is de termined by TxClk_n. the TAO S data pat h
is sho wn in Fig ure 34. TAOS do es not o perate in A nalog l oopback or Remote loopback m odes, however wi ll
function in Digital loopback mode.
FIGURE 34. TRANSMIT ALL ONES (TAOS)
TRing
TTIP
RRing
RTIP
RxPOS
RxNEG
RxCLK
TxNEG
TxCLK
TxPOS HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JITTER
ATTENUATOR
JITTER
ATTENUATOR
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
Tx
Rx
TAOS
Transmit A ll 1's
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7.0 MICROPROCESSOR INTERFACE BLOC K
The Micr oproc es so r I nter face secti on sup ports co mmuni ca tio n between the loc al mi croproce ssor ( µP) and the
LIU. The XRT75R06 sup ports a paralle l i nterface a sync hr ono us ly or sy nc hronously ti med to the LIU. The mi-
cropr oce ss or interface is sel ec ted by the sta t e of the Pm ode i npu t p in. S el ec ting the mi cr op ro ce ss or i nte rface
mode is shown in Table 11.
The local µP configures the LIU by writing data into specific a ddressable, on-chip Read/Wr ite registers. The
µP provides the signals which are required for a general purpose microprocessor to read or write data into
these r egister s. The µP al so s upports poll ed an d inte rr upt dri ven environments. A s impl ified block diagram of
the microprocessor is shown in Figure 35.
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE
PMODE MICROPROCESSOR MODE
"Low" Asynchronous Mode
"High" Synchronous Mode
FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
Microprocessor
Interface
WR
RD
Pmode
RDY
RESET
PCLK
CS
INT
Addr[7:0]
D[7:0]
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7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are de-
scr ibed below in Table 12. The microproc essor interface can be configur ed to operate in Asynchro nous mode
or Synchronous mode.
TABLE 12: XRT75R06 MICROPROCESSOR INTERFACE SIGNALS
PIN NAME TYPE DESCRIPTION
Pmode IMicroprocessor Interface Mode Select Input pin
This pin is used to specify the microprocessor interface mode.
D[7:0] I/O Bi-Directional Data Bus for register "Read" or "Write" Operations.
Addr[7:0] I Eight-Bit Address Bus Inputs
The XRT75R06 LIU microprocessor interface uses a direct address bus. This address bus is
provided to perm it the user to select an on-chip register for Read/Write access.
CS IChip Select Input
This active low signal selects the microprocessor interface of the XRT75R06 LIU and enables
Read/Write operations with the on-chip register locations.
RD IRead Signal This active low input functions as the read signal from the local µP. Wh en this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read operation has been
requested and begins the process of the read cycle.
WR IWrit e Sign al This active low input functions as the write signal from the local µP. When this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write operation has been
requested and begins the process of the write cycle.
RDY OReady Output This active low signal is provided by the LIU device. It indicates that the current
read or write cycle is complete, and the LIU is waiting for the next command.
INT OInterrupt Output This active low signal is provided by the LIU to alert the local mP that a
change in alarm status has occured. This pin is Reset Upon Read (RUR) once the alarm sta-
tus registers have been cleared.
RESET IReset Input This active low input pin is used to Reset the LIU.
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7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION
Whether the LIU is con figured for Asynchr onous or Sy nchronous mode, the following descr iptions app ly. Th e
synchron ous mode requir es an input clock (PCLK) to be us ed as the microproc essor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS p in of the L IU, by toggl in g i t "Low". This act ion e nables c om munic ati on be tween the µP an d
the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Lo w". The LIU does this
to inf orm the µP that the data is available to be read by the µP, and that it is ready for the next command.
5. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6. The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local µP wishes to write a byte or word of data into a register within the LIU, it should do the f ollow-
ing.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS p in of the L IU, by toggl in g i t "Low". This act ion e nables c om munic ati on be tween the µP an d
the LIU microprocessor interface block.
3. The µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus D[7:0].
4. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
5. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inf orm the µP that the data has been written into the internal register location, and that it is ready for the
next command.
6. The CS input pin must be pulled "High" before a new command can be issued.
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TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS
FIGURE 37. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
FIGURE 36. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Falling Edge 0 - ns
t1CS Falling Edge to RD Assert 0 - ns
t2RD Assert to RDY Assert - 65 ns
NA RD Pulse Width (t2)70-ns
t3CS Falling Edge to WR Assert 0 - ns
t4WR Assert to RDY Assert - 65 ns
NA WR Pulse Width (t4)70-ns
CS
Addr[7:0]
D[7:0]
RD
WR
RDY
Valid Data for Readback Data Available to Write Into the LIU
READ OPERATION WRITE OPERATION
t0t0
t1
t4
t2
t3
Valid Address Valid Address
CS
Addr[7:0]
D[7:0]
RD
WR
RDY
Valid Data for Readback Data Available to Write Into the LIU
READ OPERATION WRITE OPERATION
t0t0
t1
t4
t2
t3
Valid Address Valid Address
PCLK
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TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS
N
OTE
: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLK
period
* 2) + 5ns
SYMBOL PARAMETER MIN MAX UNITS
t0Valid Address to CS Falling Edge 0 - ns
t1CS Falling Edge to RD Assert 0 - ns
t2RD Assert to RDY Assert - 35 ns, see note 1
NA RD Pulse Width (t2)40-ns
t3CS Falling Edge to WR Assert 0 - ns
t4WR Assert to RDY Asser t - 35 ns, see note 1
NA WR Pulse Width (t4)40-ns
PCLK Period 15 ns
PCLK Duty Cycle
PCLK "High /Low" time
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FIGURE 38. INTERRUPT PROCESS
ERROR CONDITION
OCCURS
Interrupt enable
bits at 0x60 and
0xn1 set?
Interrupt status bits
at
0x61 and 0xn2 set.
Interrupt Generated
INT pin goes "Low"
Interrupt Service
Routine
reads the status
register at 0x61
Interrupt Service
Routine
reads the status
register at 0xn2
Interrupt is being
serviced.
Interrupt Pending ? INT pin goes "High"
Normal Operation
YES
YES
NO
NO
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7.2.1 Hardware Reset:
The hardware res et is initiat ed by pulling the RESET pin “Low” for a minimum of 5 µs. After the RESET pi n is
released, the register values are put in default states.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS
(HEX)PARAMETER
NAME
DATA BITS
76543210
0x00 APS/Redun-
dancy #1 Reserved TxON_5 TxON_4 TxON_3 TxON_2 TxON-1 TxON_0
0x08 APS/ Redun-
dancy #2 Reserved RxON_5 RxON_4 RxON_3 RxON_2 RxON_1 RxON_0
0x60 Interrupt Enable
(read/write) Reserved INTEN_5 INTEN_4 INTEN_3 INTEN_2 INTEN_1 INTEN_0
0x61 Interrupt Status
(read only) Reserved INTST_5 INTST_4 INTST_3 INTST_2 INTST_1 INTST_0
0x62 -
0x6D Reserved
0x6E Chip_id
(read only) 01110101
0x6F Chip_revision _id
(read only) Chip versio n number
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TABLE 16: R EGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)TYPE REGISTER
NAME SYMBOL DESCRIPTION DEFAULT
VALUE
0x00 R/W APS # 1 TxON_n Tabl e b elow sho w s the statu s o f t he transmitte r ba sed
on the bit and pin setting. 0
0x08 R/W APS # 2 RxON_n Set this bit to turn on individual Receiver. 0
0x60 R/W Interrupt
Enable INTEN_n Set this bit to enable the interrupts on per channel
basis. 0
0x61 ROR Interrupt
Status INTST_n Bits are set when an interrupt occurs.The respective
source level interrupt status registers are read to
determine the cause of interrupt.
0
0x62 -
0x6D Reserved
0x6E R Device _ id Chip_id This read only register contains device id. 01110101
0x6F R Version
Number Chip_version This read only register contains chip version number
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS
(HEX)PARAMETER
NAME
DATA BITS
76543210
0x01 (ch 0)
0x11 (ch 1)
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
0x51 (ch 5)
Interrupt
Enable
(read/write)
Reserved PRBSER
CNTIE_n PRBSERI
E_n FLIE_n RLOLIE_n RLOSIE_
nDMOIE_n
0x02 (ch 0)
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
ox52 (ch 5)
Interrupt
Status
(reset on read)
Reserved PRBSER
CNTIS_n PRBSERI
S_n FLIS_n RLOLIS_n RLOSIS_
nDMOIS_n
Bit
0
0
Transmitter Status
OFF
OFF
Pin
0
1
1
1
OFF
ON
0
1
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0x03 (ch 0)
0x13 (ch 1)
0x23 (ch 2)
0x33 (ch 3)
0x43 (ch 4)
0x53 (ch 5)
Alarm Status
(read only) Reserved PRBSLS_n DLOS_n ALOS_n FL_n RLOL_n RLOS_n DMO_n
0x04 (ch 0)
0x14 (ch 1)
0x24 (ch 2)
0x34 (ch 3)
0x44 (ch 4)
0x54 (ch 5)
Transmit
Control
(read/write)
Reserved TxMON_n INSPRBS
_n Reserved TAOS_n TxCLKINV
_n TxLEV_n
0x05 (ch 0)
0x15 (ch 1)
0x25 (ch 2)
0x35 (ch 3)
0x45 (ch 4)
0x55 (ch 5)
Receive
Control
(read/write)
Reserved DLOSDIS
_n ALOSDIS
_n RxCLKIN
V_n LOSMUT_
nRxMON_n REQEN_
n
0x06 (ch 0)
0x16 (ch 1)
0x26 (ch 2)
0x36 (ch 3)
0x46 (ch 4)
0x56 (ch 5)
Block Control
(read/write) Reserved CLKOUTE
N_n PRBSEN_
0RLB_n LLB_n E3_n STS1/
DS3_n SR/DR_n
0x07 (ch 0)
0x17 (ch 1)
0x27 (ch 2)
0x37 (ch 3)
0x47 (ch 4)
0x57 (ch 5)
Jitter
Attenuator
Control
(read/write)
Reserved DFLCK_n PNTRST_
nJA1_n JATx/Rx_n JA0_n
0x0A (ch 0)
0x1A (ch 1)
0x2A (ch 2)
0x3A (ch 3)
0x4A (ch 4)
0x5A (ch 5)
PRBS Error
Count Reg.
MSB
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
0x0B (ch 0)
0x1B (ch 1)
0x2B (ch 2)
0x3B (ch 3)
0x4B (ch 4)
0x5B (ch 5)
PRBS Error
Count Reg.
LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0C (ch 0)
0x1C (ch 1)
0x2C (ch 2)
0x3C (ch 3)
0x4C (ch 4)
0x5C (ch 5 )
PRBS Error
Count Holding
Register
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS
(HEX)PARAMETER
NAME
DATA BITS
76543210
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TABLE 18: R EGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)TYPE REGISTER
NAME BIT# SYMBOL DESCRIPTION DEFAULT
VALUE
0x01 (ch 0)
0x11 (ch 1)
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
0x51 (ch 5)
R/W Interrupt
Enable
(source
level)
D0 DMOIE_n If the Driver Monitor (connected to the output of the
channel) detects the absence of pulses for 128 con-
secutive cycles, it will set the interrupt flag if this bit
has been set.
0
D1 RLOSIE_n This flag will allow a loss of receive signal(for that
channel) to send an interrupt to the Host when this
bit is set.
0
D2 R LO LI E_n This flag will a llow a lo ss of lock condition to se nd an
interrupt to the Host when this bit is set. 0
D3 FLIE_n Set this bit to enable the interrupt when the FIFO
Limit of the Jitter Attenuator is within 2 bits of over-
flow/underflow condition.
N
OTE
: This bit field is ignored when the Jitter Atten-
uator is disabled.
0
D4 PRBSERIE
_n Set this bit to enable the interrupt when the PRBS
error is detected. 0
D5 PRBSERC
NTIE_n Set this bit to enable the interrupt when the PRBS
error count register saturates. 0
D6-D7 Reserved
0x02 (ch 0)
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
0x52 (ch 5)
Reset
on
Read
Interrupt
Status
(source
level)
D0 DMOIS_n If the Drive monitor circuot detects the absence of
pulses for 128 consecutive cycles, t will set this
interrupt status flag (if enabled) This bit is set on a
change of state of the DMO circuit.
0
D1 RLOSIS_n This flag will indicate a change of “loss of Receive
signal” to the Host when this bit is set. 0
D2 R LOLI S_n This flag will allo w a ch ange in the los s of loc k condi -
tion to send an interrupt to the Host when this bit is
enabled.Loss of lock is defined as a difference of
greater than 0.5% between the recovered clock and
the channel’s reference clock. Any change (return to
lock) will trigger the interrupt status flag again.
0
D3 FLIS_n This bit will generate an interrupt if the jitter attenua-
tor FIFO reaches (or leaves) a limit condition. This
limit condition is defined as the FIFO being within
two counts of full or empty.
0
D4 PRBSERIS
_n This bit is set when the PRBS error occurs. 0
D5 PRBSERC
NTIS_n This bit is set when the PRBS error count register
saturates. 0
D7-D6 Reserved
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0x03 (ch 0)
0x13 (ch 1)
0x23 (ch 2)
0x33 (ch 3)
0x43 (ch 4)
0x53 (ch 5)
Read
Only Alarm Sta-
tus
D0 DMO_n This bit is set when no transitions on the TTIP/
TRING have been detected for 128 ± 32 TxCLK
periods.It will be cleared when pulses resume.
0
D1 RLOS_n This bit is set every time the receiver declares an
LOS condition.It will be cleared when the signal is
recognized again.
0
D2 RLOL_n This bit is set when the detected clock is greater
than 0.5% oof fr equency from the ref eren ce cl ock .By
definition, the two frequencies are “not in lock” with
eac h other. It w ill be cleare d when they are “i n lock”
again..
0
D3 FL_n This bit is set when the FIFO reaches its limit.The
limit is defined to be within two bits of either under-
flow or overflow.
0
D4 ALOS_n This bit is set when the receiver declares that the
Analog signal has degraded to the point that the si g-
nal has been lost.
0
D5 DLOS_n This bit is set when no input signals have been
received for 10 to 255 bit times in E3 or 100 to 250
bit t i me s in D S3 o r S T S- 1 mo d es.Th is i s a co mp let e
lack of incoming pulses rather than signal attenua-
tion (ALOS). It should be noted that this time period
is built into the Analog detector for E3 mode. Even
though DS3/STS-1 mode does not require analog
detection level, but it is provided and could help to
determine the “quality of the line” for DS/STS-1
applications.
0
D6 PRBSLS_n This bit is set when the PRBS detector has been
enabled and it is not in sync with the incoming data
pattern. Once the sync is achieved, it will be c leared.
0
D7 Reserved
TABLE 18: R EGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)TYPE REGISTER
NAME BIT# SYMBOL DESCRIPTION DEFAULT
VALUE
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0x04 (ch 0)
0x14 (ch 1)
0x24 (ch 2)
0x34 (ch 3)
0x44 (ch 4)
0x54 (ch 5)
R/W Transmit
Control
D0 TxLEV_n This bit s hould be s et when the tran smitte r is driving
a line greater than 225 feet in the DS3 or STS-1
modes. It is not active in E3 mode.
0
D1 TxCLKINV
_n Set this bit to sample the data on TPOS/TNEG pins
on the rising edge of TxCLK.Default is to sample on
the falling edge of TxCLK.
0
D2 TAOS_n This bit should be set to transmit a continuous “all
ones” data pattern. Timing will come from TxCLK if
available otherwise from channel refernce clock.
0
D3 Reserved
D4 INSPRBS_
nThis bit causes a single bit error to be inserted in the
transmitted PRBS pattern if the PRBS generator/
detector has been enabled.
0
D5 TxMON_n When set, this bit enables the DMO circuit to moni-
tor its own channel’s transmit driver. Otherwise, it
uses the MTIP/MRING pins to monitor another
channel or device.
0
D7-D6 Reserved
0x05 (ch 0)
0x15 (ch 1)
0x25 (ch 2)
0x35 (ch 3)
0x45 (ch 4)
0x55 (ch 5)
R/W Receive
Control
D0 REQEN_n This bit enables the Receiver Equalizer. When set,
the equalizer boosts the high frequency components
of the signal to make up for cable losses.
N
OTE
: See section 5.01 for detailed description.
0
D1 RxMON_n Set this bit to place the Receiver in the monitoring
mode. In this mode, it can process signals (at RTIP/
RRING) with 20dB of flat loss. This mode allows the
channel to act as mo nitor of a line w itho ut load ing the
circuit.
0
D2 LOSMUT_
nWhen set, the data on RPOS/RNEG is forced to
zero when LOS occurs. Thus any residual noise on
the line is not output as spurious data.
N
OTE
: If this bit has been set, it will remain set evan
after the LOS condition is cleared.
0
D3 RxCLKINV
_n When this bit is set, RPOS and RNEG will change
on the falling edge of RCLK.Default is for the data to
change on the rising edge of RCLK and be sampled
by the terminal equipment on the falling edge of
RCLK.
0
D4 ALOSDIS_
nThis bit is set to disable the ALOS detector. This flag
and the DLOSDIS are normally used in diagnostic
mode. Normal operation of DS3 and STS-1 would
have AL OS disabled.
0
D5 DLOSDIS_
nThis bit d is ables the di gital LOS detec tor. This would
normally be disabled in E3 mode as E3 is a function
of the level of the input.
0
D7-D6 Reserved
TABLE 18: R EGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)TYPE REGISTER
NAME BIT# SYMBOL DESCRIPTION DEFAULT
VALUE
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0x06 (ch 0)
0x16 (ch 1)
0x26 (ch 2)
0x36 (ch 3)
0x46 (ch 4)
0x56 (ch 5)
R/W Block Con-
trol
D0 SR/DR_n Setting this bit configures the Receiver and Trans-
mitter in Single-Rail (NRZ) mode.
N
OTE
: See section 4.0 for detailed description.
0
D1 STS-1/
DS3_n Setting this bit configures the channel into STS-1
mode.
N
OTE
: This bit field is ignored if the channel is con-
figured to operate in E3 mode.
0
D2 E3_n Setting this bit configures the channel in E3 mode. 0
D3 LLB_n Setting this bi t c onf igu r es the ch an nel in Local Lo op -
back mode. 0
D4 RLB_n This bit along with LLB_n determine the diagnostic
mode as shown in the table below. 0
D5 PRBSEN_
nSetting this bit enables the PRBS generator/detec-
tor. When in E3 mode, an unframed 223-1 patter n is
used. For DS3 an d STS-1, un fram ed 2 15-1 pa ttern is
used. This mode of operation will use TCLK for tim-
ing. One should insure that a stable frequency is
provided. Looping th is signal back to its ow n receive
channel and using RCLK to generate TCLK will
cause an unstable condition and should be avoided.
0
D6 CLKOUTE
N_n Set this bit to enab le the CLKOUTs on a pe r ch annel
basis. The frequency of the output clock is depen-
dent on the configuration of the channels, either E3,
DS3 or STS-1.
0
D7 Reserved
TABLE 18: R EGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)TYPE REGISTER
NAME BIT# SYMBOL DESCRIPTION DEFAULT
VALUE
RLB_n
0
0
Loopback Mode
Normal Operation
Analog Local
LLB_n
0
1
1
1
Remote
Digital
0
1
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0x07 (ch 0)
0x17 (ch 1)
0x27 (ch 2)
0x37 (ch 3)
0x47 (ch 4)
0x57 (ch 5)
R/W Jitter
Attenuator
D0 JA0_n This bit along with JA1_n bit configures the Jitter
Attenuator as shown in the table below. 0
D1 JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
Transmit Path. A “0” selects in the Receive Path. 0
D2 JA1_n This bit along with the JA0_n configures the Jitter
Attenuator as shown in the table. 0
D3 PNTRST_n Setting this bit res et s the FI FO po int ers to th ei r i niti al
state and flushes the FIFO. All existing FIFO data is
lost.
0
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
This helps to reduce the time for the PLL to lock to
incoming frequency when the Jitter Attenuator
switches to narrow band.
0
D7-D5 Reserved
TABLE 18: R EGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)TYPE REGISTER
NAME BIT# SYMBOL DESCRIPTION DEFAULT
VALUE
JA0_n
0
0
Mode
16 bit FIFO
32 bit FIFO
JA1_n
0
1
1
1
Disable Jitter
Attenuator
0
1Disable Jitter
Attenuator
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8.0 ELECTRICAL CHARACTERISTICS
N
OTES
:
1. Expo sure to or o pera t in g ne ar t he M in or M ax v alu es for e xt end ed p eri od m ay c aus e p erm an ent fail ure and im pa ir
reliability of the device.
2. ESD testing method is per MIL-STD-883D,M-3015.7
3. With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.
N
OTES
:
1. Not applicable for pins with pull-up or pull-down resistors.
2. The Digital inputs are TTL 5V compliant.
TABLE 19: ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER MIN MAX UNITS COMMENTS
VDD Supply Voltage -0.5 6.0 V Note 1
VIN Input Voltage at any Pin -0.5 5.5 V Note 1
IIN Input current at any pin 100 mA Note 1
STEMP Storage Temperature -65 150 0CNote 1
ATEMP Ambient Operating Temperature -40 85 0Clinear airflow 0 ft./min
Theta JA Thermal Resistance 23 0C/W linear air flow 0ft/min
(See Note 3 below)
MLEVL Exposure to Moisture 4 level EIA/JEDEC
JESD22-A112-A
ESD ESD Rating 2000 V Note 2
TABLE 20: DC ELECTRICAL CHARACTERISTICS:
SYMBOL PARAMETER MIN.TYP.MAX.UNITS
DVDD Digital Supply Voltage 3.135 3 .3 3.465 V
AVDD Analog Suppl y Voltage 3.135 3 .3 3.465 V
ICC Supply current requirements 725 850 mA
PDD Power Dissipation 2.64 2.93 W
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 5.5 V
VOL Output Low Voltage, IOUT = - 4mA 0.4 V
VOH Output High Voltage, IOUT = 4 mA 2.4 V
ILInput Leakage Current1±10 µA
CIInput Capacitance 10 pF
CLLoad Capacitance 10 pF
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APPENDIX - A
TRANSFORMER VENDOR INFORMATION
TABLE 21: TRANSFORMER RECOMMENDATIONS
PARAMETER VALUE
Turns Ratio 1:1
Primar y Indu cta nc e 40 µH
Isolation Voltage 1500 V rms
Leakage Inductance 0.6 µH
TABLE 22: TRANSFORMER DETAILS
PART NUMBER VENDOR INSULATION PACKAGE TYPE
PE-68629 PULSE 3000 V Large Thru-hole
PE-65966 PULSE 1500 V Small Thru-hole
PE-65967 PULSE 1500 V SMT
T 3001 PULSE 1500 V SMT
TG01-0406NS HALO 1500 V SMT
TTI 7601-SM TransPower 1500 V SMT
Pulse
Cor porate Office
12220 World Trade Drive
San Diego, CA 92128
Te l: (8 58)- 674 -8100
FA X: (8 58)- 674 -8262
Europe
1 & 2 Huxley Road
The Surrey Research Park
Guildfor d, Surrey GU2 5RE
United Kingd om
Te l: 44- 14 83-401 700
FA X: 44- 148 3-401 701
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapor e 368 324
Te l: 65- 28 7-8998
Website: http://www.pulseeng.com
Halo Electronics
Corporate Office
P.O. Box 5826
Redwood City, CA 94063
Tel: (650)568- 580 0
FA X: (6 50)56 8- 616 5
Email: info@haloelectronics.com
Website: http://www.haloelectronics. com
Tr anspower Technologies, Inc.
Corporate Office
Park Center West Building
9805 Double R Blvd, Suite # 100
Reno, NV 89511
(800)500- 59 30 or (775) 85 2-014 0
Email: info@trans-power.com
Website: http://www.trans-power. com
XRT75R06
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ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT75R06IB 217 Lead BGA (23 x 23 mm) - 40°C to + 85°C
PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE
SYMBOL MIN MAX MIN MAX
A 0.067 0.098 1.70 2.50
A1 0.016 0.028 0.40 0.70
A2 0.012 0.024 0.30 0.60
A3 0.039 0.047 1.00 1.20
D 0.898 0.913 22.80 23.20
D1 0.800 BSC 20.32 BSC
D2 0.780 0.795 19.80 20.20
b 0.024 0.035 0.60 0.90
e 0.050 BSC 1.27 BSC
β10° 20° 10° 20°
INCHES MILLIMETERS
N ote: The control dimension is in millimeter.
BOTTOM VIEW
(A1 corner feature is mfger option)
β
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NOTICE
EXAR Corporati on rese rves the righ t to make changes to the product s co ntaine d in this publi catio n in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purpose s and ma y var y de pendin g upon a us er’s spec ific appl icati on. W hile the in forma tion i n thi s pub lica tion
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or ma lfunctio n of the product ca n reasonably be expecte d to cause fai lure of the life s upport system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Cor poratio n receives, i n writin g, assurances to its sati sfactio n that: (a) th e risk of i njury or dam age has
been minimized; (b) the user assumes all such risks; (c) poten tial liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Cor poratio n
Datasheet December 2004.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISIONS
REVISION DATE COMMENTS
P1.0.0 06/11/04 First release of the preliminary datasheet.
P1.0.1 07/15/04 Second release of the preliminary datasheet.
1.0.0 12/14/04 Release to production. Entered power dissapation and power supply current in electrical.
