ECL 100K input and output levels Delays stable and precise 24-pin DIP package (.375 high) Available in delays up to 77.8ns Available in 18 delay steps with resolution from 0.1 to 5.0ns Propagation delays fully compensated All delays digitally programmable 70 ECL DC fan-out capacity design notes The oped by Engineered Components Company have been designed to allow for final delay adjustment during or after installation These Logic Delay Lines incorporate required driv- ing and pick-off circuitry and are contained in a 24-pin DIP DIP Series of Programmable Logic Delay Lines devel- in a circuit. package compatible with ECL 100K Series circuits. The design includes compensation for propagation delays and incar- porates internal termination at the output; no additional external components are needed to obtain the required delay. 2 ECL 100K COMPATIBLE 4-BIT _ PROGRAMMABLE LOGIC DELAY LINE The Logic Delay Lines are digitally programmable by the presence of either a "1" of a O" at each of the programming pins. Since the input and the output terminals are fixed and the programming is accomplished only by DC voltage levels, pro- gramming may be accomplished by remote switching or perma- nent termination of the appropriate programming pins of the Logic Delay Line to Vcc; the Logic Delay Line may also be programmed automatically by computer generated data. MUX set-up time is Tns maximum, When no need exists in the appli- cation to change delay time during normal use, the desired delay is most conveniently established by use of a Vec pad around each programming pin; programming is accomplished by cutting off those pins which are to remain at state "O" before insertion of the Logic Delay Line into the printed circuit board. The PECLDL is designed for use with positive input pulses and will reproduce these at the output without inversion, All modules can be driven from a standard ECL gate with an external pulldown resister of 50 or 100 ohms ta 2V or 470 ohms to -4.5V. Qutput is standard ECL 100K open emitter; program- ming inputs are standard ECL 100K single fan-in. These Logic Delay Lines have the capability of driving up to 70 ECL DC loads. a L engineered components company 3580 Sacramento Drive, P. O. Box 8121, San Luis Obispo, CA 93403-8121 Phone: (805) 544-3800DESIGN NOTES (continued) The PECLDL is offered in 18 models with time delays to a maximum of 77.8ns and with step resolution as shown in the Part Number Table. Programming of maximum delays is accomplished in 16 delay steps in accordance with the Truth Table Examples shown on page 3. Tolerances on minimum delay, delay change per step and deviation from programmed delay are shown in the Part Number Table on page 3. Rise time for all Logic Delay Lines is 2ns maximum, when measured from 20% to 80% pulse amplitude. Temperature coefficient of delay is less than 150 ppm/'C over the operating temperature range of O to +85C. These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements, The ICs utilized in these modules are burned-in to Level B of MIL-STD- 883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50C ground fixed environ- ment, is in excess of 750,000 hours, The DIP Series Programmable Logic Delay Lines are packaged in a 24-pin DIP housing, molded of flame-proof Diallyl Phthalate per MIL-M-14, Type SOG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD- 202, Method 208. Corner standofts on the housing provide posi- tive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability. Marking consists of manufacturer's name, logo {EC2), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215. BLOCK DIAGRAM |S SHOWN BELOW IN Vee Vee P, Po Pg Pq 24 19 #18 16 $15 14 13 o Pe rena er es = 1 | | I I | ( | | L ree. ] | Ly DIGITALLY | | INPUT 1a) PROGRAMMABLE [py OUTPUT | BUFFER BUFFER = DELAY LINE | l C i l o a 1 6 12 -2V Vee OUT GROUND GROUND Page 2 of 3 MECHANICAL DETAIL IS SHOWN BELOW 1.350 | IN Ve Ve Py Po Pg Py * PECLDL-2.8-_ -2V VelVe OUT | 1 oa 8718 MADE IN SLO USA rT TI rth 0 +.030 | Te fy .060 TYP. 100 TYP. +- TYP, K 050 200 TYP. ele o ] iJ 550 TYP.+4 = 100 TYP. TEST CONDITIONS 1. All measurements are made at 25 C. ?, Vee supply voltage is maintained at4.5V DC. 3. All units are tested using a positive input pulse provided by a ECL 100K gate. put utilizea 50 ohm pulldown resistor ta 2V: the output is alsa loaded with one ECL 100K gate. standard open emitter The input and out- @4. Input pulse width used is 10ns for units with delay change of 0.1 to 1.0ns/step and 25ns 9 for units with delay change of Pulse period for all units is 1000ns. 1,0ns/step and greater. OPERATING SPECIFICATIONS Supply Voltage: 4.2 to 4.8 to Vee Supply Current: sss eee 140ma typical Logic 1 Input at 25C. Voltage 6 2 see ees -1.165 min. Current ee tee ee 35Qua max. Logic O Input at 26C. Voltage errr * -1.475 max. Current ese ets eee Bua min, Logic 1 Output at 25C. + +++ + -1.025V min. Logic 0 Output at 25C. +++ ++ 1.620V max. Operating ternperature range: - + Oto +85C Storage temperature; +--+ +--+ S5to+125C.PART NUMBER TABLE 6 DELAYS AND TOLERANCES {in ns) Part Number *Step Zero Maximum Delay| Delay Change wevicne toca Delay Time Time (Nom) Per Step Programmed Delay PECLDL-2.8- 0.1 2.84.2 4.3 0.1 +.04 +1 PECLDL-2.8- 0.2 2.84.2 5.8 0.2 +.05 +.2 PECLDL- 2.8-0.3 2.84.2 7.3 0.34.1 +.25 PECLDL- 2.8-0.4 2.8 4.2 8.8 0.44.1 3 PECLDL-2.8- 0.5 2.8 +.2 10.3 0.5 +.15 +.35 PECLDL-2.8- 0.6 2.8 +.2 11.8 0.6 4.15 +4 PECLDL-2.8- 0.7 2.8 4.2 13.3 0.7 +.2 +.45 PECLDL- 2.8-0.8 2.84.2 14.8 0.8 +.2 +.5 PECLDL- 2.8-0.9 2.8 +.2 16.3 0.9 +.2 +.5 PECLDL-2.8- 1,0 2.82.2 17.8 1.0 4.2 5 PECLDL-2.8- 1.5 2.84.2 25.3 1.5 4.25 +8 PECLDL- 2.8- 2.0 2.8+.2 32.8 2.04.25 +1.0 PECLDL-2.8- 2.5 2.84.2 40.3 2.5 +.3 1.3 PECLDL-2.8- 3.0 2.84.2 47.8 3.0 +.3 15 PECLDL-2.8- 3.5 2.8 +.2 55.3 3.5 +.35 +18 PECLDL- 2.8- 4.0 2.84.2 62.8 4.0+.4 +2.0 PECLDL-2.8-4.5 2.84.2 70.3 4.5 +.45 +2.3 PECLDL- 2.85.0 2.8 4.2 77.8 5.04.5 +2.5 TRUTH TABLE EXAMPLES a 4 oO] 0 ololojovfitiatiyailiy+ay1]t Pins|2 9 | 9 | 0 r}itrtafolo;o;o;a}i}i1]4 Part ololilatolealr1lt+tololti1|4 o|1|4 rer 1 oflrfola}oflitofirifo}iajolif{ofr1fo}.4 PECLDL-2.8- 0.1 28] .1|.2).3] 4] 5] 6] 7 | 8] 9 /1.0)1.1]1.2] 1.3) 14/15 PECLDL- 2.8-0.5 2.8) .5 11.0 ]1.5 |2.0]2.5 |3.0/3.5 |4.0] 4.5] 5.0/5.5] 6.0/6.5] 7.0] 7.5 PECLDL-2.8- 2.0 28| 2|4]6] 8 /10 |12 | 14 | 16| 18 | 20| 22 | 24) 26| 28] 30 ETC. | * Delay at step zero is referenced to the input pin. ** All delay times after step zero are referenced to step zera. All modules can be operated with a minimum input pulse width of ans or 20% of full delay, whichever is greater, and pulse period approaching square wave, since delay accuracies may be somewhat degraded, it is suqgested that the module be evaluated under the intended specific operating conditions. Special modules can be readily manufactured to improve accuracies and/or provide customer specified delay times for specific applications, Page Sof 3 Catalog No, C/O40180R