MM908E621 - Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

Document Number : MM908E621

Rev. 5.0, 6/200 8

Freescale Semiconductor

Technical Data

Integrated Quad Half-bridge and

Triple High Side with Embedded

MCU and LIN for High End

Mirror

The 908E621 is an integrated single package solution that

includes a high performance HC08 microcontroller with a

SMARTMOSTM analog control IC. The HC08 includes flash memory,

a timer, enhanced serial communications interface (ESCI), a 10 bit

analog-to-digital converte r (ADC), serial peripheral interface (SPI)

(only internal), and an internal clo ck generator module (ICG). The

analog control die provides four half-bridge and three high side

outputs with diagnostic functions, a Hall -effect sensor input, analog

inputs, voltage regulator, window watchdog, and local interconnect

network (LIN) physical layer.

The single package solution, together with LIN, provides optimal

application performance adjustments and space saving PCB design.

It is well suited for the control of automotive high end mirrors.

Features

• High performance M68HC908EY16 core

• 16K bytes of on-chip flash memory, 512 bytes of RAM

• Two 16-bit, 2-channel timers

• LIN physical layer interface

• Autonomous MCU watchdog / MCU supervision

• One analog input with switchable current source

• Four low RDS(ON) half-bridge outputs

• Three low RDS(ON) high side outputs

• Wake-up and 2/3-pin hall-effect sen sor input

• 12 microcontroller I/Os

Figure 1. 908E621 Simplified Application Diagram

QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE

SWITCH WITH EM BEDDED MCU AND LIN

908E621

ORDERING INFORMATION

Device Temperature

Range (TA)Package

MM908E621ACDWB/R2 -40°C to 85°C 54 SOICW-EP

DWB SUFFIX

98ASA10712D

54-PIN SOICW-EP

RST_A

RST

IRQ_A

IRQ

VSSA/VREFL

LIN

VDDA/VREFH

EVDD

VDD

EVSS

VSS

HS1

VSUP[1:8]

A0CST

High Side Output 3

High Side Output 2

High Side Output 1

HS2

HS3

HVDD

GND[1:4]

Switched 5V output

Analog Input with cur rent sourc e

Analog Input current source trim

2-/3-pin hall sensor input

Wake Up Input

4,7µF

100nF

>22µF

HB1

HB2

MM 4 x Half Bridge Outputs

HB3

HB4

PTC2/MCLK

PTC3/OSC2

PTC4/OSC1

µC PortC

PTB3/AD3

PTB4/AD4

PTB5/AD5

µC PortB

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

µC PortA

PTE1/RxD

Internally connected

µC PortE

PTD0/TACH0

Internally connected

µC PortD PTD1/TACH1

TESTMODE Pull to ground for user mode

100nF

Analog Integrated Circuit Device Data

2Freescale Semiconductor

908E621

INTERNAL BLOCK DIAGRAM

Figure 2. 908E621 Simplified Internal Block Diagram

M68HC08 CPU

ALU

PORT B

DDRB

PTB0/AD0

ADOUT Analog

Multiplexer Analog Port

with Current

Source

CPU

Registers

DDRE

PORT E

PTE1/RXD

PTE0/TXD

PTB0/AD0

PTB2/AD2

PTB3/AD3

PTB4/AD4

PTB5/AD5

PTB6/AD6/TBCH0

PTB7/AD7/TBCH1

DDRD

PORT D

PTD1/TACH1

PTD0/TACH0

PORT C

DDRC

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTC1/MOSI

PTC0/MISO

BEMF Module

Prescaler Module

Arbiter Module

Periodic Wake-up

Timebase Module

Configuration

Serial Peripheral

Interface Module

Computer Operating

Properly Module

Enhanced Serial

Communication

Interface Module

2-channel Timer

Interface Module B

2-channel Timer

Interface Module A

5-Bit Keyboard

Interrupt Module

Single Breakpoint

Break Module

DDRA

PORT A

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

PTA5/SPSCK

PTA6/SS

Security Module

Power-ON

Reset Module

POWER

VSS

VDD

10 Bit Analog-to-

Digital Converter

Module

VSSA

VREFL

VDDA

VREFH

Single External

IRQ Module

IRQ

24 Integral System

Integration Module

RST

Internal Clock

Generator Module

OSC1

OSC2

User Flash Vector

Space, 36 Bytes

Flash programming

(Burn-in), ROM 1024 Bytes

Monitor ROM, 310 Bytes

User RAM, 512 Bytes

User Flash, 15,872 Bytes

Control and Status

Internal Bus

FLSVPP

PTD1/TACH1

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

VDDA/VREFH

EVDD

EVSS

VSSA/VREFL

RST

IRQ

RST_A

IRQ_A

PTE1/RXD

PTD0/TACH0

LIN

TESTMODE

VSUP[1:8]

GND[1:4]

PTB0/AD0

PTA5/SPSCK SPSCK

MOSI

PTC1/MOSI

MISO

PTC0/MISO

PWM

PTA6/SS

PTD0/TACH0

PTE0/TXD

PTE1/RXD RXD

TXD

SPI

CONTROL

HALLPORT

Half Bridge

Driver &

Diagnostic

Half Bridge

Driver &

Diagnostic

Half Bridge

Driver &

Diagnostic

Half Bridge

Driver &

Diagnostic

High Side Driver

& Diagnostic

High Side Driver

& Diagnostic

High Side Driver

& Diagnostic

Autonomous

Watchdog

Reset

Control

LIN

Physical Layer

Wakeup Port

Voltage

Regulator

Switched VDD

Driver &

Diagnostic

A0CST

HB4

HB3

HB2

HB1

HS3

HS2

HS1[a:b]

HVDD

VDD

VSS

Analog Integrated Circuit Device Data

Freescale Semiconductor 3

908E621

PIN CONNECTIONS

Figure 3. Pin Connections

Table 1. Pin Definitions

A functional description of each pin can be found in the Function al Pin Description section beginning on page 21.

Die Pin Pin Name Formal Name Definition

MCU 1

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

Port C I/Os These pins are special function, bidirectional I/O port pins that are

shared with other functional modules in the MCU.

MCU 4

PTB5/AD5

PTB4/AD4

PTB3/AD3

Port B I/Os These pins are special function, bidirectional I/O port pins that are

shared with other functional modules in the MCU.

MCU 7 IRQ External Interrupt

Input This pin is an asynchronous external interrupt input pin.

MCU 8 RST External Reset This pin is bidirectional, allowing a reset of the entire system. It is driven

low when any internal reset source is asserted.

MCU /

Analog 9 (PTD0/TACH0/BEMF

-> PWM) PWM signal This pin is the PWM signal test pin. It internally connects the MCU

PTD0/TACH0 pin with the Analog die PWM input.

Note: Do not connect in the application.

MCU 10 PTD1/TACH1 Port D I/Os This pin is a special function, bidirectional I/O port pin that is shared with

other functional modules in the MCU.

MCU /

Analog 44 (PTE1/RXD <- RXD) LIN Transceiver

Output This pin is the LIN Transceiver output test pin. It internally connects the

MCU PTE1/RXD pin with the Analog die LIN transceiver output pin

RXD.

Note: Do not connect in the application.

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

VDDA/VREFH

EVDD

EVSS

VSSA/VREFL

(PTE1/RXD <- RXD)

VSS

VDD

HVDD

HS3

VSUP8

HS2

VSUP7

HS1b

HS1a

VSUP6

VSUP5

GND4

HB1

VSUP4

FLSVPP

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

RST

(PTD0/TACH0/BEMF -> PWM)

PTD1/TACH1

RST_A

IRQ_A

LIN

A0CST

GND1

HB4

VSUP1

GND2

HB3

VSUP2

TESTMODE

GND3

HB2

VSUP3

Exposed

Pad

Transparent Top

View of Package

Analog Integrated Circuit Device Data

4Freescale Semiconductor

908E621

PIN CONNECTIONS

MCU 45

48 VSSA/VREFL

VDDA/VREFH ADC Supply and

Reference Pins These pins are the power supply and voltage reference pins for the

analog-to-digital converter (ADC).

MCU 46

47 EVSS

EVDD MCU Power Supply

Pins These pins are the ground and power supply pins, respectively. The

MCU operates from a single power supply.

MCU 49

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

Port A I/Os These pins are special function, bidirectional I/O port pins that are

shared with other functional modules in the MCU.

MCU 51 FLSVPP Test Pin For test purposes only. Do not connect in the application.

Analog 11 RST_A Internal Reset This pin is the bidirectional reset pin of the analog die.

Analog 12 IRQ_A Internal Interrupt

Output This pin is the interrupt output pin of the analog die indicating errors or

wake-up events.

Analog 13 LIN LIN Bus This pin represents the single wire bus transmitter and receiver.

Analog 14 A0CST Analog Input Trim Pin This is the analog input trim pin for the A0 input. This is to connect a

known fixed resistor value to trim the curren t source measurement.

Analog 15 A0 Analog Input Pin This pin is an analog input port with selectable source values.

Analog 16

GND1

GND2

GND3

GND4

Power Ground Pins These pins are device power ground connections.

Analog 29

HB1

HB2

HB3

HB4

Half-bridge Outputs This device includes power MOSFETs configured as four half-bridge

driver outputs. These outputs may be configured for DC motor drivers,

or as high side and low side switches.

Note: The HB3 and HB4 have a lower RDS(ON) then HB1 and HB2.

Analog 18

VSUP1

VSUP2

VSUP3

VSUP4

VSUP5

VSUP6

VSUP7

Power Supply Pins These pins are device power supply pins.

–22

23 NC

NC No Connect These pins are not connected.

Analog 24 TESTMODE TESTMODE Input Pin for test purpose only. In application this pin needs to be tied GND.

Analog 34

35 HS1a

HS1b High Side HS1 Output This output pin is a low RDS(ON) high side switch.

Analog 36

HS2

HS3

High Side HS2 Output

High Side HS3 Output These output pins are low RDS(ON) high side switches.

Analog 39 H0 Hall-Effect Sensor /

General Purpose

Input

This pin provides an input for a Hall-effect sensor or general purpose

input.

Analog 40 L0 Wake-up Input This pin provides an high voltage input, which is wake-up capable.

Analog 41 HVDD Switchable VDD

Output This pin is a switchable VDD output for driving resistive loads requiring

a regulated 5.0V supply; e.g. potentiometers.

Analog 42 VDD Voltage Regulator

Output The +5.0V voltage regulator output pin is intended to supply the

embedded microcontroller.

Table 1. Pin Definitions (continued)

A functional description of each pin can be found in the Function al Pin Description section beginning on page 21.

Die Pin Pin Name Formal Name Definition

Analog Integrated Circuit Device Data

Freescale Semiconductor 5

908E621

PIN CONNECTIONS

Analog 43 VSS Voltage Regulator

Ground Ground pin for the connection of all non-power ground connections

(microcontroller and sensors).

– EP Exposed Pad Exposed Pad The exposed pad pin on the bottom side of the package conducts heat

from the chip to the PCB board.

Table 1. Pin Definitions (continued)

A functional description of each pin can be found in the Function al Pin Description section beginning on page 21.

Die Pin Pin Name Formal Name Definition

Analog Integrated Circuit Device Data

6Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to

the device.

Rating Symbol Value Unit

ELECTRICAL RATINGS

Supply Voltage

Analog Chip Supply Voltage under Normal Operation (Steady-state)

Analog Chip Supply Voltage under Transient Conditions(1)

MCU Chip Supply Voltage

VSUP(SS)

VSUP(PK)

VDD

-0.3 to 28

-0.3 to 40

-0.3 to 5.5

Input Pin Voltage

Analog Chip

Microcontroller Chip

VIN(ANALOG)

VIN(MCU)

-0.3 to 5.5

VSS-0.3 to VDD+0.3

Maximum Microcontroller Current per Pin

All Pins except VDD, VSS, PTA0:PTA4

PTA0:PTA4

IPIN(1)

IPIN(2)

±15

±25

Maximum Microcontroller VSS Output Current IMVSS 100 mA

Maximum Microcontroller VDD Input Current IMVDD 100 mA

LIN Supply Voltage

Normal Operation (Steady-state)

Transient Input Voltage (per ISO7637 Specification) and with

External Components (Figure 4, page 18)

VBUS(SS)

VBUS(PK)

-18 to 40

-150 to 100

ESD Voltage(2)

Human Body Model H0 pin

Human Body Model all other pins

Machine Model

Charge Device Model

VESD1-1

VESD1-2

VESD2

VESD3

±1000

±2000

±200

±750

Notes

1. Transient capability for pulses with a time of t < 0.5 sec.

2. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100pF, RZAP=1500Ω), the Machine Model

(CZAP=200pF, RZAP=0Ω) and the Charge Device Model, Robotic (CZAP =4.0pF).

Analog Integrated Circuit Device Data

Freescale Semiconductor 7

908E621

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

THERMAL RATINGS

Operating Ambient Temperature(3) TA-40 to 85 °C

Operating Junction Temperature(4) TJ-40 to 125 °C

Storage Temperature TSTG -40 to 150 °C

Peak Package Reflow Temperature During Reflow(6), (7) TPPRT Note 7 °C

Notes

3. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.

4. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because

of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions.

5. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to

the device.

Rating Symbol Value Unit

Analog Integrated Circuit Device Data

8Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SUPPLY VOLTAGE RANGE

Nominal Operating Voltage VSUP1 9.0 — 16 V

Extended Operating Voltage (LIN only 8..18V)(9) VSUP2 7.5 — 20 V

SUPPLY CURRENT RANGE

Normal Mode(9)

VSUP = 12V, Analog Chip in Normal Mode (PSON=1), MCU Operating

Using Internal Oscillator at 32MHz (8.0MHz Bus Frequency), SPI, ESCI,

ADC Enabled

Stop Mode(9), (10)

VSUP = 12V, Voltage Regulator with limited current capability

Sleep Mode(9), (10)

VSUP = 12V, Voltage Regulator off

IRUN

ISTOP

ISLEEP

—

μA

DIGITAL INTERFACE RATINGS (ANALOG DIE)

Output pins RST_A, IRQ_A, RXD (MISO probe only)

Low-state Output Voltage (IOUT = -1.5mA)

High-state Output Voltage (IOUT = 250μA)

VOL

VOH

–

3.85 –

–0.4

–

Output pin RXD - Capacitance(11) COUT –4.0–pF

Input pins RST_A, PWM (SS, MOSI, TXD probe only)

Input Logic Low Voltage

Input Logic High Voltage VIL

VIH

–

3.5 –

–1.5

–

Input pins - Capacitance(11) CIN –4.0–pF

Pins IRQ_A, RST_A - Pullup Resistor RPULLUP1 –10–kΩ

Pins SS - Pullup Resistor RPULLUP2 –100–kΩ

Pins MOSI, SPSCK, PWM - Pulldown Resistor RPULLDOWN –100–kΩ

Pin TXD - Pullup Current Source IPULLUP –35–μA

Notes

8. Device is fully functional, but some of the parameters might be out of spec.

9. Total current measured at GND pins.

10. Stop and Sleep mode current will increase if VSUP exceeds 15V.

11. This parameter is guaranteed by process monitoring but is not production tested.

Analog Integrated Circuit Device Data

Freescale Semiconductor 9

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

SYSTEM RESETS AND INTERRUPTS

Low Voltage Reset (LVR)

Threshold

Hysteresis VLVRON

VLVR_HYS

3.8

50 4.2

–4.65

300 V

Low Voltage Interrupt (LVI)

Threshold

Hysteresis VLVION

VLVI_HYS

6.0

0.3 –

–7.5

0.8

High Voltage Interrupt (HVI)

Threshold

Hysteresis VHVION

VHVI_HYS

0.5 –

–24

1.5

High Temperature Interrupt (HTI)(12)

Threshold TJ

Hysteresis

TION

TIH

125

5.0 –

–150

10.0

°C

High Temperature Reset (HTR)(12)

Threshold TJ

Hysteresis

TRON

TIH

155

5.0 –

–180

10.0

°C

VOLTAGE REGULATOR(13)

Normal Mode Output Voltage(14)

IOUT = 60mA, 7.5V < VSUP < 20V

IOUT = 60mA, VSUP < 7.5V and VSUP > 20V

VDDRUN1

VDDRUN2

4.75

4.75 5.0

5.0 5.25

5.25

Normal Mode Total Output Current IOUTRUN –120150mA

Load Regulation - IOUT = 60mA, VSUP = 9.0V, TJ = 125°CV

LR ––100mV

STOP Mode Output Voltage(14) VDDSTOP 4.75 5.0 5.25 V

STOP Mode Total Output Current IOUTSTOP 150 500 1100 μA

Notes

12. This parameter is guaranteed by process monitoring but is not production tested.

13. Specification with external low ESR ceramic capacitor 1.0μF< C < 4.7μF and 200mΩ≤ESR ≤10Ω. Its not recommended to use

capacitor values above 4.7μF

14. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage

specification.

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

LIN PHYSICAL LAYER

LIN Transceiver Output Voltage

Recessive State, TXD HIGH, IOUT = 1.0μA

Dominant State, TXD LOW, 500Ω External Pullup Resistor VLIN_REC

VLIN_DOM

VSUP-1

——

1.4

Normal Mode Pullup Resistor to VSUP RPU 20 30 47 kΩ

Stop, Sleep Mode Pullup Current Source IPU —20—μA

Output Current Shutdown Threshold IBLIM 100 230 280 mA

Output Current Shutdown Timing IBLS 5.0 – 40 µs

Leakage Current to GND

VSUP Disconnected, VBUS at 18V

Recessive state, 8.0V ≤ VSUP ≤ 18V, 8.0V ≤ VBUS ≤ 18V, VBUS ≥ VSUP

GND Disconnected, VGND = VSUP, VBUS at -18V

IBUS

IBUS-PAS-REC

IBUS-NOGND

–

0.0

-1.0

1.0

3.0

–

1.0

µA

LIN Receiver

Receiver Threshold Dominant

Receiver Threshold Recessive

Receiver Threshold Center

Receiver Threshold Hysteresis

VBUS_DOM

VBUS_REC

VBUS_CNT

VBUS_HYS

–

0.6

0.475

–

0.5

–

0.4

–

0.525

0.175

VSUP

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 11

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

HIGH SIDE OUTPUT HS1

Switch On Resistance

TJ = 25°C, ILOAD = 1.0A RDS(ON)-HS1 –185225

mΩ

Over-current Shutdown IHSOC1 6.0 – 9.0 A

Over-current Shutdown blanking time(15) tOCB –4-8–µs

Current to Voltage Ratio(16)

VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0A) CRRATIOHS1 0.84 1.2 1.56 V/A

High Side Switching Frequency(15) fPWMHS ––25kHz

High Side Freewheeling Diode Forward Voltage

TJ = 25°C, ILOAD = 1.0A VHSF –0.9–V

Leakage Current ILeakHS –<0.210µA

HIGH SIDE OUTPUTS HS2 AND HS3(17)

Switch On Resistance

TJ = 25°C, ILOAD = 1.0 A RDS(ON)-HS23 –440500

mΩ

Over-current Shutdown IHSOC23 3.6 – 5.6 A

Over-current Shutdown blanking time(15) tOCB –4-8–µs

Current to Voltage Ratio(16)

VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0A) CRRATIOHS23 1.16 1.66 2.16 V/A

High Side Switching Frequency(15) fPWMHS ––25kHz

High Side Freewheeling Diode Forward Voltage

TJ = 25°C, ILOAD = 1.0A VHSF –0.9–V

Leakage Current ILeakHS –<0.210µA

Notes

15. This parameter is guaranteed by process monitoring but is not production tested.

16. This parameter is guaranteed only if correct trimming was applied.

17. The high side HS3 can be only used for resistive loads.

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

HALF-BRIDGE OUTPUTS HB1 AND HB2

Switch On Resistance

High Side, TJ = 25°C, ILOAD = 1.0A

Low Side, TJ = 25°C, ILOAD = 1.0A

RDS(ON)-HB12 –

–750

750 900

900

mΩ

Over-current Shutdown

High Side

Low Side

IHBOC12 1.0

1.0 –

–1.5

1.5

Over-current Shutdown blanking time(18) tOCB –4-8–

μs

Switching Frequency(18) fPWM ––25

kHz

Freewheeling Diode Forward Voltage

High Side, TJ = 25°C, ILOAD = 1.0A

Low Side, TJ = 25°C, ILOAD = 1.0A

VHSF

VLSF

–

–0.9

0.9 –

–

Leakage Current ILeakHB –<0.210µA

Low Side Current to Voltage Ratio(19)

VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 200mA)

VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 500mA)

CRRATIOHB12 17.5

3.5 25.0

5.0 32.5

6.5

V/A

HALF-BRIDGE OUTPUTS HB3 AND HB4

Switch On Resistance

High Side, TJ = 25°C, ILOAD = 1.0A

Low Side, TJ = 25°C, ILOAD = 1.0A

RDS(ON)-HB34 –

–275

275 325

325

mΩ

Over-current Shutdown

High Side

Low Side

IHBOC34 4.8

4.8 –

–7.2

7.2

Over-current Shutdown blanking time(18) tOCB –4-8–

μs

Switching Frequency(18) fPWM ––25

kHz

Freewheeling Diode Forward Voltage

High Side, TJ = 25°C, ILOAD = 1.0A

Low Side, TJ = 25°C, ILOAD = 1.0A

VHSF

VLSF

–

–0.9

0.9 –

–

Leakage Current ILeakHB –<0.210µA

Low Side Current to Voltage Ratio(19)

VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 500mA)

VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 2.0A)

CRRATIOHB34 3.5

0.7 5.0

1.0 6.5

1.3

V/A

Notes

18. This parameter is guaranteed by process monitoring but is not production tested.

19. This parameter is guaranteed only if correct trimming was applied

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 13

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

SWITCHABLE VDD OUTPUT HVDD

Over-current Shutdown IHVDDOC 25 35 50 mA

Over-current Shutdown Blanking Time(20)

HVDDT1:0 = 00

HVDDT1:0 = 01

HVDDT1:0 = 10

HVDDT1:0 = 11

tHVDDOCB –

–

950

536

234

–

µs

Over-current Flag Delay(20) tHVDDOCFD –0.5–ms

Dropout Voltage @ ILOAD = 20mA VHVDDDROP –110300mV

VSUP DOWN SCALER(21)

Voltage Ratio (RATIO VSUP = VSUP / VADOUT)RATIO

VSUP 4.75 5.0 5.25 –

INTERNAL DIE TEMPERATURE SENSOR(21)

Voltage / Temperature Slope(20) STtoV –26–mV/°C

Output Voltage @25°C VT25 1.7 1.9 2.1 V

Notes

20. This parameter is guaranteed by process monitoring but is not production tested.

21. This parameter is guaranteed only if correct trimming was applied

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

HALL-EFFECT SENSOR INPUT H0 - GENERAL PURPOSE INPUT MODE (H0MS = 0)

Input Voltage Low Threshold VLT ––1.5V

Input Voltage High Threshold VHT 3.5 – – V

Input Voltage Hysteresis VHH 100 – 500 mV

Pullup resistor RPH 7.0 10 13 kΩ

HALL-EFFECT SENSOR INPUT H0 - 2PIN HALL SENSOR INPUT MODE (H0MS = 1)

Output Voltage

VSUP < 17V

VSUP >17V

VHALL1

VHALL2

–

–VSUP-1.2

–

15.8

Output Drop @ IOUT = 15mA VH0D ––2.5V

Sense Current Threshold IHSCT 6.0 7.9 10 mA

Sense Current Hysteresis IHSCH 650 – 1650 µA

Sense Current Limitation VHSCLIM 20 40 70 mA

ANALOG INPUT A0, A0CST

Current Source A0, A0CST(22), (23)

CSSEL1:0 = 00

CSSEL1:0 = 01

CSSEL1:0 = 10

CSSEL1:0 = 11

ICS1

ICS2

ICS3

ICS4

–

120

320

800

–

µA

WAKE-UP INPUT L0

Input Voltage Threshold Low VLT ––1.5V

Input Voltage Threshold High VHT 3.5 – – V

Input Voltage Hysteresis VLH 0.5 – – V

Input Current IN-10 – 10 µA

Wake-up Filter Time(24) tWUP –20–µs

Notes

22. This parameter is guaranteed only if correct trimming was applied

23. The current values are optimized to read a NTC temperature sensor, e.g. EPCOS type B57861 (R25 = 3000Ω, R/T characteristic 8016)

24. This parameter is guaranteed by process monitoring but is not production tested.

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

908E621

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Charac teristics

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet fo r characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

LIN PHYSICAL LAYER

Driver Characteristics for Normal Slew Rate(25), (26)

Dominant Propagation Delay TXD to LIN tDOM-MIN ——50μs

Dominant Propagation Delay TXD to LIN tDOM-MAX ——50μs

Recessive Propagation Delay TXD to LIN tREC-MIN ——50μs

Recessive Propagation Delay TXD to LIN tREC-MAX ——50μs

Duty Cycle 1: D1 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 50μs, VSUP = 7.0V..18V D1 0.396 – –

Duty Cycle 2: D2 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 50μs, VSUP = 7.6V..18V D2 – – 0.581

Driver Characteristics for Slow Slew Rate(25), (27)

Dominant Propagation Delay TXD to LIN tDOM-MIN — — 100 μs

Dominant Propagation Delay TXD to LIN tDOM-MAX — — 100 μs

Recessive Propagation Delay TXD to LIN tREC-MIN — — 100 μs

Recessive Propagation Delay TXD to LIN tREC-MAX — — 100 μs

Duty Cycle 3: D3 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 96μs, VSUP = 7.0V..18V D3 0.417 – –

Duty Cycle4: D4 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 96μs, VSUP = 7.6V..18V D4 – – 0.590

Driver Characteristics for Fast Slew Rate

LIN High Slew Rate (Programming Mode) SRFAST —20—V/μs

Receiver Characteristics and Wake-up Timings

Receiver Dominant Propagation Delay(28) tRL —3.56.0μs

Receiver Recessive Propagation Delay(28) tRH —3.56.0μs

Receiver Propagation Delay Symmetry tR-SYM -2.0 — 2.0 μs

Bus Wake-up Deglitcher tPROPWL 30 50 150 μs

Bus Wake-up Event Reported(29) tWAKE —20—μs

Notes

25. VSUP from 7.0V to 18V, bus load R0 and C0 1.0nF/1.0kΩ, 6.8nF/660Ω, 10nF/500Ω. Measurement thresholds: 50% of TXD signal to

LIN signal threshold defined at each parameter.

26. See Figure 6, page 18.

27. See Figure 7, page 19.

28. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.

29. tWAKE is typically 2 internal clock cycles after LIN rising ed ge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the VDD

rise time is strongly dependent upon the decoupling capacitor at VDD pin.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

908E621

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SPI INTERFACE TIMING

SPI Operating Recommended Frequency(30) fSPIOP 0.25 — 4.0 MHz

State Machine

Reset Low Level Duration after VDD High tRST 0.8 1.25 1.94 ms

Normal Request Timeout tNORMREQ 51 80 150 ms

Window Watchdog Timer(31)

Watchdog Period (WDP1:0 = 00) tWD80 52 80 124 ms

Watchdog Period (WDP1:0 = 01) tWD40 26 40 62 ms

Watchdog Period (WDP1:0 = 10) tWD20 13 20 31 ms

Watchdog Period (WDP1:0 = 11) tWD10 6.5 10 15.5 ms

Notes

30. This parameter is guaranteed by process monitoring but is not production tested.

31. This parameter is guaranteed only if correct trimming was applied. Additionally See Watchdog Period Range Value (AWD Trim) on page

Table 4. Dynamic Electrical Characteristics (continue d)

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet fo r characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 17

908E621

MICROCONTROLLER PARAMETRICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MICROCONTROLLER PARAMETRICS

Table 5. Microcontroller

For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.

Module Description

Core High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0MHz

Timer Two 16-Bit Timers with 2 Channels (TIM A and TIM B)

Flash 16K Bytes

RAM 512 Bytes

ADC 10-Bit Analog-to-Digital Converter

SPI SPI Module

ESCI Standard Serial Communication Interface (SCI) Module

Bit-Time Measurement

Arbitration

Prescaler with Fine Baud Rate Adjustment

ICG Internal Clock Generation Module

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

908E621

TIMING DIAGRAMS

DYNAMIC ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 4. Test Circuit for Transient Te st Pulses

Figure 5. Test Circuit for LIN Timing Measurements

Figure 6. LIN Timing Measurements for Normal Slew Rate

LIN, L0

10k 1nF

Transient Pulse

Generator

Note: Waveform in acco r da nc e to I S O76 37 part 1, test pulses 1 , 2, 3a and 3b.

VSUP

RXD

TXD LIN R0 and C0 combinations:

- 1k Ohm and 1nF

- 660 Ohm and 6.8nF

- 500 Ohm and 10nF

R0 and C0 Combinations:

• 1.0kΩ and 1.0nF

• 600Ω and 6.8nF

• 500Ω and 10nF

VSUP

tDOM-MIN

tDOM-MAX

tRL

TXD

LIN

RXD

tRH

tREC-MIN

tREC-MAX

58.1% VSUP

40% VSUP

28.4% VSUP 42.2% VSUP

60% VSUP

74.4% VSUP

VLIN

Analog Integrated Circuit Device Data

Freescale Semiconductor 19

908E621

TIMING DIAGRAMS

DYNAMIC ELECTRICAL CHARACTERISTICS

Figure 7. LIN Timi ng Measurements for Slow Slew Rate

Figure 8. Wake-up Stop Mode Timing

Figure 9. Wake-up Sle ep Mode Timing

tDOM-MIN

tDOM-MAX

tRL

TXD

LIN

RXD

VLIN

tRH

tREC-MIN

tREC-MAX

61.6% VSUP

40% VSUP

25.1% VSUP 38.9% VSUP

60% VSUP

77.8% VSUP

IRQ_A

LIN

Vrec

TpropWL Twake

Dominant level

0.4VSUP

tPROPWL tWAKE

Dominant Level

0.4 VSUP

VLIN_REC

VDD

LIN

Vrec

TpropWL Twake

Dominant level

0.4VSUP

VLIN_REC

0.4 VSUP

Dominant Level

tPROPWL tWAKE

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

908E621

TIMING DIAGRAMS

DYNAMIC ELECTRICAL CHARACTERISTICS

Figure 10. Power On Reset and Normal Reques t Time out Timing

VSUP

TRST

VDD

RST_A

TNORMREQ

Analog Integrated Circuit Device Data

Freescale Semiconductor 21

908E621

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 908E621 was designed and developed as a highly

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

908E621 is well suited to perform complete mirror control via

a three wire LIN bus.

This device combines an HC908EY16 MCU core with

flash memory together with a SMARTMOS IC chip. The

SMARTMOS IC chip combines power and control in one

chip. Power switches are provided on the SMARTMOS IC

configured as half-bridge outputs and three high side

switches. Other ports are also provided, which include one

Hall-effect sensor input port, one analog input port with a

switched current source, one wake-up pin, and a selectable

HVDD pin. An internal voltage regulator provides pow er to

the MCU chip.

Also included in this device is a LIN physical layer, whi c h

communicates using a single wire. This enables this device

to be compatible with three wire bus systems, where one wire

is used for communication, one for battery, and one for

ground.

FUNCTIONAL PIN DESCRIPTION

See Figure 2, 908E621 Simplified Inte rnal Block Diagram,

page 2, for a graphic representation of the various pins

referred to in the following paragraphs. Also, see the pin

diagram on page 3 for a depiction of the pin locations on the

package.

PORT A I/O PINS

These pins are special function, bidirectional I/O port pins

that are shared with other functional modules in th e MCU.

PTA0:PTA4 are shared with the keyboard interrupt pins,

KBD0:KBD4.

The PTA5/SPSCK pin is not accessible in this device and

is internally connected to the SPI clock pin of the analog die.

The PTA6/SS pi n is not accessi ble in this device and is

internally connected to the SPI slave select input of the

analog die.

For details refer to the 68HC908EY16 datashe et.

PORT B I/O PINS

These pins are special function, bidirectional I/O port pins

that are shared with other functional modules in the MCU. All

pins are shared with the ADC module.

PTB0/AD0 is internally connected to the ADOUT pin of the

analog die, allowing diagno stic measurements to be

calculated (e.g., current recopy, VSUP, etc.).

The PTB1/AD1, PTB2/AD2, PTB6/AD6/TBCH0, PTB7/

AD7/TBCH1 pins are not accessible in this device.

For details refer to the 68HC908EY16 datashe et.

PORT C I/O PINS

These pins are special function, bidirectional I/O port pins

that are shared with other functional modules in the MCU. For

example, PTC2:PTC4 are shared with the ICG mo dule.

PTC0/MISO and PTC1/MOSI are not accessible in this

device and are intern ally connected to the MISO and MOSI

SPI pins of the analog die.

For details refer to the 68HC908EY16 datasheet.

PORT D I/O PINS

PTD0/TACH0/BEMF and PTD1/TACH1 are specia l

function, bidirectional I/O port pins that can also be

programmed to be timer pins.

PTD0/TACH0 pin is internally connected to the PWM input

of the analog die and only accessi ble for test purposes (can

not be used in the application).

For details refer to the 68HC908EY16 datasheet.

PORT E I/O PIN

PTE0/TXD and PTE1/RXD are special function,

bidirectional I/O port pins that can also be programmed to be

enhanced serial communication.

PTE0/TXD is internally connected to the TXD pin of the

analog die. The connection for the receiver must be done

externally.

PTE1/RXD is internally connected to the RXD pin of the

analog die and only accessible for test purposes (can not be

used in the application).

For details refer to the 68HC908EY16 datasheet.

EXTERNAL INTERRUPT PIN (IRQ)

The IRQ pin is an asynchronous external interrupt pin. This

pin contains an internal pullup resistor that is always

activated, even when the IRQ pin is pulled LOW.

For details refer to the 68HC908EY16 datasheet.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

908E621

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

EXTERNAL RESET PIN (RST)

A logic [0] on the RST pin forces th e MCU to a known

startup state. RST is bidirectional, allowing a reset of the

entire system. It is driven LOW when any internal reset

source is asserted.

This pin contains an internal pullup resistor that is always

activated, even when the reset pin is pulled LOW.

For details refer to the 68HC908EY16 datashe et.

POWER SUPPLY PINS (VSUP1:VSUP8)

VSUP1:VSUP8 are de vice power supply pins. The

nominal input voltage is designed for operation from 12V

systems. Owing to the low ON-resistance and current

requirements of the half-bridge driver outputs and high side

output drivers, multiple VSUP pins are provided.

All VSUP pins must be connected to get full chip

functionality.

POWER GROUND PINS (GND1:GND4)

GND1:GND4 are device power ground connections.

Owing to the low ON-resistance and current requirements of

the half-bridge driver outputs and high side output drivers,

multiple pins are provided.

GND1 and GND2 pins must be connected to get full chip

functionality.

HALF-BRIDGE OUTPUT PINS (HB1:HB4)

The 908E621 device includes power MOSFETs

configured as four half-bridge driver outputs. The HB3:HB4

have a lower RDS(ON), to run higher currents (e.g. fold motor),

than the HB1:B2 outputs.

The HB1:HB4 outputs are short-circuit and over-

temperature protected, and they feature current recopy.

Over-current protection is done on both high side and low

side FET’s. The current recopy are done on the low side

MOSFETs.

HIGH SIDE OUTPUT PINS (HS1:HS3)

The HS output pins are a low RDS(ON) high side switches.

Each HS switch is protected against over-temperature and

over-current . Th e ou tput is capabl e of li mi ti ng th e in rush

current with an automatic PWM or feature a real PWM

capability using the PWM input.

The HS1 has a lower RDS(ON), to run higher currents (e.g.

heater), than the HS2 and HS3 outputs.

For the HS1 two pins (HS1a:HS1b) are necessary for the

current capability and have to be connected externally.

Important: T he HS3 can be only used to drive resistive

loads.

HALL-EFFECT SENSOR INPUT PIN (H0)

The Hall-effect sensor input pin H0 provides an input for

Hall-effect sensors (2pin or 3pin) or a switch.

ANALOG INPUT PINS (A0, A0CST)

These pins are analog inputs with selectable current

source values. The A0CST intent is to trim the A0 input.

WAKE-UP INPUT PIN (L0)

This pin is 40V rated input. It can be used as wake-up

source for a system wake-up. The input is falling or rising

edge sensitive.

Important: If unused this pin should be connected to

VSUP or GND to avoid parasitic transitions. In Low Power

mode this could lead to random wake-up events.

SWITCHABLE VDD OUTPUT PIN (HVDD)

The HVDD pin is a switchable VDD output for driving

resistive loads requiring a regulated 5.0V supply (e.g., 3-pin

Hall-effect sensors or potentiometers). The output is short-

circuit protected.

LIN BUS PIN (LIN)

The LIN pin represents the single wire bus transmitter and

receiver. It is suited for automotive bus systems and is based

on the LIN bus specification.

+5.0V VOLTAGE REGULATOR OUTPUT PIN (VDD)

The VDD pin is needed to place an external capacitor to

stabilize the regulated output voltage. The VDD pin is

intended to supply the embedded microcontroller.

Important: The VDD pin should not be used to supply

other loads; use the HVDD pin for this purpose. The VDD,

EVDD and VDDA/VREFH pins must be connected together.

VOLTAGE REGULATOR GROUND PIN (VSS)

The VSS pin is the ground pin for the connection of all non-

power ground connections (microcontroller and sensors).

Important: VSS, EVSS and VSSA/VREFL pins must be

connected together.

RESET PIN (RST_A)

RST_A is the bidirectional reset pin of the analog die. It is

an open drain with pullup resistor and must be connected to

the RST pin of the MCU.

INTERRUPT PIN (IRQ_A)

IRQ_A is the interrupt output pin of the analog die

indicating errors or wake-u p events. It is an open drain with

pullup resistor and must be connected to the IRQ pin of the

MCU.

Analog Integrated Circuit Device Data

Freescale Semiconductor 23

908E621

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ADC SUPPLY/REFERENCE PINS (VDDA/VREFH

AND VSSA/VREFL)

VDDA and VSSA are the power supply pins for the analog-

to-digital converter (ADC).

VREFH and VREFL are the reference voltage pins for the

ADC.

The supply and reference signals are internally connected.

It is recommended that a high quality ceramic decoupling

capacitor be placed between these pins.

For details refer to the 68HC908EY16 datashe et.

MCU POWER SUPPLY PINS (EVDD AND EVSS)

EVDD and EVSS are the power supply an d ground pins.

The MCU operates from a single power supply.

Fast signal transitions on MCU pins place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU.

For details refer to the 68HC908EY16 datashe et.

TEST MODE PIN (TESTMODE)

This pin is for test purpose only. In the application this pin

has to be forced to GND.

For Programming/Test this pin has to be forced to VDD to

bring the analog die into Test mode. In Test mode the Reset

Timeout (80ms) is disabled and the LIN receiver is disabled

NOTE: After detecting a RESET (internal o r exte rnal), the

PSON bit needs to be set within 80ms. If not, the device will

automatically enter sleep mode.

MCU TEST PIN (FLSVPP)

This pin is for test purposes only. This pin should either be

left open (not connected) or can be connected to GND.

NO CONNECT PINS (NC)

The NC pins are not connected internally.

Note: Each of the NC pins can be left open or conne cted

to ground (recommended).

EXPOSED PAD PIN

The exposed pad pin on the bottom side of the package

conducts heat from the chip to the PCB board. For thermal

performance, the pad must be soldered to the PCB board. It

is recommended that the pad be connecte d to the ground

potential.

4,7µF0,1µF

VDDA/VREFH

EVDD

EVSS

VSSA/VREFL

VDD

VSS

µC Analog

Die

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

908E621

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

SMARTMOS ANALOG CONTROL IC

INTERNAL REGULATORS & SAFETY:

VOLTAGE REGULATION

The voltage regulator circuitry provides the regulated

voltage for the Analog IC as well as the VDD/VSS rails for the

core IC. The on-chip regulator consis ts of two elements, the

main regulator, and the low voltage reset circuit. The VDD

regulator accepts an unregulated input supply, and provides

a regulated VDD supply to all digital sections of the device.

The output of the regulator is also connected to the VDD pin,

to provide the 5.0V to the microcontroller.

SWITCHED VDD

This function provides a switchable +5.0V VDD rail for an

external load.

WATCHDOG TIMER

The watchdog timer module generates a reset, in case of

a watchdog timeout or wrong watchdog timer reset. A

watchdog reset event will reset all registers in the SPI,

excluding th e R S R .

RESET, IRQ & WAKE-UP

There are several functions on the Analo g IC that can

generate a reset or wake-up signal to the core IC. There is a

pin that is used to detect an external wake-up event. The

Reset signal has many possible sources in the Analog IC

circuitry. The IRQ function on the Analog IC, will notify the

core IC of pending system critical conditions.

CONTROL & INTERFACE:

HALL SENSOR INTERFACE

This interface can be configured to support an input pin as

a general purpose input, or as a hall-effect sensor input, to be

able to read 3-pin / 2-pin hall sensors or switches.

MM908E621 - Functional Block Diagram

Internal Regulators & Safety OutputsControl & Interface

MC68HC908EY16 Core

SMARTMOS Analog Control IC

M68HC08 CPU

w/ ALU, RAM, Flash ROM

Power Module

w/Power-On Reset

Internal Clock Module

10-Bit ADC Module

I/O Ports A, B, C, D, E

Reset & IRQ

Analog Multiplexer

Voltage Regulation Reset, IRQ & Wake-up

Switched VDD Watchdog Timer

Internal Regulators & Safety

Control & Interface

Outputs

High Side Drivers & Diagnostics

H-Bridge Drivers & Diagnostics

Hall Sensor Interface

MC68HC908EY16 Core

Timer Modules

Communication Modules

LIN Interface

Analog Input w/Integrated Current Source

SPI Interface & PWM Control

Analog Integrated Circuit Device Data

Freescale Semiconductor 25

908E621

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

SPI INTERFACE & PWM CONTROL

The SPI and PWM interfaces are mastered by the core IC

(CPU), and are used to control the output functions of the

Analog IC, as well as to report status and failure information

of the Analog IC .

LIN INTERFACE

The LIN interface function supports the single wire bus

transmit and receive capabilities. It is suited for automotive

bus systems and is based on the LIN bus/physical layer

specification. The LIN driver is a low side MOSFET with slope

control, internal current limitation, and thermal shutdown.

ANALOG MULTIPLEXER

To be able to have different sources for the MCU with one

single signal, an analog multiplexer is integrated in the analog

IC. This mult ip l exer has eleven dif fe r en t so urces on the

Analog IC, which can be selected with the SS[3:0] bits

(through SPI communication) in the A0MUCTL register.

ANALOG INPUT W/INTEGRATED CURRENT

SOURCE

The terminal A0 provides a switchable current source, to

allow the reading of switches, NTC, etc., without the need for

an additional supply line for the sensor (single wire). There

are four different selectable current source values.

OUTPUTS:

HIGH SIDE DRIVERS & DIAGNOSTICS

The HS outputs are low RDS(ON) high side switches.

Each HS switch is protected against over-temperature and

over-current . Th e ou tput is capabl e of li mi ti ng th e in rush

current with an automatic PWM, or feature a real PWM

capability using the PWM input.

H-BRIDGE DRIVERS & DIAGNOSTICS

The device includes power MOSFETs configured as four

half-bridge driver outputs. These outputs are short-circuit and

over-temperature protected. Over-current protection is done

on both high side and low side MOSFETs.

MM68HC908EY16 CORE IC

M68HC08 CPU W/ALU, RAM, FLASH ROM

This possesses the functionality of the CPU08

architecture, along with 512 bytes of RAM and 15,872 bytes

of FLASH memory, with in-circuit programming.

POWER MODULE W/P0WER-ON-RESET

This block of circuitry manages the powe r supplied to the

core IC, as well as providing POR, LVI, Watchdog timer, and

MCU supervision circuitry (COP).

INTERNA L CLOCK MODULE

This module provides the cl ocks needed by the core

IC functions, without the need for external components.

Software selectable bus frequencies are availa ble. It

also provides a clock monitor functio n.

10-BIT ADC MODULE

This module provides an 8-channel, 10-bit successive

approximation analog-to-digital converter (AD C).

I/O PORTS A, B, C, D, E

There are many I/O pins that are controlled by the CPU

through the several I/O ports of the core IC.

TIMER MODULES

There are two 16-bit, 2 channel timer interface modules

with selectable input capture, output compare, and PWM

capabilities, for each channel.

COMMUNICATION MODULES

There are several communication functions supported by

the core IC, including an enhanced serial communication

interface module (ESCI) for the LIN communication, and an

SPI module for inter-IC communication.

RESET & IRQ

There are interrupt and re set connections between the

Analog IC and the core IC, for concise control and error/

exception management.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

908E621 ANALOG DIE MODES OF OPERATION

The 908E621 offers three operating modes: Normal (Run),

Stop, and Sleep. In Normal mode, the device is active and is

operating under normal application conditions. The Stop and

Sleep modes are low power modes with wake-up capabilities.

The different modes can be selected by the STOP and

SLEEP bits in the System Control Register.

Figure 11 describes how transitions are done between the

different operating modes and Table 6, page 28, gives an

overview of the operating modes.

Figure 11. Operating Modes and Trans iti ons

Normal Mode

This Mode is the normal operating mode of the device, all

functions and power stages are active and can be enabled/

disabled. The voltage regulator provides the +5V VDD to the

MCU.

After a reset (e.g. Power-On-Reset, Wake-up from Sleep),

the MCU has to set the PSON bit in the System Control

the MCU has started up and is operating correctly. If the

PSON bit is not set within the required time frame, the device

enters SLEEP mode to reduce power consumption (fail safe).

This MCU monitoring can be disabled (e.g. for

programming) by appl ying VDD on the TESTMO DE pin.

Stop Mode

In Stop mode, the voltage regulator still supplies the MCU

with VDD (limited current capability). To enter the Stop mode,

the STOP bit in the System Control Register must be set, and

the MCU has to be stopped also (see 908EY16 datasheet for

details).

Wake-up from this mode is possible by the LIN bus activity

or the wake-up input L0. It is maskable with the LINIE and/or

L0IE bits in the Interrupt Mask Register. The analog die is

generating an interrupt on IRQ_A pin to wake-up the MCU.

The wake-up / interrupt source can be evaluated with the

L0IF and LINIF bits in the Interrupt Flag Register.

Stop mode has a higher current consumption than Slee p

mode, but allows a quicker wake-up. Additionally th e wake-

RESET

Power

Down Power Up Normal

Request

VDD High and Reset Delay (tRST) expired

NORMAL

SLEEP

Wake-Up (Reset)

STOP

Reset (LVR, ext. Reset, (HTR))

SLEEP Command

STOP Command

Wake-Up In terrupt

PSON = 1

VDD Low

Reset (LVR, HTR, WDR, e xt. R e se t)

Reset (LVR, ext. Reset)

TESTMODE = 1

PSON = 0 and Normal R equest

timeout (tNORMREQ) expired

Analog Integrated Circuit Device Data

Freescale Semiconductor 27

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

up sources can be selected (maskable), which is not possible

in Sleep mode.

Figure 12 show the procedure to enter the Stop mode and

how the system is waking up.

Figure 12. STOP Mode Wake-up Procedure

Sleep Mode

In Sleep mode, the voltage regulator is turned off and the

MCU is not supplied (VDD = 0V), also the RST_A pin is pulled

low.

To enter the Sleep mode, the Sleep bit in the System

Control Register has to be set.

Wake-up from this mode is possible by LIN bus activity or

the wake-up input L0, and is not maskable. The wake-u p

behaves like a power on reset. The wake-up / reset source

can be evaluated by the L0WF and/or LINWF bits in the

Reset Status Register.

Sleep mode has a lower curre nt consumption than Stop

mode, but requires a longer time to wake-up. The wake-up

sources can not be selected (not maskable).

Figure 13 show the procedure to enter the Sleep mode

and how a wake-up is performed.

Figure 13. SLEEP Mode Wake-up Procedure

Table 6 summarized the Operating modes.

From Reset

initialize

operate

SPI:

STOP =1

MCU STOP

IRQ

interrupt

SPI: reason for

interrupt

Switch to VREG

low current mode

Assert IRQ

Switch to VREG

high current mode

MCU Power Die

Wake-up on

LIN or L0 ?

Enable/disable

LIN/L0 wakeup

From Re se t

initialize

operate

SPI:

SLEEP =1 Switch off VREG

VDD low, RST low

Store Wake-up

Event

Start VREG

VDD high, RST

high

MCU Power Die

Wake-up on

LIN or L0 ?

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

OPERATING MODES OF THE MCU

For a detailed description of the operating modes of the

MCU, refer to the MC68HC908EY16 datasheet.

INTERRUPTS

The 908E621 has seven different in terrupt sources. An

interrupt pulse on the IRQ_A pin is generated to report an

event or fault to the MCU. All interrupts are maskable and can

be enabled/disabled via the SPI (Interrupt Mask Reg ister).

After reset, all interrupts are automatically disabled.

Low Voltage Interrup t

Low voltage interrupt (LVI) is related to external su pply

voltage VSUP. If this voltage falls below the LVI threshold, it

will set the LVIF bit in the Interrupt Flag Register. If the low

voltage interrupt is enabled (LVIE = 1), an interrupt will be

initiated.

During Sleep and Stop mode, the low voltage inte rrupt

circuitry is disabled.

High Voltage Interrupt

The High voltage Interrupt (HVI) is related to the external

supply voltage VSUP. If this voltage rises above the HVI

threshold, it will set the HVIF bit in the Interrupt Flag Register.

If the High voltage Interrupt is enabled (HVIE = 1), an

interrupt will be initiated.

During Stop and Sleep mode, the HVI circuitry is disabled.

High Temperature Interrupt

The high temperature interrupt (HTI) is generated by the

on chip temperature sensors. If the chip temperature is above

the HTI threshold, the HTIF bit in the Interrupt Flag Register

will be set. If the high temperature interrupt is enabled (HTIE

= 1), an interrupt will be initiated.

During Stop and Sleep mode, the HTI circuitry is disabled.

LIN Interrupt

The LIN Interrupt is related to the Stop mode. If the LIN

interrupt is enabled (LINIE = 1) in Stop mode, an interrupt is

asserted if a rising edge is detected, and the bus was

dominant longer than TPROPWL. After the wake-up / int errupt,

the LINIF indicates the reason for the wake-up / interrupt.

Power Stage Fail Interrupt

The power stage fail flag indicates an error condition on

any of the power stages (see Figure 14, page 29). If the

power stage fail interrupt is enabled (PSFIE = 1), an interrupt

will be initiated if:

During Stop and Sleep mode, th e PSFI circuitry is

disabled.

HO Input Interrupt

The H0 interrupt flag H0IF is set in run mode by a state

change of the H0F flag (rising or falling edge on the enabled

input). The interrupt function is avail able if the input is

selected as General Purpose, or as a 2pin Hallsensor input.

The interrupt is maskable with the H0IE bit in the Interrupt

Mask Register.

During Stop and Sleep mode, the H0I circuitry is disabled.

Table 6. Operating Modes Overview

Device Mode Voltage Regulator Wake-up Capabilities RST_A

Output MCU monitoring/

Watchdog Function Power Stages LIN Interface

Reset VDD ON N/A LOW Disabled Disabled Disabled

Normal Request VDD ON N/A HIGH

tNORMREQ (80ms

typical) time out to set

PSON bit in System

Control Register

Disabled Disabled

Normal (Run) VDD ON N/A HIGH Window Watchdog

active if enabled Enabled Enabled

Stop VDD ON with limited

current capability

LIN wake-up,

L0 state change

(SPI PSON=1)(32) HIGH Disabled Disabled Recessive state with

wake-up capability

Sleep VDD OFF LIN wake-up

L0 state change LOW Disabled Disabled Recessive state with

wake-up capability

Notes

32. The SPI is still active in Stop mode. However, due to the limited current capability of the voltage regulator in Stop mode, the PSON bit

has to be set before the incr eased current caused from a running MCU causes an LVR.

Analog Integrated Circuit Device Data

Freescale Semiconductor 29

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

L0 input Interrupt

The L0 interrupt flag L0IF is set in run mode by a state

change of the L0F flag (rising or falling edge). The interrupt is

maskable with the L0IE bit in the interrupt mask register.

INTERRUPT FLAG REGISTER (IFR)

L0IF - L0 Input Flag Bit

This read/write flag is set on a falling or rising edge at the

L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears

the L0IF bit. Writing a logic [0] to L0IF has no effect.

1 = rising or falling edge on L0 input detected

0 = no state change on L0 input detected

H0IF - H0 Input Flag Bit

This read/write flag is set on a falling or rising edge at the

H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset

clears the H0IF bit. Writing a logic [0] to H0IF has no effect.

1 = state chang e on th e ha l l fl ag s de te cted

0 = no state change on the hallflags detected

LINIF - LIN Flag Bit

This read/write flag is set if a rising edge is detected and

the bus was dominant longer than TpropWL. Clear LINIF by

writing a lo gic [1] to LINIF. Re set clears the LINIF bi t. Writing

a logic [0] to LINIF has no effect.

1 = LIN bus interrupt has occurred

0 = not LIN bus interrupt occurred since last clear

HTIF - High Tempe rature Flag Bit

This read/write flag is set on high temperature condition.

Clear HTIF by writing a logic [1] to HTIF. If high temperature

condition is still present while writing a logical one to HTIF,

the writing has no effect. Therefore, a high temperature

interrupt cannot be lost due to inadvertent clearing of HTIF.

Reset clears the HTIF bit. Writing a logic [0] to HTIF has no

effect.

1 = high temperature condition has occurred

0 = high temperature condition has not occurre d

LVIF - Low Voltage Fl ag Bit

This read/write flag is set on low voltage condition. Clear

LVIF by writing a logic [1] to LVIF. If the low voltage condition

is still present while writing a logical one to LVIF, the writing

has no effect. Therefore, a low voltage interrupt cannot be

lost due to inadvertent clearing of LVIF. Reset clears the LVIF

bit. Writing a logic [0] to LVIF has no effect.

1 = low voltage condition has occurred

0 = low voltage condition has not occurred

HVIF - High Voltage Flag Bit

This read/write flag is set on a high voltage condition.

Clear HVIF by writing a logic [1] to HVIF. If the high voltage

condition is still present while writing a logical one to HVIF,

the writing has no effect. Therefore, a high voltage interrupt

cannot be lost due to inadvertent clearing of HVIF . Reset

clears the HVIF bit. Writing a logic [0] to HVIF has no effect.

1 = high voltage condition has occurred

0 = high voltage condition has not occurred

PSFIF - Power Stage Fail Bit

This read-only flag is set on a fail condition on one of the

power outputs (HBx, HSx, HVDD, H0). Reset clears the

PSFIF bit. Clear this flag by writing a logic [1] to the

appropriate fail flag.

1 = power stage fail condition has occurred

0 = power stage fail condition has not occurred

Figure 14. Principal Implementation of the PSFIF

Bit7 6 5 4 3 2 1 Bit0

Read L0IF H0IF LINIF 0HTIF LVIF HVIF PSFIF

Write

Reset 00000000

HS3OC

HS2OC

HS1OC

HB4OC

HB3OC

HB2OC

HB1OC

HVDDOCF

H0OCF

HBFF

HSFF

HVDDOCF

H0OCF

PSFIF

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

INTERRUPT MASK REGISTER (IMR)

L0IE - L0 Input Interrupt Ena ble Bit

This read/write bit enables CPU interrupts by the L0 flag,

L0IF. Reset clears the L0IE bit.

1 = interrupt requests from L0IF flag enabled

0 = interrupt requests from L0IF flag disabled

H0IE - H0 Input Interrupt Enable Bit

This read/write bit enables CPU interrupts by the Hallport

flag, H0IF. Reset clears the H0IE bit.

1 = interrupt requests from H0IF flag enabled

0 = interrupt requests from H0IF flag disabled

LINIE - LIN line Interrupt Enable Bit

This read/write bit enables CPU interrupts by the LIN flag,

LINIF. Reset clea rs th e LI N IE bit.

1 = interrupt requests from LINIF flag enabled

0 = interrupt requests from LINIF flag disabled

HTRD - High Temperature Reset Disable Bit

This read/write bit disables the high temp e rature reset

function. Reset clears the HTRD bit.

1 = high temperature reset is disabled

0 = high temperature reset is enabled

Note: Disabling of the high temperature reset can lead to

a destruction of the part in cases of high temperature. This bit

was foreseen for test purposes only!

HTIE - High Temperature Interrupt Enable Bit

This read/write bit enables CPU interrupts by the high

temperature flag, HTIF. Reset clears the HT IE bit.

1 = interrupt requests from HTIF flag enabled

0 = interrupt requests from HTIF flag disabled

LVIE - Low Voltage Interrupt Enable Bit

This read/write bit enables CPU interrupts by the low

voltage flag, LVI F.Reset clears the LVIE bit.

1 = interrupt requests from LVIF flag enab led

0 = interrupt requests from LVIF flag disabled

HVIE - High Voltage Interrupt Enable Bit

This read/write bit enables CPU interrupts by the high

voltage flag, HVIF.Reset clears the HVIE bit.

1 = interrupt requests from HVIF flag enabled

0 = interrupt requests from HVIF flag disabled

PSFIE - Power Stage Fail Interrupt Enable Bit

This read/write bit enables CPU interrupts by power stage

fail flag, PSFIF. Reset clears the PSFIE bit.

1 = interrupt requests from PSFIF flag enabled

0 = interrupt requests from PSFIF flag disabled

RESETS

The 908E621 has four internal and one external reset

source.

Each internal reset event will cause a reset pin low for tRST

(1.25ms typical), after the reset event is gone.

Bit7 654321Bit0

Read L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE

Write

Reset 00000000

Analog Integrated Circuit Device Data

Freescale Semiconductor 31

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 15. Internal Reset Rout ing

RESET SOURCE

High Temperature Reset

The device is protected against high temperature. When

the chip temperature exceeds a certain temperature, a reset

(HTR) is generated. The reset is flagged by the HTR bit in the

Interrupt Flag Register. A HTR event will reset all registers in

the SPI excluding the RSR.

The HTR can be disabled by bit HTRD in the Interrupt

Mask register.

Note: Disabling the high temperature reset ca n lead to

destruction of the part in cases of high temperature. This bit

was foreseen for test purposes only!

Watchdog Reset

The watchdog module generates a reset, because of a

watchdog timeout or wrong watchdog timer reset. Reset is

flagged by the WDR bit in the Reset Status Register. A

watchdog reset event will reset all registers in the SPI

excluding the RSR.

Main VREG Low Voltage Reset

The LVR is related to the Main VDD. If the voltage falls

below a certain threshold, it will pull do wn the RST_A pin.

Reset is flagged by the LVR bit in the Reset Status Register.

An LVR event will reset all register in th e SPI excluding the

RSR.

Power On Reset

The POR is related to the internal 5V supply. If the device

detects a power on, the POR bit in the Reset Status Register

(RSR) is set. A power on reset will reset all register in the SPI

including the RSR and set the POR bit.

The Power On Reset circuitry will force the RST_A pin low

for tRST after the VDD has reached its nominal value (above

LVR Threshold). Also see Figure 10, page 20).

Reset Pin / External Reset

An external reset can be applied by pulling down the

RST_A pin. The reset event is flagged by the PINR bit in the

reset status register.

Reset Status Register

This register contains five flags that shows the source of

the last reset. A power-on-reset sets the POR bit and clears

all other bits i n the R ese t Status Register . All bi ts ca n be

cleared by writing a one to the corresponding bit. Uncleared

bits remain set as long as they are not cleared by a power-

on-reset or by software.

In addition, the register includes two flags which will

indicate the source of a wake-up from Sleep mode: Either LIN

bus activity, or an event on the L0 wake-up input pin.

RSR

WDRE

WD Reset Sensor

VDD

RST_A

SPI REGISTERS

Reset SPI Register

(not RSR)

POR internal VREG

LVR Main VREG

HTRD

HTR Reset Sensor

MONO FLOP

Pulse Duration

after reset event is

removed

Clear RSR and set

POR Bit

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

POR— Power On Reset bit

This read/write bit is set after power on. Bit is cleared by

writing a logic “1” to this location.

1 = Reset due to power on

0 = no power on reset

PINR— Reset Forced from External Reset Pin Bit

This read/write bit is set after a reset was forced on the

external reset RST_A pin. The bit is cleared by writing an

logic “1” to this location.

1 = reset source is external reset pin

0 = no external reset

WDR— Watch Dog Reset Bit

This read/write flag is set due to a watchdog timeout or

wrong watchdog timer reset. Clear WDR by writing a logic “1”

to WDR.

1 = reset source is watchdog

0 = no watchdog reset

HTR— High Temperature Reset Bit

This read/write bit is set if the chip temperature exceeds a

certain value. The bit is cleared by writi ng a logic “1” to this

location.

1 = reset due to high temperature condition

0 = no high temperature reset

LVR— Low Voltage Reset Bit

This read/write bit is set if the external VDD voltage coming

from the main voltage regulator falls belo w a certain value.

The bit is cleared by writing a logic “1” to this location.

1 = reset due to low voltage condition

0 = no low voltage reset

LINWF— LIN Wake-up Fl ag

This read/write bit is set if a bus activity was the case of an

wake-up. The bit is cleared by writing a logic “1” to this

location.

1 = Wake-up due to bus activity

0 = no wake-up due to bus activity

L0WF— L0 Wake-u p Fla g

This read/write bit is set if a event on the L0 pin caused an

wake-up. The bit is cleared by writing a logic “1” to this

location.

1 = Wake-up due to L0 pin

0 = no Wake-up due to L0 pin

ANALOG DIE INPUTS/O UTPUTS

LIN PHYSICAL LAYER

The LIN bus pin provides a physical layer for single wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification.

The LIN driver is a low side MOSFET with internal current

limitation and thermal shutdown. An internal pullup resistor

with a serial diode structure is integrated, so no external

pullup components are required for the application in a slave

node. The fall time from dominant to recessive and the rise

time from recessive to dominant is controlled. The symmetry

between both slew rate controls is guaranteed.

The slew rate can be selected for optimized operation at

10 and 20kBit/s as well as high baud rates for test and

programming. The slew rate can be adapted with 2 bits

SRS[1:0] i n the System Cont rol Register. T he initial slew rate

is optimized for 20kBit/s.

The LIN pin offers high susceptib ility immunity level from

external disturbance, guarantee ing communication during

external disturbance.

The LIN transmitter circuitry is enabled by setting the

PSON bit in the System Control Register (SYSCTL).

If the transmitter works in the current limitation region, the

LINCL bit in the System Status Register (SYSSTAT) is set

and the LIN transceiver is disabled after a certain time.

For improved performance and safe behavior, in case of

LIN bus short to Ground or LIN bus leakage during low power

mode, the internal pullup resistor on the LIN pin is

disconnected from VSUP and a small current source keeps

the LIN bus at recessive level. In case of a LIN bus short to

GND, this feature will reduce the current consumption in

STOP and SLEEP modes.

Bit7 6 5 4 3 2 1 Bit0

Read POR PINR WDR HTR LVR 0LINWF LOWF

Write

POR 1 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 33

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 16. LIN Interface

TXD Pin

The TXD pin is the MCU interface to control the state of the

LIN transmitter (see Figure 2, page 2). When TXD is LOW,

the LIN pin is low (dominant state). When TXD is HIGH, the

LIN output MOSFET is turned off (recessive state). The TXD

pin has an internal pullup current source to set the LIN bus to

a recessive state in the event, for instance, if the

microcontroller could not control it during system power-up or

power-down.

RXD Pin

The RXD transceiver pin is the MCU interfa c e, which

reports the state of the LIN bus voltage. LIN HIGH (recessive

state) is reported by a high level on RXD, LIN LOW (dominant

state) by a low level on RXD.

STOP Mode and Wake-up Feature

During STOP mode operation the transmitter of the

physical layer is disabled and the internal pullup resistor is

disconnected from VSUP and a small current source keeps

the LIN pin in recessive state. The receiver is still active and

able to detect wake-up events on th e LIN bus line.

If the LIN interrupt is enabled (LINIE bit in the Interrupt

Mask register is set), a dominant level longer than TPROPWL

followed by an rising edge will set the LINIF flag and generate

an interrupt which causes a system wake-up (see Figure 8,

page 19)

SLEEP Mode and Wake-up Feature

During SLEEP mode operation the transmitter of the

physical layer is disabled, the internal pullup resistor is

disconnected from VSUP, and a small current source keeps

the LIN pin in the recessive state. The receiver is still active

to be able to detect wake-up events on the LIN bus line.

A dominant level longer than TPROPWL followed by an

rising edge will generate a system wake-up (reset) and set

the LINWF flag in the Reset Status register (RSR). Also see

Figure 9, page 19).

A0 INPUT AND ANALOG MULTIPLEXER

A0 - Analog Input

Input A0 is an analog input used for reading switches, or

as analog inputs for potentiometers, NTC, etc.

A0 is internally connected to the analog multiplexer. This

pin offers a switchable current source. To read the Analog

Input, the pin has to be selected with the SS[3:0] bits in the

A0MUCTL register.

Control

Receiver

Wake-up

RXD

TXD

GND

VSUP

Slope

Control

30k

10µA

LIN bus

SRS[1:0]

PSON

LINCL

LINIF

Wake-up

Filter

MODE

TESTMODE

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 17. Analog Input and Multiplexer

A0 Current Source

The pin A0 provides a switchable current source, to be

able to read in switches, NTC, etc., without the need of an

additional supply line for the sensor. The overall enab le of

this feature is done by setting th e PSON bit in the System

Control regi st er. In addition, the pin has to be selected with

the SS[3:0] bits. The current source can be enabled with the

CSON Bit and adjusted with the bits CSSEL[1:0].

With the CSSEL[1:0] bit’s, four different current values can

be selected (40, 120, 320 and 800µA). This function is halted

during STOP and SLEEP mode operations.

The current source is derived from the VDD voltage, and is

constant up to an output voltage of ~4.75V.

To calibrate the current sources, an extra pin (A0CST) is

envisioned. On this pin, an accurate resistor can to be

connected. Switching the current sources to this resistor,

allows the user to measure the current and use the measured

value for calculating the current on A0.

Analog Multiplexer / ADOUT pin

The ADOUT pin is the analog outp ut interface to the

Analog-to-digital converter of the MCU. To be able to have

different sources for the MCU with one single signal, an

analog multiplexer is integra ted in the analog die. This

multiplexer has eleven different sources, which can be

selected with th e SS[3 :0 ] bi ts in the A0MUCTL register.

Half-bridge (HB1:HB4) Current Recopy

The multiplexer is connected to the fou r current sense

circuits on the low side FET of the half bridges. This sense

circuits offers a voltage proportional to the current through the

MOSFET. The resolution is depending on the CSA bit in the

A0 and Multiplexer control register (A0MUCTL).

High Side (HS1:HS3) Current Recopy

The multiplexer is connected to the three high side

switches. This sense circuit offers a voltage proportional to

the current through the transistor.

Analog Input A0 and A0CST

A0 and A0CST are directly connected to the analog

multiplexer. It offers the possibility to read analog values from

the periphery.

Analog

Multiplexer

ADOUT

PSON

CSON

CSSEL

SSx

Source Selection Bits

VDD

A0CST

Analog Port A0/A0CST

Selectable

Current

Source

SS[0:3]

IA0(UA0)

UA0[V]

54.75

100%

Analog Integrated Circuit Device Data

Freescale Semiconductor 35

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Temperature Sensor

The analog die includes an on chip temperatu r e sensor.

This sensor offers a voltage which is proportional to the

actual mean chip junction temperature.

VSUP Prescaler

The VSUP prescaler offers a possibility to measure the

external supply voltage. The output of this voltage is VSUP /

RATIOVSUP.

A0 and Multiplexer Control Register (A0MUCTL)

CSON — Current Source on/off

This read/write bit enables the current source for the A0 or

A0CST inputs. Reset clears CSON bit.

1 = Current Source enabled

0 = Current Source disabled

CSSEL[1:0] — Current Source Select Bits

These read/write bits select the current source values for

A0 or A0CST input. Reset clears CSSEL[1:0] bits.

Table 7. A0 Current Source Level Selection Bits

CSA — H-bridges Current Sense Amplification Select Bit

This read/write bit selects the current sense amplifi ca ti on

of the H-Bridges HB1:HB4 current recopy. Reset clears the

CSA bit.

1 = low current sense amplification

0 = high current sense amplification

SS[3:0] — Analog Source Input Select Bits

These read/write bits sele cts the analog input source for

the ADOUT pin. Reset clears the SS[3:0] bits Analog

Multiplexer Configuration Bits.

Hall-effect Sensor Input Pin H0

The H0 pin can be configured as general purpose input

(H0MS = 0) or as hall-effect sensor input (H0MS = 1) to be

able to read 3pin / 2pin hall sensors or switches.

Bit7 654321Bit0

Read CSON CSSEL

1CSSEL

0CSA SS3 SS2 SS1 SS0

Write

Reset 00000000

CSSEL1 CSSEL0 Current Source Enable (typ.)

0 0 40µA

0 1 120µA

1 0 320µA

1 1 800µA

SS3 SS2 SS1 SS0 Channel

0000 current recopy HB1

0001 current recopy HB2

0010 current recopy HB3

0011 current recopy HB4

0100 current recopy HS1

0101 current recopy HS2

0110 current recopy HS3

0111 not used

1000 Chip temperature

1001 VSUP prescaler

1010 Pin A0

1011 Pin A0CST

1100 not used

1101 not used

1110 not used

1111 not used

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 18. General purpose / Hall-effect Sensor Input (H0)

Current Coded Hallsensor In put

H0 is selected as “2-pin hallsensor input”, if the

corresponding H0MS bit in the H0/L0 Status and Control

GND is monitored by a special sens e circuitry. Setting the

H0EN bit in the H0/L0 Status and Control Register, switches

the output to VSUP and enables the sense circuitry. The

result of the sense operation is given by the H0F flag. The

flag is low if the sensed current is higher than the sense

current threshold IHSCT. In this configuration, the HO pin is

protected (current limitation) against short-circuit to GND.

After switching on the hallport (H0EN = “1”), the hallsensor

needs some time to stabilize the output. In RUN mode, the

software has to take care about waiting for a few µs (40)

before sensing the hallflags.

The hallport output current is sensed. In case of an over-

current (short to GND), the hallport over-current flag

(H0OCF) is set and the current is limited. For proper

operation of the current limitation, an external capacitor

(>100nF) close to the H0 pin is required.

Figure 19. H0 Used as 2-pin Hallsensor Input

Current

Sense

H0EN

VSUP

H0EN

H0F

H0MS H0MS

VDD

10k

H0PD

Current

Sense

H0EN

VSUP

H0F

2 pin hall sensor

GND

>0.1uF

Analog Integrated Circuit Device Data

Freescale Semiconductor 37

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

General Purpose Input

H0 is selected as a general purpose input, if the H0MS bit

in the H0/L0 Status and Control Register (HLSCTL) is

cleared. In this mode, the input is usable as a standard 5V

input. The H0 input has a selectable internal pullup resistor.

The pullup can be switched off with the H0PD bit in the H0/L0

Status and Control Register (HLSCTL). After reset, the

internal pullup is enable d.

Figure 20. H0 Used as 3 Pin Hall-effect Sensor Input

Figure 21. H0 Used to Read in Standard Switches

H0 Interrupt

The interrupt functionality on this pin is only avai lable in

RUN mode. The H0 interrupt flag H0IF is set in run mode by

a state change of the H0 flag (rising or falling edge on the

enabled input). The interrupt function is available if the input

is selected as General Purpose or as 2-pin Hallsensor input.

The interrupt can be masked with the H0IE bit in the interrupt

mask register.

Wake-up input L0

The device provides one wake-up capable input for

reading VSUP or VDD related signals.

3 pin hall sensor

HVDDON

VDD

H0PD

VDD

10k

H0F H0

HVDD

GND

OUT

GND

H0PD

VDD

10k

H0F

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

RUN Mode

The actual input state is reflected in the L0F bit of the H0/

L0 Status and Control register (HLSC T L).

The L0 pin offers an interrupt capability on the rising and

falling edge. The interrupt can be enabled with the L0IE bit in

the Interrupt Mask regist er.

STOP/SLEEP Mode

During STOP and SLEEP mode, the pin can be used to

wake-up the device.

Before entering the STOP or SLEEP mode, the actual

state of the input is stored. If the state is changing during in

the STOP or SLEEP mode, a wake-up is initiated.

H0 / L0 Status and Contro l Register (HLSCTL)

L0F — L0 Flag Bit

This read only flag reflects the state of the L0 input

1 = L0 input high

0 = L0 input low

H0OCF — H0 Over-current Fl ag Bit

This read/write flag is set at over-current condition on H0

during 2-pin hallsensor mode. Clear H0OCF by writing a

logic [1] to H0OCF. Reset clears the H0OCF bit.

1 = over-current condition on H0 pin has occurred

0 = no over-current condition on H0 pin has occurred

H0F — H0 Flag Bit

This read only flag reflects the state of the H0 input

1 = Hallport sensed high / current below threshold

detected

0 = Hallport sensed low / current above thresh old

detected

H0EN — H0 Input 2-pin Hall-effect sensor Enable Bit

This read/write bit enables the 2-pin hall-effect sensor

sense circuitry. Reset clears H0EN bit.

1 = Hallport H0 is switched on and sensed

0 = Hallport H0 disabled

H0PD — Hallport Pullup Disable Bit

This read/write bit disables the H0 Pullu p resistor. Reset

clears H0PD bit.

1 = Hallport pullup resistor on H0 disabled

0 = Hallport pullup resistor on H0 enable d

H0MS — H0 Mode Select

These read/write bits select the mode of the H0 inpu t

Reset clears H0MS bit.

1 = H0 is 2-pin hallsensor input

0 = H0 is general purpose input

Half-bridge Outputs

Outputs HB1:HB4 provide four low-resistive half-bridge

output stages. The half-bridges can be used in H-bridge, high

side or low side configurations.

Reset clears all bits in the H-bridge Output Register

(HBOUT) owing to the fact that all half-bridge outputs are

switched off.

HB1:HB4 output features

• Short-circuit (over-current) protection on high side and

low side MOSFETs

• Current recopy feature (low side MOSFET)

• Over-temperature protection

• Over-voltage and unde r-voltage protection

• Active clamp on low side MOSFET

Bit7 654321Bit0

Read L0F 0 0 H0OCF H0F H0EN H0PD H0MS

Write

Reset 00000000

Analog Integrated Circuit Device Data

Freescale Semiconductor 39

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 22. Half-brid ge Push-Pull Output Driver

Half-bridge Control

Each output MOSFET can be controlled individually. The

general enable of the circuitry is done by setting PSON in the

System Control Register (SYSCTL). The HBx_L and HBx_H

bits form one half-bridge. It is not possible to switch on both

MOSFETs in one half-bridge at the same time. If both bits are

set, the high side MOSFET is in PWM mode.

To avoid both MOSFETs (high side and low side) of one

half-bridge being on at the same ti me, a break-before-make

circuit exists. Switching the high side MOSFET on is inhibited

as long as the potential between gate and VSS is not below a

certain threshold. Switching the low side MOSFET on is

blocked as long as the potential between gate and source of

the high side MOSFET did not fall below a certain threshold.

HALF-BRIDGE OUTPUT REGISTER (HBOU T)

HBx_H, HBx_L — Half-bridge Output Switches

These read/write bits select the output of each half-bridge

output according to Table 8. Reset clears all HBx_H, HBx_L

bits.

High Side Driver

Charge Pump

Over-temperature Protection

Over-current Protection

Low Side Driver

Current Recopy

Current Limitation

Active Clamp

Over-current Protection

Control

On/Off

Status

On/Off

Status

PWM

HBx

VSUP

GND

PWM

Bit7 654321Bit0

Read HB4_

HHB4_

LHB3_

HHB3_

LHB2_

HHB2_

LHB1_

HHB1_

Write

Reset 00000000

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 8. Half-bridge Configuration

Half-bridge PWM mode

The PWM mode is selected by setting both HBxL and

HBxH of one half-bridge to “1”. In this mode, the high side

MOSFET is controlled by the incoming PWM signal on the

PWM pin (see Figure 2, page 2).

If the incoming signal is high, th e high side MOSFET is

switched on.

If the incoming signal is low, the high side MOSFET is

switched off.

With the current recirculation mode control bit CRM in the

Half-bridge Status and Control Register (HBSCTL), the

recirculation behavior in PWM mode can be controlled. If

CRM is set, the corresponding low side MOSFET is switched

on, if the PWM controlled high side MOSFET is off.

Half-bridge Current Recopy

Each low side MOSFET has an additional sense output to

allow a current recopy featu r e. These sense sources are

internally amplified and switched to the Analog Multiplexer.

The factor for the Current Sense amplification can be

selected via the CSA bit in the A0MUCTL register (see

page 33)

CSA = “1”: low resolution selected

CSA = “0”: high resolution selected

Half-bridge Over-temperature Protection

The outputs are protected against over-temperature

conditions. Each power output comprises two different

temperature thresholds.

The first threshold is the high temperature interrupt (HTI).

If the temperature reaches this threshold, the HTIF bit in the

Interrupt Flag Register (IFR) is set, and an interrupt will be

initiated if the HTIE bit in the Interrupt Mask register is set. In

addition, this interrupt can be used to automatically turn off

the power stages. This shutdown can be enabled/disabled by

the HTIS0-1 Bits in the System Control Register (SYSCTL).

The high temperature interrupts flag (HTIF) is cleared (and

the outputs reenabled) by writing a “1” to the HTIF flag in the

Interrupt Flag Register (IFR) or by a reset. Clearing this flag

has no effect as long as a high temperature condition is

present.

If the HTI shutdown is disabled, a second threshold high

temperature reset (HTR) will be used to turn off all power

stages (HB (all Fet’s), HS, HVDD, H0) in order to protect the

device.

Half-Bridge Over-current Protection

The Half-bridges are protected against short to GND,

VSUP, and load shorts. The over-current protection is

implemented on each HB. If an over-current condition on the

high side MOSFET occurs, the high side MOSFET is

automatically switched off. An over-current condition on the

low side MOSFET will automati cally turn off the low side

MOSFET. In both cases, the corresponding HBxOCF flag in

the Half-bridge Status and Control Register (HBSCTL) is set.

The over-current status flag is cleared (and the

corresponding half-bridge MOSFETs reenabled) by writing a

“1” to the HBxOCF in the Half-bridge Status and Control

Half-bridge Over-voltage/Under-voltage Protection

The half-bridge outputs are protected against under-

voltage and over-voltage conditions. This protection is done

by the low and high voltage interrupt circuitry. If one of these

flags (LVIF, HVIF) are set, the outputs are automatically

disabled when the VIS bi t in the System Control Register

(SYSCTL) is cleared.

The over-voltage and under-voltage status flags are

cleared (and the outputs reenabled) by writing a “1” to the

LVIF / HVIF flags in the Interrupt Flag Register (IFR), or by a

reset. Clearing this flag has no effect as long as the high

voltage or low voltage condition is still present.

Half-bridge Status and Control Register (HBSCTL)

CRM — Current Recirculation Mode bit

This read/write bit selects the recirculati o n mode during

PWM. Reset clears the CRM bit.

1 = recirculation via switched on low side MOSFET

0 = recirculation via low side free wheeling diode

HBx_H HBx_L Mode

Low side and high side MOSFET off

High side MOSFET off,

low side MOSFET on

High side MOSFET on,

low side MOSFET off

High side MOSFET in PWM mode

Bit7 6 5 4 3 2 1 Bit0

Read CRM 0 0 0 HB4

OCF HB3

OCF HB2

OCF HB1

OCF

Write

Reset 0 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 41

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

HBxOCF — Half-bridges Over-current Flag Bit

This read/write bit indicates that an over-current condition

on either the LS or the HS FET on HBx has occurred.

Clear HBxOCF and enable half-bridge by writing a logic [1]

to HBxOCF. Writing a logic [0] to HBxOCF has no effect.

Reset clears the HBxOCF bit.

1 = over-current condition on HBx occurred

0 = no over-current condition on HBx

High Side Drivers

The high side outputs are low resistive high side switches,

targeted for driving lamps. The high sides are protected

against over-temperature, over-current, and over-voltage/

under-voltage.

Figure 23. HS Circuitry

HIGH SIDE OPERATING MODES

The high side outputs are enabled if the PSON bit in the

System Control Register (SYSCTL) is set.

Each high side output is permanently switched on, if the

HSxON bit in the High Side Output Register (HSOUT) is set.

PWM control of the output is enabled, if the HSxPWM bit

High Side Output Register (HSOUT) is set. In this operating

mode, the high side MOSFET is on if the input PWM signal

(PWM pin) is high.

The following table shows the behavior of the high side

MOSFETs depending on the HSONx and PWMHSx bits.

VSUP

HSx

HS - Driver

charge pump

over-current protection

inrush current limiter

PWM

Control

on/off

Current

Limit

Status

PSON

HSxON

HSxPWM

PWM

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 9. High Side Configuration Bits

High Side Over-voltage / Under-voltage Protection

The outputs are protected against under /over-voltage

conditions. This protection is done by the low and high

voltage interrupt circuitry. If an over /under-voltage condition

is detected (LVIF / HVIF), and Bit VIS in the High Side Status

The over /under-voltage status flags are cleared (and the

output reenabled), by writing a logic [1] to the LVIF / HVIF

flags in the Interrupt Flag Register, or by reset. Clearing this

flag has no effect as long as a high or low voltage condition

is present.

HIGH SIDE OVER-TEMPERATURE PROTECTION

The outputs are protected against over-temperature

conditions.

Each power output comprises two different temperature

thresholds.

The first threshold is the high temperature interrupt (HTI).

If the temperature reach this threshold, the HTI bit in the

interrupt flag register is set and an interrupt will be generated,

if the HTIE bit in the interrupt mask register is set. In addition,

this interrupt can be used to automatically turn off the power

stages (all high sides, on Half-bridges just the high side

FET’s). This shutdown can be enabled/disabled by the HTIS0

bit.The high temperature interrupts flag (HTIE) is cleared (and

the outputs reenabled) by writing a logic [1] to the HTIF flag

in the Interrupt Status Register, or by reset. Clearing this flag

has no effect as long as a high temperature condition is

present.

If the HTIS shutdown is disabled, a second threshold

(HTR) will be used to turn off all power stages (HB (all Fet’s),

HS, HVDD, H0) in order to protect the device.

High Side Over-current Protect ion

The HS outputs are protected against over-current. When

the over-current limit is reached, the output will be

automatically switched off and the over-current flag is se t.

Due to the high inrush current of bulbs, a special feature

was implemented to avoid a over-current shutdown during

this inrush current. If a PWM frequency will be supplied to the

PWM input during the switch on of a bulb, the inrush current

will be limited to the over-current shutdown limit. This means,

if the current reaches the over-current shutdown, the high

side will be switched off, but each rising edge on the PWM

input will enable the driver again. The duty cycle supplied by

the MCU has no influence on the switch-on time of the high

side driver.

In order to distinguish between a shutdown due to an

inrush current or a real shutdown, the software checks if the

over-current status flag (HSxOCF) in the High Side Status

HSxPWM HSxON Mode

High side MOSFET off

High side MOSFET on if over-current,

the over-current flag (HSxOCF) is set,

and the High side MOSFET is turned off

10In this mode, the PWM duty cycle is

either controlled by the PWM input

signal, or if the over-current shutdown

value is reached by the part itself.

Without reaching the over-current

shutdown, the high side driver is directly

driven from the PWM input signal. If the

Input signal is high, the output is on. If

low, the output is off (PWM control).

If the current reaches the over-current

shutdown value, the high side will be

automatically turned off. With the next

rising edge of the PWM input signal, the

output will turn on again (current

limitation). The HSxOCF bit will be set.

The software has to distinguish between

an inrush current and a real short on the

output.

High side MOSFET is switched on and

the inrush current limitation is enabled.

This means the high side will start

automatically with a current limitation

around the over-current shutdown

threshold. (PWM signal must be applied,

see Figure 24)

If the high side enters current limitation,

the HSxOCF bit is set, but the output is

not disabled. The software needs to

distinguish between an inrush current

and a real short on the output.

Analog Integrated Circuit Device Data

Freescale Semiconductor 43

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 24. Inrush Current Limitation on HS Outputs

High Side Current Recopy

Each High Side has an additional sense output to allow a

current recopy feature. This sense source is internally

connected to a shunt resistor. The drop voltage is amplified

and switched to the Analog Multiplexer.

Switchable HVDD Outputs

The HVDD pin is a switchable 5V output pin. It can be used

for driving external circuitry, which requires a 5V voltage. The

output is enabled with the PSON bit in the System Control

in the High Side Out register. Low or high voltage conditions

(LVIF / HVIF) will have no influence on this circuitry.

HVDD Over-temperature Protection

The output is protected against over-temperature

conditions.

HVDD Over-current Protection

The HVDD output is protected against over-current. In

case the current reaches the over-current limit, the output

current will be limited, and the HVDDOCF over-current flag in

the System Status register is set.

HIGH SIDE OUT REGISTER (HSOUT)

HVDD-ON — HVDD On Bit

This read/write bit enables the HVDD output.

Reset clears HVDDON bit.

1 = HVDD enabled

0 = HVDD disabled

HSxON — High Side on/off Bits

These read/write bits turn on the High Side Fet’s

permanently. Reset clears the HSxON bits.

1 = High Side x is turned on

0 = High Side x is turned off

HS Current HS Over-current Shutdown Threshold

PW M Pin

Bit7 6 5 4 3 2 1 Bit0

Read HVDD

0HS3P

WM HS2P

WM HS1P

WM HS3O

NHS2O

NHS1O

Write

Reset 0 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data

44 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

HSxPWM — High Side PWM on/off Bits

These read/write bits enable the PWM control of the High

Side Fet’s. Reset clears the HSxPWM bits.

1 = High Side x is controlled by PWM input signal

0 = High Side x is not controlled by PWM input sign al

High Side Status Register (HSSTAT)

HSxOCF — High Side Over-current Flag Bit

This read/write flag is set by an over-current condition at

the high side drivers x. Clear HSxOCF and enable the HS

Driver by writing a logic [1] to HSxOCF. Writing a logic [0] to

HSxOCF has no effect. Reset clears the HSxOCF bit.

1 = over-current condition on high side drivers has

occurred

0 = no over-current condition on high side drivers has

occurred

HVDDOCF — HVDD Output Over-current Flag Bit

This read/write flag is set by an over-current condition at

HVDD pin. Clear HVDDOCF and enable the output by writing

a logic [1] to the HVDDOCF Flag. Writing a logic [0] to

HVDDOCF has no effect. Reset clears the HVDDOCF bit.

1 = over-current condition on VDD output has occurred

0 = no over-current condition on VDD output has

occurred

System Control Register (SYSCTL)

PSON — Power Stages On Bit

This read/write bit enables the power stages (half-bridges,

high sides, LIN transmitter, A0 Current Sources and HVDD

output). Reset clears the PSON bit.

1 = power stages enabled

0 = power stages disabled

STOP — Change to STOP Mode Bit

This write bit instructs the chip to enter Stop mode (See

Operational Modes on page 26). Reset or CPU interrupt

requests clear the STOP bit.

1 = go to Stop mode

0 = not in stop mode

In order to safely enter Stop mode, all other bits (Bit7-Bit2)

have to be “0”. Otherwise the STOP command will not

execute.

SLEEP — Change to SLEEP Mode Bit

This write bit instructs the chip to enter Sleep mode (See

Operational Modes on page 26). Reset or CPU interrupt

requests clear the SLEEP bit.

1 = go to Sleep mode

0 = not in sleep mode

In order to safely enter Sleep mode all other bits (Bit7-Bit2)

have to be “0”. Otherwise the SLEEP command will not

execute.

HTIS0-1 — High Temperat ure In terrupt Shutdown Bits

This read/write bit selects the power stage behavio r at

High Temperature Interru pt (HTI). Reset clears the HTIS0-1

bits.

The HTIS0 bit selects the behavior of the high side HS1:3

and the high side FET of the half-bridges HB1:4.

1 = automatic HTI shutdown of the high side drivers

disabled

0 = automatic HTI shutdown of the high side drivers

enabled

The HTIS1 bit selects the behavior of the low side drivers

of the half-bridges HB1:4.

1 = automatic HTI shutdown of the low side drivers

disabled

0 = automatic HTI shutdown of the low side drivers

enabled

The user has to take care to protect the device against

thermal destruction!

VIS — Over/Under-voltage Interrupt Shutdown

This read/write bit selects the power stage behavior at LVI/

HVI. Reset clears the VIS bit.

1 = automatic LVI/HVI shutdown disabled

0 = automatic LVI/HVI shutdown enabled

SRS0-1 — LIN Slew Rate Select Bits

These read/write bits ena ble the user to select the

appropriate LIN slew rate for different Baudrate

configurations. Reset clears the SRS1:0 bits.

Bit7 6 5 4 3 2 1 Bit0

Read HVDD

OCF

0 0 0 0 HS3O

CF HS2O

CF HS1O

Write

Reset 00000000

Bit7 6 5 4 3 2 1 Bit0

Read PSON 00

HTIS1 HTIS0 VIS SRS1 SRS0

Write STOP SLEEP

Reset 0 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 45

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 10. LIN Slew Rate Selection Bi ts

The high speed slew rates are used, for example, for

programming via the LIN, and are not intended for use in the

application.

System Status Register (SYSSTAT)

LINCL — LIN Current Limitation Bit

This read only bit is set if the LIN transmitter operates in

current limitation region. Due to excessive power dissipation

in the transmitter, the driver will be automatically turned off

after a certain time.

1 = transmitter operating in current limitation region

0 = transmitter not operating in current limitatio n region

HTIF— Over-temperature Sta t us Bit

This read only bit is a copy of the HTIF bit in the Interrupt

Flag register

1 = over-temperature condition

0 = no over-temperature co ndition

VF — Voltage Failure Bit

This read only bit indicates that the supply voltage was out

of the allowed range. The bit is set if either the LVIF or the

HVIF in the Interrupt Flag register i s set .

1 = low/high voltage condition detected

0 = no voltage failure condition detected

Figure 25. VF Flag Generation

H0F — H0 Failure Bit

This read only bit is a copy of the H0OCF bit in the H0/L0

Status and Control Register (HLSCTL)

1 = over-current detected on H0

0 = no over-current on H0

HVDDF— HVDD Failure Bit

This read only bit is a copy of the HVDDOCF bit in the High

Side Status register

1 = HVDD pin fail

0 = HVDD normal operating

HSF— HS1:3 Failure Bit

This read only bit is set if a fail condition on one of the high

side outputs is present

1 = HS1:3 pin fail

0 = HS1:3 normal operating

Figure 26. HSF Flag Generation

HBF— HB1:4 Failure Bit

This read only bit is set if a fail condition on one of the half-

bridge outputs is present.

1 = HB1:4 pin over-current fail

0 = HB1:4 normal operating

Figure 27. HBF Flag Generation

WINDOW WATCHDOG

The window watchdog is used to supervise the device, and

to recover from, e.g. code runaways, or similar conditions.

The use of a window watchdog adds additional safety, as

the watchdog clear has not only to occur, but be done at a

certain time frame / window.

Normal mode

The window watchdog function is only available in Normal

mode, and is halted in Stop and Sleep mode. On setting the

WDRE bit, the watchdog functionality is activated. Once this

function is enabled, it is not possible to disable it via software.

Reset clears the WDRE bit.

To prevent a Watchdog reset, the Watchdog timer has to

be cleared in the Window Open frame. This is done by writing

a logic “1” to the WDRST bit in the Watchdog Control register

(WDCTL). The actual reset of the watchdog counter occurs at

the end of the corresponding SPI transmission, with the rising

edge of the SS signal.

SRS1 SRS0 Slew rate

0 0 Initial Slew Rate (20kBaud)

0 1 High Speed II (8x)

1 0 Slow Slew Rate (10kBaud)

1 1 High Speed I (4x)

Bit7 6 5 4 3 2 1 Bit0

Read LINC

LHTIF VF H0F HVD

DF HSF HBF 0

Write

Reset 0 0 0 0 0 0 0 0

LVIF

HVIF VF

HS3OCF

HS2OCF

HS1OCF

HSF

HB1OCF

HB2OCF

HB3OCF

HB4OCF

HBF

Analog Integrated Circuit Device Data

46 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

If the watchdog is enabled, it will generate a system reset,

if the timer has reached its end value, or if a watchdog reset

(WDRST) has occurred in the closed window.

The watchdog period can be selected with 2 bits in the

WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.

Figure 28. Window Watc hd og Period

Stop mode

Operations of the watchdog function is halted in stop mode

(counter/oscillator stopped). After wake-up, the watchdog

timer is automatically cleare d, in order to give the MCU the

full time to reset the watchdog.

Sleep mode

Operations of the watchdog function is halted in sleep

mode. Because the main voltage regulator asserts an LVR

reset, the Watchdog functionality is disabled, and the WDRE

bit is cleared as soon as sleep mode is entered. To re-enable

this function bit WDRE has to be set after wake-up.

Watchdog Control Register (WDCTL)

WDRE - Watchdog Reset Enable Bit

This read/write (write once) bit activates the watchdog.

The WDRE can only be set and can not be cleared by

software. Reset clears th e WDR E bi t.

1 = Watchdog enabled

0 = Watchdog disabled

WDP1:0 - Watchdog Period Select Bits

This read/write bit select the clock rate of the Watchdog.

Reset clears the WDP1:0 bits.

Table 11. Watchdog Period Selection Bits

WDRST - Watchdog Reset Bit

This write only bit resets the Watchdog. Write a logic [1] to

reset the watchdog timer.

1 = Reset WD and restart timer

0 = no effect

Voltage Regulator

The 908E621 contains a low power, low drop voltage

regulator, to provide internal power and external po wer for

the MCU. The on-chip regulator consist of two elements, the

main regulator and the low voltage reset circuit.

The VDD regulator accepts an un regulated input supply

and provides a regulated VDD supply to all digital sections of

the device. The output of the regulator is also connected to

the VDD pin to provide the 5.0V to the microc ontroller.

Run mode

During RUN mode the main voltage regulator is on. It will

provide a regulated supply to all digital sections.

STOP mode

During STOP mode, the Stop mode regulator will take care

of suppling a regulated output voltage. The Stop mode

regulator has a limited output current capability.

SLEEP mode

In Sleep mode, the main voltage regulator external, V DD,

is turned off and the LVR circuitry will force the RST_A pin

low.

Bit7 6 5 4 3 2 1 Bit0

Read WDRE WDP1 WDP000000

Write WDRST

Reset 0 0 0 0 0 0 0 0

Window closed

no watch dog clear allowed Window open

for watch dog clear

WD timing x 50% WD timing x 50%

WD period ( timing selected by Bits WDP1:0)

WDP1 WDP0 Mode

0 0 80ms window watchdog period

0 1 40ms window watchdog period

1 0 20ms window watchdog period

1 1 10ms window watchdog period

Analog Integrated Circuit Device Data

Freescale Semiconductor 47

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

908E621 SERIAL PHERIPHERAL INTERFACE (SPI)

The Serial Peripheral Interface (SPI) creates the

communication link between the MCU and the analog die.

The interface consists of four pins

• MOSI - Master Out Slave In (internal pull down)

• MISO - Master In Slave Out

• SPSCK - Serial Clock (internal pulldown)

•SS - Slave Select (inter na l pu llup)

A complete data transfer via the SPI, consists of 2 bytes.

The master sends address and data, the slave returns

system status and the data of the selected address.

Figure 29. SPI Protocol

• During the inactive phase of SS, the new data transfer

will be prepared. The falling edge on the SS line,

indicates the start of a new data transfer (framing), and

puts MISO in the low impedance mode. The first valid

data are moved to MISO with the rising edge of SPSCK.

• The MOSI, MISO will change data on a rising edge of

SPSCK.

• The MOSI, MISO will be sampled on a falling edge of

SPSCK.

• The data transfer is only valid, if exactly 16 sample clock

edges are present in the active phase of SS.

• After a write operation, the transmitted data will be

latched into the register by the rising edge of SS.

• Register read data is internally latched into the SPI at

the time when the parity bit is transferred

•SS

high will force MISO to high impedance

Master Address Byte

A4 - A0

Includes the address of the desired register.

R/W

Includes the information, if it is a read or a write operation.

•If R/W = 1 (read operation), the second byte of master

contains no valid information, and the slave just

transmits back regist er data.

•If R/W

= 0 (write operation), the master sends data to be

written in the second byte, the slave sends concurrently

contents of selected register prior to write operati on,

and the write data is latched in the SMARTMOS

registers on rising edge of SS.

Parity P

Completes the total number of 1 bits of (R/W,A[4-0]) to an

even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.

The parity bit is only evaluated during a write operations

and ignored for read operations.

Bit X

Not used

Master Data Byte

This byte includes data to be written, or no valid data,

during a read operation.

S7 S6 S5 S4 S3 S2 S1 S0

R/W A4 A3 A2 A1 A0 P X D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

System Status Register

Read/Write, Address, Parity Data (Register write)

Data (Register read)

Rising edge of SPSCK

Change MISO/MOSI

Output

Falling edge of SPSCK

Sample MISO/MOSI

Input

Slave lat ch

data

MOSI

MISO

SPSCK

Analog Integrated Circuit Device Data

48 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Slave Status Byte

This byte always includes the contents of the system

status register ($0C), independent if it is a write or read

operation, or which register was selecte d.

Slave Data Byte

This byte includes the contents of selected register, during

a write operation, it includes the register conte nt prior to the

write operation.

Analog Integrated Circuit Device Data

Freescale Semiconductor 49

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI REGISTER OVERVIEW

TABLE 12 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER.

Table 12. SPI Register Overview

Addr Register Name R/W Bit

76543210

$00 System Control

(SYSCTL) RPSON 00

HTIS1 HTIS0 VIS SRS1 SRS0

WSTOP SLEEP

$01 Half-bridge Output

(HBOUT) RHB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L

$02 High Side Output

(HSOUT) RHVDDON 0HS3PWM HS2PWM HS1PWM HS3ON HS2ON HS1ON

$03 Half-bridge Status and

Control (HBSCTL) RCRM 000

HB4OCF HB3OCF HB2OCF HB1OCF

$04 High Side Status and

Control (HSSCTL) RHVDDOCF 0000

HS3OCF HS2OCF HS1OCF

$05 Reserved Rreserved

$06 Reserved Rreserved

$07 H0/L0 Status and

Control (HLSCTL) RL0F 0 0 H0OCF H0F H0EN H0PD H0MS

$08 A0 and Multiplexer

Control (A0MUCTL) RCSON CSSEL1 CSSEL0 CSA SS3 SS2 SS1 SS0

$09 Interrupt Mask

(IMR) RL0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE

$0A Interrupt Flag

(IFR) RL0IF H0IF LINIF 0 HTIF LVIF HVIF PSFIF

$0B Watchdog Control

(WDCTL) RWDRE WDP1 WDP0 00000

WWDRST

$0C System Status

(SYSSTAT) RLINCL HTIF VF H0F HVDDF HSF HBF 0

$0D Reset Status

(RSR) RPOR PINR WDR HTR LVR 0LINWF L0WF

$0E System Test

(SYSTEST) Rreserved

$0F System Trim 1

(SYSTRIM1) RHVDDT1 HVDDT0 reserved reserved itrim3 itrim2 itrim1 itrim0

$10 System Trim 2

(SYSTRIM2) R00000000

WCRHBHC1 CRHBHC0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0

$11 System Trim 3

(SYSTRIM3)

R00000000

WCRHBHC3 CRHBHC2 CRHS5 CRHS4 CRHS3 CRHS2 CRHS1 CRHS0

Analog Integrated Circuit Device Data

50 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

FACTORY TRIMMING AND CALIBRATION

To enhance the ease-of-use of the 908E621, various

parameters (e.g. ICG trim value) are stored in the flash

memory of the device. The following flash memory locations

are reserved for this purpose and might have a value different

from the “empty” ($FF) state:

• $FD80:$FDDF Trim and Calibration Values

• $FFFE:$FFFF Reset Vector

In the event the application uses these parameters, one

has to take care not to erase or override these values. If these

parameters are not used, these flash locations can be erased

and otherwise used.

Trim Values

The usage of the trim values located in the flash memory

are explained through the following:

Internal Clock Generator (ICG) Trim Value

The internal clock generator (ICG) module is used to

create a stable clock source for the microcontroller without

using any external components. The untrimmed frequency of

the low frequency base clock (IBASE), will vary as much as

±25 percent due to process, temperature, and voltage

dependencies. To compensate these dependencies, an ICG

trim value is located at address $FDC2. After trimming, the

ICG has a typ. range of ±2% (±3% ma x.), at no minal

conditions (filtered (100nF), stabilized (4,7μF) VDD = 5V,

TAmbient~25°C), and will vary over temperature and voltage

(VDD) as indicated in the 68HC908EY16 datasheet.

To trim the ICG, this value has to be copied to the ICG Trim

Important: T he value must be copied after every reset.

Watchdog Period Range Value (AWD Trim)

The window watchdog supervise s device recovery (e.g.

from code runaways).

The application software has to clear the watchdog within

the open window. Due to the high variation of the watchdog

period, and therefore the reduced wid th of the watchdog

window, a value is stored at address $FDCF. This value

classifies the watchdog period into 3 ranges (Range 0, 1, 2).

This allows the application software to select one of three

time intervals to clear the watchdog, based on the sto red

value. The classification is done, so that the applica tion

software can have up to ±19% variations of the optimal clear

interval (e.g. caused by ICG variation).

Effective Open Window

Having a variation in the watchdog period in conjunction

with a 50% open window, results in an effective open window,

which can be calculated by:

latest window open time: t_open = t_wd max / 2

earliest window closed time: t_closed = t_wd min

Optimal Clear Interval

The optimal clear interval, meaning the clear interval with

the biggest possible variation to latest window open time, and

to the earliest window closed time, can be calculated with the

following formula:

t_opt = t_open + (t_open+t_closed) / 2

See Table 13 to select the optimal clear interval for the

watchdog based on the Window No. and chosen perio d.

Table 13. Window Clear Interval

Window Range Period Select bits Watchdog Period t_wd Effective Open Window Optimal Clear Interval

$FDCF WDP1:0 min. max. Unit t_open t_closed Unit t_opt Unit max.

variation

00 68 92

46 68

ms ±19.3%

01 34 46 23 34 28.5

10 17 23 11.5 17 14.25

11 8.5 11.5 5.75 8.5 7.125

00 92 124

62 92

ms ±19.5%

01 46 62 31 46 38.5

10 23 31 15.5 23 19.25

11 11.5 15.5 7.75 11.5 9.625

00 52 68

34 52

ms ±20.9%

01 26 34 17 26 21.5

10 13 17 8.5 13 10.75

11 6.5 8.5 4.25 6.5 5.375

Analog Integrated Circuit Device Data

Freescale Semiconductor 51

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Analog Die System Trim Values

For improved application performance, and to ensure the

outlined datasheet values, the analog die needs to be

trimmed. For this purpose, 3 trim values are stored in the

Flash memory at addresses $FDC4 - $FDC6. These values

have to be copied into the analog die SPI registers:

• copy $FDC4 into SYSTRIM1 register $0F

• copy $FDC5 into SYSTRIM2 register $10

• copy $FDC6 into SYSTRIM3 register $11

Note: These values must be copied to the respec tive SPI

System Test Register (SYSTEST)

The System Test Register is reserved for production

testing and is not allowed to be written to.

System Trim Register 1 (SYSTRIM1)

HVDDT1:0 - HVDD Over-current Shutdown Delay Bits

These read/write bits allow changes to the filter time (for

capacitive load) for HVDD over-current detection. Reset

clears the HVDDT1:0 bits and sets the delay to the maximum

value.

Table 14. HVDD Over-current Shutdown Selection Bits

ITRIM3:0 - IRef Trim Bits

These write only bits are for trimming the internal current

references IRef (also A0, A0CST). The provided trim values

have to be copied into these bits after every reset. Reset

clears the ITRIM3:0 bits.

Table 15. IRef Trim Bits

System Trim Register 2 (SYSTRIM2)

CRHBHC1:0 - Current Recopy HB1:2 Trim Bits

These write only bits are for trimming the current recopy of

the half-bridge HB1 and HB2 (CSA=0). The provided trim

values have to be copied into these bits after every reset.

Reset clears the CRHBHC1:0 bits.

Table 16. Current Recopy Trim for HB1:2 (CSA=0)

Bit7 6 5 4 3 2 1 Bit0

Read reserved reserved reserved reserved reserved reserved reserved reserved

Write

Reset 0 0 0 0 0 0 0 0

Note: do not write to the reserved bits

Bit7 654321Bit0

Read HVDDT1 HVDDT0 0

reserved 0

reserved ITRIM3 ITRIM2 ITRIM1 ITRIM0

Write

Reset 00000000

Note: do not change (set) the reserved bits

HVDDT1 HVDDT0 Typical Delay

0 0 950μs

0 1 536μs

1 0 234μs

1178

μs

itrim3 itrim2 itrim2 itrim0 Adjustment

0000 0

0001 2%

0010 4%

0011 8%

0100 12%

0101 -2%

0110 -4%

0111 -8%

1000 -12%

Bit7 6 5 4 3 2 1 Bit0

Write CRHBHC1 CRHBHC0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0

Reset 0 0 0 0 0 0 0 0

CRHBHC1 CRHBHC0 Adjustment

00 0

01 -10%

10 5%

1 1 10%

Analog Integrated Circuit Device Data

52 Freescale Semiconductor

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

CRHB5:3 - Current Recopy HB3:4 Trim Bits

These write only bits are for trimming the current recopy of

the half-bridge HB3 and HB4 (CSA=1). The provided trim

values have to be copied into these bits after every reset.

Reset clears the CRHB5:3 bits.

Table 17. Current Rec opy Trim for HB3 :4 (CSA=1)

CRHB2:0 - Current Recopy HB1:2 Trim Bits

These write only bits are for trimming the current recopy of

the half-bridge HB1 and HB2 (CSA=1). The provided trim

values have to be copied into these bits after every reset.

Reset clears the CRHB2:0 bits.

Table 18. Current Rec opy Trim for HB1 :2 (CSA=1)

System Trim Register 3 (SYSTRIM3)

CRHBHC3:2 - Current Recopy HB3:4 Trim Bits

These write only bits are for trimming the current recopy of

the half-bridge HB3 and HB4 (CSA=0). The provided trim

values have to be copied into these bits after every reset.

Reset clears the CRHBHC3:2 bits.

Current Recopy Trim for HB3:4 (CSA=0)

CRHS5:3 - Current Recopy HS2:3 Trim Bits

These write only bits are for trimming the current recopy of

the high side HS2 and HS3. The provided trim values have to

be copied into these bits after every reset. Reset clears the

CRHS5:3 bits.

Table 19. Current Recopy Trim for HS2:3

CRHB5 CRHB4 CRHB3 Adjustment

000 0

001 -5%

010 -10%

011 -15%

1 0 0 reserved

101 5%

110 10%

111 15%

CRHB2 CRHB1 CRHB0 Adjustment

000 0

001 -5%

010 -10%

011 -15%

1 0 0 reserved

101 5%

110 10%

111 15%

Bit7 654321Bit0

Write CRHBH

C3 CRHBH

C2 CRHS5 CRHS4 CRHS3 CRHS2 CRHS1 CRHS0

Reset 00000000

CRHBHC3 CRHBHC2 Adjustment

00 0

01 -10%

10 5%

1 1 10%

CRHS5 CRHS4 CRHS3 Adjustment

000 0

001 -5%

0 1 0 -10%

0 1 1 -15%

1 0 0 reserved

101 5%

110 10%

111 15%

Analog Integrated Circuit Device Data

Freescale Semiconductor 53

908E621

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

CRHS2:0 - Current Recopy HS1 Trim Bits

These write only bits are for trimming the current recopy of

the high side HS1. The provided Trim values have to be

copied into these bits after every reset. Reset clears the

CRHS2:0 bits.

Current Recopy Trim for HS1

CRHS2 CRHS1 CRHS0 Adjustment

000 0

001 -5%

0 1 0 -10%

0 1 1 -15%

1 0 0 reserved

101 5%

110 10%

111 15%

Analog Integrated Circuit Device Data

54 Freescale Semiconductor

908E621

TYPICAL APPLICATIONS

DEVELOPMENT SUPPORT

As the 908E621 has the MC68HC908EY16 MCU

embedded, typically all th e development tools available for

the MCU also apply for this device. However, due to the

additional analog die circuitry and the nominal +12V supply

voltage, some additional items have to be considered:

• nominal 12V rather than the 5V or 3V supply

• high voltage VTST might be applied not only to IRQ pin,

but IRQ_A pin

• MCU monitoring (Normal request timeout) has to be

disabled

For a detailed information on the MCU related

development support, see the MC68HC908EY16 datasheet -

section development support.

The programming is principally possible at two stages in

the manufacturing process, first on chip level, before the IC is

soldered onto a pcb board, and second after the IC is

soldered onto the pcb board.

Chip level programming

At the Chip level, the easiest way is to only power the MCU

with +5V (see Figure 30), and not to provide the analog chip

with VSUP. In this setup, all the anal og pins should be left

open (e.g. VSUP[1:8]), and interconnections between the

MCU and analog die have to be separated (e.g. IRQ - IRQ_A).

This mode is well described in the MC68HC908EY16

datasheet, section development support.

Figure 30. Normal Monitor Mode Circuit (MCU only)

Of course it is also possible to supply the whole system

with VSUP instead (12V) as described in Figure 31, page 55.PCB level programming

If the IC is soldered onto the pcb board, it is typicall y not

possible to separately power the MCU with +5V. The whole

system has to be powered up providing VSUP (see

Figure 31).

MM908E621

RST_A

RST

IRQ_A

IRQ

VSUP[1:8]

GND[1:4]

PTC4/OSC1

PTB3/AD3

PTB4/AD4

PTA0/KBD0 PTA1/KBD1

TESTMODE

MAX232

10k

RS232

DB-9

C1+

C1-

C2+

C2-

VCC

GND

V+

V- 6

1µF +

+1µF

1µF

+1µF

74HC125

9.8304MHz CLOCK

+5V

DATA

CLK

+5V

10k

VTST

T2OUT

R2IN

T2IN

R2OUT

VSSA/VREFL

VDDA/VREFH

EVDD

VDD

EVSS

VSS

4.7µF100nF

+5V

Analog Integrated Circuit Device Data

Freescale Semiconductor 55

908E621

TYPICAL APPLICATIONS

Figure 31. Normal Monitor Mode Circuit

Table 20 summarizes the possible configurations and the

necessary setups.

EMC/EMI RECOMMENDATIONS

This paragraph gives some device specific

recommendations to improve EMC/EMI performance.

Further generic design recommendation s can be found on

the Freescale web site www.freescale.com.

VSUP Pins (VSUP[1:8])

It is recommended to place a high quality ceramic

decoupling capacitor close to the VSUP pins to improve

EMC/EMI behavior.

MM908E621

RST_A

RST

IRQ_A

IRQ VSSA/VREFL

VDDA/VREFH

EVDD

VDD

EVSS

VSS

VSUP[1:8]

GND[1:4]

4.7µF100nF

PTC4/OSC1

PTB3/AD3

PTB4/AD4

PTA0/KBD0 PTA1/KBD1

TESTMODE

MAX232

10k

RS232

DB-9

C1+

C1-

C2+

C2-

VCC

GND

V+

V- 6

1µF +

+1µF

1µF

+1µF

74HC125

9.8304MHz CLOCK

VDD

DATA

CLK

VDD

10k

VDD

VTST

VSUP

47µF +100nF

T2OUT

R2IN

T2IN

R2OUT

Table 20. Monitor Mode Signal Requir ements and Options

Mode IRQ RST TESTMODE Reset

Vector

Serial

Communication Mode

Selection ICG COP Normal

Request

Time-out

Communication Speed

PTA0 PTA1 PTB3 PTB4 External

Clock Bus

Frequency Baud

Rate

Normal

Monitor VTST VDD 1 X 1 0 0 1 OFF disabled disabled 9.8304

MHz 2.4576

MHz 9600

Forced

Monitor

VDD VDD 1$FFFF

(blank) 10XX

OFF disabled disabled 9.8304

MHz 2.4576

MHz 9600

GND ON disabled disabled — Nominal

1.6MHz Nominal

6300

User VDD VDD 0not $FFFF

(not blank) X X X X ON enabled enabled — Nominal

1.6MHz Nominal

6300

Notes

33. PTA0 must have a pullup resistor to VDD in monitor mode

34. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1

35. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256

36. X = don’t care

37. VTST is a high voltage VDD +3.5V ≤ VTST ≤ VDD +4.5V

Analog Integrated Circuit Device Data

56 Freescale Semiconductor

908E621

TYPICAL APPLICATIONS

LIN Pin

For DPI (Direct Power Injection) and ESD (Electrostatic

Discharge), it is recommended to place a high quality ceramic

decoupling capacitor near the LIN pin. An additional varistor

will further increase the immunity against ESD. A ferrite in the

LIN line will suppress some of the noise induced.

Voltage Regulator oUtput Pins (VDD and VSS)

Use a high quality ceramic decoupl ing capacitor to

stabilize the regulated voltage.

MCU Digital Supply Pins (EVDD and EVSS)

Fast signal transitions on MCU pins place high, short

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU. It is recommended that a high quality

ceramic decoupling capacitor be placed between these pins.

MCU aNalog Supply Pins (VREFH/VDDA and VREFL/

VSSA)

To avoid noise on the analog supply pins, it is important to

take special care on the layout. The MCU digital and analog

supplies should be tied to the same potential via separate

traces, and connected to the voltage regulator output.

Figure 32 and Figure 33 show the recommendations on

schematics and layout level, and Table 21 indicates

recommended external components an d layout

considerations.

Figure 32. EMC/EMI recommendations

MM908E621

EVDD

VDD

EVSS

VSS

VSUP[1:8]

GND[1:4]

VSUP +

VDDA/VREFH

VSSA/VREFL

LINLIN

C1 C2

C3 C4

Analog Integrated Circuit Device Data

Freescale Semiconductor 57

908E621

TYPICAL APPLICATIONS

Figure 33. PCB Layo ut Recommendations

908E621

LIN

VBAT

GND3 GND4

VSUP3 VSUP4

VSUP5

VSUP6

GND

EVDD

EVSS

VDDA/VREFH

VSSA/VREFL

VDD

GND1

VSS

VSUP1

LIN

GND2

VSUP2

VSUP7

VSUP8

Table 21. Component Value Recommendation

Component Recommended Value(1) Comments / Signal routing

D1 reverse battery protection

C1 Bulk Capacitor

C2 100nF, SMD Ceramic, Low ESR Close to VSUP pins with good ground return

C3 100nF, SMD Ceramic, Low ESR Close (<3mm) to digital supply pins (EVDD, EVSS) with good ground

return.

The positive analog (VREFH/ VDDA) and the digital (EVDD) supply

should be connected right at the C3.

C4 4,7μF, SMD Ceramic, Low ESR Bulk Capacitor

C5 180pF, SMD Ceramic, Low ESR Close (<5mm) to LIN pin.

Total Capacitance on LIN has to be below 220pF.

(Ctotal = CLIN-Pin + C5 + CVaristor ~ 10pF + 180pF + 15pF)

V1(2) Varistor Type TDK AVR-M1608C270MBAAB Optional (close to LIN connector)

L1(2) SMD Ferrite Bead Type TDK MMZ2012Y202B Optional, (close to LIN connector)

Notes

1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings

or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their

application.

2. Components are recommended to improve EMC and ESD performance.

Analog Integrated Circuit Device Data

58 Freescale Semiconductor

908E621

PACKAGE DIMENSIONS

Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A

drawing number: 98ASA10712 D.

DWB SUFFIX

54-PIN SOICW-EP

98ASA10712D

ISSUE 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 59

908E621

PACKAGE DIMENSIONS

DWB SUFFIX

54-PIN SOICW-EP

98ASA10712D

ISSUE 0

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

908E621

PACKAGE DIMENSIONS

DWB SUFFIX

54-PIN SOICW-EP

98ASA10712D

ISSUE 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 61

908E621

ADDITIONAL INFORMATION

THERMAL ADDENDUM (REV 1.0)

ADDITIONAL INFORMATION

THERMAL ADDENDUM (REV 1.0)

INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER

WITH EMBEDDED MCU AND LIN FOR MIRROR

Introduction

This thermal addendum is provided as a supplement to the MM908E621

technical data sheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, applicatio n and packaging information is provided in the data sheet.

Package and Therma l Cons id era t io ns

This MM908E621 is a dual die package. There are two heat sources in the

package independently heati ng with P1 and P2. This results in two junction

temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.

For m, n=1, R

θJA11 is the thermal resistance from Junction 1 to the reference

temperature while only heat source 1 is heating with P1.

For m=1, n=2, R

θJA12 is the thermal resistance from Junction 1 to the

reference temperature while heat source 2 is heating with P2. This applies to

RθJ21 and RθJ22, respectively.

The stated values are solely for a thermal performance compari s on of one

package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a

package in an application-specific environment. Stated values were obtained by measurement and simulation according to the

standards listed below.

54-PIN

SOICW-EP

908E621

DWB SUFFIX

98ARL105910

54-PIN SOICW-EP

Note For package dimensions, refer to the

908E621 device datasheet.

TJ1

TJ2 =RθJA11

RθJA21

RθJA12

RθJA22 .P1

Standards

Figure 34. Thermal Land Pattern for Direct Thermal

Attachment Per JEDEC JESD51-5

Table 22. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip [°C/W]

m=1,

n=1 m=1, n=2

m=2, n=1 m=2,

n=2

RθJAmn (1)(2) 23 20 24

RθJBmn (2)(3) 9.0 6.0 10

RθJAmn (1)(4) 52 47 52

RθJCmn (5) 1.0 0 2.0

Notes:

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

1.0

0.2

Soldermast

openings

Thermal vias

connected to t

buried plane

54 Terminal SOIC-EP

0.65 mm Pitch

17.9 mm x 7.5 mm Body

10.3 mm x 5.1 mm Exposed Pad

* All measurements

are in millimeters

Analog Integrated Circuit Device Data

62 Freescale Semiconductor

908E621

ADDITIONAL INFORMATION

THERMAL ADDENDUM (REV 1.0)

Figure 35. Thermal Test Board

Device on Thermal Test Board

RθJA is the thermal resistance between die junction and

ambient air.

RθJSmn is the thermal resistance between die junction and

the reference location on the board surface near a center

lead of the package. This device is a dual die package. Index

m indicates the die that is heate d. Index n refers to the

number of the die where the junction temp erature is sensed.

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

VDDA/VREFH

EVDD

EVSS

VSSA/VREFL

(PTE1/RXD <- RXD)

VSS

VDD

HVDD

HS3

VSUP8

HS2

VSUP7

HS1b

HS1a

VSUP6

VSUP5

GND4

HB1

VSUP4

FLSVPP

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

RST

(PTD0/TACH0/BEMF -> PWM)

PTD1/TACH1

RST_A

IRQ_A

LIN

A0CST

GND1

HB4

VSUP1

GND2

HB3

VSUP2

TESTMODE

GND3

HB2

VSUP3

Exposed

Pad

908E621 Pin Connections

54-Pin SOICW-EP

0.65 mm Pitch

17.9mm x 7.5mm Body

10.3mm x 5.1mm Exposed Pad

Material: Single layer printed circuit board

FR4, 1.6mm thickness

Cu traces, 0.07mm thickness

Outline: 80mm x 100mm board area,

including edge connector for

thermal testing

Area A: Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

Table 23. Thermal Resistanc e Performance

Thermal

Resistance Area A

(mm2)

1 = Power Chip, 2 = Logic Chip (°C/W)

m=1,

n=1 m=1, n=2

m=2, n=1 m=2,

n=2

RθJAmn 053 48 53

300 39 34 38

600 35 30 34

RθJSmn 021 16 20

300 15 11 15

600 14 9.0 13

Analog Integrated Circuit Device Data

Freescale Semiconductor 63

908E621

ADDITIONAL INFORMATION

THERMAL ADDENDUM (REV 1.0)

Figure 36. Device on Thermal Test Board RθJA

Figure 37. Transient Ther mal Resistance RθJA (1.0W Step Response)

Device on Thermal Test Board Area A = 6 00(mm2)

Heat spreading ar ea A [mm²]

Thermal Res is tanc e [ºC/W ]

0 300 600

JA11

JA22

JA12

JA21

0.1

100

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

Time[s]

T her m al Res istance [º C/W ]

JA11

JA22

JA12

JA21

Analog Integrated Circuit Device Data

64 Freescale Semiconductor

908E621

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

3.0 2/2007 • Implemented Revision History page

• Changed Table 3, Statistic Electrical Characteristics, Hall-Effect Sensor Input H0 - 2pin Hall Sensor

Input Mode (H0MS = 1), Sense Current Hysteresis on page 14 from a Minimum of 800 to 600 and

Typical from 1100 to none.

• Removed “Advance” watermark and updated to final Data Sheet.

• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Electrical Characteristics on page 6. Added note with instructions from www.freescale.com.

4.0 6/2007 • Updated to Final by removing “Advance Information” from page 1.

5.0 6/2008 • Changed STOP Mode Total Output Current on page 9 from 850 to 1100μA

• Changed Sense Current Hysteresis on page 14 from 800 to 650μA

• Changed Normal Request Timeout on page 16 from 124 to 150ms

• Updated Freescale form and style to the current format

• Updated package drawing

• Added Functional Internal Block Description section

MM908E621

Rev. 5.0

6/2008

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