FT6164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Common Data I/O High Speed (Equal Access and Cycle Times) - 8/10/12/15/20/25/35/70/100 ns (Commercial) - 10/12/15/20/25/35/70/100 ns(Industrial) - 12/15/20/25/35/45/70/100 ns (Military) Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) - 28-Pin 300 mil Plastic DIP, SOJ - 28-Pin 600 mil Plastic DIP (70 & 100ns) - 28-Pin 300 mil SOP (70 & 100ns) - 28-Pin 300 mil Ceramic DIP - 28-Pin 600 mil Ceramic DIP - 28-Pin 350 x 550 mil LCC - 32-Pin 450 x 550 mil LCC - 28-Pin CERPACK Low Power Operation Output Enable and Dual Chip Enable Control Functions Single 5V10% Power Supply Data Retention with 2.0V Supply, 10 A Typical Current (FT6164L Military) DESCRIPTION The FT6164 is a 65,536-bit ultra high-speed static RAM organised as 8K x 8. The CMOS memory requires no clocks or refreshing and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. With battery backup, data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 A from a 2.0V supply. Access times as fast as 8 nanoseconds are available, permitting greatly enhanced system operating speeds. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS The FT6164 is available in 28-pin 300 mil DIP and SOJ, 28pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK. The 70ns and 100ns FT6164s are available in the 600 mil plastic DIP. DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), CERPACK (F4), SOP(S6) 1519B SEE PAGE 7 FOR LCC PIN CONFIGURATIONS REV 1.6 1 of 17 FT6164 MAXIMUM RATINGS(1) Symbol Parameter Value Unit Power Supply Pin with Respect to GND -0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC +0.5 V TA Operating Temperature -55 to +125 C VCC Symbol RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Industrial Commercial Ambient Temperature GND VCC -55C to +125C -40C to +85C 0C to +70C 0V 0V 0V 5.0V 10% 5.0V 10% 5.0V 10% Parameter Value Unit TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit CIN Input Capacitance COUT Output Capacitance VOUT = 0V VIN = 0V 5 pF 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Parameter Symbol FT6164 Min Max 2.2 VCC +0.5 Test Conditions VIH Input High Voltage VIL Input Low Voltage V HC VLC CMOS Input High Voltage V CD Input Clamp Diode Voltage VCC = Min., I IN = -18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage IOH = -4 mA, VCC = Min. (TTL Load) VCC = Max. Mil. Input Leakage Current Ind./Com'l. VIN = GND to VCC VOL VOH ILI ILO ISB ISB1 -0.5(3) 0.8 FT6164L Unit Min Max 2.2 VCC +0.5 V -0.5(3) 0.8 VCC -0.2 VCC +0.5 VCC -0.2 VCC +0.5 CMOS Input Low Voltage -0.5 (3) 0.2 -0.5 V V 0.2 V -1.2 -1.2 V 0.4 0.4 V (3) V 2.4 2.4 -10 -5 +10 +5 -5 n/a +5 n/a A -10 -5 +10 +5 -5 n/a +5 n/a A ___ ___ 40 ___ ___ 40 n/a mA Standby Power Supply Current (TTL Input Levels) CE1 VIH or Mil. CE2 VIL, Ind./Com'l. VCC= Max, f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE1 VHC or Mil. CE2 VLC, Ind./Com'l. VCC= Max, f = 0, Outputs Open VIN VLC or V IN VHC ___ ___ 25 ___ ___ 1 n/a mA Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC Ind./Com'l. Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. REV 1.6 Mil. 2 of 17 30 15 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with V IL and I IL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. FT6164 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current* Industrial Military -8 -10 -12 -15 -20 -25 -35 45 -70 -100 Unit 200 180 170 160 155 150 145 N/A 130 125 mA N/A 190 180 170 160 155 150 N/A 145 140 mA N/A N/A 180 170 160 155 150 145 145 145 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH DATA RETENTION CHARACTERISTICS (FT6164L, Military Temperature Only) Symbol Parameter Test Condition V DR VCC for Data Retention ICCDR Data Retention Current t CDR Chip Deselect to CE2 0.2V, VIN VCC - 0.2V Data Retention Time or VIN 0.2V tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM REV 1.6 Max VCC = 2.0V 3.0V 3 of 17 Unit V 10 CE1 VCC - 0.2V or *TA = +25C Typ.* VCC = 2.0V 3.0V 2.0 Operation Recovery Time tR Min 15 200 300 A 0 ns tRC ns FT6164 AC ELECTRICAL CHARACTERISTICS--READ CYCLE (VCC = 5V 10%, All Temperature Ranges) (2) Symbol Parameter -8 -10 -12 -15 -20 -25 -35 -45 -70 -100 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 8 10 12 15 20 25 35 45 70 100 ns tAC Chip Enable Access Time 8 10 12 15 20 25 35 45 70 100 ns tOH Output Hold from Address Change 3 3 3 3 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 5 6 7 8 8 10 15 20 35 45 ns tOE Output Enable Low to Data Valid 5 6 7 9 10 13 18 20 35 45 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 8 10 2 12 2 5 0 2 6 0 8 15 2 7 0 10 20 2 9 0 12 25 2 9 0 15 35 2 12 0 20 45 2 15 0 20 70 2 20 0 20 100 2 35 0 25 ns ns 45 0 35 ns ns 45 ns OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 1 (OE Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE 2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE 2 transition HIGH. REV 1.6 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 4 of 17 FT6164 TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) CE1, CE2 CONTROLLED)(5,7,10) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE 2 causes them. AC CHARACTERISTICS--WRITE CYCLE (VCC = 5V 10%, All Temperature Ranges) (2) Symbol Parameter tWC Write tCW tAW tAS tWP tAH tDW ycle ime C -8 -10 -12 -15 -20 -25 -35 -45 -70 -100 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 8T 10 12 15 20 25 35 45 70 100 ns Chip Enable Time to End of Write 6 7 8 12 15 18 25 33 50 70 ns Address Valid to End of Write 7 8 10 12 15 18 25 33 50 70 ns 0 0 0 0 0 0 0 0 0 0 ns 7 8 9 12 15 18 20 25 40 50 ns 0 0 0 0 0 0 0 0 0 0 ns 6 7 8 9 11 13 15 20 30 40 ns 0 T 0 0 0 0 0 0 0 0 0 ns Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write tDH Date old imeH tWZ Write Enable to Output in High Z tOW Output Active from End of Write REV 1.6 6 3 7 3 7 3 7 3 8 3 5 of 17 10 3 14 3 18 3 30 3 40 3 ns ns FT6164 WE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE Notes: 11. CE1 and WE must be LOW, and CE 2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show t WZ and t OW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously withWE HIGH, the output remains in a high impedance state. REV 1.6 14. Write Cycle Time is measured from the last valid address to the first transitioning address. 6 of 17 FT6164 AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE1 CE2 OE WE I/O Power Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V Standby X L X X High Z Standby Output Timing Reference Level 1.5V DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the FT6164/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). LCC PIN CONFIGURATIONS LCC (L5) "L" - STANDARD PIN-OUT REV 1.6 LCC (L5) "LS" - SPECIAL PIN-OUT 7 of 17 LCC (L6) FT6164 ORDERING INFORMATION FT6164 L XX X X M5004 SELECTION GUIDE The FT6164 is available in the following temperature, speed and package options. The FT 6164L is available only over the military temperature range. Spe e d (ns) Te m pe ra ture Ra nge Commercial Industrial Pa cka ge Plastic DIP (300 mil) 8 10 12 15 20 25 35 45 70 100 -8PC -10PC -12PC -15PC -20PC -25PC -35PC N/A N/A N/A -100P6C Plastic DIP (600 m il) N/A N/A N/A N/A N/A N/A N/A N/A -70P6C Plastic S OJ -8JC -10JC -12JC -15JC -20JC -25JC -35JC N/A N/A N/A Plastic S OP N/A N/A N/A N/A N/A N/A N/A N/A -70SNC -100SNC Plastic DIP (300 m il) N/A -10PI -12PI -15PI -20PI -25PI -35PI N/A N/A N/A Plastic DIP (600 m il) N/A N/A N/A N/A N/A N/A N/A N/A -70P6I -100P6I Plastic S OJ N/A -10JI -12JI -15JI -20JI -25JI -35JI N/A N/A N/A Plastic S OP N/A N/A N/A N/A N/A N/A N/A N/A -70SNI -100SNI N/A = Not available REV 1.6 8 of 17 FT6164 SELECTION GUIDE (continued) Temperature Range Military Temperature Military Processed * Package Speed (ns) 8 10 12 15 20 25 35 45 70 100 Side Brazed DIP N/A N/A -12CM -15CM -20CM -25CM -35CM -45CM -70CM -100CM CERDIP (300 mil) N/A N/A -12DM -15DM -20DM -25DM -35DM -45DM -70DM -100DM CERDIP (600 mil) N/A N/A -12DWM -15DWM -20DWM -25DWM -35DWM -45DWM -70DWM -100DWM CERPACK N/A N/A -12FM -15FM -20FM -25FM -35FM -45FM -70FM -100FM 28-Pin LCC N/A N/A -12LM -15LM -20LM -25LM -35LM -45LM -70LM -100LM 28-Pin LCC ** 32-Pin LCC N/A N/A -12LSM -15LSM -20LSM -25LSM -35LSM -45LSM -70LSM -100LSM N/A N/A -12L32M -15L32M -20L32M -25L32M -35L32M -45L32M -70L32M -100L32M Side Brazed DIP N/A N/A -12CMB -15CMB -20CMB -25CMB -35CMB -45CMB -70CMB -100CMB CERDIP (300 mil) N/A N/A -12DMB -15DMB -20DMB -25DMB -35DMB -45DMB -70DMB -100DMB CERDIP (600 mil) N/A N/A -12DWMB -15DWMB -20DWMB -25DWMB -35DWMB -45DWMB CERPACK N/A N/A -12FMB -15FMB -20FMB -25FMB -35FMB -45FMB -70FMB -100FMB 28-Pin LCC N/A N/A -12LMB -15LMB -20LMB -25LMB -35LMB -45LMB -70LMB -100LMB 28-Pin LCC ** 32-Pin LCC N/A N/A N/A N/A -12LSMB -12L32MB -15LSMB -15L32MB -20LSMB -20L32MB -25LSMB -25L32MB -35LSMB -35L32MB -45LSMB -45L32MB * Military temperature range with MIL-STD-883 M5004 ** SPECIAL PINOUT N/A = Not available REV 1.6 9 of 17 -70DWMB -100DWMB -70LSMB -100LSMB -70L32MB -100L32MB FT6164 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C5 SIDE BRAZED DUAL IN-LINE PACKAGE (300 mils) 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - C5-1 SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils) 28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - REV 1.6 10 of 17 FT6164 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 REV 1.6 D5-1 CERDIP DUAL IN-LINE PACKAGE 28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15 D5-2 CERDIP DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15 11 of 17 FT6164 Pkg # # Pins Symbol A b c D E e k L Q S S1 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q F4 CERPACK CERAMIC FLAT PACKAGE 28 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.730 0.330 0.380 0.050 BSC 0.005 0.018 0.250 0.370 0.026 0.045 0.085 0.005 - J5 SOJ SMALL OUTLINE IC PACKAGE 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - REV 1.6 12 of 17 FT6164 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE REV 1.6 L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 L6 RECTANGULAR LEADLESS CHIP CARRIER 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 13 of 17 FT6164 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P5 PLASTIC DUAL IN-LINE PACKAGE (300 mils) 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15 P6 PLASTIC DUAL IN-LINE PACKAGE (600 mils) 28 (600 mil) Min Max 0.090 0.200 0.000 0.070 0.014 0.020 0.015 0.065 0.008 0.012 1.380 1.480 0.485 0.550 0.600 0.625 0.100 BSC 0.600 TYP 0.100 0.200 0 15 REV 1.6 14 of 17 FT6164 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE REV 1.6 L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 L6 RECTANGULAR LEADLESS CHIP CARRIER 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 15 of 17 Ashley Crt, Henley, Marlborough, Wilts, SN8 3RH UK Tel: +44(0)1264 731200 Fax:+44(0)1264 731444 E-mail sales@forcetechnologies.co.uk www.forcetechnologies.co.uk Unless otherwise stated in this SCD/Data sheet , Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. Life Support Applications Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such improper use or sale. Copyright Force Technologies Ltd 2010 All trademarks acknowledged REV 1.6 16 of 17 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM115 FT6164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 M.S New Data Sheet 1.1 Oct-05 M.S Data sheet review 1.2 Jun-06 M.S Added 28-pin ceramic DIP 1.3 Aug-06 M.S Added Lead Free Designation 1.4 Aug-06 M.S Added "LS" - SPECIAL PIN-OUT 1.5 Aug-06 M.S Updated SOJ package information M.S Corrected SOP package details 1.6 REV 1.6 Jun-07 DESCRIPTION OF CHANGE 17 of 17