AN-4105 - Fairchild Semiconductor

Application Note AN4105

Design Considerations for Switched Mode Po wer

Supplies Using A Fairchild Pow er Switch (SPS) in a

Flyback Converter

www.fairchildsemi.com

Introduction

Flyback switched mode power supplies (SMPS) are among

the most frequently used power circuits in household and

consumer electronics. The basic function of an SMPS is to

supply regulated power to the load on the secondary, or

output side. An SMPS typically incorporates a power

transformer, secondary side rectifier diodes, switching

semiconductor device with control IC, and peripheral

circuitry. If the level of integration of the switching and

control circuitry is not high e no ugh , t he n a ddit i o na l, sepa ra te

circuits will be required to accommodate all functions. Such

additional components raise the overall SMPS cost and not

uncommonly reduce reliability.

Fairchild Power Switch (SPS) is a range of highly integrated

ICs for power supply applications. They combine a high

volta ge power MOSFET (SenseFE T) a nd pulse w idth

modulation (PWM) based control IC in one package.

Moreover, they provide enhanced IC functionality, thereby

minimizing the number of additional components needed in

an SMPS. Fairchild Power Switch (SPS) ICs are widely used

in the power circuits of a variety of equipment, such as color

TVs, printers, PCs, monitors, battery chargers and ac

adapters. They typically incorporate a variety of enhanced

protection functions and permit much reduced power

consumption in standby modes. This application note

considers the three major functional blocks of an SMPS:

Fairchild Power Switch (SPS), flyback converter, and

transformer. It discusses a variety of issues important to their

design and use in the overall SMPS.

Figure1. In ternal block diagram of a Fairchild Power Switch(SPS).

Source

GND

Drain

Sense

Feedback

Soft Start

& Sync. LEB

Rsense

2.5R

OSC.

Reset

1mA2uA Vck

6.3V Sync.

7.5V

Reset

Voffset

#3 Vcc

Voltage

Ref.

UVLO

32V

OVP Control IC

Sense

FET

Thermal

Proction

Source

GND

Drain

Sense

Feedback

Soft Start

& Sync. LEB

Rsense

2.5R

OSC.

Reset

1mA2uA Vck

6.3V Sync.

7.5V

Reset

Source

GND

Drain

Sense

Feedback

Soft Start

& Sync. LEB

Rsense

2.5R

OSC.

Reset

1mA2uA Vck

6.3V Sync.

7.5V

Reset

Voffset

#3 Vcc

Voltage

Ref.

UVLO

32V

OVP

Voffset

#3 Vcc

Voltage

Ref.

UVLO

32V

OVP Control IC

Sense

FET

Thermal

Proction

Rev. 1.0.1

AN4105 APPLICATION NOTE

1. Block Diag ram and Basic Operation

of a Fairchild Power Switch(SPS)

1.1 Block diagram

Figure 1 presents a block diagram of a Fairchild Power

Switch (SPS). It can be divided into several large, functional

sections: under v oltage lockout circuitry ( UVLO); refere nce

voltage; oscillator (OSC); pulse width modulation (PWM)

block; protection circuits; and gate driving circuits.

1.2 Under voltage lockout (UVLO)

A Fairchild Power Switch (SPS) under voltage lockout

(UVLO) circuitry (Figure 2) guarantees stable operation of

the IC’s control circu it by stopping and starting it as a

fun ctio n of the va lue of VCC (Figure 3). T he tur o ff and turn

on voltage thresholds are fixed internally at 10V and 15V,

respectively. Therefore the UVLO circuitry turns off the

control circuit when VCC is lower than 10V and starts it

when VCC is higher than 15V. Once the control circuit starts

operating, VCC must drop below the 10V level for the

UVLO to stop the circuit again. Before switching starts, the

IC current is less than 300µA. IC operation starts when CCC

(Figure 2) char ges to 15V. Because only a small current

(<1 mA) is allowed to flow in through the resistor during

normal operation this techniq ue reduces the current

dissipation in the SMPS start up resistor.

Figure 2. Detail of the undervoltage lockout (UVLO)

circuitry in a Fairchild Power Switch. The gate

operating circuit holds in a low state du ring UVLO,

thereby maintaining the SenseFET at turnoff.

Figure 3. Fai rchild Power Switch (SPS) control circu it statu s vs. Vcc.

1.3 Feedback control circuit

The Fairchild Power Switch(SPS) control IC uses a current

mode PWM and operates such that MOSFET cur ren t is

proportional to the feedback voltage Vfb. This limits the

MOSFET current at every cycle. It also offers other

advantages, such as a well regulated SMPS output voltage

with input voltage changes. This method of control also

works successfully in SMPSs used for monitors, which may

have a broad range of synchronizing frequencies to deal

with. As shown in Figure 4, the Fairchild Power Switch

(SPS) oscillator turn s on the MOSFET. The feed back

comparator oper ates to turn it off ag ain, when the MOSFET

current reaches a set value proportional to Vfb. The

MOSFET turn off operation is as follows:(1) the internal

(R+2.5R) voltage divider sets the voltage fed back to one

input of the feedback comparator at Vfb /3.5; (2) a current

proportional to the drain current flows to the MOSFET sense

terminal making Vsense proportional to the drain current;

and, (3) when Vsense becomes greater than Vfb, the output of

the feedback comparator goes high, turn ing off the

MOSFET. Figure 4 also shows that the circuit is designed

Vcc

15V/10V

UVL

Vz Vref

Internal Bias

Good Logic

Power On

Reset

Latch

Comparator

LINK Rg

Ccc

SPS

Fairchild Power

Switch(SPS)

15V10V

Icc

[mA]

[V]

0.3

Power On

Reset Range

[V]

APPLICATIO N NOTE AN4105

to use an opto isolator in the feedback loop. This is

appropriate for an off line design where input to output

isolation is required. Cfb improves the noise characteristics.

If the control IC incorporates an error amp however, as in

Fairchild’s KA3842B/3B/4B/5B current mode PWM

controller ICs for SMPSs then a resistor and capacitor are

required to provide the feedback to the error amp. This

would provided the same functions as those provided by the

circuit of Figure 4, e.g., fine control of the output voltage

through Vfb. Similarly, other appropriate devices here are

Fairchild’s LM431/TL431/KA431 series of three terminal

shunt regulators. These have a very sharp turn on

characteristic much like a Zener diode and are widely used in

SMPS secondary side error amplifiers.

Figure 4. Fairchild Power Switch(SPS) feedback circuit appropriate for off line SMPS use (current mode PWM).

1.4 Example Fairchild Power Switch (SPS)

control circuit

Figure 5 shows two approaches to controlling feedback in a

Fairchild Power Switch (SPS). The design in Figure 5a uses

the LM431 regu lator , and th at of Figure 5b uses a Zene r diode.

Although the re are di f f e renc es a mon g Ze ne rs, and t he ir

constant voltage characteristics are slightly poorer than shunt

regulators’, a design using a Zener diode has cost advantages.

In Figure 5a, C1 together with R1 produce a zero point to

compensate the pole formed by the Fairchild Power Switch

(SPS)’s internal 3.5KΩ resistor and Cfb; There would be no

safety problems if the zero did not exist, but it is added to

improve dyna mic r e sponse. If dynami c response is no t a

factor, C1 can be removed (as in fact was done in Figure 5b).

C2 increases the loop gain enough at low frequencies to

improve the output load regulation. R3, through the LM431’s

bias resistor, can set the photodiode current at almost zero. R4

limits the ma xi mum cur re nt of t he ph otodi ode to 2.3m A

[(12V - 2.5 V - 2V ) / 3.3K Ω, where 2.5V is the LM431's

saturation voltage and 2 V is the photodiode's voltage drop].

Cfb should be determined by considering the shutdown delay

time (see Section 2.1). In Figure 5b, R3 sets a fixed current to

the Zener diode to stabilize its voltage.

Rsense

2.5R

OSC.

Ioffset Sense

1mA2uA Vck

Precision

Current Source

Vfb

Vfb*

Reset

Vss

Vsense Isense

Idrain

Off

Cfb

Css

SPS

Fairchi ld Power S witch(SPS)

AN4105 APPLICATION NOTE

Figure 5. Fairchild Power Switch(SPS) feedback control circuit.

1.5 Soft start operation

Normally, the SMPS output voltage increases from start up

with a fixed time constant. This is due to the capacitive

component of the load. At start up, therefore, the feedback

signal applied to the PWM comparator's inverting input

reaches its maximum value (1V), Th is is because the

feedback loop is effectively open. Also at this time, the drain

current is at its peak value (Ipeak) and maximum allowable

power is being delivered to the secondary load. With that

said, note that when the SMPS pushes maximum power to

the secondary side for this initial fixed time, the entire

circuit is seriously stressed. Use of a soft start function

avoids such stresses. Figure 6 shows how to implement a

soft start for a Fairchild Power Switch (SPS). At turn on, the

soft start capacitor CS on pin 5 of the Fairchild Power

Switch(SPS) starts to charge through the 1mA current

source. When the voltage across CS reaches 3V, diode DS

turns off. No more current flows to it from the 1mA current

source. Cs then continues to charge to 5V through the 5 0kΩ

resistor.

Rsense

OSC.

Ioffset

1mA2uA Vck

Vfb

Vfb*

Sense

Cfb

Vo, 80V 12V

33n 2k

2.2k

33k

0.1u

PC817

(b) Control circuit that used the zener diode

R2 Vz

R1 R3

Rsense

OSC.

Ioffset

1mA2uA Vck

Vfb

Vfb*

Sense

Cfb

Vo, 80V 12V

33n 2k

33n

KA431

3.3k

33k

10n

PC817

(a) Control circuit that used KA431(LM431)

SPS

LM431

Fairchild Power Switch(SPS)

Fairchild Power Swit ch (SPS)

Control Circuit using KA431(LM431) Control IC

Control Circuit using a Zener Diode Control IC

APPLICATIO N NOTE AN4105

Figure 6. Soft start circuit.

Note that when the voltage across CS exceeds 3V, The v oltage

at the comparator’s inverting terminal no longer follows the

voltage across CS. Instead, it follows the output voltage

feedback signal. In shutdown or protection circuit operation,

capacitor CS is discharged, to enable it to charge from 0V at

restart.

1.6 Synchronization

In an SMPS intended for use with monitors, synchronization

is handled differently than in a general purpose SMPS. For

monitor use, it is necessary to prevent noise from appearing on

the monitor display. To accomplish this, it is necessary to

synchronize the SMPS switching frequency with the

monitor’ s h ori zont a l sync fre qu ency. The monitor’s horizontal

scan flyback signal is commonly used as the external sync

signal for the SMPS. By synchr onizing th e switching with the

horizontal scan’s flyback, the switching noise is positioned at

the far left of the monitor display where it cannot be seen.

Figure 7 shows how to implement the external

synchronization scheme. The external sync signal, applied

across resistor Rs, cannot drop below 0.6V because of diode

Dsync. After the conclu sion of the initial so ft start, the voltag e

across Cs remains at 5V until the external sync signal is

applied , at which p oint it looks l ik e VRs of Figure 8. The sync

comparator compares VCs against a 6.3V level and produces

the comparator out pu t wave for m, V comp of Figure 8.

A Fairchild Power Switch (SPS) has an internal timing

capacitor , Ct. Fi gure 8 show s that when t he voltage on C t, VCt,

reaches an upper threshold, it begins to discharge; then, when

it reaches a lower threshold, it again starts to charge.

This operation is controlled by the internal oscillator. The

oscillator ou tput signal, VCk in Figure 8, which goes low

Figure 7. Synchron izatio n circui t.

when Ct recharges and high when it discharges, is applied to

the Fairchild Power Switch (SPS) S/R Latch Set terminal. In

the absence of an external sync signal, the voltage across Ct

oscillates at the basic frequency of 20kHz. In the presence of

a sync signal, however, the Set signal goes high because VCt

charges to the high threshold following the external sync

signal, and, ultimately, the Set signal, which determines the

switching frequency, synchronizes to the external sync

signal. It is necessary to limit the Set signal's high duration to

5% or less of the full cycle. As the Set signal drops low the

gate turns on. If the device were not synchronized to the

horizontal scan of the monitor, noise would appear on the

screen. When the Set signal goes high, the sync is

synchronized with the horizontal scan flyback. Because the

high duration is 5% (maximum) of the full cycle, the start o f

the horizontal scan (as the Set signal goes low) turns on the

switch. The switch turn on noise, therefore, is hidden in the

horizontal blanking period at the far left of the monitor

display.

Figure 8. Synchron ization circuit oper ation.

2#1$

10V

External

Sync Input

50k

5V PWM

Comparator

Fairchild Power

Switch (SPS)

KA5XX Series

KA5SXX

KA5QXX

Series

#5#4

Fairchild Power Switch(SPS)

KA2SXX

KA3SXX

OSC .

OSC .OSC .

OSC .

External

Sync

Input VRS

5V PWM

comparator

VCOMP

6.3V

Sync

comparator

VCS

Dsync

SPS

Fairchild Power Swit ch( SPS)

VCS

VCOMP

VCT

Vck

VRS 2V

VThL

VThH

AN4105 APPLICATION NOTE

2. Fairchild Power Switch(SPS) Built

In Protection Circuits

Since a Fairchild Power Switch (SPS)’s built in protection

circuits do not require additional, external components,

reliability is increased without increasing cost. Note that the

protective circ uitry can co mpletely stop the SMPS o peration

(latch mode protection) u ntil the power is tu rned off and on

again, and can make the control voltage restart above the

ULVO level should the latch be released below ULVO

(Auto Restart Mode protection).

2.1 Output overload protection

An overload is any load greater than the load defined as

normal for operation. This is not a short circuit. The Fair-

child Power Switch (SPS) overload protection determines

whether the overload is true or merely transient. Only a true

overload will trigger the overload protec tion. When the

Fairchild Power Switch (SPS) senses an overload, it waits

for a specified time. If the overload is still present after this,

it is considered a true overload and the device shuts down.

The Fairchild Power Switch (SPS) h as a current control that

prohibits current flow above a set maximum, which means

the maximum input power is limited at any given voltage.

Therefore, if the output load tries to draw more than this

level, Vo (Figure 9) drops below the set voltage and LM431

can draw only a given minimum current. As a result, the opto

coupler secondary current drops to almost zero. Almost the

entire current flow at the node is from the Fairchild Power

Switch (SPS) 1mA curre nt source. Hence, the internal 3KΩ

resistor (2.5R + R = 3KΩ) moves Vfb to 3V. From this point

on, however, the 5µA current source starts to charge Cfb,

and, because the opto coupler secondary current is almost

zero, Vfb continues to increase. When Vfb reaches 7.5V, the

Fairchild Power Switch (SPS) shuts down.

Figure 9. Fairchild Power Switch(SPS) overload protection circuit.

The shutdown delay interval is therefore determined by Cfb.

When Cfb is 10nF, the shutdown delay t2 (see Figure 10b) is

about 9mS. With Cfb at 0.1µF, t2 is about 90mS. Such delay

intervals do not allo w the typical tran sients observed to shut

down the Fairchild Power Switch (SPS). Note that, if a

longer delay is needed, Cfb cannot be made arbitrarily large

because it is important in determining the dynamic response

of the SMPS. When a large value of Cfb is necessary, a series

connected capacitor and Zener diode can be connected

across Cfb as shown in Figure 10a. The combination works

in this way: When Vfb is below 3V, the low valued Cfb

allows the SMPS to have a good dynamic response. When

Vfb is above 3.9V, the high valued Cd extends the delay t ime

to the desired shutdown point. Of course, where transients

are insignificant and good dynamic response is not required,

then do without Cd and the Zener, thereby eliminating their

added costs.

Rsense

OSC.

Ioffset

1mA2uA Vck

Vfb

Vfb*

Sense

Reset

Thermal

Shutdown

7.5V

Cfb

Shutdown

Vo #4

SPS

KA431

D1 D2 2.5R

Fairchild Power Switch(SPS)

LM431

APPLICATIO N NOTE AN4105

Figure 10. Long delay shutdown.

2.2 Output short circuit protection

When the SMPS’s output terminal is short circuited the input

current is at maximum. The output power however, is not a

maximum. This is because there can be no load voltage since

the load is a short circuit. Under such conditions the output

short circuit protection operates as follows.

When the output load short circuits a relatively large

transformer winding in the SMPS, the Fairchild Power

Switch(SPS)’s MOSFE T current becomes much greater than

Ipeak because the inductor’s magnetic core is u nable to r eset.

This is due to low transformer coil voltage at turn off. This

occurs because th e current remaining in th e inductor during

the Fairchild Power Switch(SPS)’s minimum turn on time

cannot decrease by that amount during the remaining turn of f

time. Even though it is a large current, it does not unduly

stress the MOSFET but does greatly stress the transformer’s

secondary coils and the secondary side rectifiers.

In most flyback or forward converters the controller g ets its

power from a small secondary bias winding in the

transformer. Furthermore, this controller voltage is

proportional to the output voltage (see circuit of Figure 11a).

This is fairly straightforward becau se, for a flyback

converter, the coil voltage when the switch turns off is

proportional to the output voltage. For a forward converter,

the transformer av erage voltage at turn off is proportional to

the output voltage. For a flyback converter SMPS, the output

shor t c irc ui t pro te cti on c ir cui t c a n be op erat e d in ei ther l atc h

mode or auto restart mode.

The change in Vcc as a function of Rsd is shown in Figure

11b. Rsd is shown in Figure 11a. When Rsd is zero, Vcc

reaches the maxim um value of Vtx (see lower primary

winding, Figure 11a), i.e., n'Vsn/n, which is proportional

to the maximum transformer current. For this case, if

the output short circuits, Vcc increases and, after a

specified delay, the protection circuit operates, entering

the latch mode.

However, when Rsd is made sufficiently large, Vcc can

become smaller than n'Vo. Therefore, if the output short

circuits, Vcc drops, but, if Ccc (see Figure 11a) is sufficiently

large, Vcc stays at a level higher than the UVLO's lower

threshold vol t age (10V) until V fb reaches 7.5V (Figure

11c-2) and latch mode protection starts. In contrast, if Ccc is

small enough Vcc approaches the UVLO's low threshold

before Vfb reaches 7.5V (Figure 11c-3), and the UVLO

operates instead of the protection circuit, stopping the device

switching. In such a case, if Vcc exceeds the ULVO's upper

threshold voltage (15V), auto restart operates again. Rsd,

Ccc, and Cfb have affects even at start up and power down, so

their values must be decided upon c a r efully. Our

experiments have indicated that 10 - 20W is most

appropriate for Rsd.

Time Constant

= 3.5R*Cfb

2uA = Cfb*0.9V/t2

2uA = Cd*3.6V/t3

Shutdown

< SPS long Delayed Shutdown >

(b)

7.5V

t2t1

3.9V

1mA2uA

Vfb

Vfb*

7.5V

4D1 D2

Vz=3.9V

SPS

KA431

(a)

LM431

Fairchild Power Switch(SPS)

AN4105 APPLICATION NOTE

Figure 11. Operation of the SMPS fl yback converter’s output s hort cir cuit protecti on (latch mod e ).

Cvcc

Vtx n*Vo

n*Vin/n

n*Vsn/n

(b) Flayback converter controller voltage and Rsd dependent Vcc

No Rsd

Low Rsd

Large Rsd

10V

7.5V

Vcc

Output short Shutdown

UVLO

(1)

(2)

(3)

Shutdown

UVLO

Shutdown

Vfb

(

)

Vcc and Vfb waveforms de

endin

on the relative size of Cvcc at out

ut short

SPS

VccVfb

Vtx

Control

Vin Vsn

CccCfb

Rsd

n:1

n*:1

(a) Flyback converter

KA431

5LM431

Fairchild Power Swit ch( SPS)

The voltage V tx ware form of NB and VCC(the rectified VNB) de pending on Rsd

Vin

APPLICATIO N NOTE AN4105

2.3 Fast protection without delay

It was mentioned above that the Fairchild Power

Switch(SPS) shutdown capability is associated with a delay,

to allow normal transients to occur without shutting down

the system. In effect, this restricts the protection range. If

fast protection is required, then additional circuitry is called

for. Figure 12 shows how it’s done. A transistor is used to

force the feedback photodiode current to increase causing

the primary side Vfb to be forced below 0.3V. Therefore the

Fairchild Power Switch (SPS) stops switching. Depending

on the magnitude of the photodiode current, the protection

can be made to operate sufficiently fast. In such a case, when

the transistor is turned of f, the protection shifts to auto restart

mode for normal operation. It is also possible to use this

circuit as an output enable circuit. Fast latch mode protection

can be implemented by adding a photocoupler. Thus, when

the output terminal latch mode transistor turns on, a large

current flows through the photodiode PC2. A large current

therefore flows through the primary phototransistor, which

increases Vfb rapi dly.

This executes fast latch mode protection with no time delay.

Figure 12. A fa st protection circuit without a shutdown delay.

2.4 Overvoltage protection

The Fairchild Power Switch (SPS) has a self protection

feature that operates even when faults exist in the feedback

path. These could include an open or short circuit. On the

primary side, if the feedback ter minal is short circuited, then

the voltage on it is zero and hence the Fairchild Power

Switch (SPS) is unable to start switching. If the feedback

path open circuits, the protection circuit operates as though a

secondary overload is present. Further, if the feedback

terminal looks open due say, to some fault in the primary

feedback circuit, the primary side could switch at the set

maximum current level until the protection circuit operates.

This causes the secondary voltage to become much greater

than the r ated voltage. Note that in such a case if there were

no protection c ircuit, the fuse could blow or, more serious, a

fire could start. It is possible that, without a regulator,

devices directly connected to the seconda ry output could be

destroyed. Instead, however, the Fairchild Power Switch

(SPS) over voltage protection circuit operates. Since VCC is

proportional to the output, in a n over voltage situation it will

also increase. In the Fairchild Power Switch (SPS), the

protection circuit operates when Vcc exceeds 25V. Therefore

in normal operation Vcc must be set below 25V.

SPS

Vcc

Vfb

Vtx

Control

Vin Vsn

Ccc

Cfb

Rsd

n:1

n*:1

KA431

PC1

PC2

PC1

Burst Mode

Shut Down

PC2

Latch Mode

Shut Down

Vo LM431

Fairchild Power Swit ch( SPS)

Vin

AN4105 APPLICATION NOTE

3. Noise Considerations at swi tch Turn On

3.1 SMPS current sensing

Whether an SMPS is current mode or v oltage mode

controlled, or uses some form of non linear control, it

requires the protection afforded by current sensing

capabilities. Even though most curren t sensing is done using

a sensing resistor or a current transformer, there are

instances where a MOSFE T is used by the SMPS to further

reduce current sensing losses. The Fairchild Power Switch

(SPS) switching element is a SenseFET. This minimises any

power losses in the sense resistor, which is integrated onto

the controller chip.

3.2 Current sensing waveform noise after

turn on

A leading edge spike is present on the current sense line

when the SMPS switching device turns on. It arises from

three causes, as shown in Figure 13: (1) reverse recovery

current; (2) charge/discharge current of the MOSFET shunt

capacitance; and (3) MOSFET g ate operating current.

(1) Reverse recovery current is generated when the SMPS

operates in continuous conduction mode (CCM; see Section

4.1). If the MOSFET is turned on while th e rectifier d iode is

conducting, the diode, during its reverse recovery time will

act like a short circuit. Therefore a large current spike will

flow in the MOSFET. There are three ways to reduce the

magnitude of this (reverse recovery) current: use a fast

recovery diode; reduce the MOSFET’s gate operating

current at turn on; or, increase the transformer leakage

inductance.

(2) The total capacitance on the MOSFET’s drain side

includes the parasitic capacitor Cds between the drain and the

source terminals, the junction capacitance of the snubber

diode, and the capacitance of the transformer windings. At

turn on, the tota l equivalent capacitor discharges through the

MOSFET.

(3) As shown in the diagram, the MOSFET gate operating

current also flows through the current sensing resistor.

Figure 13. Current sensing waveform noise after turn on.

Vin

Control

Vo Vin

Control

Vo Vin

Control

Reverse Recovery Current Charge/Discharge Current of

the equvalent capacitor MOSFET Gate Operating

Current

AN4105 APPLICATION NOTE

3.3 Dealing with leading edge noise

Among the measures taken to reduce leading edge noise, the

most commonly used technique is the RC filter. As shown in

Figure 14a the RC filter is effective against the noise, but it

has the disad vantag e that it distorts the curr ent sensi ng sign al

so that accurate current sensing becomes difficult.

Furthermore, a large RC va lue may be di ff icult to impleme nt

on an IC and may even req uire a bigger c hip. The tech nique

of leading edge blanking, as presented in Figure 14b and

14c, overcomes the distortion disadvantage of the RC

technique and works as follows. Since the problem noise

arises just after turn on, if a circuit is inserted that ignores the

current sensing line for a fix ed time just after turn on,

operation can continue normally regardless of the noise.

Whatever the details of th e location and type of circuit used,

the basic idea is to maintain a minimum turn on time i.e.,

touse the shortest turn on time that cannot be terminated

once turn on starts. Du ty ratio control with a minimum turn

on time is implemented through a non linear control method

having a very wide control range relative to a linear control.

The non linear control operates such that if load conditions

require a turn on time of 400ns when the minimum turn on

time is set at 500ns, then one switching cycle will turn on at

800ns. The next cycle will be missed, ensuring that the aver-

age turn on time is 400nS. In this case every other cycle is

missed. This is pulse skipping. In this case the switching fre-

quency will be half that of a linearly controlled system,

thereby improving SMPS efficiency at light loads. The input

power is therefore minimised. The Fairchild KA34063 dc/dc

converter is an example of a no n linear control IC.

3.3.1 Burst mode operation

The aforementioned method can be viewed as an example o f

burs t mode ope rat i o n. Bu rst mode opera ti on , by re d uc i ng t he

switching frequency, is one of the most useful ways to

improve SMPS efficiency at light loads and to reduce the

standby input power of household appliances, etc. Note that

burst mode operation is not a burst o scillation (as in ringing

choke conversion circu its), which can bring about r eliability

problems. There are mainly two types of true burst mode

operation: one type lowers the switching frequency equally.

The other switch es at normal fr equency fo r a fixed time and

stops the control IC operation for a large number of cycles.

Even though in the first method the control IC continues to

cons ume powe r, the output voltage ripple is minimized . The

second method can be a useful way to reduce the minimum

input po we r at st andb y (sin ce obv iou sly the st and by powe r is

greatly reduced when the IC is stopped). Indeed, it is often

used in cell phones to reduce the dc/dc converter’s power

consumption in standby mode. However, it has the

disadvantage of a larger output voltage ripple. Currently,

Europe restricts a household appliance’s standby input

power to less than 5W, and in time it will be required to be

less than 3W.

For such needs, burst mode operation will be a powerful

method to satisfy the requirement for reduced stand by input

power.

AN4105 APPLICATION NOTE

Figure 14. Leading ed ge blanking.

PWM

MOSFET

Current

Sensing

< Noise elimination using RC filter >

< Noise elimination and waneforms in LEB >

Feedback

Circuit

Ifb

Ifb Vfb

Vis

Cfb

LEB

OSC Vi

Vck

Vis Vfb

< Internal block diagram for noise elimination using LEB>

(a)

(b)

APPLICATIO N NOTE AN4105

4. Flyback Converter Operation

4.1 Operation in continuous conduc tion mode

(CCM)

Figure 15 show s a ty pica l fl yb ack c onv er ter. When the current

through the converter’s inductor is always greater than zero

within a switching cycle, the converter is said to operating i n

the continuous conduction mode (CCM). Figure 16 show s the

waveforms of CCM o pera tion , whic h op erate s as f oll ows.

4.1.1 For t0 ~ t1 = TON

At t0 the MOSFET turns on. Immediately before t0, the

inductor current was flowing through diode D, but when the

MOSFET turns on, D turns off thereby isolating the output

terminal from the input terminal. At MOSFET turn on, its

VDS goes to zero, hence VD becomes (Vo + V i/n). During the

interval after MOSFET turn on (i.e., from t0 on), Vi is

applied to Lm, so ILm increases linearly with a slope as

shown by the following equation:

When the energy flow is examined, it is seen that the input

power source su ppli es energy to Lm while the MOSFET is on.

However, since the energy in Lm continues to increase while

the output terminal is isolated from the input terminal, it is Co

that has to supply the output current during this interval.

4.1.2 For t1 ~ t2 = TOFF

At t1 the MOSFET turns off. At the instant of turn off, the

inductor current that had been flowing through the MOSFET

starts to flow through diode D. When D turns on, VDS

becomes (Vi +nVo). During this interval the voltage nVo is

applied to Lm so that ILm decreases in a straight line with the

following slope:

When the energy flow during this interval is examined, it is

seen that the inductor energy is delivered to the output. The

energy in Lm is red uced by the amount o f energy it delivers

to the output. When the MOSFET turns on again, at t2, one

switching cycle will end.

4.1.3 Relationship between input and output

As shown in Figure 16, the colored areas A and B of the

waveform VLm (the volta ge applied to the indu ctor) must be

equal because the average voltage of the inductor or

transformer in steady state is always zero. Therefore:

The input and output currents becom e:

Hence the input and output powers are equal. An ideal

waveform is shown here because the effect of leakage

inductance has been ignored. In reality leakage inductance

will cause ringing.

Figure 15. A typical flyback converter.

Figure 16. Flyback converter operating waveforms in

continuous current mode (CCM).

Slope Vi

--------=

Slope

nVO

-------------=

nVO

------------ TON

TOFF

----------------- D

D%–

-------------==

ViTONnVOTOFF

IOn%D–()ILm, AVG

IiDILm, AVG

Vin

ICRO

VDS

VLm

ILm

IDS n:1

t0t1t2t3

VGS

VDS

ILm

0ON OFF

VLm

Slpoe=nVO/L m

Slope=Vi/Lm

Vi+nVO

TON TOFF

0Vi

nV0

V0+Vi/n

IDS

AN4105 APPLICATION NOTE

4.2 Discontinuous conduction mode (DCM)

The appearance of an interval in which the inductor current

becomes zero during a switching cycle marks flyback

converter operation as discontinuous conduction mode

(DCM). As shown in Figure 17, the voltage waveform

applied to the inductor, VLm, becomes more complex in

DCM. Hence, to avoid difficulties in computation TOFF is

not used. Instead, three input and output relationships of a

converter are derived by using TOFF * , the time when the

output rectifier diode is actually conducting.

Figure 17. Flyback converter operating waveforms in

discontinuous current mode (DCM ).

The boundary condition between DCM and CCM is:

The following input output relationship in DCM is derived

by using the fact that the colored areas A and B of VLm in

Figure 17 mu st always be equal because, in steady state, the

average inductor (or transforme r)

voltage is always zero.

Deriving the above equation again, using Io and the fact that

the input and output powers are equal, Vo is obtained as:

The following equation rep resen ts the input powe r:

where fsw is the switching frequency.

4.3 Flyback converter design

4.3.1 Turns ratio considerations

The turns r atio of a n SMPS’s flyback con verter tran sformer

is an important variable. It affects the voltage and current

levels associated with the p rimary side switching device and

the secondary side rectifier, as well as th e number of turns on

the transformer and the current through it. A frequently

discussed design concept suggests operating at maximum

duty ratio when the input voltage is a minimum. For

simplified calculations, here it is assumed that operating

conditions change as listed immediately below.

- Vac input : 85 ~ 265Vac

- Vdc (rectified voltage) : 100 ~ 400Vdc

- Output voltage: 50Vdc

- Inductor current: Continuous conduction mode (CCM)

operation assumed.

The input power taken by the dc source is the product of the

dc voltage and average input current. Using a wide duty

cycle to deliver equal average current reduces efficiency. A

narrow duty cycle increases the effective current on the

primary side, increasing the operating temperature of the

primary winding and the MOSFET. Also, it is best to decide

on a turns ratio, n, based on the device used. If the voltage on

the primary side MOSFET is relatively low (e.g., 600V),

make n small; if it is on the high side (e.g., 800V), make n

large. As the value of n increases, the primary side switching

device current and the secondary side rectifier diode voltage

decreases Hence, with high output voltage and

multiple secondary side outputs, it is advantageous to

increase n.

t0t1t2t3

VGS

VDS

ILm

0ON OFF

VLm

TON TOFF

TOFF*

Vi+nVOVi

nV0

Vi+nVO

Slpoe=Vi/LmSlope=nVO/Lm

VO+Vi/n VO

IDS

Slope

IiIO

+Vi

2Lm

------------TON

---------TON

T*OFF

---------------------D*

%D*–

-----------------==

ViTONnVOT*OFF

ViTON

()

2IO

----- LmTONTOFF

+()Vi

----------------------------------------------------------------------=

--- LmILm,(peak)

2fsw=

APPLICATIO N NOTE AN4105

4.3.2 Deciding on the operating current mode

As discussed in Sections 4.1 and 4.2, there are two

different operating current modes possible in a flyback

converter: the continuous conduction mode (CCM); and the

dis c ontinuous conduction mode (DCM). He re the

advantages and disadvantages of each are reviewed, to help

the designer make a proper choice between them.

4.3.2.1 Characteristics of the discontinuous

conduction mode

In a flyback converter design, if discontinuous conduction

occurs just at minimum input voltage and maximum output

power, then discontinuous conduction must be considered to

be the case for all input conditions. The flyback converter ’s

input power in discontinuous conduction mode can be

expressed as:

Regardless of any changes in input voltage, the power

equation indicates that the input current is limited by the

peak value of the current flowing through the MOSFET in

the transformer primary. A Fairchild Power Switch (SPS)

has an integ rated overcurre nt protection fea ture (see Sectio n

2.1, above). This feature do es not require external

components and operates across the range of input current.

However, the fixed operating current of DCM, tends

somewhat to offset the effect of the larger effective primary

side current. The gain is at the low frequency end where core

loss i s no t a pr obl em s inc e onl y a min im um n um ber o f tur ns

need be wound. Also, turn on loss is not a serious problem

due to the low input current. Other losses such as eddy

current, skin effect, proximity ef fect, etc., are not significant.

A more clearly defined advantage of DCM operation is that

it permits the use of a slow and hence, low cost secondary

rectifier diode. In contrast to the continuous conduction

mode, in the discontinuous conduction mode the effective

current is higher, requiring the use of heavier wire and hence

thicker coils. Therefore DCM does not bring an advantage

insofar as transformer construction is concerned. Moreover,

DCM causes the MOSFET operating temperature to increase

because of the large effective primary side current, as was

described above (Section 4.3.1).

4.3.2.2 C haracter istics of the

continuous conduction mode

Since the coils’ effective current is decreased CCM brings

the advantage of lighter wire. The smaller effective current

also reduces MOSFET heating. This is a definite advantage

for average input current. On the other hand, CCM operation

brings with it a nee d to consider the rectifier dio de’s reverse

recovery cur rent. Depend ing on the diod e’s rev erse recov ery

time (trr), the reverse recovery current may stress the diode

and increase the loss at its end terminals. It is therefore

necessary to use a diode with the minimum trr possible

within the allowable cost range.

--- LmIP

2fsw=

AN4105 APPLICATION NOTE

Figure 18. The current and volta g e ratings req uired on the primary si de switching device and the secondary side

rectifier diode depend on the turns ratio (n) selected.

4.3.2.3 De sign er’s choice

As is clear from the above discussion, DCM operation can

be advantageous, in terms of cost and efficiency, if the input

is small and it is required to precisely control the input power

through the primary side switch (MOSFET) current. On the

other hand, for large inputs and where switching turn on loss

could be a major problem, a CCM design would be more

advantageous. In conclusion, therefore, the system designer

must decide between the two modes according to which

mode best fits the characteristics of the system being

designed.

n Vi=100V Vi=400V Merits & demerits

VDS

=167V

VD=125V

VDS=467V

VD=317V

-Voltage applied to switch device is

low

-Effective current in switching device

and prim ary w inding is low

-V oltage applied to rectifier diode is

high

-Output voltage ripple is small

-Control must be done through short

turn-on tim e

VDS

=200V

VD=100V VDS=500V

VD=250V

-Intermediate Design Method

VDS

=250V

VD=83V VDS=550V

VD=183V

-Voltage applied to switch device is

high

-Effective current in switching device

and prim ary w inding is high

-V oltage applied to rectifier diode is

low

-Output voltage ripple is largel

-Control must be done through long

turn-on tim e

Vi=100V

nVO=67V

VDS

Vi/n=75V

VO=50V

Vi=100V

nVO=100V

VDS

Vi/n=50V

VO=50V

Vi=100V

nVO=150V

VDS

Vi/n=33V

VO=50V

Vi=400V

nVO=67V

Vi/n=267V

VO=50V

VDS

Vi=400V

nVO=100V

Vi/n=200V

VO=50V

VDS

Vi=400V

nVO=150V

VDS

Vi/n=133V

VO=50V

VDS

VLm

n:&

APPLICATIO N NOTE AN4105

5. The Transforme r

5.1 Why a transformer is needed

There are three reasons for n eeding a transformer in a power

conversion circuit. The first reason is safety. A transformer

affords electrical isolation between the primary and

secondary sides, as shown in Figure 19a. In addition, a true

ground on the output side helps prevent electric shock. The

second reason is for voltage conversion. For example, if a

dc/dc converter (such as the buck converter shown in Figure

19b) switching at 50kHz is used to obtain 5V from 100V.

The duty cycle would only be 5%. Using a 5 0kHz sw itching

frequency, the control circuit may have only about 1µs to

act, which is not an easy task. Even if this were possible, the

internal voltage and current for each eleme nt would be very

large reducing efficiency. The problem is ag gravated at high

output current. In the above example, using a transformer to

lower the voltage to 1 0V would then a llowing an on time o f

about 10µs. This is an advantageous strategy for lowering

cost and raising efficiency. Th e thir d reason to use a

transformer has to do with high voltages and voltage

fluctuations. For example, even though all control for a

1000V supply is done at the 5V power source on the GND

side, a transformer is necessary if power is needed for

current sensing at the 1000V output terminal or for other

control. If the isolation voltage between the transformer

windings is sufficient, a 1000V potential difference can be

safely maintained between the prim ary and secondary

windings and power can be delivered. Further, a transformer

is also required when the power GND has a sudden potential

fluctuation as in a half bridge converter, gate drive power

source.

Figure 19. Why a transformer is needed.

5.2 The ideal transformer

The transformer is a device that uses inductive coupling

between its windings to deliver power or signals from one

winding to the another. This is usually from the primary

winding to the secondary winding. The voltages across the

windings can be raised or lowered with respect to each other,

and, if necessary, the primary and secondary sides can be

isolated from each other. Figure 20 shows an ideal

transformer, a simplistic model useful in describing the

transformer concept. An ideal transformer which is actually

a fictional concept must satisfy the following three

conditions:

1.The coupling coefficient between the windings

is unity (i.e., the leakage flux is zero);

2.The coil loss is zero (the device has no losses).

3.The inductance of each coil is infinite.

AC220V

& Rectifier DC

Output

Electric short when touched Safe to touch

GND

(a) For safty

(b) For voltage change

100V ----> Duty 5% ----> 5V

50kHz --> Ton=1uS

100V --> 10V --> Duty 50% --> 5V

50kHz -> Ton=10uS

10:1

1000V

Vin=100V

Vo=5V

Shock

Safety

AN4105 APPLICATION NOTE

Figure 20. Ideal transformer.

The input to output voltage ratio of an ideal transformer is

directly proportional to the turns ratio. This is the ratio of the

number of turns on the primary winding to the turns on the

secondary. The polarity is represented schematically by the

placement of a dot on each winding. Since n = Vp/Vs, and an

ideal transformer has no loss, the current ratio is inversely

proportional to the turns ratio. The current direction is such

that it enters on o ne side and leaves at another. Th us the sum

of all the nI that flow into the dot is zero. The dot, indicating

the winding polarity, is placed to make the flux direction in

the transformer core uniform when current flows into the

dot. Furthermore, in the case of an ideal transformer, if the

path on the secondary side windings is opened, there is no

secondary current flow, and the current on the primary side

also goes to zero.

5.3 The Real transformer

Significant differences exist between an ideal transformer

and a real one. In a real transformer:

1. The coupling coefficient between each coil is finite, and

when a gap is placed in the core as is done in many power

transformers, the coupling coefficient becomes still smaller

(i.e., there is leakage flux);

2. There are losses, such as iron (hysteresis) loss, eddy current

loss, coil resistance loss, etc.; and,

3. The inductance of each coil is finite. When a gap is

placed in the core the inductance becomes still smaller.

In a real transformer, should the secondary side be opened

current would continue to flow in the primary (as in 3,

above). So, while energy cannot be stored in the ideal

transformer, it is stored in a real transformer. The so-called

magnetizing inductance accounts for this energy storage

phenomenon. The circui t of F igure 21 is a simp listic view of

an actual transformer and shows the magnetizing inductance.

Figure 22 presents a more complete equivalent circuit of a

real transformer, showing inductances and loss resistances.

Figure 21. A m od el of an actual transformer sh ow ing the

magnetizing inductance Lm, which accounts for energy

storage.

Figure 22. A more complete equivalent circuit of an actual

transform er, showing induct ances an d loss resistances.

6. Transform er Desi gn

6.1 Core selection

The maximum power that a tran sf ormer core can deliver an d

the maximum energy a transformer inductor can store

depends on the shape and size of the core. In general, as the

effective cross sectional area (Ae) increases, more power can

be delivered. Also, as the window area (Aw) on which the

coils are wound increases, more and thicker wind ings can be

used, allowing a further increase in the power that can be

delivered. The product of Aw and Ae is called the area

product, AP, and the maximum power a transformer can

deliver is proportional to an exponential power of AP.

Indeed, recent transformer theory shows designs depending

almost entirely on AP. In the broader view, a flyback

converter transformer can be viewed as a coupled inductor,

so it's common to design a flyback transformer using

inductor design methods. The two equations below, (a) and

(b), represent two ways to calculate AP. Equation (a) below,

is a met hod base d on whet her or no t the core i s satur ated, is

appropriate at low operating freq uencies. Equation (b),

limited by core loss, is appropriate at high frequencies. For

VPVS

IPIS

NP:N

VP:V

S=NP:N

IP:I

S=NS:N

VPVS

IPIS

NP:N

VP:V

S=NP:N

IP*:I

S=NS:N

IP*

Ideal Transformer

RsRp Llp Lls

Ideal Transformer

- Rp:Primary side winding resistance

- Rs:Secondary side winding resistance

- Llp:Primary side leakage inductance

- Lls:Secondary side leakage inductance

- Lm:Magnetizing inductance

- Rm:Transformer core loss resistance

APPLICATIO N NOTE AN4105

any given design, it is necessary to calculate AP using both

equations, and the equation that gives the higher value is the

one that must be considered correct. Equation (a) assumes

that all losses are wire losses and ignores the core (iron) loss.

L and BMAX are in Henries and Tesla units, respectively, and

K is listed in Table 1, below. From the above equation the

current density (J) per unit area of wire is obtained from the

current by the relationship below, which assumes that the

temperature of the inductor’s “hot spot” is 30°C above

ambient.

At any operating frequency high enough so that the core

losses become large, the following equation should be used.

Specifically, it assumes that the total transformer losses are

split equally (50/50) between the wire and the core.

In equation (b), KH is the hysteresis co efficient (typicall y 4 x

10-5 for ferrite cores) and KE is the eddy current coefficient

(typically 4 x 10-10 for ferrite cores). T he current density

relationship here, represented by the equation for J30, below,

assumes a hot spot temperature of 15°C above ambient, with

the iron loss adding on an additional 15°C (again, a total of

30°C above ambie nt) .

The pa ra mete r K in eq uat ion (a) i s th e prod uct of th e win do w

utilization factor KU with the primary area factor KP. (See

Table 1.) KU is the ratio of the cross sectional area of the

winding’s copper to the entire window area, and it is

significant in setting the isolation between the primary and

secondary sides. Because it is related to the transformer

shape and winding method, the designer should know the

value of KU for the transformer usually used. The value of

KU can vary greatly, depending particularly on how closely

the isolation safety standards (re isolatio n) are followed; the

KU of Table 1 assumes a general bobbin is used. KP is the

ratio of the area of the primary winding to that of the total

winding. In Table 1, it is unity for the inductors because a

buck boost inductor has no secondary windings. For the

flyback transformer coupled inductor, KP is usually 0.5, as

Table 1 shows; such an inductor has the highest efficiency

when the primary and secondary winding areas are equal.

When there are more secondary windings, however, the KP

for a flyback transformer coupled inducto r can be lower than

0.5. Note that the ease and speed of obtaining an accurate AP

from equa t ions (a) and (b) de pe n ds on t he designer' s

experience. A reasonably good knowledge of the probable

values of the three parameters KU, KP, and J for the flyback

transformer being designed will reduce the number of trial

and error attempts necessary.

AP LIPIRMS%04

420KBMAX

---------------------------------







%.3%

cm2

[] a) =

L = Inductance of Transformer

Ip = Operating peak current

Bmax = MAximum operating flux density

Irms = RMS current

J30 420 AP 0.24–Acm

⁄[]=

AP L∆ImIRMS104

130K

------------------------------------------







1.58

KHfSW KEfsw

()

+()

0.66 cm2

[]b)=

L = Inductance of Transformer

Ip = Operating peak current

Irms = RMS current

J30 297AP 0.24–Acm

⁄[]=

AN4105 APPLICATION NOTE

6.2 Determination of t he nu mber of turns

Although the equation for the minimum number of flyback

transformer turns can be determined using applied voltage

and maximum turn on time, the equations used here are

derived from the relationship between L and IP. For an AP

determined from equation (a), above, calculate NMIN using

the following equations:

For an AP determined from equation (b), above, calculate

NMIN using the following equations:

6.3 The windings

The cross sectional area of the winding must be obtained

from the calculated effective current and the current density

(from the appropriate eq uation above), factoring in the

number of turns (as determined from a calculation of

NMIN). If eddy current loss is not a serious problem simply

divide the effective current by the current density, thereby

determining the coil cross sectional area. Be aware,

however, that as the coil becomes thicker, the problem of

eddy current loss will arise. Using twisted thin coil strands

(Litz wire), instead of a single heavy wire, can reduce the

eddy current loss, but KU will become smaller.

6.4 Determination of the gap

It is not easy to precisely calculate the required gap.

However, the gap can be calculated from the following

equat ion. It i s based on the fringing effect of the surroundi ng

flux. Note that the calculated value of L is usually lar ger than

required.

Therefore, the gap must be changed to obtain the required

value of L.

References

1. Transformer and Inductor Design Handbook. 2nd ed.

Col. Wm. T. McLyman. Marcel Dekker, Inc., 1988.

2. Swi tch Mode Power Supply Handbook. Keith H .

Billings. McGraw-Hill, Inc., 1989.

Table 1. KU, KP, and K

KU K

P K = KU KP

CCM Buck, Boost Inductor 0.7 1.0 0.7

DCM Buck, Boost Inductor 0.7 1.0 0.7

CCM Flyback Transformer 0.4 0.5 0.2

DCM Flyback Transformer 0.4 0.5 0.2

NMIN LIP

BMAXAC

-----------------------104

L = Inductance of Transformer

Ip = Operating peak current

Bmax = Maximum operating flux density

Ae = Effective cross-sectional area of core

NMIN L∆Im

∆BmAC

--------------------104

L = Inductance of Transformer

Ip = Operating peak current

Bmax = Maximum operating flux density

Ae = Effective cross-sectional area of core

IguOurN2AC

----------------------------10 2–cm[]=

Uo = Permeability of free space

Ur = Relative permeability

APPLICATIO N NOTE AN4105

AN4105 APPLICATION NOTE

4/17/01 0.0m 002

Stock#ANxxxxxxxxx

 2001 Fairchild Semi conductor Corporation

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