LTC4236CUFD-2#PBF - ANALOG DEVICES

LTC4236

4236f

For more information www.linear.com/LTC4236

Typical applicaTion

FeaTures DescripTion

Dual Ideal Diode-OR and

Single Hot Swap Controller

with Current Monitor

The LT C

4236 offers ideal diode-OR and Hot Swap func-

tions for two power rails by controlling external N-channel

MOSFETs. MOSFETs acting as ideal diodes replace two

high power Schottky diodes and the associated heat sinks,

saving power and board area. A Hot Swap control MOSFET

allows a board to be safely inserted and removed from a

live backplane by limiting inrush current. The supply output

is also protected against short-circuit faults with a fast

acting foldback current limit and electronic circuit breaker.

The LTC4236 regulates the forward voltage drop across

the ideal diode MOSFETs to ensure smooth current transfer

from one supply to the other without oscillation. The ideal

diode MOSFETs turn on quickly to reduce the load voltage

droop during supply switchover. If the input supply fails

or is shorted, a fast turn-off minimizes reverse current

transients.

A current sense amplifier translates the voltage across the

sense resistor to a ground referenced signal. The LTC4236

provides adjustable start-up delay, turn-on/-off control,

and reports fault and power good status for the supply.

applicaTions

n Ideal Diode-OR and Inrush Current Control for

Redundant Supplies

n Low Loss Replacement for Power Schottky Diodes

n Enables Safe Board Insertion into a Live Backplane

n 2.9V to 18V Operating Range

n Current Monitor Output

n Controls N-Channel MOSFETs

n Limits Peak Fault Current in ≤ 1µs

n Adjustable Current Limit with Foldback

n Adjustable Start-Up and Current Limit Fault Delay

n 0.5µs Ideal Diode Turn-On and Turn-Off Time

n Smooth Switchover without Oscillation

n Fault, Power Good and Diode Status Outputs

n LTC4236-1: Latch Off After Fault

n LTC4236-2: Automatic Retry After Fault

n 28-Pin 4mm x 5mm QFN Package

n Redundant Power Supplies

n High Availability Systems and Servers

n Telecom and Network Infrastructure

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 7920013, 8022679.

Ideal Diode-OR with Hot Swap Application

ADC

SENSE+SENSE–

CS+

12V

CPO1

GND

13.7k

CLOAD

12V

INTVCC D2OFF

IN1 DGATE1 DGATE2

LTC4236

4236 TA01a

SiR158DP SiR158DP0.003Ω

HGATE OUTCPO2

0.1µF

IN2D2SRC

0.1µF

SiR158DP

0.1µF0.1µF

DTMR

0.1µF

FTMR

REG

0.1µF

FAULT

PWRGD

DSTAT1

DSTAT2

15k

IMON

Smooth Supply Switchover

200ms/DIV

IN1

1V/DIV

IN2

1V/DIV

IN2

IN1

IIN1

2A/DIV

IIN2

2A/DIV

4236 TA01b

LTC4236

4236f

For more information www.linear.com/LTC4236

absoluTe MaxiMuM raTings

Supply Voltages

IN1, IN2 .................................................. –0.3V to 24V

INTVCC ..................................................... –0.3V to 7V

REG ...........................SENSE+ – 5V to SENSE+ + 0.3V

Input Voltages

ON, D2OFF, EN ...................................... –0.3V to 24V

FTMR, DTMR ......................... –0.3V to INTVCC + 0.3V

FB ............................................................ –0.3V to 7V

SENSE+, SENSE–, CS+, D2SRC .............. –0.3V to 24V

Output Voltages

IMON ....................................................... –0.3V to 7V

FA U LT, PWRGD, DSTAT1, DSTAT2 ........... –0.3V to 24V

CPO1, CPO2 (Notes 3, 4) ....................... –0.3V to 35V

DGATE1, DGATE2 (Notes 3, 4) ............... –0.3V to 35V

HGATE (Note 5) ..................................... –0.3V to 35V

OUT ....................................................... –0.3V to 24V

Average Currents

FA U LT, PWRGD, DSTAT1, DSTAT2 ......................... 5mA

INTVCC ...............................................................10mA

Operating Ambient Temperature Range

LTC4236C ................................................ 0°C to 70°C

LTC4236I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

9 10

TOP VIEW

UFD PACKAGE

28-LEAD (4mm × 5mm) PLASTIC QFN

11 12 13

28 27 26 25 24

SENSE–

SENSE+

CS+

IN1

INTVCC

GND

IN2

D2SRC

FAULT

DSTAT1

DSTAT2

D2OFF

REG

DGATE1

CPO1

HGATE

OUT

PWRGD

DGATE2

CPO2

DTMR

FTMR

IMON

815

TJMAX = 125°C, θJA = 43°C/W (NOTE 6)

EXPOSED PAD (PIN 29) PCB GND CONNECTION OPTIONAL

pin conFiguraTion

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4236CUFD-1#PBF LTC4236CUFD-1#TRPBF 42361 28-Lead (4mm x 5mm) Plastic QFN 0°C to 70°C

LTC4236CUFD-2#PBF LTC4236CUFD-2#TRPBF 42362 28-Lead (4mm x 5mm) Plastic QFN 0°C to 70°C

LTC4236IUFD-1#PBF LTC4236IUFD-1#TRPBF 42361 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C

LTC4236IUFD-2#PBF LTC4236IUFD-2#TRPBF 42362 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

(Notes 1, 2)

LTC4236

4236f

For more information www.linear.com/LTC4236

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VIN Input Supply Range l2.9 18 V

IIN Input Supply Current l2.7 4 mA

VINTVCC Internal Regulator Voltage I = 0, –500µA l4.5 5 5.5 V

VINTVCC(UVL) Internal VCC Undervoltage Lockout INTVCC Rising l2.1 2.2 2.3 V

∆VINTVCC(HYST) Internal VCC Undervoltage Lockout Hysteresis l30 60 90 mV

Ideal Diode Control

∆VFWD(REG) Forward Regulation Voltage

(VINn – VSENSE+)

l2 15 28 mV

∆VDGATE External N-Channel Gate Drive

(VDGATE1 – VIN1) and (VDGATE2 – VD2SRC)

IN < 7V, ∆VFWD = 0.15V; I = 0, –1µA

IN = 7V to 18V, ∆VFWD = 0.15V; I = 0, –1µA

∆VDGATE(ST) Diode MOSFET On Detect Threshold

(VDGATE1 – VIN1) and (VDGATE2 – VD2SRC)

DSTAT Pulls Low, ∆VFWD = 50mV l 0.3 0.7 1.1 V

ID2SRC D2SRC Pin Current D2SRC = 0Vl–90 –130 µA

ICPO(UP) CPOn Pull-Up Current CPO = IN = D2SRC = 2.9V

CPO = IN = D2SRC = 18V

–60

–50

–100

–90

–130

–120

µA

IDGATE(FPU) DGATEn Fast Pull-Up Current ∆VFWD = 0.2V, ∆VDGATE = 0V, CPO = 17V –1.5 A

IDGATE(FPD) DGATEn Fast Pull-Down Current ∆VFWD = –0.2V, ∆VDGATE = 5V 1.5 A

IDGATE2(DN) DGATE2 Off Pull-Down Current D2OFF = 2V, ∆VDGATE2 = 2.5V l50 100 200 µA

tON(DGATE) DGATEn Turn-On Delay ∆VFWD = 0.2V , CDGATE = 10nF l0.25 0.5 µs

tOFF(DGATE) DGATEn Turn-Off Delay ∆VFWD = –0.2V, CDGATE = 10nF l0.2 0.5 µs

tPLH(DGATE2) D2OFF Low to DGATE2 High l50 100 µs

Hot Swap Control

∆VSENSE(TH) Current Limit Sense Voltage Threshold

(VSENSE+ – VSENSE–)

FB = 1.3V

FB = 0V

22.5

5.8

8.3

27.5

10.8

VSENSE+(UVL) SENSE+ Undervoltage Lockout SENSE+ Rising l1.8 1.9 2 V

∆VSENSE+(HYST)SENSE+ Undervoltage Lockout Hysteresis l10 50 90 mV

ISENSE+ SENSE+ Pin Current SENSE+ = 12V l 0.3 0.8 1.3 mA

ISENSE–SENSE– Pin Current SENSE– = 12V l10 40 100 µA

ICS+ CS+ Pin Current CS+ = 12V, ∆VSENSE = 0V l ±1 µA

∆VHGATE External N-Channel Gate Drive

(VHGATE–VOUT)

IN < 7V, I = 0, –1µA

IN = 7V to 18V, I = 0, –1µA

∆VHGATE(H) Gate High Threshold (VHGATE – VOUT)l3.6 4.2 4.8 V

IHGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V l–7 –10 –13 µA

IHGATE(DN) External N-Channel Gate Pull-Down Current Gate Drive Off, OUT = 12V,

HGATE = OUT + 5V

l1 2 4 mA

IHGATE(FPD) External N-Channel Gate Fast Pull-Down

Current

Fast Turn-Off, OUT = 12V,

HGATE = OUT + 5V

l100 200 350 mA

tPHL(SENSE) Sense Voltage (SENSE+ – SENSE–)

High to HGATE Low

∆VSENSE = 200mV, CHGATE = 10nF l 0.5 1 µs

tOFF(HGATE) ON Low to HGATE Low

EN High to HGATE Low

SENSE+ Low to HGATE Low

SENSE+ UVLO

µs

tD(HGATE) ON High, EN Low to HGATE Turn-On Delay DTMR = INTVCC l 50 100 150 ms

tP(HGATE) ON to HGATE Propagation Delay ON = Step 0.8V to 2V l10 20 µs

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.

LTC4236

4236f

For more information www.linear.com/LTC4236

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Inputs

VD2OFF(H,TH) D2OFF Pin High Threshold D2OFF Rising l1.21 1.235 1.26 V

VD2OFF(L,TH) D2OFF Pin Low Threshold D2OFF Falling l1.19 1.215 1.24 V

∆VD2OFF(HYST) D2OFF Pin Hysteresis l10 20 30 mV

VIN(TH) ON, FB Pin Threshold Voltage Voltage Rising l1.21 1.235 1.26 V

∆VON(HYST) ON Pin Hysteresis l40 80 120 mV

∆VFB(HYST) FB Pin Hysteresis l10 20 30 mV

VON(RESET) ON Pin Fault Reset Threshold Voltage ON Falling l0.57 0.6 0.63 V

IIN(LEAK) Input Leakage Current (ON, FB, D2OFF) V = 5V l0 ±1 µA

VEN(TH) EN Pin Threshold Voltage EN Rising l1.185 1.235 1.284 V

∆VEN(HYST) EN Pin Hysteresis l60 110 200 mV

IEN(UP) EN Pull-Up Current EN = 1V l –7 –10 –13 µA

VTMR(H) FTMR, DTMR Pin High Threshold l 1.198 1.235 1.272 V

VTMR(L) FTMR, DTMR Pin Low Threshold l0.15 0.2 0.25 V

IFTMR(UP) FTMR Pull-Up Current FTMR = 1V, In Fault Mode l –80 –100 –120 µA

IFTMR(DN) FTMR Pull-Down Current FTMR = 2V, No Faults l 1.3 2 2.7 µA

DRETRY Auto-Retry Duty Cycle l 0.07 0.15 0.23 %

IDTMR(UP) DTMR Pull-Up Current DTMR = 0.6V l –8 –10 –12 µA

IDTMR(DN) DTMR Pull-Down Current DTMR = 1.5V l 1 5 10 mA

∆VDTMR(TH) DTMR Pin Threshold Voltage

(VDTMR – VINTVCC)

tD(HGATE) Start-Up Delay l–0.1 –0.3 –0.5 V

tRST(ON) ON Low to FAULT High l20 40 µs

tPG(FB) FB Low to PWRGD High l20 40 µs

Outputs

IOUT OUT Pin Current OUT = 11V, IN = 12V, ON = 2V

OUT = 13V, IN = 12V, ON = 2V

2.5

100

µA

VOL Output Low Voltage

(FAULT, PWRGD, DSTAT1, DSTAT2)

I = 1mA

I = 3mA

0.15

0.4

1.2

VOH Output High Voltage (FAULT, PWRGD) I = –1µA lINTVCC – 1 INTVCC – 0.5 V

IOH Input Leakage Current

(FAULT, PWRGD, DSTAT1, DSTAT2)

V = 18V l0 ±1 µA

IPU Output Pull-Up Current (FAULT, PWRGD) V = 1.5V l–7 –10 –13 µA

Current Monitor

∆VREG Floating Regulator Voltage

(VSENSE+ – VREG)

IREG = ±1µA l3.6 4.1 4.6 V

∆VSENSE(FS) Input Sense Voltage Full Scale

(VSENSE+ – VSENSE–)

SENSE+ = 12V l25 mV

VIMON(OS) IMON Input Offset Voltage ∆VSENSE = 0V l ±150 µV

GIMON IMON Voltage Gain ∆VSENSE = 20mV and 5mV l 99 100 101 V/V

VIMON(MAX) IMON Maximum Output Voltage ∆VSENSE = 70mV, 5V ≤ SENSE+ ≤ 18V

∆VSENSE = 35mV, SENSE+ = 2.9V

3.5

2.7

5.5

2.9

VIMON(MIN) IMON Minimum Output Voltage ∆VSENSE = 200µV l 40 mV

RIMON(OUT) IMON Output Resistance ∆VSENSE = 200µV l 15 20 27 kΩ

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.

LTC4236

4236f

For more information www.linear.com/LTC4236

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

specified.

Note 3: An internal clamp limits the DGATE1 and CPO1 pins to a minimum

of 10V above and a diode below IN1. Driving these pins to voltages beyond

the clamp may damage the device.

Note 4: An internal clamp limits the DGATE2 and CPO2 pins to a minimum

of 10V above and a diode below D2SRC. Driving these pins to voltages

beyond the clamp may damage the device.

Note 5: An internal clamp limits the HGATE pin to a minimum of 10V

above and a diode below OUT. Driving this pin to voltages beyond the

clamp may damage the device.

Note 6: Thermal resistance is specified when the exposed pad is soldered

to a 3" x 5" , four layer, FR4 board.

LTC4236

4236f

For more information www.linear.com/LTC4236

Typical perForMance characTerisTics

Hot Swap Gate Voltage vs Current

Hot Swap Gate Voltage vs IN

Voltage CPO Voltage vs Current

Diode Gate Voltage vs Current Diode Gate Voltage vs IN Voltage

FAULT, PWRGD, DSTAT1, DSTAT2

Output Low Voltage vs Current

IN Supply Current vs Voltage SENSE+ Current vs Voltage OUT Current vs Voltage

TA = 25°C, VIN = 12V, unless otherwise noted.

VIN (V)

IIN (mA)

3.5

2.5

1.5

0.5

06 12

4236 G01

183 159

VSENSE+ = VIN – 0.5V

VOUT = 12V

VOUT = 0V

VOUT = 3.3V

VSENSE+ (V)

ISENSE+ (mA)

1.4

1.2

0.8

0.4

0.6

0.2

06 12

4236 G02

183 159

VOUT (V)

IOUT (mA)

3.5

2.5

1.5

0.5

–0.5

6 12

4236 G03

183 159

VIN = 12V, VSENSE+ = 11.5V

IHGATE (µA)

∆VHGATE (V)

0–4 –8

4236 G04

–12–2 –10–6

VOUT = VIN

VIN = 12V

VIN = 2.9V

VIN (V)

∆VHGATE (V)

46 12

4236 G05

183 159

VOUT = VIN

ICPO (µA)

VCPO – VIN (V)

–2 –40 –120–80

4236 G06

–140–20 –100–60

VIN = 18V

VIN = 2.9V

IDGATE (µA)

∆VDGATE (V)

–2 –40 –120–80

4236 G07

–140–20 –100–60

VSENSE+ = VIN – 0.15V

VIN = 18V

VIN = 2.9V

VIN (V)

∆VDGATE (V)

46 12

4236 G08

183 159

VSENSE+ = VIN – 0.15V

CURRENT (mA)

OUTPUT LOW VOLTAGE (V)

0.6

0.2

0.8

0.4

02 4

4236 G09

51 3

VIN = 12V

VIN = 2.9V

LTC4236

4236f

For more information www.linear.com/LTC4236

Typical perForMance characTerisTics

IMON Voltage vs Sense Voltage

IMON Voltage Gain vs

Temperature

IMON Propagation Delay vs

Sense Voltage

Adjustable HGATE Start-Up Delay

with 0.1µF Capacitor at DTMR pin

Ideal Diode Start-Up Waveform

on IN Power-Up

100ms HGATE Start-Up Delay with

DTMR Pin Connected to INTVcc

Current Limit Threshold Foldback

Current Limit Delay vs Sense

Voltage

Current Sense Amplifier Input

Offset Voltage vs Temperature

TA = 25°C, VIN = 12V, unless otherwise noted.

FB VOLTAGE (V)

CURRENT LIMIT SENSE VOLTAGE

VSENSE+ – VSENSE– (mV)

00.4 0.8

4236 G10

1.41.20.2 1.00.6

SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV)

CURRENT LIMIT DELAY (µs)

100

0.1 80 120

4236 G11

20040 160

CHGATE = 10nF

10ms/DIV

10V/DIV

SENSE+

10V/DIV

4236 G16

CPO

DGATE

20ms/DIV

5V/DIV

HGATE

10V/DIV

OUT

10V/DIV

PWRGD

10V/DIV

4236 G17 20ms/DIV

5V/DIV

HGATE

10V/DIV

OUT

10V/DIV

PWRGD

10V/DIV

4236 G18

TEMPERATURE (°C)

–50

INPUT OFFSET VOLTAGE (µV)

–30

–20

–10

–40 0 75

4236 G12

100–25 5025

VIN = 12V

VIN = 2.9V

IMON VOLTAGE (V)

020

4236 G13

5010 4030

VIN = 12V

VIN = 2.9V

SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV) TEMPERATURE (°C)

–50

IMON VOLTAGE GAIN (V/V)

101

100

100.5

99.5

99 0 75

4236 G14

100–25 5025

VIN = 12V

VIN = 2.9V

IMON PROPAGATION DELAY (µs)

120

100

4236 G15

51 43

SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV)

LTC4236

4236f

For more information www.linear.com/LTC4236

pin FuncTions

CPO1, CPO2: Charge Pump Output. Connect a capacitor

from CPO1 or CPO2 to the corresponding IN1 or D2SRC

pin. The value of this capacitor is approximately 10×

the gate capacitance (CISS) of the external MOSFET for

ideal diode control. The charge stored on this capacitor

is used to pull up the ideal diode MOSFET gate during a

fast turn-on. Leave this pin open if fast ideal diode turn-

on is not needed.

CS+: Positive Current Sense Input for Current Sense Am-

plifier. Connect this pin to the input of the current sense

resistor. The voltage between CS+ and SENSE– is translated

to a ground referenced signal at IMON pin.

DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Out-

put. Connect this pin to the gate of an external N-channel

MOSFET for ideal diode control. An internal clamp limits

the gate voltage to 12V above and a diode voltage below

IN1 or D2SRC. During fast turn-on, a 1.5A pull-up charges

DGATE from CPO. During fast turn-off, a 1.5A pull-down

discharges DGATE1 to IN1 and DGATE2 to D2SRC.

D2OFF: Control Input. A rising edge above 1.235V turns

off the external ideal diode MOSFET in the IN2 supply path

and a falling edge below 1.215V allows the MOSFET to be

turned on. Connect this pin to an external resistive divider

from IN1 to make IN1 the higher priority input supply when

IN1 and IN2 are equal.

D2SRC: Ideal Diode MOSFET Gate Drive Return. Connect

this pin to the source of the external N-channel MOSFET

switch in the IN2 power path. The gate fast pull-down cur-

rent returns through this pin when DGATE2 is discharged.

DSTAT1: Diode MOSFET Status Output. Open drain out-

put that pulls low when the MOSFET gate drive voltage

between DGATE1 and IN1 exceeds 0.7V indicating that the

MOSFET diode path is on. Otherwise it goes high imped-

ance. It requires an external pull-up resistor to a positive

supply. Leave open if unused.

DSTAT2: Diode MOSFET Status Output. Open drain out-

put that pulls low when the MOSFET gate drive voltage

between DGATE2 and D2SRC exceeds 0.7V indicating

that the MOSFET diode path is on. Otherwise it goes high

impedance. It requires an external pull-up resistor to a

positive supply. Leave open if unused.

DTMR: Debounce Timer Capacitor Terminal. Connect

this pin to either INTVCC for fixed 100ms delay or an

external capacitor to ground for adjustable start-up delay

(123ms/µF) when EN toggles low.

EN: Enable Input. Ground this pin to enable Hot Swap

control. If this pin is pulled high, the Hot Swap MOSFET

is not allowed to turn on. A 10µA current source pulls this

pin up to a diode below INTVCC. Upon EN going low when

ON is high, there is a start-up delay for debounce as con-

figured at the DTMR pin, after which the fault is cleared.

FAUL

T: Overcurrent Fault Status Output. Output that pulls

low when the fault timer expires during an overcurrent

fault. Otherwise it is pulled high by a 10µA current source

to a diode below INTVCC. It may be pulled above INTVCC

using an external pull-up. Leave open if unused.

FB: Foldback and Power Good Comparator Input. Connect

this pin to an external resistive divider from OUT. If the

voltage falls below 1.215V, the PWRGD pin pulls high to

indicate the power is bad. If the voltage falls below 0.9V,

the output power is considered bad and the current limit

is reduced. Tie to INTVCC to disable foldback.

FTMR: Fault Timer Capacitor Terminal. Connect a capacitor

between this pin and ground to set a 12ms/µF duration

for current limit before the external Hot Swap MOSFET is

turned off. The duration of the off time is 8s/µF, resulting

in a 0.15% duty cycle.

GND: Device Ground.

LTC4236

4236f

For more information www.linear.com/LTC4236

pin FuncTions

HGATE: Hot Swap MOSFET Gate Drive Output. Connect

this pin to the gate of the external N-channel MOSFET for

Hot Swap control. An internal 10µA current source charges

the MOSFET gate. An internal clamp limits the gate volt-

age to 12V above and a diode voltage below OUT. During

an undervoltage generated turn-off, a 2mA pull-down

discharges HGATE to ground. During an output short or

INTVCC undervoltage lockout, a fast 200mA pull-down

discharges HGATE to OUT.

IN1, IN2: Positive Supply Input and Ideal Diode MOSFET

Gate Drive Return. Connect this pin to the power input

side of the external ideal diode MOSFET. The 5V INTVCC

supply is generated from IN1, IN2 and OUT via an internal

diode-OR. The voltage sensed at this pin is used to control

DGATE. The gate fast pull-down current returns through

IN1 pin when DGATE1 is discharged.

INTVCC: Internal 5V Supply Decoupling Output. This pin

must have a 0.1µF or larger capacitor to GND. An external

load of less than 500µA can be connected at this pin. An

undervoltage lockout threshold of 2.2V will turn off both

MOSFETs.

IMON: Current Sense Monitoring Output. This pin voltage

is proportional to the sense voltage across the current

sense resistor with a voltage gain of 100. An internal 20k

resistor is connected from this pin to ground.

ON: ON Control Input. A rising edge above 1.235V turns

on the external Hot Swap MOSFET and a falling edge below

1.155V turns it off. Connect this pin to an external resistive

divider from SENSE+ to monitor the supply undervoltage

condition. Pulling the ON pin below 0.6V resets the fault

latch after an overcurrent fault. Tie to INTVCC if unused.

OUT: Hot Swap MOSFET Gate Drive Return. Connect this

pin to the output side of the external MOSFET. The gate

fast pull-down current returns through this pin when

HGATE is discharged.

PWRGD: Power Status Output. Output that pulls low when

the FB pin rises above 1.235V and the MOSFET gate drive

between HGATE and OUT exceeds 4.2V. Otherwise it is

pulled high by a 10µA current source to a diode below

INTVCC. It may be pulled above INTVCC using an external

pull-up. Leave open if unused.

REG: Internal Regulated Supply for Current Sense Ampli-

fier. A 0.1µF or larger capacitor should be tied from REG to

SENSE+. This pin is not designed to drive external circuits.

SENSE+: Positive Current Sense Input. Connect this pin

to the diode-OR output of the external ideal diode MOS-

FETs and input of the current sense resistor. The voltage

sensed at this pin is used for monitoring the current limit

and also to control DGATE for forward voltage regulation

and reverse turn-off. This pin has an undervoltage lockout

threshold of 1.9V that will turn off the Hot Swap MOSFET.

SENSE–: Negative Current Sense Input. Connect this pin

to the output of the current sense resistor. The current

limit circuit controls HGATE to limit the voltage between

SENSE+ and SENSE– to 25mV or less depending on the

voltage at the FB pin.

LTC4236

4236f

For more information www.linear.com/LTC4236

block DiagraM

–

GD1

–

1.235V

–

0.2V

TM2

1.235V

FTMR

TM1

TM4

TM3

10µA

INTVCC

100µA

2µA

INTVCC

LOGIC

4236 BD

GATE

DRIVER

CPO1

0.9V

FOLDBACK

INTVCC

10µA

INTVCC

10µA

FAULT

PWRGD

CPO2

IMON

IN1 SENSE–IN2SENSE+

PG1

PG2

OUT

4.2V

HGATE

DSTAT1

IN1

0.7V

DGATE1

DSTAT2

D2SRC

0.7V

DGATE2

UVLO1

UVLO2

1.9V

2.2V

SENSE+

1.235V

–

0.6V

RST

FAULT RESET

1.235V

HGATE ON

DGATE2 OFF

–

1.235V

DOFF

D2OFF

5V LDO

CHARGE

PUMP 2

f = 2MHz

100µA

CHARGE

PUMP 1

f = 2MHz

10µA

DGATE1 DGATE2

15mV15mV

GD2

12V12V

12V

REGCS+

OUT 20k

200Ω

4.1V

HGATE

D2SRC

DSTAT2

DSTAT1

EXPOSED PAD

–

0.2V

1.235V

DTMR

INTVCC

0.3V

10µA

GND

LTC4236

4236f

For more information www.linear.com/LTC4236

operaTion

The LTC4236 functions as an input supply diode-OR with

inrush current limiting and overcurrent protection by

controlling the external N-channel MOSFETs (MD1, MD2

and MH) on a supply path. This allows boards to be safely

inserted and removed in systems with a backplane powered

by redundant supplies. The LTC4236 has a single Hot Swap

controller and two separate ideal diode controllers, each

providing independent control for the two input supplies.

When the LTC4236 is first powered up, the gates of the

external MOSFETs are held low, keeping them off. As the

DGATE2 pull-up can be disabled by the D2OFF pin, DGATE2

will pull high only when the D2OFF pin is pulled low. The

gate drive amplifier (GD1, GD2) monitors the voltage be-

tween the IN and SENSE+ pins and drives the respective

DGATE pin. The amplifier quickly pulls up the DGATE pin,

turning on the MOSFET for ideal diode control, when it

senses a large forward voltage drop. With the ideal diode

MOSFETs acting as input supply diode-OR, the SENSE+

pin voltage rises to the highest of the supplies at the IN1

and IN2 pins. An external capacitor connected at the CPO

pin provides the charge needed to quickly turn on the

ideal diode MOSFET. An internal charge pump charges

up this capacitor at device power-up. The DGATE pin

sources current from the CPO pin and sinks current into

the IN1, D2SRC and GND pins. When the DGATE1 to IN1

or DGATE2 to D2SRC voltage exceeds 0.7V, the respec-

tive DSTAT pin pulls low to indicate that the ideal diode

MOSFET is turned on.

Pulling the ON pin high and EN pin low initiates a debounce

timing cycle that can be a fixed 100ms or adjustable delay

as configured at the DTMR pin. After this timing cycle, a

10µA current source from the charge pump ramps up

the HGATE pin. When the Hot Swap MOSFET turns on,

the inrush current is limited at a level set by an external

sense resistor (RS) connected between the SENSE+ and

SENSE– pins. An active current limit amplifier (CL) servos

the gate of the MOSFET to 25mV or less across the cur-

rent sense resistor depending on the voltage at the FB

pin. Inrush current can be further reduced, if desired, by

adding a capacitor from HGATE to GND. When FB voltage

rises above 1.235V and the MOSFET’s gate drive (HGATE

to OUT voltage) exceeds 4.2V, the PWRGD pin pulls low.

The high side current sense amplifier (CM) provides ac-

curate monitoring of current through the current sense

resistor. The sense voltage is amplified by 100 times and

level shifted from the positive rail to a ground-referred

output at the IMON pin. The output signal is analog and

may be used as is or measured with an ADC.

When the ideal diode MOSFET is turned on, the gate drive

amplifier controls DGATE to servo the forward voltage

drop (VIN – VSENSE+) across the MOSFET to 15mV. If the

load current causes more than 15mV of voltage drop,

the gate voltage rises to enhance the MOSFET. For large

output currents, the MOSFET’s gate is driven fully on and

the voltage drop is equal to ILOAD•RDS(ON) of the MOSFET.

In the case of an input supply short-circuit when the

MOSFETs are conducting, a large reverse current starts

flowing from the load towards the input. The gate drive

amplifier detects this failure condition and turns off the

ideal diode MOSFET by pulling down the DGATE pin.

the case where an overcurrent fault occurs on the supply

output, the current is limited with foldback. After a delay

set by 100µA charging the FTMR pin capacitor, the fault

timer expires and pulls the HGATE pin low, turning off the

Hot Swap MOSFET. The FAULT pin is also latched low. At

this point, the DGATE pin continues to pull high and keeps

the ideal diode MOSFET on.

Internal clamps limit both the DGATE1 and CPO1 to IN1,

and DGATE2 and CPO2 to D2SRC voltages to 12V. The

same clamps also limit the DGATE and CPO pins to a diode

voltage below the IN1 or D2SRC pins. Another internal

clamp limits the HGATE to OUT voltage to 12V and also

clamps the HGATE pin to a diode voltage below the OUT pin.

Power to the LTC4236 is supplied from either the IN or

OUT pins, through an internal diode-OR circuit to a low

dropout regulator (LDO). That LDO generates a 5V supply

at the INTVCC pin and powers the LTC4236’s internal low

voltage circuitry.

LTC4236

4236f

For more information www.linear.com/LTC4236

High availability systems often employ parallel-connected

power supplies or battery feeds to achieve redundancy and

enhance system reliability. Power ORing diodes are com-

monly used to connect these supplies at the point of load at

the expense of power loss due to significant diode forward

voltage drop. The LTC4236 minimizes this power loss by

using external N-channel MOSFETs as the pass elements,

allowing for a low voltage drop from the supply to the load

when the MOSFETs are turned on. When an input source

voltage drops below the output common supply voltage,

the appropriate MOSFET is turned off, thereby matching

the function and performance of an ideal diode. By adding

a current sense resistor and a Hot Swap MOSFET after

the parallel-connected ideal diode MOSFETs, the LTC4236

enhances the ideal diode performance with inrush current

limiting and overcurrent protection (see Figure1). This

allows the board to be safely inserted and removed from

a live backplane without damaging the connector.

applicaTions inForMaTion

Internal VCC Supply

The LTC4236 operates with an input supply from 2.9V to

18V. The power supply to the device is internally regulated

at 5V by a low dropout regulator (LDO) with an output at

the INTVCC pin. An internal diode-OR circuit selects the

highest of the supplies at the IN and OUT pins to power the

device through the LDO. The diode-OR scheme permits the

device’s power to be kept alive by the OUT voltage when

the IN supplies have collapsed or shut off.

An undervoltage lockout circuit prevents all of the MOSFETs

from turning on until the INTVCC voltage exceeds 2.2V. A

0.1µF capacitor is recommended between the INTVCC and

GND pins, close to the device for bypassing. No external

supply should be connected at the INTVCC pin so as not

to affect the LDO’s operation. A small external load of less

than 500µA can be connected at the INTVCC pin.

Figure1. Card Resident Diode-OR with Hot Swap Application

ADC

CPO1

GND

FAULT

PWRGD

DSTAT1

DSTAT2

680µF

12V

INTVCC

SMAJ15A

D2OFF

IN1 DGATE1 DGATE2

4236 F01

MD2

SiR158DP

0.003Ω

HGATE OUT

SENSE+CS+SENSE–

D2SRCCPO2

0.1µF

IN2

13.7k

15k

10Ω

RHG

CHG

10nF

REG

0.1µF

MD1

SiR158DP

SMAJ15A

DTMR

CFT

0.1µF

CDT

0.1µF

FTMR IMON

0.1µF

LTC4236

BACKPLANE

CONNECTOR

VIN1

12V

VIN2

12V

CARD

CONNECTOR

VSENSE+

100k

100k R8

100k

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

Turn-On Sequence

The board power supply at the OUT pin is controlled

with external N-channel MOSFETs (MD1, MD2 and MH) in

Figure1. The ideal diode MOSFETs connected in parallel

on the supply side function as a diode-OR, while MH on

the load side acts as a Hot Swap MOSFET controlling the

power supplied to the output load. The sense resistor RS

monitors the load current for overcurrent detection. The

HGATE capacitor CHG controls the gate slew rate to limit

the inrush current. Resistor RHG with CHG compensates

the current control loop, while RH prevents high frequency

oscillations in the Hot Swap MOSFET.

During a normal power-up, the ideal diode MOSFETs turn

on first. As soon as the internally generated supply, INTVCC,

rises above its 2.2V undervoltage lockout threshold, the

internal charge pump is allowed to charge up the CPO

pins. Because the ideal diode MOSFETs are connected in

parallel as a diode-OR, the SENSE+ pin voltage approaches

the highest of the supplies at the IN1 and IN2 pins. The

MOSFET associated with the lower input supply voltage

will be turned off by the corresponding gate drive amplifier.

Before the Hot Swap MOSFET can be turned on, EN must

remain low and ON must remain high for a debounce cycle

as configured at the DTMR pin, to ensure that any contact

bounces during the insertion have ceased. At the end of

the debounce cycle, the internal fault latch is cleared. The

Hot Swap MOSFET is then allowed to turn on by charging

up HGATE with a 10µA current source from the charge

pump. The voltage at the HGATE pin rises with a slope

equal to 10µA/CHG and the supply inrush current flowing

into the load capacitor CL is limited to:

IINRUSH =

CHG

•10µA

The OUT voltage follows the HGATE voltage when the Hot

Swap MOSFET turns on. If the voltage across the current

sense resistor RS becomes too high based on the FB pin

voltage, the inrush current will be limited by the internal

current limiting circuitry. Once the MOSFET gate overdrive

exceeds 4.2V and the FB pin voltage is above 1.235V, the

PWRGD pin pulls low to indicate that the power is good.

Once OUT reaches the input supply voltage, HGATE con-

tinues to ramp up. An internal 12V clamp limits the HGATE

voltage above OUT.

When the ideal diode MOSFET is turned on, the gate

drive amplifier controls the gate of the MOSFET to servo

the forward voltage drop across the MOSFET to 15mV.

If the load current causes more than 15mV of drop, the

MOSFET gate is driven fully on and the voltage drop is

equal to ILOAD • RDS(ON).

Turn-Off Sequence

The external MOSFETs can be turned off by a variety of

conditions. A normal turn-off for the Hot Swap MOSFET is

initiated by pulling the ON pin below its 1.155V threshold

(80mV ON pin hysteresis), or pulling the EN pin above its

1.235V threshold. Additionally, an overcurrent fault that

exceeds the fault timer period also turns off the Hot Swap

MOSFET. Normally, the LTC4236 turns off the MOSFET by

pulling the HGATE pin to ground with a 2mA current sink.

All of the MOSFETs turn off when INTVCC falls below its

undervoltage lockout threshold (2.2V). The DGATE pin is

pulled down with a 100µA current to one diode voltage

below the IN1 or D2SRC pins, while the HGATE pin is pulled

down to the OUT pin by a 200mA current. When D2OFF

is pulled high above 1.235V, the ideal diode MOSFET in

the IN2 power path is turned off with DGATE2 pulled low

by a 100µA current.

The gate drive amplifier controls the ideal diode MOSFET

to prevent reverse current when the input supply falls

below SENSE+. If the input supply collapses quickly, the

gate drive amplifier turns off the ideal diode MOSFET with

a fast pull-down circuit. If the input supply falls at a more

modest rate, the gate drive amplifier controls the MOSFET

to maintain SENSE+ at 15mV below IN.

Board Presence Detect with EN

If ON is high when the EN pin goes low, indicating a board

presence,

the LTC4236 initiates a timing cycle as configured

at the DTMR pin for contact debounce. It defaults to inter-

nal 100ms delay if DTMR is tied to INTVCC. If an external

capacitor CDT is connected from the DTMR pin to GND,

the delay is given by charging the capacitor to 1.235V with

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

a 10µA current. Thereafter, the capacitor is discharged to

ground by a 5mA current. For a given debounce delay, the

equation for setting the external capacitor CDT value is:

CDT = tDB •0.0081 [µF/ms]

Upon board insertion, any bounces on the EN pin restart

the timing cycle. When the debounce timing cycle is done,

the internal fault latch is cleared. If the EN pin remains low

at the end of the timing cycle, HGATE is charged up with

a 10µA current source to turn on the Hot Swap MOSFET.

If the EN pin goes high, indicating a board removal, the

HGATE pin is pulled low with a 2mA current sink after a

20µs delay, turning off the Hot Swap MOSFET without

clearing any latched fault.

Overcurrent Fault

The LTC4236 features an adjustable current limit with

foldback that protects the external MOSFET against short

circuits or excessive load current. The voltage across the

external sense resistor RS is monitored by an active current

limit amplifier. The amplifier controls the gate of the Hot

Swap MOSFET to reduce the load current as a function of

the output voltage sensed by the FB pin during active current

limit. A graph in the Typical Performance Characteristics

shows the current limit sense voltage versus FB voltage.

An overcurrent fault occurs when the output has been in

current limit for longer than the fault timer period configured

at the FTMR pin. Current limiting begins when the sense

voltage between the SENSE+ and SENSE– pins reaches

8.3mV to 25mV depending on the FB pin voltage. The gate

of the Hot Swap MOSFET is brought under control by the

current limit amplifier and the output current is regulated

to limit the sense voltage to less than 25mV. At this point,

the fault timer starts with a 100µA current charging the

FTMR pin capacitor. If the FTMR pin voltage exceeds its

1.235V threshold, the external MOSFET turns off with

HGATE pulled to ground by 2mA and FAULT pulls low.

After the Hot Swap MOSFET turns off, the FTMR pin ca-

pacitor is discharged with a 2µA pull-down current until

its threshold reaches 0.2V. This is followed by a cool-off

period of 14 timing cycles as described in the FTMR Pin

Functions. Figure 2 shows an overcurrent fault on the

12V output.

200µs/DIV

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

20A/DIV

4236 F02

Figure2. Overcurrent Fault on 12V Output

5µs/DIV

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

20A/DIV

4236 F03

Figure3. Severe Short-Circuit on 12V Output

In the event of a severe short-circuit fault on the 12V output

as shown in Figure3, the output current can surge to tens

of amperes. The LTC4236 responds within 1µs to bring the

current under control by pulling the HGATE to OUT voltage

down to zero volts. Almost immediately, the gate of the Hot

Swap MOSFET recovers rapidly due to the charge stored

in the RHG and CHG network and current is actively limited

until the fault timer expires. Due to parasitic supply lead

inductance, an input supply without any bypass capaci-

tor may collapse during the high current surge and then

spike upwards when the current is interrupted. Figure9

shows the input supply transient suppressors comprising

of Z1, RSNUB1, CSNUB1 and Z2, RSNUB2, CSNUB2 for the two

supplies if there is no input capacitance.

FTMR Pin Functions

An external capacitor CFT connected from the FTMR pin

to GND serves as fault timing when the supply output is

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

in active current limit. When the voltage across the sense

resistor exceeds the foldback current limit threshold (from

25mV to 8.3mV), FTMR pulls up with 100µA. Otherwise,

it pulls down with 2µA. The fault timer expires when the

1.235V FTMR threshold is exceeded, causing the FAULT

pin to pull low. For a given fault timer period, the equation

for setting the external capacitor CFT value is:

CFT = tFT • 0.083 [µF/ms]

After the fault timer expires, the FTMR pin capacitor pulls

down with 2µA from the 1.235V FTMR threshold until it

reaches 0.2V. Then, it completes 14 cooling cycles consist-

ing of the FTMR pin capacitor charging to 1.235V with a

100µA current and discharging to 0.2V with a 2µA current.

At that point, the HGATE pin voltage is allowed to start up

if the fault has been cleared as described in the Resetting

Fault section. When the latched fault is cleared during the

cool-off period, the FAULT pin pulls high. The total cool-off

time for the MOSFET after an overcurrent fault is:

tCOOL = CFT • 8 [s/µF]

After the cool-off period, the HGATE pin is only allowed

to pull up if the fault has been cleared for the latchoff

part. For the auto-retry part, the latched fault is cleared

automatically following the cool-off period and the HGATE

pin voltage is allowed to restart.

Resetting Fault (LTC4236-1)

For the latchoff part, an overcurrent fault is latched after

the fault timer expires and the FAULT pin is asserted low.

Only the Hot Swap MOSFET is turned off and the ideal

diode MOSFETs are not affected.

To reset a latched fault and restart the output, pull the

ON pin below 0.6V for more than 100µs and then high

above 1.235V. The fault latch resets and the FAULT pin

de-asserts on the falling edge of the ON pin. When ON

goes high again and the cool-off cycle has completed, a

debounce timing cycle is initiated before the HGATE pin

voltage restarts. Toggling the EN pin high and then low

again also resets a fault, but the FAULT pin pulls high at

the end of the debounce cycle before the HGATE pin volt-

age starts up. Bringing all the supplies below the INTVCC

undervoltage lockout threshold (2.2V) shuts off all the

MOSFETs and resets the fault latch. A debounce cycle is

initiated before a normal start-up when any of the supplies

is restored above the INTVCC UVLO threshold.

Auto-Retry after a Fault (LTC4236-2)

For the auto-retry part, the latched fault is reset automati-

cally at the end of the cool-off period as described in the

FTMR Pin Functions section. At the end of the cool-off

period, the fault latch is cleared and FAULT pulls high.

The HGATE pin voltage is allowed to start up and turn on

the Hot Swap MOSFET. If the output short persists, the

supply powers up into a short with active current limiting

until the fault timer expires and FAULT again pulls low. A

new cool-off cycle begins with FTMR ramping down with

a 2µA current. The whole process repeats itself until the

output short is removed. Since tFT and tCOOL are a function

of FTMR capacitance CFT, the auto-retry cycle is equal to

0.15%, irrespective of CFT.

Figure4 shows an auto-retry sequence after an overcur-

rent fault.

100ms/DIV

FTMR

2V/DIV

FAULT

10V/DIV

HGATE

20V/DIV

OUT

10V/DIV

4236 F04

Figure4. Auto-Retry Sequence After a Fault

Monitor Undervoltage Fault

The ON pin functions as a turn-on control and an input

supply monitor. A resistive divider connected between

the supply diode-OR output (SENSE+) and GND at the

ON pin monitors the supply for undervoltage condition.

The undervoltage threshold is set by proper selection of

the resistors at the ON rising threshold voltage (1.235V).

For Figure 1, if R1 = 2k, R2 = 13.7k, the input supply

undervoltage threshold is set to 9.7V.

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

An undervoltage fault occurs if the diode-OR output sup-

ply falls below its undervoltage threshold. If the ON pin

voltage falls below 1.155V but remains above 0.6V, the

Hot Swap MOSFET is turned off by a 2mA pull-down from

HGATE to ground. The Hot Swap MOSFET turns back on

instantly without the debounce cycle when the diode-OR

output supply rises above its undervoltage threshold.

However, if the ON pin voltage drops below 0.6V, it turns

off the Hot Swap MOSFET and clears the fault latch. The

Hot Swap MOSFET turns back on only after a debounce

cycle when the diode-OR output supply is restored above

its undervoltage threshold.

During the undervoltage fault condition, FAULT will not

be pulled low but PWRGD will be pulled high as HGATE

is pulled low. The ideal diode function controlled by the

ideal diode MOSFET is not affected by the undervoltage

(UV) fault condition.

Power Good Monitor

Internal circuitry monitors the MOSFET gate overdrive

between the HGATE and OUT pins. Also, the FB pin that

connects to OUT through a resistive divider is used to

determine a power good condition. The power good

comparator drives high when the FB pin rises above

1.235V, and drives low when FB falls below 1.215V. The

power good status for the input supply is reported via an

open-drain output, PWRGD. It is normally pulled high by

an external pull-up resistor or the internal 10µA pull-up.

The PWRGD pin pulls low when the FB power good com-

parator is high and the HGATE drive exceeds 4.2V. The

PWRGD pin goes high when the HGATE is turned off by

the ON or EN pins, or when the FB power good comparator

drives low, or when INTVCC enters undervoltage lockout.

Current Sense Monitor

The current through the external sense resistor is moni-

tored by LTC4236’s current sense amplifier at the CS+

and SENSE– pins (see Figure 5). The amplifier uses

auto-zeroing circuitry to achieve an offset below 150µV

over temperature, sense voltage and input supply volt-

age. The frequency of the auto-zero clock is 10kHz. An

internal resistor RIN is connected between the amplifier’s

negative input terminal and CS+ pin. The sense amplifier

loop forces the negative input terminal to have the same

potential as SENSE– and that develops a potential across

RIN to be the same as the sense voltage VSENSE. A cor-

responding current, VSENSE/RIN, will flow through RIN.

The high impedance inputs of the sense amplifier will not

conduct this input current, allowing it to flow through an

internal MOSFET to a resistor ROUT connected between the

IMON and GND pins. The IMON output voltage is equal to

(ROUT/RIN)•VSENSE. The resistor ratio ROUT/RIN defines

the voltage gain of the sense amplifier and is set to 100

with RIN = 200Ω and ROUT = 20k. Full scale input sense

voltage to the sense amplifier is 25mV, corresponding to

an output of 2.5V. For input supply voltages greater than

0.1µF

10µF 5V

IMON VOUT

ILOAD

VCC

RIN

200Ω

12V

0.1µF

VSENSE

ROUT

20k

2-WIRE I2C

INTERFACE

LTC4236

4236 F05

HGATE

LOAD

SENSE+

REF+

REF–

SENSE–

GND

REG

SCL

SDA

LTC2451IN

VOUT = ––––– • VSENSE = 100 • VSENSE

ROUT

RIN

CS+

Figure5. High Side Current Monitor with LTC2451 ADC

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

5V, the output clamps at 3.5V if the allowable input sense

voltage range is exceeded.

IMON Output Filtering

A capacitor connected in parallel with ROUT will give a

low pass response. This will reduce unwanted noise at

the output, and may also be useful as a charge reservoir

to keep the output steady while driving a switching circuit

such as an ADC (see Figure 5). This output capacitor

COUT in parallel with ROUT will create a pole in the output

response at:

fC=

2•π•ROUT •COUT

REG Pin Bypassing

The LTC4236 has an internally regulated supply near

SENSE+ for internal bias of the current sense amplifier. It

is not intended for use as a supply or bias pin for external

circuitry. A 0.1µF capacitor should be connected between

the REG and SENSE+ pins. This capacitor should be located

very near to the device and close to the REG pin for the

best performance.

REG and IMON Start-Up

The start-up current of the current sense amplifier when

the LTC4236 is powered on consists of two parts: the

first is the current necessary to charge the REG bypass

capacitor, which is nominally 0.1µF. Since the REG voltage

charges to approximately 4.1V below the SENSE+ voltage,

this can require a significant amount of start-up current.

The second source is the output current that flows into

ROUT, which upon start-up may temporarily drive the

IMON output high for less than 2ms. This is a temporary

condition which will cease when the sense amplifier settles

into normal closed-loop operation.

CPO and DGATE Start-Up

The CPO pin voltage is initially pulled up to a diode below

the IN1 or D2SRC pin when first powered up (see Figure1).

However, for application with back-to-back MOSFETs in

IN2 power path, CPO2 starts off at 0V since D2SRC is

near ground (see Figure8). CPO starts ramping up 7µs

after INTVCC clears its undervoltage lockout level. Another

40µs later, DGATE also starts ramping up with CPO. The

CPO ramp rate is determined by the CPO pull-up current

into the combined CPO and DGATE pin capacitances. An

internal clamp limits the CPO pin voltage to 12V above

the IN1 or D2SRC pin, while the final DGATE pin voltage

is determined by the gate drive amplifier. An internal 12V

clamp limits the DGATE1 and DGATE2 pin voltages above

IN1 and D2SRC respectively.

CPO Capacitor Selection

The recommended value of the capacitor between the CPO1

and IN1, and CP02 and D2SRC pins is approximately 10×

the input capacitance CISS of the ideal diode MOSFET. A

larger capacitor takes a correspondingly longer time to

charge up by the internal charge pump. A smaller capacitor

suffers more voltage drop during a fast gate turn-on event

as it shares charge with the MOSFET gate capacitance.

MOSFET Selection

The LTC4236 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFETs are

on-resistance RDS(ON), the maximum drain-source voltage

BVDSS and the threshold voltage.

The gate drive for the ideal diode and Hot Swap MOSFET

is guaranteed to be greater than 5V when the supply

voltages at IN1 and IN2 are between 2.9V and 7V. When

the supply voltages at IN1 and IN2 are greater than 7V,

the gate drive is guaranteed to be greater than 10V. The

gate drive is limited to 14V. An external Zener diode can

be used to clamp the potential from the MOSFET’s gate

to source if the rated breakdown voltage is less than 14V.

The maximum allowable drain-source voltage BVDSS

must be higher than the supply voltage including supply

transients as the full supply voltage can appear across the

MOSFET. If an input or output is connected to ground,

the full supply voltage will appear across the MOSFET.

The RDS(ON) should be small enough to conduct the

maximum load current, and also stay within the MOSFET’s

power rating.

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

Supply Transient Protection

When the capacitances at the input and output are very

small, rapid changes in current during input or output

short-circuit events can cause transients that exceed the

24V absolute maximum ratings of the IN and OUT pins.

To minimize such spikes, use wider traces or heavier

trace plating to reduce the power trace inductance. Also,

bypass locally with a 10µF electrolytic and 0.1µF ceramic,

or alternatively clamp the input with a transient voltage

suppressor (Z1, Z2). A 100Ω, 0.1µF snubber damps the

response and eliminates ringing (See Figure9).

Design Example

As a design example for selecting components, consider a

12V system with a 7A maximum load current for the two

supplies (see Figure1).

First, select the appropriate value of the current sense

resistor RS for the 12V supply. Calculate the sense resistor

value based on the maximum load current ILOAD(MAX) and

the lower limit for the current limit sense voltage threshold

∆VSENSE(TH)(MIN).

RS=Δ

SENSE(TH)(MIN)

ILOAD(MAX)

=22.5mV

7A =3.2mΩ

Choose a 3mΩ sense resistor with a 1% tolerance.

Next, calculate the RDS(ON) of the ideal diode MOSFET to

achieve the desired forward drop at maximum load. Assum-

ing a forward drop, ∆VFWD of 30mV across the MOSFET:

RDS(ON) ≤Δ

FWD

ILOAD(MAX)

30mV

7A =4.2mΩ

The SiR158DP offers a good choice with a maximum

RDS(ON) of 1.8mΩ at VGS = 10V. The input capacitance

CISS of the SiR158DP is about 4980pF. Slightly exceeding

the 10× recommendation, a 0.1µF capacitor is selected

for C2 and C3 at the CPO pins.

Next, verify that the thermal ratings of the selected Hot

Swap MOSFET are not exceeded during power-up or an

overcurrent fault.

Assuming the MOSFET dissipates power due to inrush

current charging the load capacitor CL at power-up, the

energy dissipated in the MOSFET is the same as the energy

stored in the load capacitor, and is given by:

ECL =

•CL•V

IN2

For CL = 680µF, the time it takes to charge up CL is cal-

culated as:

tCHARGE =

•V

IINRUSH

680µF •12V

1A =8ms

The inrush current is set to 1A by adding capacitance CHG

at the gate of the Hot Swap MOSFET.

CHG =

•I

HGATE(UP)

INRUSH

=680µF •10µA

1A =6.8nF

Choose a practical value of 10nF for CHG.

The average power dissipated in the MOSFET is calculated as:

PAVG =ECL

tCHARGE

2•680µF •12V

( )

8ms =6W

The MOSFET selected must be able to tolerate 6W for 8ms

during power-up. The SOA curves of the SiR158DP provide

45W (1.5A at 30V) for 100ms. This is sufficient to satisfy

the requirement. The increase in junction temperature due

to the power dissipated in the MOSFET is ∆T=PAVG•ZthJC

where ZthJC is the junction-to-case thermal impedance.

Under this condition, the SiR158DP data sheet indicates

that the junction temperature will increase by 3°C using

ZthJC = 0.5°C/W (single pulse).

Next, the power dissipated in the MOSFET during an

overcurrent fault must be safely limited. The fault timer

capacitor (CFT) is used to prevent power dissipation in

the MOSFET from exceeding the SOA rating during active

current limit. A good way to determine a suitable value

for CFT is to superimpose the foldback current limit profile

shown in the Typical Performance Characteristics on the

MOSFET data sheet’s SOA curves.

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

For the SiR158DP MOSFET, this exercise yields the plot

in Figure6.

1ms

10ms

100ms

10s

BVDSS LIMITED

ID LIMITED

IDM LIMITED

LIMITED BY RDS(ON)*

MOSFET POWER

DISSIPATION CURVE

RESULTING FROM

FOLDBACK ACTIVE

CURRENT LIMIT

TA = 25°C, SINGLE PULSE

VDS – DRAIN-TO-SOURCE VOLTAGE (V)

4236 F06

* VGS > MINIMUM VGS AT WHICH RDS(ON) IS SPECIFIED

ID – DRAIN CURRENT (A)

0.01 10 10010.1

100

0.1

0.01

Figure6. SiR158DP SOA with Design Example

MOSFET Power Dissipation Superimposed

As can be seen, the LTC4236’s foldback current limit profile

roughly coincides with the 100ms SOA contour. Since

this SOA plot is for an ambient temperature of 25°C only,

a maximum fault timer period of much less than 100ms

should be considered, such as 10ms or less. Selecting a

0.1µF ±10% value for CFT yields a maximum fault timer

period of 1.75ms which should be small enough to protect

the MOSFET during any overcurrent fault scenario.

Next, select the values for the resistive divider at the ON

pin that defines the undervoltage threshold of 9.7V for the

12V supply at SENSE+. Since the leakage current for the

ON pin can be as high as ±1µA, the total resistance in the

divider should be low enough to minimize the resulting

offset error. Calculate the bottom resistor R1 based on

the following equation to obtain less than ±0.2% error

due to leakage current.

R1=VON(TH)

IIN(LEAK)

⎛

⎝

⎜

⎞

⎠

⎟•0.2% =1.235V

1µA

⎛

⎝

⎜⎞

⎠

⎟•0.2% =2.4k

Choose R1 to be 2k to achieve less than ±0.2% error and

calculating R2 yields:

R2 =V

IN(UV)

VON(TH)

– 1

⎛

⎝

⎜

⎞

⎠

⎟•R1

R2 =9.7V

1.235V – 1

⎛

⎝

⎜⎞

⎠

⎟•2k =13.7k

It remains to select the values for the FB pin resistive

divider in order to set a power good threshold of 10.5V.

Keeping in mind the FB pin’s ±1µA leakage current, choose

a value of 2k for the bottom resistor R3. Calculating the

top resistor R4 value yields:

R4 =VOUT(PG)

FB(TH)

– 1

⎛

⎝

⎜

⎞

⎠

⎟•R3

R4 =10.5V

1.235V – 1

⎛

⎝

⎜⎞

⎠

⎟•2k =15k

The subsequent offset error due to the FB pin leakage

current will be less than ±0.2%.

The final components to consider are a 0.1µF bypass (C1)

at the INTVCC pin and a 0.1µF capacitor (C4) connected

between the REG and SENSE+ pins.

PCB Layout Considerations

To achieve accurate current sensing, a Kelvin connection

for the sense resistor is recommended. The PCB layout

should be balanced and symmetrical to minimize wiring

errors. In addition, the PCB layout for the sense resistor

and the power MOSFET should include good thermal

management techniques for optimal device power dissipa-

tion. A recommended PCB layout is illustrated in Figure7.

Connect the IN and OUT pin traces as close as possible to

the MOSFETs’ terminals. Keep the traces to the MOSFETs

wide and short to minimize resistive losses. The PCB traces

associated with the power path through the MOSFETs

should have low resistance. The suggested trace width for

1oz copper foil is 0.03" for each ampere of DC current to

keep PCB trace resistance, voltage drop and temperature

rise to a minimum. Note that the sheet resistance of 1oz

copper foil is approximately 0.5mΩ/square, and voltage

drops due to trace resistance add up quickly in high cur-

rent applications.

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

It is also important to place the bypass capacitor C1 for

the INTVCC pin, as close as possible between INTVCC and

GND. Also place C2 near the CPO1 and IN1 pins, C3 near

the CPO2 and D2SRC pins, and C4 near the REG and

SENSE+ pins. The transient voltage suppressors Z1 and

Z2, when used, should be mounted close to the LTC4236

using short lead lengths.

Power Prioritizer

Figure8 shows an application where the IN1 supply is

passed to the output on the basis of priority, rather than

simply allowing the highest voltage to prevail. This is

achieved by connecting a resistive divider from IN1 at the

D2OFF pin to suppress the turn-on of the back-to-back

ideal diode MOSFETs, MD2 and MD3 in the IN2 power path.

In this application, the 5V primary supply (VIN1) is passed

to the output whenever it is available; power is drawn

from the 12V backup supply (VIN2) only when the primary

supply is unavailable. As long as VIN1 is above the 4.7V

threshold set by the R6-R7 divider at the D2OFF pin, MD2

and MD3 are turned off, allowing VIN1 to be connected to

the output through MD1. The common source terminals of

MD2 and MD3 are connected to D2SRC pin, which allows

the body-diode of MD2 to reverse block the current flow

from the higher backup supply (VIN2) to the output. If the

primary supply fails and VIN1 drops below 4.3V, D2OFF is

allowed to turn on MD2 and MD3, and connect the VIN2 to

the output. When VIN1 returns to a viable voltage, MD2 and

MD3 turn off, and the output is connected to VIN1. Adding

R5 in the R6-R7 divider and bypassing it with DSTAT2 pin

control allows the D2OFF pin hysteresis to be increased

from 20mV to 100mV. The resistive divider at the ON pin

sets the SENSE+ undervoltage threshold to 4.1V.

•

D G

D S

S D

G D

S D

G D

••• •

•

•• •

•

•••

PowerPAK SO-8

MD1

PowerPAK SO-8

MD2

PowerPAK SO-8

WIN1

VIA TO IN1

CURRENT FLOW

TO LOAD

OUT

WIN2

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03" PER AMPERE

ON 1oz Cu FOIL

VIA TO C2 (CPO1)

VIA TO DGATE2

VIA TO C4 (REG)

VIA TO SENSE+

VIA TO GND PLANE

VIA TO DGATE1

9 10 11 12 13

28 27 26 25 24

815

LTC4236UFD

4236 F07

Figure7. Recommended PCB Layout for Power MOSFETs and Sense Resistor

LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

ADC

VIN1

PRIMARY

SUPPLY

VIN2

CPO1

GND

FAULT

PWRGD

DSTAT1

470µF

12V

INTVCC

SMAJ15A

D2OFF

IN1 DGATE1 DGATE2

4236 F08

MD3

SiR818DP

0.004Ω

HGATE OUT

SENSE+CS+SENSE–

D2SRCCPO2

0.1µF

IN2

4.64k

4.87k

10Ω

RHG

CHG

10nF

MD2

SiR818DP

REG

0.1µF

MD1

SiR818DP

CDT

0.1µF

12V

BACKUP

BATTERY

SMAJ15A

DTMR

CFT

0.1µF

FTMR

IMON

20k

56.2k

2.2k

0.1µF

DSTAT2

LTC4236

Figure8. 2-Channel Power Prioritizer

BACKPLANE

CONNECTOR

VIN1

12V

VIN2

12V

CARD

CONNECTOR

12V

10A

10k

SMAJ15A

4236 F09

MD2

SiR158DP

0.002Ω

VSENSE+

0.1µF

10Ω

0.1µF

MD1

SiR158DP

PWREN

SMAJ15A RSNUB1

100Ω

CSNUB1

0.1µF

RSNUB2

100Ω

CSNUB2

0.1µF

2.7k

D1, D2, D3: GREEN LED LN1351C

D4: RED LED LN1261CAL

2.7k

ADC

CPO1

GND

INTVCC D2OFF

IN1 DGATE1 DGATE2

LTC4236

OUTIN2

DTMR

2.7k

0.1µF

CDT

0.1µF

FTMR

CFT

0.1µF

SENSE+CS+

0.1µF

REG

220µF

15k

FAULT

PWRGD

DSTAT1

DSTAT2

IMON

D2SRC

RHG

CHG

10nF

CPO2 HGATE

SENSE–

Figure9. 12V, 10A Card Resident Application

LTC4236

4236f

For more information www.linear.com/LTC4236

Typical applicaTion

Plug-In Card 3.3V Prioritized Power Supply at IN1

ADC

CPO1

GND

FAULT

PWRGD

DSTAT1

100µF

3.3V

INTVCC

SMAJ13A

D2OFF

IN1 DGATE1 DGATE2

4236 TA02

MD2

SiR818DP

0.004Ω

HGATE OUT

D2SRCCPO2

0.1µF

IN2

2.21k

2.37k

10Ω

RHG

CHG

10nF

0.1µF

MD1

SiR818DP

SMAJ13A

DTMR

CFT

0.1µF

FTMR

IMON

20k

R10

28.7k

2.2k

0.1µF

DSTAT2

LTC4236

SENSE+CS+SENSE–

0.1µF

REG

BACKPLANE

CONNECTOR

VMAIN

3.3V

VAUX

3.3V

CARD

CONNECTOR

VSENSE+

10k

LTC4236

4236f

For more information www.linear.com/LTC4236

package DescripTion

Please refer to http://www.linear.com/product/LTC4236#packaging for the most recent package drawings.

4.00 ±0.10

(2 SIDES)

2.50 REF

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

27 28

BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115

TYP

R = 0.05

TYP

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UFD28) QFN 0506 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.50 REF

3.50 REF

4.10 ±0.05

5.50 ±0.05

2.65 ±0.05

3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

2.65 ±0.10

3.65 ±0.10

3.65 ±0.05

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

LTC4236

4236f

For more information www.linear.com/LTC4236

 LINEAR TECHNOLOGY CORPORATION 2015

LT 1215 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4236

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, TSOT23-6

LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8, SO-8 or MSOP-10

LTC4215 Single Channel Hot Swap Controller Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24

LTC4216 Single Channel Hot Swap Controller Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12

LTC4218 Single Channel Hot Swap Controller Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16

LTC4221 Dual Channel Hot Swap Controller Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16

LTC4222 Dual Channel Hot Swap Controller Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32

LTC4223 Dual Supply Hot Swap Controller Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16

LTC4224 Dual Channel Hot Swap Controller Operates from 1V to 6V, Active Current Limiting, MSOP-10 or DFN-10

LTC4227 Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, Controls Three N-Channels, SSOP-16 or QFN-20

LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, Controls Four N-Channels, SSOP-28 or QFN-28

LTC4229 Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, Controls Tw o N-Channels, SSOP-24 or QFN-24

LTC4235 Dual 12V Ideal Diode-OR and Single Hot Swap

Controller with Current Monitor

Operates from 9V to 14V, Controls Three N-Channels, QFN-20

LTC4352 Low Voltage Ideal Diode Controller Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12

LTC4353 Dual Low Voltage Ideal Diode Controller Operates from 0V to 18V, Controls Tw o N-Channels, MSOP-16 or DFN-16

LTC4355 Positive High Voltage Ideal Diode-OR and Monitor Operates from 9V to 80V, Controls Tw o N-Channels, SO-16, DFN-14 or MSOP-16

LTC4357 Positive High Voltage Ideal Diode Controller Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6

ADC

1000µF

12V

BULK

SUPPLY

BYPASS

CAPACITOR

13.7k

0.1µF

BULK

SUPPLY

BYPASS

CAPACITOR

BACKPLANE

VIN1

12V

VIN2

12V

PLUG-IN

CARD

CPO1

GND

ON FAULT

PWRGD

DSTAT1

DSTAT2

INTVCC

D2OFF

IN1 DGATE1 DGATE2

4236 TA03

MD2

SiR158DP

0.004Ω

HGATE OUT

D2SRCCPO2

0.1µF

IN2

15k

10Ω

RHG

CHG

10nF

0.1µF

MD1

SiR158DP

DTMR

CFT

0.1µF

FTMR IMON

LTC4236

SENSE+SENSE–

0.1µF

REG CS+

12V, 5A Backplane Resident Ideal Diode-OR Application with Inrush Current Limiting