STM32H723VE STM32H723VG STM32H723ZE STM32H723ZG 32-bit Arm(R) Cortex(R)-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces Datasheet - production data Features Core * 32-bit Arm(R) Cortex(R)-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions LQFP100 (14x14 mm) LQFP144 (20x20 mm) FBGA TFBGA100 (8x8 mm) FBGA UFBGA144 (7x7 mm) Memories * Up to 1 Mbyte of embedded Flash memory with ECC * SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes) * Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories * 2 x Octo-SPI interface with XiP * 1.62 V to 3.6 V application supply and I/O * POR, PDR, PVD and BOR * Dedicated USB power * Embedded LDO regulator * Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI * External oscillators: 4-50 MHz HSE, 32.768 kHz LSE Low power * Sleep, Stop and Standby modes * VBAT supply for RTC, 32x32-bit backup registers * 2 x SD/SDIO/MMC interface * Bootloader Analog Graphics * Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load * LCD-TFT controller supporting up to XGA resolution Clock, reset and supply management * 2x16-bit ADC, up to 3.6 MSPS in 16-bit: up to 18 channels and 7.2 MSPS in doubleinterleaved mode * 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels * 2 x comparators * 2 x operational amplifier GBW = 8 MHz * 2x 12-bit D/A converters July 2020 DS13313 Rev 1 1/226 www.st.com STM32H723xE/G Digital filters for sigma delta modulator (DFSDM) * 8 channels/4 filters * SWPMI single-wire protocol master I/F * MDIO slave interface Mathematical acceleration 4 DMA controllers to offload the CPU * 1 x MDMA with linked list support * CORDIC for trigonometric functions acceleration * 2 x dual-port DMAs with FIFO * FMAC: Filter mathematical accelerator * 1 x basic DMA with request router capabilities Digital temperature sensor 24 timers True random number generator * Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input * 2x watchdogs, 1x SysTick timer CRC calculation unit RTC with sub-second accuracy and hardware calendar ROP, PC-ROP, tamper detection Debug mode 96-bit unique ID * SWD andJTAG interfaces All packages are ECOPACK2 compliant * 2-Kbyte embedded trace buffer Up to 114 I/O ports with interrupt capability Up to 35 communication interfaces * Up to 5 x I2C FM+ interfaces (SMBus/PMBusTM) * Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART * Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode) * 2x SAI (serial audio interface) * 1x FD/TT-CAN and 2xFD-CAN * 8- to 14-bit camera interface * 16-bit parallel slave synchronous interface * SPDIF-IN interface * HDMI-CEC * Ethernet MAC interface with DMA controller * USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY 2/226 DS13313 Rev 1 STM32H723xE/G Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.6 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.9.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.9.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.12 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.13 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 31 3.15 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 31 3.16 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 31 3.17 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.18 Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 32 DS13313 Rev 1 3/226 7 Contents 4/226 STM32H723xE/G 3.19 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.20 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.23 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.24 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 36 3.27 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28 PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.30 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.31 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.31.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.31.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.31.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.31.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 43 3.31.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.31.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.31.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.32 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 44 3.33 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.34 Universal synchronous/asynchronous receiver transmitter (USART) . . . 45 3.35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46 3.36 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 47 3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.38 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.39 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 48 3.40 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 49 3.41 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 49 3.42 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 49 3.43 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 50 3.44 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 50 DS13313 Rev 1 STM32H723xE/G Contents 3.45 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.46 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5 Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 53 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 93 6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . . 94 6.3.5 Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . . 95 6.3.6 Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 I/O system current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105 High-speed external user clock generated from an external source . . . . . . . . .105 Low-speed external user clock generated from an external source . . . . . . . . . .106 High-speed external clock generated from a crystal/ceramic resonator. . . . . . .107 Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .108 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109 48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .109 64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .110 4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .111 DS13313 Rev 1 5/226 7 Contents STM32H723xE/G Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .117 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .117 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 118 Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .124 Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .126 6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Synchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 SDRAM waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 6.3.18 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 6/226 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.22 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.24 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 174 6.3.25 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 175 6.3.26 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.3.27 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.3.28 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.3.29 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.3.30 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 180 6.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 183 6.3.32 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 184 DS13313 Rev 1 STM32H723xE/G Contents 6.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 185 6.3.34 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.35 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.36 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .199 USB OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 7.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 7.4 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Device marking for UFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 7.5.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 DS13313 Rev 1 7/226 7 List of tables STM32H723xE/G List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 8/226 STM32H723xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32H723 pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32H723 pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 91 VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 93 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Typical and maximum current consumption in Run mode, code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 100 Typical consumption in Run mode and corresponding performance versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical current consumption in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Typical current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 102 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 114 PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 115 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DS13313 Rev 1 STM32H723xE/G Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. List of tables EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 122 Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 123 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 129 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 129 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 131 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 131 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 133 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 134 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 140 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 152 Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 DS13313 Rev 1 9/226 10 List of tables Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. 10/226 STM32H723xE/G PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 199 Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 200 USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 204 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 205 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 205 Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 214 LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 UFBGA144 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 220 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 DS13313 Rev 1 STM32H723xE/G List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM32H723xE/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32H723xE/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 128 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 130 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 132 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 139 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 144 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 145 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 162 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DS13313 Rev 1 11/226 12 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. 12/226 STM32H723xE/G SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LQFP100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 UFBGA144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA144 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 DS13313 Rev 1 STM32H723xE/G 1 Introduction Introduction This document provides information on STM32H723xE/G microcontrollers, such as description, functional overview, pin assignment and definition, packaging, and ordering information. This document should be read in conjunction with the STM32H723xE/G reference manual (RM0468), available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-M7 core, refer to the Cortex(R)-M7 Technical Reference Manual, available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS13313 Rev 1 13/226 52 Description 2 STM32H723xE/G Description STM32H723xE/G devices are based on the high-performance Arm(R) Cortex(R)-M7 32-bit RISC core operating at up to 550 MHz. The Cortex(R) -M7 core features a floating point unit (FPU) which supports Arm(R) double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections). The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC co-processor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. * 14/226 Standard peripherals - Five I2Cs - Five USARTs, five UARTs and one LPUART - Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization. (Note that the five USARTs also provide SPI slave capability.) - Two SAI serial audio interfaces - One SPDIFRX interface with four inputs - One SWPMI (Single Wire Protocol Master Interface) - Management Data Input/Output (MDIO) slaves - Two SDMMC interfaces - A USB OTG high-speed interface with full-speed capability (with the ULPI) - Two FDCANs plus one TT-FDCAN interface - An Ethernet interface - Chrom-ART Accelerator - HDMI-CEC DS13313 Rev 1 STM32H723xE/G * Description Advanced peripherals including - A flexible memory control (FMC) interface - Two Octo-SPI memory interfaces - A camera interface for CMOS sensors - An LCD-TFT display controller Refer to Table 1: STM32H723xE/G features and peripheral counts for the list of peripherals available on each part number. STM32H723xE/G devices operate in the -40 to +85 C ambient temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.7.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. Dedicated supply inputs for USB are available to allow a greater power supply choice. A comprehensive set of power-saving modes allows the design of low-power applications. STM32H723xE/G devices are offered in several packages ranging from 100 to 144 pins/balls. The set of included peripherals changes with the device chosen. These features make STM32H723xE/G microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile applications, Internet of Things * Wearable devices: smart watches. Figure 1 shows the device block diagram. DS13313 Rev 1 15/226 52 Description STM32H723xE/G Figure 1. STM32H723xE/G block diagram MII / RMII To APB1-2 peripherals MDIO as AF AHB1 D-TCM 64KB I-TCM 64KB Arm CPU Cortex-M7 550 MHz 1 MB FLASH LCD-TFT FIFO WWDG OCTOSPI1 FMC_signals CORDIC FMAC SRAM1 SRAM2 16 KB 16 KB ADC1 AHB3 FIFO SDMMC1 TIM6 AXI/AHB34 (275MHz) 16b TIM7 16b SWPMI AHB4 AHB2 (275MHz) DCMI PSSI Up to 20 analog inputs Most are common to ADC1 & 2 ADC2 AHB/APB DLYBOS1-2 AHB/APB DLYBSD2 HSYNC, VSYNC, PIXCLK, D[13:0] PDCK, DE, RDY, D[15:0] RNG OCTOSPI2 signals DLYBSD1 D[7:0], D123DIR, D0DIR, CMD, CKas AF DMA Mux1 OCTOSPI1 signals OCTOSPI2 APB3 (138MHz) FIFO 64-bit AXI BUS-MATRIX 16 Streams FIFO CHROM-ART (DMA2D) 32-bit AHB BUS-MATRIX FMC AHBS LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK DMA/ FIFO FIFO AXIM D-Cache 32KB MDMA DMA/ FIFO 8 Stream 8 Stream FIFOs FIFOs AXI/AHB12 (275MHz) ETM I-Cache 32KB DMA2 (275MHz) PHY ETHER SDMMC2 OTG_HS MAC AHB1 (275 TRACECLK TRACED[3:0] JTAG/SW 128 KB AXI SRAM AHB2 (275MHz) NJTRST, JTDI, JTCK/SWCLK JTDO/SWDIO, JTDO DMA1 Shared AXI I-TCM 192KB AHBP OCTOSPIM D-TCM 64KB D[7:0],DP, DM, STP, D123DIR, NXT,ULPI:CK D0DIR, , D[7:0], DIR, CMD, CKas AF ID, VBUS 32b TIM2 CH[4;1], ETR as AF 16b TIM3 CH[4;1], ETR as AF 16b TIM4 CH[4;1], ETR as AF 32b TIM5 CH[4;1], ETR as AF 32b TIM23 CH[4;1], ETR as AF 32b TIM24 CH[4;1], ETR as AF 16b TIM12 CH[2;1] as AF 16b TIM13 CH1 as AF 16b TIM14 CH1 as AF AHB/APB USART2 RX, TX, CK, CTS, RTS, DE as A USART3 FIFO AHB4 USART10 RX, TX, CK, CTS, RTS, DE as AF USART6 16b 16b A P B 10 MHz 3 MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF SCL, SDA, SMBA as AF I2C3/SMBUS I2C5/SMBUS SCL, SDA, SMBA as AF MDIOS MDC, MDIO as AF TT-FDCAN1 FDCAN2 FDCAN3 16 KB SRAM 4 KB BKP RAM SPDIFRX1 HDMI-CEC GPIO PORTJ,K 16b RCC Reset & control SAI4 COMP1&2 LPTIM5 16b OUT as AF LPTIM4 16b OUT as AF LPTIM3 16b I2C4 MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6 RX, TX, CK, CTS, RTS as AF LPUART1 IN1, IN2, ETR, OUT as AF LPTIM2 16b AHB/APB VREF IN1, IN2, ETR, OUT as AF VINM, VINP, VOUT as AF OPAMP2 VINM, VINP, VOUT as AF Voltage regulator 3.3 to 1.2V @VDD IWDG HSI RC HSI HSI48 HSI48 RC CSI RC CSI LSI LSI RC VDD VSS VCAP, VDDLDO VBAT XTAL 32 kHz Temperature sensor CEC as AF OUT1, OUT2 as AF LPTIM1 @VSW SYSCFG EXTI WKUP IN[1:4] as AF OPAMP1 LS OUT as AF TX, RX, RXFD_MODE, TXFD_MODE as AF TX, RX, RXFD_MODE, TXFD_MODE as AF TX, RX, RXFD_MODE, TXFD_MODE as AF @VDD VCORE BBgen + POWER MNGT PWRCTRL GPIO PORTA.. H SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF USBCR DAC PA..H[15:0] SCL, SDA, SMBA as AF CRC ADC3 PJ,PK[11:0] SD_[A;B], SCK_[A;B], FS_[A;B], MCLK_[A;B], D[3:1], CK[2:1] as AF COMPx_INP, COMPx_INM, COMPx_OUT as AF HSEM RX, TX, CTS, RTS, DE as AF SPI2/I2S2 I2C2/SMBUS RTC Backup registers LS Up to 17 analog inputs Some common to ADC1 and 2 TIM1/PWM TIM8/PWM AHB4 (275MHz) CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2 as AF USART1 RX, TX, CTS, RTS, DE as AF UART8 SPI3/I2S3 RAM I/F 32-bit AHB BUS-MATRIX APB4 (max) APB4 138138MHz MHz (max) CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2 as AF DAP RX, TX, CTS, RTS, DE as AF UART7 FIFO RX, TX, CK, CTS, RTS, DE as AF BDMA AHB4 RX, TX, CK, CTS, RTS, DE as AF DMA Mux2 RX, TX, CTS, RTS, DE as AF UART5 I2C1/SMBUS APB1 138MHz (max) UART9 10 KB SRAM SPI1/I2S1 AHB4 RX, TX, CTS, RTS, DE as AF SPI4 AHB4_MEMD3 (275MHz) MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF TIM15 AHB4 (275MHz) MOSI, MISO, SCK, NSS as AF RX, TX, CK, CTS, RTS, DE as A UART4 Digital filter 2 compl. chan.(TIM15_CH1[1:2]N), 2 chan. (TIM_CH15[1:2], BKIN as AF TIM17 TIM16 AHB4 1 compl. chan.(TIM17_CH1N), 1 chan. (TIM17_CH1, BKIN as AF 1 compl. chan.(TIM16_CH1N), 1 chan. (TIM16_CH1, BKIN as AF SPI5 APB2 138 MHz (max) MOSI, MISO, SCK, NSS as AF SAI1 AHB4 SD_[A;B], SCK_[A;B], FS_[A;B], MCLK_[A;B], D[3:1], CK[2:1] as AF DFSDM APB4 138 MHz (max) CKOUT, DATIN[7:0], CKIN[7:0] AWU OSC32_IN OSC32_OUT TS, TAMP1, TAMP3, OUT, REFIN @VDD XTAL OSC 4- 48 MHz PLL1+PLL2+PLL3 OSC_IN OSC_OUT @VDD POR reset Int SUPPLY SUPERVISION POR/PDR/BOR PVD VDDA, VSSA NRESET WKUP[1;2;4;6] MSv52561V3 16/226 DS13313 Rev 1 STM32H723xE/G Description Table 1. STM32H723xE/G features and peripheral counts STM32H723 STM32H723 STM32H723 STM32H723 VGH/VEH VGT/VET ZGT/ZET ZGI/ZEI Peripherals Flash memory (Kbytes)(1) SRAM (Kbytes) 1024 / 512 1024 / 512 SRAM mapped onto AXI bus 128 SRAM1 (D2 domain) 16 SRAM2 (D2 domain) 16 SRAM4 (D3 domain) 16 RAM shared between ITCM and AXI (Kbytes) 192 ITCM RAM (instruction) 64 DTCM RAM (data) 128 TCM RAM (Kbytes) Backup SRAM (Kbytes) 1024 / 512 1024 / 512 4 Interface 1 NOR Flash memory/RAM controller - - yes yes Multiplexed I/O NOR Flash memory yes yes yes yes 16-bit NAND Flash memory yes yes yes yes 16-bit SDRAM controller - - yes yes GPIO 80 80 112 114 Octo-SPI interface 2(2) 2(2) 2 2 FMC OTFDEC no CORDIC yes FMAC yes Timers Wakeup pins General purpose 32 bits 2 2 2 2 General purpose 16 bits 10 10 10 10 Advanced control (PWM) 2 2 2 2 Basic 2 2 2 2 Low-power 5 5 5 5 RTC 1 1 1 1 Window watchdog / independent watchdog 2 2 2 2 4 4 4 4 DS13313 Rev 1 17/226 52 Description STM32H723xE/G Table 1. STM32H723xE/G features and peripheral counts (continued) STM32H723 STM32H723 STM32H723 STM32H723 VGH/VEH VGT/VET ZGT/ZET ZGI/ZEI Peripherals Tamper pins 2 2 Random number generator yes Cryptographic accelerator no SPI / I2S 5/4 6/4 6/4 5 5 5 5 USART/UART/ LPUART 5/5/1 5/5/1 5/5/1 5/5/1 SAI/PDM 2/1(3) 2/1(3) 2/1 2/1 SPDIFRX 1 HDMI-CEC 1 SWPMI 1 MDIO 1 SDMMC 2 FDCAN/TT-FDCAN 2/1 2/1 2/1 2/1 USB [OTG_HS(ULPI)/FS(PHY)] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] Ethernet [MII/RMII] 1 [1/1] 1 [1/1] 1 [1/1] 1 [1/1] yes yes Camera interface/PSSI LCD-TFT yes yes yes Chrom-ART Accelerator (DMA2D) yes Number of ADCs 16-bit ADCs 2 Number of direct channelsADC1/ADC2 2/2 0 0 2/2 Number of fast channels ADC1/ADC2 3/2 3/2 4/3 4/3 Number of slow channels ADC1/ADC2 9/8 11/10 12/11 12/11 Number of ADCs 12-bit ADCs 1 Number of direct channels 2 2 2 2 Number of fast channels 6 2 6 6 Number of slow channels 9 0 4 9 Present in IC 12-bit DAC DFSDM 18/226 2 5/4 I2C Communication interfaces 2 yes Number of channels 2 Comparators 2 Operational amplifiers 2 Present in IC yes DS13313 Rev 1 STM32H723xE/G Description Table 1. STM32H723xE/G features and peripheral counts (continued) Peripherals STM32H723 STM32H723 STM32H723 STM32H723 VGH/VEH VGT/VET ZGT/ZET ZGI/ZEI Maximum CPU frequency USB separate supply pad USB internal regulator 550 MHz yes - yes yes - - - - - - LDO yes SMPS step-down converter Operating voltage Operating temperatures Package - - 1.62 to 3.6 V 1.71 to 3.6 V 1.62 to 3.6 V Ambient temperature -40C to +85C Junction temperature -40C to +125C TFBGA100 LQFP100 LQFP144 UFBGA144 1. STM32H723xGy products have 1024 Kbytes of Flash memory, whereas STM32H723xEy products have 512 Kbytes 2. The two Octo-SPI/Quad-SPI interfaces are available only in Muxed mode. 3. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7: STM32H723 pin and ball descriptions. DS13313 Rev 1 19/226 52 Functional overview STM32H723xE/G 3 Functional overview 3.1 Arm(R) Cortex(R)-M7 with FPU The Arm(R) Cortex(R)-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: * Six-stage dual-issue pipeline * Dynamic branch prediction * Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache) * 64-bit AXI interface * 64-bit ITCM interface * 2x32-bit DTCM interfaces The following memory interfaces are supported: * Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency * Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses * AXI Bus interface to optimize Burst transfers * Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 1 shows the general block diagram of the STM32H723xE/G family. 3.2 Memory protection unit (MPU) The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. 20/226 DS13313 Rev 1 STM32H723xE/G Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H723xE/G devices embed up to 1 Mbyte of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: * one Flash word (8 words, 32 bytes or 256 bits) * 10 ECC bits (single-error correction and double-error detection). The Flash memory is organized as follows: 3.3.2 * up to 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes (4 K Flash memory words) * 128 Kbytes of system Flash memory from which the device can boot * 2 Kbytes (64 Flash words) of user option bytes for user configuration Embedded SRAM All devices feature: * from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain * SRAM1 mapped on D2 domain: 16 Kbytes * SRAM2 mapped on D2 domain: 16 Kbytes * SRAM4 mapped on D3 domain: 16 Kbytes * 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or VBAT mode. * RAM mapped to TCM interface (ITCM and DTCM): Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the Cortex(R)-M7CPU(AHBSAHBP): - 64 to 256 Kbytes of ITCM-RAM (instruction RAM) This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU. - 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports) The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex(R)-M7 dual issue capability. The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte granularity. DS13313 Rev 1 21/226 52 Functional overview STM32H723xE/G Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: * 7 ECC bits are added per 32-bit word. * 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection. 22/226 DS13313 Rev 1 STM32H723xE/G 3.4 Functional overview Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space * All RAM address space: ITCM, DTCM RAMs and SRAMs * The System memory bootloader The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to application note AN2606 "STM32 microcontroller System memory Boot mode" for details. 3.5 CORDIC co-processor (CORDIC) The CORDIC co-processor provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks. The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. CORDIC features * 24-bit CORDIC rotation engine * Circular and Hyperbolic modes * Rotation and Vectoring modes * Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root, Natural logarithm * Programmable precision up to 20-bit * Fast convergence: 4 bits per clock cycle * Supports 16-bit and 32-bit fixed point input and output formats * Low latency AHB slave interface * Results can be read as soon as ready without polling or interrupt * DMA read and write channels DS13313 Rev 1 23/226 52 Functional overview 3.6 STM32H723xE/G Filter mathematical accelerator (FMAC) The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks. FMAC features * 16 x 16-bit multiplier * 24+2-bit accumulator with addition and subtraction * 16-bit input and output data * 256 x 16-bit local memory * Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers * Input and output sample buffers can be circular * Buffer "watermark" feature reduces overhead in interrupt mode * Filter functions: FIR, IIR (direct form 1) * AHB slave interface * DMA read and write data channels 3.7 Power supply management 3.7.1 Power supply scheme STM32H723xE/G power supply voltages are the following: 24/226 * VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins. * VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE * VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and OPAMP. * VDD33USB: allows the support of a VDD supply different from 3.3 V while powering the USB transceiver with 3.3V on VDD33USB. * VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present. * VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V, 1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The VCORE domain is split into the following power domains that can be independently switch off. - D1 domain containing some peripherals and the Cortex(R)-M7 core - D2 domain containing a large part of the peripherals - D3 domain containing some peripherals and the system control DS13313 Rev 1 STM32H723xE/G Functional overview During power-up and power-down phases, the following power sequence requirements must be respected (see Figure 2): * When VDD is below 1 V, other power supplies (VDDA, VDD33USB) must remain below VDD + 300 mV. * When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. Figure 2. Power-up/power-down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDx refers to any power supply among VDDA, VDD33USB. 3.7.2 Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: * Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in Reset mode when VDD is below this threshold, * Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold. The PDR supervisor can be enabled/disabled through PDR_ON pin. * Brownout reset (BOR) The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold. DS13313 Rev 1 25/226 52 Functional overview 3.7.3 STM32H723xE/G Voltage regulator The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off. Voltage regulator output can be adjusted according to application needs through 6 power supply levels: * * 3.8 Run mode (VOS0 to VOS3) - Scale 0: boosted performance - Scale 1: high performance - Scale 2: medium performance and consumption - Scale 3: optimized performance and low-power consumption Stop mode (SVOS3 to SVOS5) - Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C, LPTIM) are operational - Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt. Low-power strategy There are several ways to reduce power consumption on STM32H723xE/G: * Decrease the dynamic power consumption by slowing down the system clocks even in Run mode and by individually clock gating the peripherals that are not used. * Save power when the CPU is idle, by selecting among the available low-power modes according to the user application needs. This allows the best compromise between short startup time and low power consumption to be achieved, according to the available wakeup sources. The devices feature several low-power modes: * CSleep (CPU clock stopped) * CStop (CPU sub-system clock stopped) * DStop (Domain bus matrix clock stopped) * Stop (System clock stopped) * DStandby (Domain powered down) * Standby (System powered down) CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex(R)-Mx core is set after returning from an interrupt service routine. A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode. 26/226 DS13313 Rev 1 STM32H723xE/G Functional overview Table 2. System versus domain low-power mode System power mode D1 domain power mode D2 domain power mode D3 domain power mode Run DRun/DStop/DStandby DRun/DStop/DStandby DRun Stop DStop/DStandby DStop/DStandby DStop Standby DStandby DStandby DStandby 3.9 Reset and clock controller (RCC) The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), thus the system frequency can be changed without modifying the baudrate. 3.9.1 Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs. The RCC receives the following clock source inputs: * * Internal oscillators: - 64 MHz HSI clock - 48 MHz RC oscillator - 4 MHz CSI clock - 32 kHz LSI clock External oscillators: - HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated from a crystal/ceramic resonator) - LSE clock: 32.768 kHz The RCC provides three PLLs: one for system clock, two for kernel clocks. The system starts on the HSI clock. The user application can then select the clock configuration. DS13313 Rev 1 27/226 52 Functional overview 3.9.2 STM32H723xE/G System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: 3.10 * Power-on reset (pwr_por_rst) * Brownout reset * Low level on NRST pin (external reset) * Window watchdog * Independent watchdog * Software reset * Low-power mode security reset * Exit from Standby General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs register reset values in the device reference manual). The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.11 Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow the interconnection of bus masters with bus slaves (see Figure 3). 28/226 DS13313 Rev 1 STM32H723xE/G Figure 3. STM32H723xE/G bus matrix AHBS OR DMA2D LTDC D1-to-D2 AHB DMA2_MEM MDMA DMA1_MEM SDMMC1 DMA2 Ethernet SDMMC2 USBHS1 MAC DMA2_PERIPH DMA1 AHBP AXIM I$ D$ 32KB 32KB ITCM 64 Kbyte ITCM 192 Kbyte DTCM 128 Kbyte DMA1_PERIPH CPU Cortex-M7 AXI SRAM 192K byte SRAM1 16 Kbyte SRAM2 16 Kbyte Flash A Up to 1 Mbyte AHB1 DS13313 Rev 1 AXI SRAM 128 Kbyte AHB2 OCTOSPI1 OCTOSPI2 APB1 FMC APB2 AHB3 APB3 64-bit AXI bus matrix D1 domain 32-bit AHB bus matrix D2 domain D2-to-D1 AHB D2-to-D3 AHB D1-to-D3 AHB Legend 32-bit bus AHB4 TCM AHB AXI APB 29/226 64-bit bus Master interface Bus multiplexer Slave interface APB4 SRAM4 16 Kbyte Backup SRAM 4 Kbyte MSv65313V1 Functional overview BDMA 32-bit AHB bus matrix D3 domain Functional overview 3.12 STM32H723xE/G DMA controllers The devices feature four DMA instances and a DMA request router to unload CPU activity: * A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex(R)-M7 TCM memories. The MDMA is located in D1 domain. It is able to interface with the other DMA controllers located in D2 domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers. * Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request router capabilities. * One basic DMA (BDMA) located in D3 domain, with request router capabilities. * A DMA request multiplexer (DMAMUX) The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event. 3.13 Chrom-ART Accelerator (DMA2D) The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: * Filling a part or the whole of a destination image with a specific color * Copying a part or the whole of a source image into a part or the whole of a destination * image * Copying a part or the whole of a source image into a part or the whole of a destination * image with a pixel format conversion * Blending a part and/or two complete source images with different pixel format and copy * the result into a part or the whole of a destination image with a different color format. * All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with indexed or direct color mode, including block based YCbCr to handle JPEG decoder output. * The DMA2D has its own dedicated memories for CLUTs (color look-up tables). An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automated and are running independently from the CPU or the DMAs. 30/226 DS13313 Rev 1 STM32H723xE/G 3.14 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)-M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor context automatically saved on interrupt entry, and restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.15 Extended interrupt and event controller (EXTI) The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power domains and/or D3 domain from Stop mode. The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events and 54 direct events. Configurable events have dedicated pending flags, active edge selection, and software trigger capable. Direct events provide interrupts or events from peripherals having a status flag. 3.16 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. DS13313 Rev 1 31/226 52 Functional overview 3.17 STM32H723xE/G Flexible memory controller (FMC) The FMC controller main features are the following: * Interface with static-memory mapped devices including: 3.18 - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-,16-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided by 2. Octo-SPI memory interface (OCTOSPI) The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal SPI memories. The STM32H723xE/G embeds two separate Octo-SPI interfaces. Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of single/dual/quad/octal SPI over the same bus can be achieved using the integrated OctoSPI I/O manager (OCTOSPIM). The OCTOSPI can operate in any of the three following modes: * Indirect mode: all the operations are performed using the OCTOSPI registers * Status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting * Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an internal memory supporting both read and write operations. The OCTOSPI supports two frame formats supported by most external serial memories such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and Hyper Flash memories. Multi chip package (MCP) combining any of the above mentioned memory types can also be supported. 32/226 * The classical frame format with the command, address, alternate byte, dummy cycles and data phase * The HyperBusTM frame format. DS13313 Rev 1 STM32H723xE/G 3.19 Functional overview Analog-to-digital converters (ADCs) STM32H723xE/G devices embed three analog-to-digital converters, two of 16-bit resolution, and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14, 12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits. Each ADC shares up to 20 external channels, performing conversions in Single-shot or Scan mode. In Scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC converted values to a destination location without any software action. In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some, or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers. 3.20 Temperature sensor STM32H723xE/G devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from - 40 to +125C. The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is accessible in Read-only mode. 3.21 Digital temperature sensor (DTS) STM32H723xE/G devices embed a sensor that converts the temperature into a square wave the frequency of which is proportional to the temperature. The PCLK or the LSE clock can be used as the reference clock for the measurements. A formula given in the product reference manual allows calculation of the temperature according to the measured frequency stored in the DTS_DR register. DS13313 Rev 1 33/226 52 Functional overview 3.22 STM32H723xE/G VBAT operation The VBAT power domain contains the RTC, the backup registers and the backup SRAM. To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped below the PDR level. The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in which case, the VBAT mode is not functional. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.23 Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * left or right data alignment in 12-bit mode * synchronized update capability * noise-wave generation * triangular-wave generation * dual DAC channel independent or simultaneous conversions * DMA capability for each channel including DMA underrun error detection * external triggers for conversion * input voltage reference VREF+ or internal VREFBUF reference. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 34/226 DS13313 Rev 1 STM32H723xE/G 3.24 Functional overview Ultra-low-power comparators (COMP) STM32H723xE/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output polarity. The reference voltage can be one of the following: * An external I/O * A DAC output channel * An internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into a window comparator. 3.25 Operational amplifiers (OPAMP) STM32H723xE/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability. The operational amplifier main features are: * PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15 * One positive input connected to DAC * Output connected to internal ADC * Low input bias current down to 1 nA * Low input offset voltage down to 1.5 mV * Gain bandwidth up to 7.3 MHz The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. DS13313 Rev 1 35/226 52 Functional overview 3.26 STM32H723xE/G Digital filter for sigma-delta modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from internal ADC peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: * * 8 multiplexed input digital serial channels: - configurable SPI interface to connect various SD modulator(s) - configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): - * - Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) - integrator: oversampling ratio (1..256) * up to 24-bit output data resolution, signed output data format * automatic data offset correction (offset stored in register by user) * continuous or single conversion * start-of-conversion triggered by: * * * 36/226 internal sources: ADC data or memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: - software trigger - internal timers - external events - start-of-conversion synchronously with first digital filter module (DFSDM0) analog watchdog feature: - low value and high value data threshold registers - dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) - input from final output data or from selected input digital serial channels - continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): - up to 8-bit counter to detect 1..256 consecutive 0's or 1's on serial data stream - monitoring continuously each input serial channel break signal generation on analog watchdog event or on short circuit detector event DS13313 Rev 1 STM32H723xE/G * Functional overview extremes detector: - storage of minimum and maximum values of final conversion data - refreshed by software * DMA capability to read the final conversion data * interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence * "regular" or "injected" conversions: * - "regular" conversions can be requested at any time or even in Continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority Pulse skipper feature to support beamforming applications (delay-line like behavior). Table 3. DFSDM implementation DFSDM features DFSDM1 Number of filters 4 Number of input transceivers/channels 8 Internal ADC parallel input X Number of external triggers 16 Regular channel information in identification register X DS13313 Rev 1 37/226 52 Functional overview 3.27 STM32H723xE/G Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It features: 3.28 * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports Continuous mode or Snapshot (a single frame) mode * Capability to automatically crop the image PSSI The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It allows the transmitter to send a data valid signal to indicate when the data is valid, and the receiver to output a flow control signal to indicate when it is ready to sample the data. The main PSSI features are: * Slave mode operation * 8- or 16-bit parallel data input or output * 8-word (32-byte) FIFO * Data enable (DE) alternate function input and Ready (RDY) alternate function output. When enabled, these signals can either allow the transmitter to indicate when the data is valid or, the receiver to indicate when it is ready to sample the data, or both. The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore cannot be used simultaneously with the DCMI. 3.29 LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024 x 768) resolution with the following features: 38/226 * 2 display layers with dedicated FIFO (64x64-bit) * Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events * AXI master interface with burst of 16 words DS13313 Rev 1 STM32H723xE/G 3.30 Functional overview Random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as a NIST SP 800-90B compliant entropy source. The RNG true random number generator has been tested using German BSI statistical tests of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite. DS13313 Rev 1 39/226 52 Functional overview 3.31 STM32H723xE/G Timers and watchdogs The devices include two advanced-control timers, twelve general-purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer. All timer counters can be frozen in Debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Advanced -control Timer TIM1, TIM8 TIM2, TIM5, TIM23, TIM24 TIM3, TIM4 TIM12 DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels TIM15 TIM16, TIM17 40/226 Max interface clock (MHz) Max timer clock (MHz) (1) 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 137.5 275 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 137.5 275 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 137.5 275 16-bit Up Any integer between 1 and 65536 No 2 No 137.5 275 Up Any integer between 1 and 65536 No 1 No 137.5 275 Up Any integer between 1 and 65536 Yes 2 1 137.5 275 Up Any integer between 1 and 65536 Yes 1 1 137.5 275 General purpose TIM13, TIM14 Complementary output 16-bit 16-bit 16-bit DS13313 Rev 1 STM32H723xE/G Functional overview Table 4. Timer feature comparison (continued) Timer type Timer DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Complementary output Max interface clock (MHz) Max timer clock (MHz) (1) Yes 0 No 137.5 275 No 0 No 137.5 275 1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register. DS13313 Rev 1 41/226 52 Functional overview 3.31.1 STM32H723xE/G Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (Edge- or Center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.31.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32H723xE/G devices (see Table 4: Timer feature comparison for differences). * TIM2, TIM3, TIM4, TIM5, TIM23, TIM24 The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or One-pulse mode output. This gives up to 24 input capture/output compare/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases. 42/226 DS13313 Rev 1 STM32H723xE/G 3.31.3 Functional overview Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.31.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.31.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / One-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. A window option allows the device to be reset when a reload operation is made too early after the previous reload. 3.31.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. 3.31.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: * A 24-bit down counter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. DS13313 Rev 1 43/226 52 Functional overview 3.32 STM32H723xE/G Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator (LSE) * The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 44/226 DS13313 Rev 1 STM32H723xE/G 3.33 Functional overview Inter-integrated circuit interface (I2C) STM32H723xE/G devices embed five I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * 3.34 I2C-bus specification and user manual rev. 5 compatibility: - Slave and Master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Wakeup from Stop mode on address match * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Universal synchronous/asynchronous receiver transmitter (USART) STM32H723xE/G devices have five embedded universal synchronous receiver transmitters (USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 5: USART features for a summary of USARTx and UARTx features. These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire Half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 12.5 Mbit/s. USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. DS13313 Rev 1 45/226 52 Functional overview STM32H723xE/G All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: * Start bit detection * Any received data frame * A specific programmed data frame * Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 5. USART features USART modes/features(1) USART1/2/3/6/10 UART4/5/7/8/9 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode (Master/Slave) X - Smartcard mode X - Single-wire Half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain and wakeup from low power mode X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X USART data length 7, 8 and 9 bits Tx/Rx FIFO X Tx/Rx FIFO size X 16 1. X = supported. 3.35 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART (LPUART1). The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. 46/226 DS13313 Rev 1 STM32H723xE/G Functional overview The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: * Start bit detection * Any received data frame * A specific programmed data frame * Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.36 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability. Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available. They can be operated in Master or Slave mode, in Simplex communication modes, and can be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6 which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in Master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability. 3.37 Serial audio interfaces (SAI) The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC'97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. DS13313 Rev 1 47/226 52 Functional overview 3.38 STM32H723xE/G SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: * Up to 4 inputs available * Automatic symbol rate detection * Maximum symbol rate: 12.288 MHz * Stereo stream from 32 to 192 kHz supported * Supports Audio IEC-60958 and IEC-61937, consumer applications * Parity bit management * Communication using DMA for audio samples * Communication using DMA for control and user channel information * Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 3.39 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: * Full-duplex communication mode * automatic SWP bus state management (active, suspend, resume) * configurable bitrate up to 2 Mbit/s * automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 48/226 DS13313 Rev 1 STM32H723xE/G 3.40 Functional overview Management data input/output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: * - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers * Configurable slave (port) address * Independently maskable interrupts/events: * 3.41 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: - MDIO Register write - MDIO Register read - MDIO protocol error Able to operate in and wake up from Stop mode SD/SDIO/MMC card host interfaces (SDMMC) Two SDMMC host interfaces are available. They support MultiMediaCard System Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits. Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits. Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM. 3.42 Controller area network (FDCAN1, FDCAN2, FDCAN3) The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit. All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is shared between the three modules - FDCAN1 FDCAN2 and FDCAN3. The common clock calibration unit is optional. It can be used to generate a calibrated clock for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1. DS13313 Rev 1 49/226 52 Functional overview 3.43 STM32H723xE/G Universal serial bus on-the-go high-speed (OTG_HS) The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral that supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external PHY device connected to the ULPI is required. The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It features software-configurable endpoint setting and supports suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The main features are: 3.44 * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. 50/226 DS13313 Rev 1 STM32H723xE/G Functional overview The devices include the following features: 3.45 * Supports 10 and 100 Mbit/s rates * Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors * Tagged MAC frame support (VLAN support) * Half-duplex (CSMA/CD) and full-duplex operation * MAC control sublayer (control frames) support * 32-bit CRC generation and removal * Several address filtering modes for physical and multicast address (multicast and group addresses) * 32-bit status code for each transmitted or received frame * Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. * Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input * Triggers interrupt when system time becomes greater than target time High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.46 Debug infrastructure The devices offer a comprehensive set of debug and trace features to support software development and system integration. * Breakpoint debugging * Code execution tracing * Software instrumentation * JTAG debug port * Serial-wire debug port * Trigger input and output * Serial-wire trace port * Trace port * Arm(R) CoreSightTM debug and trace components The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. The trace port performs data capture for logging and analysis. DS13313 Rev 1 51/226 52 Memory mapping 4 STM32H723xE/G Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 52/226 DS13313 Rev 1 STM32H723xE/G 5 Pinouts, pin descriptions and alternate functions Pinouts, pin descriptions and alternate functions Figure 4. TFBGA100 pinout 1 2 3 4 5 6 7 8 9 10 A PC14OSC32_IN PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C PH0-OSC_IN VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D PH1OSC_OUT VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2_C PE6 VSS VSS VSS VCAP PD1 PC9 PC7 F PC0 PC1 PC3_C VDD VDD VDD33USB PDR_ON VCAP PC8 PC6 G VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15 H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14 J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 MSv52520V1. 1. The above figure shows the package top view. DS13313 Rev 1 53/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 5. LQFP100 pinout PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VCAP PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2_C 17 59 PD12 PC3_C 18 58 PD11 VSSA 19 57 PD10 VREF+ 20 56 PD9 VDDA 21 55 PD8 PA0 22 54 PB15 PA1 23 53 PB14 PA2 24 52 PB13 PA3 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDD LQFP100 MSv52521V1. 1. The above figure shows the package top view. 54/226 DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6. LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD33USB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VDD VSSA VREF+ VDDA PA0 PA1 PA2 MSv52522V1. 1. The above figure shows the package top view. DS13313 Rev 1 55/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Figure 7. UFBGA144 ballout 1 2 3 4 5 6 7 8 9 10 11 12 A PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13 B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 VDD33USB PA11 D PH0-OSC_IN VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E PH1OSC_OUT PF3 PF4 PF5 PDR_ON VSS VSS PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7 G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP VSS PG8 PC6 H PC0 PC1 PC2 PC3 VSS VSS VCAP PE11 PD11 PG7 PG6 PG5 J VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 MSv52523V1. 1. The above figure shows the package top view. Table 6. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.3 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Notes 56/226 Definition Bidirectional reset pin with embedded weak pull-up resistor Option for TT and FT I/Os _f I2C FM+ option _a analog option (supplied by VDDA) _u USB option (supplied by VDD33USB) _h High-speed low-voltage I/O Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 6. Legend/abbreviations used in the pinout table (continued) Name Pin functions Abbreviation Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 7. STM32H723 pin and ball descriptions 1 A3 PE2 I/O FT_h - B3 2 2 A2 PE3 I/O FT_h - TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, USART10_TX, FMC_A19, EVENTOUT - - TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SAI4_FS_A, SAI4_D2, FMC_A20, DCMI_D4/PSSI_D4, LCD_B0, EVENTOUT - - TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SAI4_SCK_A, SAI4_CK2, FMC_A21, DCMI_D6/PSSI_D6, LCD_G0, EVENTOUT - - C3 D3 3 4 3 4 UFBGA144 1 LQFP144 A3 TRACECLK, SAI1_CK1, USART10_RX, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, OCTOSPIM_P1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure Pin type Pin number B2 B3 Pin name (function after reset) PE4 PE5 I/O I/O FT_h FT_h Additional functions - E3 5 5 B4 PE6 I/O FT_h - TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI4_SD_A, SAI4_D1, SAI4_MCLK_B, TIM1_BKIN2_COMP12, FMC_A22, DCMI_D7/PSSI_D7, LCD_G1, EVENTOUT B2 6 6 C2 VBAT S - - - - A2 7 7 A1 PC13 I/O FT - EVENTOUT RTC_TAMP1/ RTC_TS, WKUP4 A1 8 8 B1 PC14-OSC32_IN I/O FT - EVENTOUT OSC32_IN B1 9 9 C1 PC15-OSC32_OUT I/O FT - EVENTOUT OSC32_OUT DS13313 Rev 1 57/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) TFBGA100 LQFP100 LQFP144 UFBGA144 Pin name (function after reset) Pin type I/O structure Notes Pin number Alternate functions - - 10 C3 PF0 I/O FT_fh - I2C2_SDA(boot), I2C5_SDA, OCTOSPIM_P2_IO0, FMC_A0, TIM23_CH1, EVENTOUT - - - 11 C4 PF1 I/O FT_fh - I2C2_SCL(boot), I2C5_SCL, OCTOSPIM_P2_IO1, FMC_A1, TIM23_CH2, EVENTOUT - - - 12 D4 PF2 I/O FT_h - I2C2_SMBA, I2C5_SMBA, OCTOSPIM_P2_IO2, FMC_A2, TIM23_CH3, EVENTOUT - - - 13 E2 PF3 I/O FT_ha - OCTOSPIM_P2_IO3, FMC_A3, TIM23_CH4, EVENTOUT ADC3_INP5 - - 14 E3 PF4 I/O FT_ha - OCTOSPIM_P2_CLK, FMC_A4, EVENTOUT ADC3_INN5, ADC3_INP9 - - 15 E4 PF5 I/O FT_ha - OCTOSPIM_P2_NCLK, FMC_A5, EVENTOUT ADC3_INP4 - 10 16 - VSS S - - - - - 11 17 - VDD S - - - - - - 18 F3 PF6 I/O FT_ha - TIM16_CH1, FDCAN3_RX, SPI5_NSS, SAI1_SD_B, UART7_RX, SAI4_SD_B, OCTOSPIM_P1_IO3, TIM23_CH1, EVENTOUT ADC3_INN4, ADC3_INP8 - TIM17_CH1, FDCAN3_TX, SPI5_SCK, SAI1_MCLK_B, UART7_TX, SAI4_MCLK_B, OCTOSPIM_P1_IO2, TIM23_CH2, EVENTOUT ADC3_INP3 - TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, SAI4_SCK_B, TIM13_CH1, OCTOSPIM_P1_IO0, TIM23_CH3, EVENTOUT ADC3_INN3, ADC3_INP7 ADC3_INP2 - - - - 19 20 F2 G3 PF7 PF8 I/O I/O FT_ha FT_ha Additional functions - - 21 G2 PF9 I/O FT_ha - TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, SAI4_FS_B, TIM14_CH1, OCTOSPIM_P1_IO1, TIM23_CH4, EVENTOUT - - 22 G1 PF10 I/O FT_ha - TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPIM_P1_CLK, SAI4_D3, DCMI_D11/PSSI_D11, LCD_DE, EVENTOUT ADC3_INN2, ADC3_INP6 C1 12 23 D1 PH0-OSC_IN I/O FT - EVENTOUT OSC_IN 58/226 DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) TFBGA100 LQFP100 LQFP144 UFBGA144 Pin name (function after reset) Pin type I/O structure Notes Pin number Alternate functions D1 13 24 E1 PH1-OSC_OUT I/O FT - EVENTOUT OSC_OUT E1 14 25 F1 NRST I/O RST - - - - FMC_D12/FMC_AD12, DFSDM1_CKIN0, DFSDM1_DATIN4, SAI4_FS_B, FMC_A25, OTG_HS_ULPI_STP, LCD_G2, FMC_SDNWE, LCD_R5, EVENTOUT ADC123_INP10 - TRACED0, SAI4_D1, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SAI4_SD_A, SDMMC2_CK, OCTOSPIM_P1_IO4, ETH_MDC, MDIOS_MDC, LCD_G5, EVENTOUT ADC123_INN10, ADC123_INP11, RTC_TAMP3, WKUP6 ADC123_INN11, ADC123_INP12 F1 F2 15 16 26 27 H1 H2 PC0 PC1 I/O I/O FT_ha FT_ha Additional functions - - - H3 PC2 I/O FT_a - PWR_DEEPSLEEP, DFSDM1_CKIN1, OCTOSPIM_P1_IO5, SPI2_MISO/I2S2_SDI, DFSDM1_CKOUT, OCTOSPIM_P1_IO2, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT E2 17 28 - PC2_C AN A TT_a - - ADC3_INN1, ADC3_INP0 ADC12_INN12, ADC12_INP13 - - - H4 PC3 I/O FT_a - PWR_SLEEP, DFSDM1_DATIN1, OCTOSPIM_P1_IO6, SPI2_MOSI/I2S2_SDO, OCTOSPIM_P1_IO0, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT F3 18 29 - PC3_C AN A TT_a - - ADC3_INP1 - - 30 - VDD S - - - - G1 19 31 J1 VSSA S - - - - - - - K1 VREF- S - - - - - 20 32 L1 VREF+ S - - - - H1 21 33 M1 VDDA S - - - - DS13313 Rev 1 59/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) H2 J2 22 23 24 35 36 J2 K2 L2 PA0 PA1 PA2 I/O I/O I/O I/O structure Pin type UFBGA144 LQFP144 34 Pin name (function after reset) FT_ha FT_ha FT_ha Notes G2 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS/I2S6_WS, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI4_SD_B, ETH_MII_CRS, FMC_A19, EVENTOUT ADC1_INP16, WKUP1 - TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS/USART2_DE, UART4_RX, OCTOSPIM_P1_IO3, SAI4_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_REF_C LK, OCTOSPIM_P1_DQS, LCD_R2, EVENTOUT ADC1_INN16, ADC1_INP17 - TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, OCTOSPIM_P1_IO0, USART2_TX(boot), SAI4_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC12_INP14, WKUP2 ADC12_INP15 K2 25 37 M2 PA3 I/O FT_ha - TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, I2S6_MCK, OCTOSPIM_P1_IO2, USART2_RX(boot), LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, OCTOSPIM_P1_CLK, LCD_B5, EVENTOUT - 26 38 - VSS S - - - - - 27 39 - VDD S - - - - - D1PWREN, TIM5_ETR, SPI1_NSS(boot)/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS/I2S6_WS, FMC_D8/FMC_AD8, DCMI_HSYNC/PSSI_DE, LCD_VSYNC, EVENTOUT ADC12_INP18, DAC1_OUT1 - D2PWREN, TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK(boot)/I2S1_CK, SPI6_SCK/I2S6_CK, OTG_HS_ULPI_CK, FMC_D9/FMC_AD9, PSSI_D14, LCD_R4, EVENTOUT ADC12_INN18, ADC12_INP19, DAC1_OUT2 G3 H3 60/226 28 29 40 41 J3 K3 PA4 PA5 I/O I/O TT_ha TT_ha DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) K3 G4 H4 J4 K4 G5 30 31 32 33 34 35 36 43 44 45 46 47 48 L3 M3 J4 K4 L4 M4 J5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 I/O I/O I/O I/O I/O I/O I/O I/O structure Pin type UFBGA144 LQFP144 42 Pin name (function after reset) FT_ha TT_ha TT_ha TT_ha TT_ha FT_ha FT_ha Notes J3 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO(boot)/I2S1_SDI, OCTOSPIM_P1_IO3, SPI6_MISO/I2S6_SDI, TIM13_CH1, TIM8_BKIN_COMP12, MDIOS_MDC, TIM1_BKIN_COMP12, DCMI_PIXCLK/PSSI_PDCK, LCD_G2, EVENTOUT ADC12_INP3 - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI(boot)/I2S1_SDO, SPI6_MOSI/I2S6_SDO, TIM14_CH1, OCTOSPIM_P1_IO2, ETH_MII_RX_DV/ETH_RMII_CRS_DV, FMC_SDNWE, LCD_VSYNC, EVENTOUT ADC12_INN3, ADC12_INP7, OPAMP1_VINM - PWR_DEEPSLEEP, FMC_A22, DFSDM1_CKIN2, I2S1_MCK, SPDIFRX1_IN3, SDMMC2_CKIN, ETH_MII_RXD0/ETH_RMII_RXD0, FMC_SDNE0, LCD_R7, EVENTOUT ADC12_INP4, OPAMP1_VOUT, COMP1_INM - PWR_SLEEP, SAI4_D3, SAI1_D3, DFSDM1_DATIN2, PSSI_D15, SPDIFRX1_IN4, OCTOSPIM_P1_DQS, ETH_MII_RXD1/ETH_RMII_RXD1, FMC_SDCKE0, COMP1_OUT, LCD_DE, EVENTOUT ADC12_INN4, ADC12_INP8, OPAMP1_VINM - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, OCTOSPIM_P1_IO1, DFSDM1_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC12_INN5, ADC12_INP9, OPAMP1_VINP, COMP1_INP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OCTOSPIM_P1_IO0, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC12_INP5, COMP1_INM - RTC_OUT, SAI4_D1, SAI1_D1, DFSDM1_CKIN1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, SAI4_SD_A, OCTOSPIM_P1_CLK, OCTOSPIM_P1_DQS, ETH_TX_ER, TIM23_ETR, EVENTOUT COMP1_INP DS13313 Rev 1 61/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) 49 M5 PF11 I/O FT_ha - - - 50 L5 PF12 I/O FT_ha - OCTOSPIM_P2_DQS, FMC_A6, TIM24_CH2, EVENTOUT ADC1_INN2, ADC1_INP6 - - 51 - VSS S - - - - - - 52 - VDD S - - - - - - 53 K5 PF13 I/O FT_ha - DFSDM1_DATIN6, I2C4_SMBA, FMC_A7, TIM24_CH3, EVENTOUT ADC2_INP2 - - 54 M6 PF14 I/O FT_fha - DFSDM1_CKIN6, I2C4_SCL, FMC_A8, TIM24_CH4, EVENTOUT ADC2_INN2, ADC2_INP6 - - 55 L6 PF15 I/O FT_fh - I2C4_SDA, FMC_A9, EVENTOUT - - - 56 K6 PG0 I/O FT_h - OCTOSPIM_P2_IO4, UART9_RX, FMC_A10, EVENTOUT - - - 57 J6 PG1 I/O TT_h - OCTOSPIM_P2_IO5, UART9_TX, FMC_A11, EVENTOUT OPAMP2_VINM H5 37 58 M7 PE7 I/O TT_ha - TIM1_ETR, DFSDM1_DATIN2, UART7_RX, OCTOSPIM_P1_IO4, FMC_D4/FMC_AD4, EVENTOUT OPAMP2_VOUT, COMP2_INM OPAMP2_VINM UFBGA144 - LQFP144 - SPI5_MOSI, OCTOSPIM_P1_NCLK, SAI4_SD_B, FMC_NRAS, DCMI_D12/PSSI_D12, TIM24_CH1, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure Pin type Pin number Pin name (function after reset) Additional functions ADC1_INP2 J5 38 59 L7 PE8 I/O TT_ha - TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, OCTOSPIM_P1_IO5, FMC_D5/FMC_AD5, COMP2_OUT, EVENTOUT K5 39 60 K7 PE9 I/O TT_ha - TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, OCTOSPIM_P1_IO6, FMC_D6/FMC_AD6, EVENTOUT OPAMP2_VINP, COMP2_INP - - 61 - VSS S - - - - - - 62 - VDD S - - - - G6 40 63 J7 PE10 I/O FT_ha - TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, OCTOSPIM_P1_IO7, FMC_D7/FMC_AD7, EVENTOUT COMP2_INM - TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS(boot), SAI4_SD_B, OCTOSPIM_P1_NCS, FMC_D8/FMC_AD8, LCD_G3, EVENTOUT COMP2_INP H6 62/226 41 64 H8 PE11 I/O FT_ha DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) 65 J8 PE12 I/O FT_h - K6 43 66 K8 PE13 I/O FT_h - TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO(boot), SAI4_FS_B, FMC_D10/FMC_AD10, COMP2_OUT, LCD_DE, EVENTOUT - G7 44 67 L8 PE14 I/O FT_h - TIM1_CH4, SPI4_MOSI(boot), SAI4_MCLK_B, FMC_D11/FMC_AD11, LCD_CLK, EVENTOUT - - TIM1_BKIN, USART10_CK, FMC_D12/FMC_AD12, TIM1_BKIN_COMP12, LCD_R7, EVENTOUT - - TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX(boot), OCTOSPIM_P1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - - H7 J7 45 46 68 69 UFBGA144 42 LQFP144 J6 TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK(boot), SAI4_SCK_B, FMC_D9/FMC_AD9, COMP1_OUT, LCD_B4, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure Pin type Pin number M8 M9 Pin name (function after reset) PE15 PB10 I/O I/O FT_h FT_fh Additional functions - K7 47 70 M10 PB11 I/O FT_f - TIM2_CH4, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX(boot), OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, LCD_G5, EVENTOUT F8 48 71 H7 VCAP S - - - - - 49 - - VSS S - - - - - 50 72 - VDD S - - - - - TIM1_BKIN, OCTOSPIM_P1_NCLK, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OCTOSPIM_P1_IO0, TIM1_BKIN_COMP12, UART5_RX, EVENTOUT - K8 51 73 M11 PB12 I/O FT_h DS13313 Rev 1 63/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) H10 52 53 75 M12 L11 PB13 PB14 I/O I/O I/O structure Pin type UFBGA144 LQFP144 74 Pin name (function after reset) FT_h FT_h Notes J8 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - TIM1_CH1N, LPTIM2_OUT, OCTOSPIM_P1_IO2, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART3_NSS, FDCAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, SDMMC1_D0, DCMI_D2/PSSI_D2, UART5_TX, EVENTOUT - - TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SDMMC2_D0, FMC_D10/FMC_AD10, LCD_CLK, EVENTOUT - - G10 54 76 L12 PB15 I/O FT_h - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM1_CKIN2, UART4_CTS, SDMMC2_D1, FMC_D11/FMC_AD11, LCD_G7, EVENTOUT K9 55 77 L9 PD8 I/O FT_h - DFSDM1_CKIN3, USART3_TX(boot), SPDIFRX1_IN2, FMC_D13/FMC_AD13, EVENTOUT - J9 56 78 K9 PD9 I/O FT_h - DFSDM1_DATIN3, USART3_RX(boot), FMC_D14/FMC_AD14, EVENTOUT - H9 57 79 J9 PD10 I/O FT_h - DFSDM1_CKOUT, USART3_CK, FMC_D15/FMC_AD15, LCD_B3, EVENTOUT - - LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, OCTOSPIM_P1_IO0, SAI4_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, FDCAN3_RX, USART3_RTS/USART3_DE, OCTOSPIM_P1_IO1, SAI4_FS_A, FMC_A17/FMC_ALE, DCMI_D12/PSSI_D12, EVENTOUT - G9 K10 64/226 58 59 80 81 H9 L10 PD11 PD12 I/O I/O FT_h FT_fh DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) 82 K10 PD13 I/O FT_fh - - - 83 - VSS S - - - - - - 84 - VDD S - - - - H8 61 85 K11 PD14 I/O FT_h - TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/FMC_AD0, EVENTOUT - G8 62 86 K12 PD15 I/O FT_h - TIM4_CH4, UART8_RTS/UART8_DE, UART9_TX, FMC_D1/FMC_AD1, EVENTOUT - - - 87 J12 PG2 I/O FT_h - TIM8_BKIN, TIM8_BKIN_COMP12, FMC_A12, TIM24_ETR, EVENTOUT - - - 88 J11 PG3 I/O FT_h - TIM8_BKIN2, TIM8_BKIN2_COMP12, FMC_A13, TIM23_ETR, EVENTOUT - - - 89 J10 PG4 I/O FT_h - TIM1_BKIN2, TIM1_BKIN2_COMP12, FMC_A14/FMC_BA0, EVENTOUT - - - 90 H12 PG5 I/O FT_h - TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT - - - 91 H11 PG6 I/O FT_h - TIM17_BKIN, OCTOSPIM_P1_NCS, FMC_NE3, DCMI_D12/PSSI_D12, LCD_R7, EVENTOUT - - - 92 H10 PG7 I/O FT_h - SAI1_MCLK_A, USART6_CK, OCTOSPIM_P2_DQS, FMC_INT, DCMI_D13/PSSI_D13, LCD_CLK, EVENTOUT - - UFBGA144 60 LQFP144 J10 LPTIM1_OUT, TIM4_CH2, I2C4_SDA, FDCAN3_TX, OCTOSPIM_P1_IO3, SAI4_SCK_A, UART9_RTS/UART9_DE, FMC_A18, DCMI_D13/PSSI_D13, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure Pin type Pin number Pin name (function after reset) Additional functions - - - 93 G11 PG8 I/O FT_h - TIM8_ETR, SPI6_NSS/I2S6_WS, USART6_RTS/USART6_DE, SPDIFRX1_IN3, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT - - 94 - VSS S - - - - F6 - 95 C11 VDD33USB S - - - - - TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0/PSSI_D0, LCD_HSYNC, EVENTOUT SWPMI_IO F10 63 96 G12 PC6 I/O FT_h DS13313 Rev 1 65/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) F9 E9 D9 C9 D10 C10 B10 66/226 64 65 66 67 68 69 70 71 98 99 100 101 102 103 104 F12 F11 E11 E12 D12 D11 C12 B12 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 I/O I/O I/O I/O I/O I/O I/O I/O I/O structure Pin type UFBGA144 LQFP144 97 Pin name (function after reset) FT_h FT_h FT_fh FT_fh FT_u FT_u FT_u FT_u Notes E10 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - DBTRGIO, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, SWPMI_TX, SDMMC1_D7, DCMI_D1/PSSI_D1, LCD_G6, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE, FMC_NE2/FMC_NCE, FMC_INT, SWPMI_RX, SDMMC1_D0, DCMI_D2/PSSI_D2, EVENTOUT - - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA(boot), I2S_CKIN, I2C5_SDA, UART5_CTS, OCTOSPIM_P1_IO0, LCD_G3, SWPMI_SUSPEND, SDMMC1_D1, DCMI_D3/PSSI_D3, LCD_B2, EVENTOUT - - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL(boot), I2C5_SCL, USART1_CK, OTG_HS_SOF, UART7_RX, TIM8_BKIN2_COMP12, LCD_B3, LCD_R6, EVENTOUT - - TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, I2C5_SMBA, USART1_TX(boot), ETH_TX_ER, DCMI_D0/PSSI_D0, LCD_R5, EVENTOUT OTG_HS_VBUS - TIM1_CH3, LPUART1_RX, USART1_RX(boot), OTG_HS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1/PSSI_D1, LCD_B1, EVENTOUT - - TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, LCD_R4, EVENTOUT OTG_HS_DM (boot) - TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI4_FS_B, FDCAN1_TX, TIM1_BKIN2, LCD_R5, EVENTOUT OTG_HS_DP (boot) DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) TFBGA100 LQFP100 LQFP144 UFBGA144 Pin name (function after reset) Pin type I/O structure Notes Pin number Alternate functions A10 72 105 A12 PA13(JTMS/SWDIO) I/O FT - JTMS/SWDIO, EVENTOUT - E7 73 106 G9 VCAP S - - - - - 74 107 - VSS S - - - - - 75 108 - VDD S - - - - A9 76 109 A11 PA14(JTCK/SWCLK) I/O FT - JTCK/SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS/I2S6_WS, UART4_RTS/UART4_DE, LCD_R3, UART7_TX, LCD_B6, EVENTOUT - - DFSDM1_CKIN5, I2C5_SDA, SPI3_SCK(boot)/I2S3_CK, USART3_TX, UART4_TX, OCTOSPIM_P1_IO1, LCD_B1, SWPMI_RX, SDMMC1_D2, DCMI_D8/PSSI_D8, LCD_R2, EVENTOUT - - DFSDM1_DATIN5, I2C5_SCL, SPI3_MISO(boot)/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPIM_P1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4, LCD_B4, EVENTOUT - - TRACED3, FMC_D6/FMC_AD6, TIM15_CH1, I2C5_SMBA, SPI6_SCK/I2S6_CK, SPI3_MOSI(boot)/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9, LCD_R6, EVENTOUT - - - A8 B9 B8 C8 77 78 79 80 110 111 112 113 A10 B11 B10 C10 PA15(JTDI) PC10 PC11 PC12 I/O I/O I/O I/O FT FT_fh FT_fh FT_h D8 81 114 E10 PD0 I/O FT_h - DFSDM1_CKIN6, UART4_RX, FDCAN1_RX(boot), UART9_CTS, FMC_D2/FMC_AD2, LCD_B1, EVENTOUT E8 82 115 D10 PD1 I/O FT_h - DFSDM1_DATIN6, UART4_TX, FDCAN1_TX(boot), FMC_D3/FMC_AD3, EVENTOUT DS13313 Rev 1 Additional functions 67/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) 83 E9 PD2 I/O I/O structure Pin type UFBGA144 LQFP144 116 Pin name (function after reset) FT_h Notes B7 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - TRACED2, FMC_D7/FMC_AD7, TIM3_ETR, TIM15_BKIN, UART5_RX, LCD_B7, SDMMC1_CMD, DCMI_D11/PSSI_D11, LCD_B2, EVENTOUT - - C7 84 117 D9 PD3 I/O FT_h - DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK, DCMI_D5/PSSI_D5, LCD_G7, EVENTOUT D7 85 118 C9 PD4 I/O FT_h - USART2_RTS/USART2_DE, OCTOSPIM_P1_IO4, FMC_NOE, EVENTOUT - B6 86 119 B9 PD5 I/O FT_h - USART2_TX, OCTOSPIM_P1_IO5, FMC_NWE, EVENTOUT - - - 120 - VSS S - - - - - - 121 - VDD S - - - - - SAI4_D1, SAI1_D1, DFSDM1_CKIN4, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, SAI4_SD_A, OCTOSPIM_P1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10, LCD_B2, EVENTOUT - - DFSDM1_DATIN4, SPI1_MOSI/I2S1_SDO, DFSDM1_CKIN1, USART2_CK, SPDIFRX1_IN1, OCTOSPIM_P1_IO7, SDMMC2_CMD, FMC_NE1, EVENTOUT - - FDCAN3_TX, SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX1_IN4, OCTOSPIM_P1_IO6, SAI4_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC/PSSI_RDY, EVENTOUT - - FDCAN3_RX, OCTOSPIM_P2_IO6, SPI1_NSS/I2S1_WS, LCD_G3, SAI4_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2, LCD_B2, EVENTOUT - C6 D6 - - 68/226 87 88 - - 122 123 124 125 A8 A9 E8 D8 PD6 PD7 PG9 PG10 I/O I/O I/O I/O FT_h FT_h FT_h FT_h DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) - - - - - 127 128 C8 B8 D7 PG11 PG12 PG13 I/O I/O I/O I/O structure Pin type UFBGA144 LQFP144 126 Pin name (function after reset) FT_h FT_h FT_h Notes - LQFP100 TFBGA100 Pin number Alternate functions Additional functions - LPTIM1_IN2, USART10_RX, SPI1_SCK/I2S1_CK, SPDIFRX1_IN1, OCTOSPIM_P2_IO7, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_TX_EN, DCMI_D3/PSSI_D3, LCD_B3, EVENTOUT - - LPTIM1_IN1, OCTOSPIM_P2_NCS, USART10_TX, SPI6_MISO/I2S6_SDI, USART6_RTS/USART6_DE, SPDIFRX1_IN2, LCD_B4, SDMMC2_D3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_NE4, TIM23_CH1, LCD_B1, EVENTOUT - - TRACED0, LPTIM1_OUT, USART10_CTS/USART10_NSS, SPI6_SCK/I2S6_CK, USART6_CTS/USART6_NSS, SDMMC2_D6, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_A24, TIM23_CH2, LCD_R0, EVENTOUT - - - - 129 C7 PG14 I/O FT_h - TRACED1, LPTIM1_ETR, USART10_RTS/USART10_DE, SPI6_MOSI/I2S6_SDO, USART6_TX, OCTOSPIM_P1_IO7, SDMMC2_D7, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25, TIM23_CH3, LCD_B0, EVENTOUT - - 130 - VSS S - - - - - - 131 - VDD S - - - - - - 132 B7 PG15 I/O FT_h - USART6_CTS/USART6_NSS, OCTOSPIM_P2_DQS, USART10_CK, FMC_NCAS, DCMI_D13/PSSI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK/I2S6_CK, SDMMC2_D2, CRS_SYNC, UART7_RX, TIM24_ETR, EVENTOUT - A7 89 133 A7 PB3 (JTDO/TRACESWO) I/O FT_h DS13313 Rev 1 69/226 85 Pinouts, pin descriptions and alternate functions STM32H723xE/G Table 7. STM32H723 pin and ball descriptions (continued) C5 B5 90 91 92 135 136 A6 B6 C6 PB4(NJTRST) PB5 PB6 I/O I/O I/O I/O structure Pin type UFBGA144 LQFP144 134 Pin name (function after reset) FT_h FT_h FT_fh Notes A6 LQFP100 TFBGA100 Pin number Alternate functions Additional functions - NJTRST, TIM16_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO/I2S6_SDI, SDMMC2_D3, UART7_TX, EVENTOUT - - TIM17_BKIN, TIM3_CH2, LCD_B5, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI/I2S6_SDO, FDCAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10/PSSI_D10, UART5_RX, EVENTOUT - - TIM16_CH1N, TIM4_CH1, I2C1_SCL(boot), CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPIM_P1_NCS, DFSDM1_DATIN5, FMC_SDNE1, DCMI_D5/PSSI_D5, UART5_TX, EVENTOUT - PVD_IN A5 93 137 D6 PB7 I/O FT_fa - TIM17_CH1N, TIM4_CH2, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC/PSSI_RDY, EVENTOUT D5 94 138 D5 BOOT0 I B - - VPP - TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6/PSSI_D6, LCD_B6, EVENTOUT - - TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA(boot), SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7/PSSI_D7, LCD_B7, EVENTOUT - B4 A4 70/226 95 96 139 140 C5 B5 PB8 PB9 I/O I/O FT_fh FT_fh DS13313 Rev 1 STM32H723xE/G Pinouts, pin descriptions and alternate functions Table 7. STM32H723 pin and ball descriptions (continued) 141 A5 PE0 I/O FT_h - C4 98 142 A4 PE1 I/O FT_h - LPTIM1_IN2, UART8_TX, FMC_NBL1, DCMI_D3/PSSI_D3, LCD_R6, EVENTOUT - - 99 - - VSS S - - - - F7 - 143 E5 PDR_ON S - - - - - 100 144 - VDD S - - - - C2 - - D2 VSS S - - - - E6 - - E6 VSS S - - - - J1 - - E7 VSS S - - - - E4 - - G4 VSS S - - - - E5 - - G8 VSS S - - - - - - - G10 VSS S - - - - - - - H5 VSS S - - - - - - - H6 VSS S - - - - D2 - - D3 VDD S - - - - F5 - - F4 VDD S - - - - K1 - - F5 VDD S - - - - F4 - - F6 VDD S - - - - - - - F7 VDD S - - - - - - - F8 VDD S - - - - - - - F9 VDD S - - - - - - - F10 VDD S - - - - - - - G5 VDD S - - - - - - - G6 VDD S - - - - - - - G7 VDD S - - - - UFBGA144 97 LQFP144 D4 LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, UART8_RX, SAI4_MCLK_A, FMC_NBL0, DCMI_D2/PSSI_D2, LCD_R0, EVENTOUT LQFP100 Alternate functions TFBGA100 Notes I/O structure Pin type Pin number Pin name (function after reset) DS13313 Rev 1 Additional functions - 71/226 85 AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PA0 - TIM2_CH 1/TIM2_ ETR TIM5_CH1 TIM8_ ETR TIM15_ BKIN SPI6_ NSS/I2S 6_WS - USART2 _CTS/ USART2 _NSS UART4_ TX SDMMC2_ CMD SAI4_SD_ B ETH_MII_ CRS FMC_A19 - - EVENT OUT PA1 - TIM2_CH 2 TIM5_CH2 LPTIM3_ OUT TIM15_ CH1N - - USART2 _RTS/ USART2 _DE UART4_ RX OCTOSPI M_P1_IO3 SAI4_ MCLK_B ETH_MII_ RX_CLK/ ETH_RMII_ REF_CLK OCTOSPI M_P1_ DQS - LCD_ R2 EVENT OUT PA2 - TIM2_CH 3 TIM5_CH3 LPTIM4_ OUT TIM15_ CH1 - OCTOSPI M_P1_IO0 USART2 _TX SAI4_SCK _B - - ETH_MDIO MDIOS_ MDIO - LCD_R 1 EVENT OUT PA3 - TIM2_CH 4 TIM5_CH4 LPTIM5_ OUT TIM15_ CH2 I2S6_ MCK OCTOSPI M_P1_IO2 USART2 _RX - LCD_B2 OTG_HS_ ULPI_D0 ETH_MII_ COL OCTOSPI M_P1_ CLK - LCD_B 5 EVENT OUT PA4 D1PWR EN - TIM5_ ETR - - SPI1_ SPI3_NSS NSS/ /I2S3_WS I2S1_WS USART2 _CK SPI6_NSS /I2S6_WS - - - FMC_D8/ FMC_AD8 DCMI_ HSYNC/ PSSI_DE LCD_ VSYNC EVENT OUT PA5 D2PWR EN TIM2_CH 1/TIM2_ ETR - TIM8_CH 1N - SPI1_ SCK/ I2S1_CK - SPI6_SCK /I2S6_CK - OTG_HS_ ULPI_CK - FMC_D9/ FMC_AD9 PSSI_D1 4 LCD_R 4 EVENT OUT PA6 - TIM1_ BKIN TIM3_CH1 TIM8_ BKIN - SPI1_ OCTOSPI MISO/ M_P1_IO3 I2S1_SDI - SPI6_ TIM13_CH MISO/I2S6 1 _SDI TIM8_ BKIN_ COMP12 MDIOS_ MDC TIM1_ BKIN_ COMP12 DCMI_ PIXCLK/ PSSI_ PDCK LCD_G 2 EVENT OUT PA7 - TIM1_CH 1N TIM3_CH2 TIM8_CH 1N - SPI1_ MOSI/I2S 1_SDO - SPI6_ TIM14_CH MOSI/I2S6 1 _SDO OCTOSPI M_P1_IO2 ETH_MII_ RX_DV/ ETH_RMII_ CRS_DV FMC_SDN WE - LCD_ VSYNC EVENT OUT - - 72/226 Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port A AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions AF0 Port SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS TIM1_CH 1 - TIM8_ BKIN2 I2C3_ SCL - I2C5_SCL USART1 _CK - - OTG_HS_ SOF UART7_RX TIM8_ BKIN2_ COMP12 LCD_B3 LCD_R 6 EVENT OUT PA9 - TIM1_CH 2 - LPUART 1_TX I2C3_ SMBA SPI2_ SCK/ I2S2_CK I2C5_ SMBA USART1 _TX - - - ETH_TX_ ER - DCMI_ D0/PSSI _D0 LCD_R 5 EVENT OUT PA10 - TIM1_CH 3 - LPUART 1_RX - - - USART1 _RX - - OTG_HS_ ID MDIOS_ MDIO LCD_B4 DCMI_ D1/PSSI _D1 LCD_B 1 EVENT OUT PA11 - TIM1_CH 4 - LPUART 1_CTS - SPI2_ NSS/ I2S2_WS UART4_ RX USART1 _CTS/ USART1 _NSS - FDCAN1_ RX - - - - LCD_R 4 EVENT OUT PA12 - TIM1_ ETR - LPUART 1_RTS/ LPUART 1_DE - SPI2_ SCK/ I2S2_CK UART4_ TX USART1 _RTS/ USART1 _DE SAI4_FS_ B FDCAN1_ TX - - TIM1_ BKIN2 - LCD_R 5 EVENT OUT PA13 JTMS/ SWDIO - - - - - - - - - - - - - - EVENT OUT PA14 JTCK/ SWCLK - - - - - - - - - - - - - - EVENT OUT PA15 JTDI TIM2_ CH1/TIM2 _ETR - - CEC UART4_ RTS/ UART4_ DE LCD_R3 - UART7_TX - - LCD_B 6 EVENT OUT SPI1_ SPI6_ SPI3_NSS NSS/ NSS/ /I2S3_WS I2S1_WS I2S6_WS STM32H723xE/G MCO1 Port A DS13313 Rev 1 PA8 Pinouts, pin descriptions and alternate functions 73/226 Table 8. STM32H723 pin alternate functions (continued) AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS 74/226 PB0 - TIM1_CH 2N TIM3_CH3 OCTO TIM8_CH SPIM_P1 2N _IO1 - DFSDM1_ CKOUT - UART4_ CTS LCD_R3 OTG_HS_ ULPI_D1 ETH_MII_ RXD2 - - LCD_G 1 EVENT OUT PB1 - TIM1_CH 3N TIM3_CH4 OCTO TIM8_CH SPIM_P1 3N _IO0 - DFSDM1_ DATIN1 - - LCD_R6 OTG_HS_ ULPI_D2 ETH_MII_ RXD3 - - LCD_G 0 EVENT OUT PB2 RTC_ OUT SAI4_D1 SAI1_D1 - DFSDM1 _CKIN1 - SPI3_ SAI1_SD_ SAI4_SD_ MOSI/I2S A A 3_SDO OCTO SPIM_P1_ CLK OCTO SPIM_P1_ DQS ETH_TX_ ER - TIM23_ ETR - EVENT OUT PB3 JTDO/ TRACE SWO TIM2_CH 2 - - - SPI1_ SCK/ I2S1_CK SPI3_SCK /I2S3_CK - CRS_ SYNC UART7_RX - - TIM24_ ETR EVENT OUT PB4 NJT RST TIM16_ BKIN TIM3_CH1 - - SPI1_ MISO/ I2S1_SDI SPI3_ MISO/ I2S3_SDI SPI2_ NSS/ I2S2_WS SDMMC2_ D3 - UART7_TX - - - EVENT OUT PB5 - TIM17_ BKIN TIM3_CH2 LCD_B5 I2C1_ SMBA SPI1_ MOSI/I2S 1_SDO I2C4_ SMBA SPI3_ SPI6_ MOSI/I2S MOSI/I2S6 3_SDO _SDO FDCAN2_ RX OTG_HS_ ULPI_D7 ETH_PPS_ OUT FMC_SDC KE1 DCMI_ D10/PSS I_D10 UART5 _RX EVENT OUT PB6 - TIM16_ CH1N TIM4_CH1 - I2C1_ SCL CEC I2C4_SCL USART1 _TX LPUART1 _TX FDCAN2_ TX OCTO SPIM_P1_ NCS DFSDM1_ DATIN5 FMC_SDN E1 DCMI_ D5/PSSI _D5 UART5 _TX EVENT OUT PB7 - TIM17_ CH1N TIM4_CH2 - I2C1_ SDA - I2C4_SDA USART1 _RX LPUART1 _RX - - DFSDM1_ CKIN5 FMC_NL DCMI_ VSYNC/ PSSI_ RDY - EVENT OUT PB8 - TIM16_C H1 TIM4_CH3 DFSDM1 _CKIN7 I2C1_ SCL - I2C4_SCL SDMMC1 _CKIN UART4_ RX FDCAN1_ RX SDMMC2_ D4 ETH_MII_ TXD3 SDMMC1_ D4 DCMI_ D6/PSSI _D6 LCD_B 6 EVENT OUT PB9 - TIM17_ CH1 TIM4_CH4 DFSDM1 _DATIN7 I2C1_ SDA SPI2_ NSS/I2S 2_WS I2C4_SDA SDMMC1 _CDIR UART4_ TX FDCAN1_ TX SDMMC2_ D5 I2C4_ SMBA SDMMC1_ D5 DCMI_ D7/PSSI _D7 LCD_B 7 EVENT OUT SPI6_SCK SDMMC2_ /I2S6_CK D2 SPI6_ MISO/ I2S6_SDI Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port B AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS - TIM2_CH 3 - LPTIM2_ IN1 I2C2_ SCL SPI2_ SCK/ I2S2_CK DFSDM1_ DATIN7 USART3 _TX - OCTO SPIM_P1_ NCS OTG_HS_ ULPI_D3 ETH_MII_ RX_ER - - LCD_G 4 EVENT OUT PB11 - TIM2_CH 4 - LPTIM2_ ETR I2C2_ SDA - DFSDM1_ CKIN7 USART3 _RX - - OTG_HS_ ULPI_D4 ETH_MII_ TX_EN/ ETH_RMII_ TX_EN - - LCD_G 5 EVENT OUT PB12 - TIM1_BKI N - OCTO SPIM_P1 _NCLK I2C2_SM BA SPI2_ NSS/ I2S2_WS DFSDM1_ DATIN1 USART3 _CK - FDCAN2_ RX OTG_HS_ ULPI_D5 ETH_MII_ TXD0/ ETH_RMII_ TXD0 OCTOSPI M_P1_IO0 TIM1_ BKIN_ COMP12 UART5 _RX EVENT OUT PB13 - TIM1_CH 1N - LPTIM2_ OUT OCTO SPIM_P1 _IO2 SPI2_ SCK/ I2S2_CK DFSDM1_ CKIN1 USART3 _CTS/ USART3 _NSS - FDCAN2_ TX OTG_HS_ ULPI_D6 ETH_MII_ TXD1/ ETH_RMII_ TXD1 SDMMC1_ D0 DCMI_ D2/PSSI _D2 UART5 _TX EVENT OUT PB14 - TIM1_CH 2N TIM12_CH TIM8_CH 1 2N USART1 _TX SPI2_ DFSDM1_ MISO/ DATIN2 I2S2_SDI USART3 _RTS/ USART3 _DE UART4_ RTS/UAR T4_DE SDMMC2_ D0 - - FMC_D10/ FMC_ AD10 - LCD_C LK EVENT OUT PB15 RTC_ REFIN TIM1_CH 3N TIM12_CH TIM8_CH 2 3N USART1 _RX SPI2_ DFSDM1_ MOSI/I2S CKIN2 2_SDO - UART4_ CTS SDMMC2_ D1 - - FMC_D11/ FMC_AD1 1 - LCD_G 7 EVENT OUT Port B DS13313 Rev 1 PB10 Pinouts, pin descriptions and alternate functions 75/226 Table 8. STM32H723 pin alternate functions (continued) STM32H723xE/G AF0 Port SYS AF2 AF3 AF4 AF12 AF13 AF14 AF15 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PC0 - FMC_D12 /FMC_AD 12 - DFSDM1 _CKIN0 - PC1 TRACE D0 SAI4_D1 SAI1_D1 DFSDM1 _DATIN0 DFSDM1 _CKIN4 PC2 PWR_ DEEP SLEEP - - PC3 PWR_ SLEEP - PC4 PWR_ DEEP SLEEP PC5 AF5 AF6 AF7 AF8 AF9 AF10 AF11 DFSDM1_ DATIN4 - SAI4_FS_ B FMC_A25 OTG_HS_ ULPI_STP LCD_G2 FMC_SDN WE - LCD_R 5 EVENT OUT SPI2_ SAI1_SD_ MOSI/I2S A 2_SDO - SAI4_SD_ SDMMC2_ A CK OCTO SPIM_P1_ IO4 ETH_MDC MDIOS_ MDC - LCD_G 5 EVENT OUT DFSDM1 _CKIN1 OCTO SPI2_ DFSDM1_ SPIM_P1 MISO/I2S CKOUT _IO5 2_SDI - - OCTOSPI M_P1_IO2 OTG_HS_ ULPI_DIR ETH_MII_ TXD2 FMC_SDN E0 - - EVENT OUT - DFSDM1 _DATIN1 OCTO SPI2_ SPIM_P1 MOSI/I2S _IO6 2_SDO - - - OCTOSPI M_P1_IO0 OTG_HS_ ULPI_NXT ETH_MII_ TX_CLK FMC_SDC KE0 - - EVENT OUT FMC_A22 - DFSDM1 _CKIN2 - I2S1_ MCK - - - ETH_MII_ SPDIFRX1 SDMMC2_ RXD0/ETH _IN3 CKIN _RMII_RXD 0 FMC_SDN E0 - LCD_R 7 EVENT OUT PWR_ SLEEP SAI4_D3 SAI1_D3 DFSDM1 _DATIN2 PSSI_D1 5 - - - - SPDIFRX1 _IN4 OCTOSPI M_P1_DQ S ETH_MII_R XD1/ETH_ RMII_RXD1 FMC_SDC KE0 COMP1_ OUT LCD_D E EVENT OUT PC6 - - TIM3_CH1 TIM8_CH 1 DFSDM1 _CKIN3 I2S2_ MCK - USART6 _TX SDMMC1_ D0DIR FMC_ NWAIT SDMMC2_ D6 - SDMMC1_ D6 DCMI_ D0/PSSI _D0 LCD_H SYNC EVENT OUT PC7 DB TRGIO - TIM3_CH2 TIM8_CH 2 DFSDM1 _DATIN3 - I2S3_ MCK USART6 _RX SDMMC1_ FMC_NE1 D123DIR SDMMC2_ D7 SWPMI_TX SDMMC1_ D7 DCMI_ D1/PSSI _D1 LCD_G 6 EVENT OUT PC8 TRACE D1 - TIM3_CH3 TIM8_CH 3 - - - USART6 _CK FMC_INT SWPMI_RX SDMMC1_ D0 DCMI_ D2/PSSI _D2 - EVENT OUT - UART5_ RTS/ UART5_ DE FMC_NE2 /FMC_ NCE 76/226 Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port C AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port DS13313 Rev 1 Port C SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PC9 MCO2 - TIM3_CH4 TIM8_CH 4 I2C3_ SDA I2S_ CKIN I2C5_SDA - UART5_C TS OCTO SPIM_P1_ IO0 LCD_G3 SWPMI_ SUSPEND SDMMC1_ D1 DCMI_D 3/PSSI_ D3 LCD_B 2 EVENT OUT PC10 - - - DFSDM1 _CKIN5 I2C5_ SDA - SPI3_SCK /I2S3_CK USART3 _TX UART4_ TX OCTO SPIM_P1_ IO1 LCD_B1 SWPMI_RX SDMMC1_ D2 DCMI_D 8/PSSI_ D8 LCD_R 2 EVENT OUT PC11 - - - DFSDM1 _DATIN5 I2C5_ SCL - SPI3_ MISO/ I2S3_SDI USART3 _RX UART4_ RX OCTO SPIM_P1_ NCS - - SDMMC1_ D3 DCMI_ D4/PSSI _D4 LCD_B 4 EVENT OUT PC12 TRACE D3 - I2C5_ SMBA SPI6_ SCK/ I2S6_CK SPI3_ MOSI/ I2S3_SDO USART3 _CK UART5_ TX - - - SDMMC1_ CK DCMI_ D9/PSSI _D9 LCD_R 6 EVENT OUT PC13 - - - - - - - - - - - - - - - EVENT OUT PC14 - - - - - - - - - - - - - - - EVENT OUT PC15 - - - - - - - - - - - - - - - EVENT OUT FMC_D6/ TIM15_CH FMC_AD6 1 Pinouts, pin descriptions and alternate functions 77/226 Table 8. STM32H723 pin alternate functions (continued) STM32H723xE/G AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PD0 - - - DFSDM1 _CKIN6 - - - - UART4_ RX FDCAN1_ RX - UART9_ CTS FMC_D2/ FMC_AD2 - LCD_B 1 EVENT OUT PD1 - - - DFSDM1 _DATIN6 - - - - UART4_ TX FDCAN1_ TX - - FMC_D3/ FMC_AD3 - - EVENT OUT PD2 TRACE D2 FMC_D7/ FMC_AD7 TIM3_ ETR - TIM15_ BKIN - - - UART5_ RX LCD_B7 - - SDMMC1_ CMD DCMI_ D11/PSSI _D11 LCD_B 2 EVENT OUT PD3 - - - DFSDM1 _CKOUT - SPI2_ SCK/ I2S2_CK - USART2 _CTS/ USART2 _NSS - - - - FMC_CLK DCMI_ D5/PSSI _D5 LCD_G 7 EVENT OUT PD4 - - - - - - - USART2 _RTS/ USART2 _DE - - OCTOSPI M_P1_IO4 - FMC_NOE - - EVENT OUT PD5 - - - - - - - USART2 _TX - - OCTOSPI M_P1_IO5 - FMC_NWE - - EVENT OUT PD6 - SAI4_D1 SAI1_D1 DFSDM1 _CKIN4 DFSDM1 _DATIN1 SPI3_ SAI1_SD_ MOSI/I2S A 3_SDO USART2 _RX SAI4_SD_ A - OCTO SPIM_P1_ IO6 SDMMC2_ CK FMC_ NWAIT DCMI_D 10/PSSI_ D10 LCD_B 2 EVENT OUT PD7 - - - DFSDM1 _DATIN4 - SPI1_ DFSDM1_ MOSI/I2S CKIN1 1_SDO USART2 _CK - SPDIFRX1 _IN1 OCTO SPIM_P1_ IO7 SDMMC2_ CMD FMC_NE1 - - EVENT OUT PD8 - - - DFSDM1 _CKIN3 - USART3 _TX - SPDIFRX1 _IN2 - - FMC_D13/ FMC_ AD13 - - EVENT OUT - - 78/226 Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port D AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port DS13313 Rev 1 Port D SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PD9 - - - DFSDM1 _DATIN3 - - - USART3 _RX - - - - FMC_D14/ FMC_AD1 4 - - EVENT OUT PD10 - - - DFSDM1 _CKOUT - - - USART3 _CK - - - - FMC_D15/ FMC_AD1 5 - LCD_B 3 EVENT OUT PD11 - - - LPTIM2_I I2C4_SM N2 BA - - USART3 _CTS/ USART3 _NSS - OCTOSPI M_P1_IO0 SAI4_SD_ A - FMC_A16/ FMC_CLE - - EVENT OUT PD12 - LPTIM1_ IN1 TIM4_CH1 LPTIM2_ IN1 I2C4_ SCL FDCAN3 _RX - USART3 _RTS/ USART3 _DE - OCTO SPIM_P1_ IO1 SAI4_FS_ A - FMC_A17/ FMC_ALE DCMI_ D12/PSS I_D12 - EVENT OUT PD13 - LPTIM1_ OUT TIM4_CH2 - I2C4_ SDA FDCAN3 _TX - - - OCTO SPIM_P1_ IO3 SAI4_ SCK_A UART9_ RTS/ UART9_DE FMC_A18 DCMI_ D13/ PSSI_ D13 - EVENT OUT PD14 - - TIM4_CH3 - - - - - UART8_ CTS - - UART9_RX FMC_D0/ FMC_AD0 - - EVENT OUT PD15 - - TIM4_CH4 - - - - - UART8_ RTS/ UART8_ DE - - UART9_TX FMC_D1/ FMC_AD1 - - EVENT OUT Pinouts, pin descriptions and alternate functions 79/226 Table 8. STM32H723 pin alternate functions (continued) STM32H723xE/G AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS 80/226 PE0 - LPTIM1_ ETR TIM4_ ETR - LPTIM2_ ETR - - - UART8_ RX - SAI4_ MCLK_A - FMC_NBL 0 DCMI_ D2/PSSI _D2 LCD_R 0 EVENT OUT PE1 - LPTIM1_ IN2 - - - - - - UART8_ TX - - - FMC_NBL 1 DCMI_ D3/ PSSI_D3 LCD_R 6 EVENT OUT PE2 TRACE CLK - SAI1_ CK1 - USART1 0_RX SPI4_ SCK SAI1_ MCLK_A - SAI4_ MCLK_A OCTOSPI M_P1_IO2 SAI4_CK1 ETH_MII_ TXD3 FMC_A23 - - EVENT OUT PE3 TRACE D0 - - - TIM15_ BKIN - SAI1_SD_ B - SAI4_SD_ B - - USART10_ TX FMC_A19 - - EVENT OUT PE4 TRACE D1 - SAI1_D2 DFSDM1 _DATIN3 TIM15_ CH1N SPI4_NS S SAI1_FS_ A - SAI4_FS_ A - SAI4_D2 - FMC_A20 DCMI_ D4/PSSI _D4 LCD_B 0 EVENT OUT PE5 TRACE D2 - SAI1_CK2 DFSDM1 _CKIN3 TIM15_ CH1 SPI4_ MISO SAI1_SCK _A - SAI4_SCK _A - SAI4_CK2 - FMC_A21 DCMI_ D6/PSSI _D6 LCD_G 0 EVENT OUT PE6 TRACE D3 TIM1_ BKIN2 SAI1_D1 - TIM15_ CH2 SPI4_ MOSI SAI1_SD_ A - SAI4_SD_ A SAI4_D1 SAI4_ MCLK_B TIM1_BKIN 2_COMP12 FMC_A22 DCMI_ D7/PSSI _D7 LCD_G 1 EVENT OUT PE7 - TIM1_ET R - DFSDM1 _DATIN2 - - - UART7_ RX - - OCTO SPIM_P1_ IO4 - FMC_D4/ FMC_AD4 - - EVENT OUT PE8 - TIM1_CH 1N - DFSDM1 _CKIN2 - - - UART7_ TX - - OCTO SPIM_P1_ IO5 - FMC_D5/ FMC_AD5 COMP2_ OUT - EVENT OUT PE9 - TIM1_CH 1 - DFSDM1 _CKOUT - - - UART7_ RTS/ UART7_ DE - - OCTO SPIM_P1_ IO6 - FMC_D6/ FMC_AD6 - - EVENT OUT Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port E AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port DS13313 Rev 1 Port E SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PE10 - TIM1_CH 2N - DFSDM1 _DATIN4 - - - UART7_ CTS - - OCTO SPIM_P1_ IO7 - FMC_D7/ FMC_AD7 - - EVENT OUT PE11 - TIM1_CH 2 - DFSDM1 _CKIN4 - SPI4_ NSS - - - - SAI4_SD_ B OCTO SPIM_P1_ NCS FMC_D8/ FMC_AD8 - LCD_G 3 EVENT OUT PE12 - TIM1_CH 3N - DFSDM1 _DATIN5 - SPI4_ SCK - - - - SAI4_SCK _B - FMC_D9/ FMC_AD9 COMP1_ OUT LCD_B 4 EVENT OUT PE13 - TIM1_CH 3 - DFSDM1 _CKIN5 - SPI4_ MISO - - - - SAI4_FS_ B - FMC_D10/ FMC_ AD10 COMP2_ OUT LCD_ DE EVENT OUT PE14 - TIM1_CH 4 - - - SPI4_ MOSI - - - - SAI4_ MCLK_B - FMC_D11/ FMC_ AD11 - LCD_ CLK EVENT OUT PE15 - TIM1_ BKIN - - - - - - - - - USART10_ CK FMC_D12/ FMC_ AD12 TIM1_ BKIN_ COMP12 LCD_ R7 EVENT OUT Pinouts, pin descriptions and alternate functions 81/226 Table 8. STM32H723 pin alternate functions (continued) STM32H723xE/G AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS 82/226 PF0 - - - - I2C2_ SDA - I2C5_SDA - - OCTO SPIM_P2_ IO0 - - FMC_A0 TIM23_ CH1 - EVENT OUT PF1 - - - - I2C2_ SCL - I2C5_SCL - - OCTO SPIM_P2_ IO1 - - FMC_A1 TIM23_ CH2 - EVENT OUT PF2 - - - - I2C2_ SMBA - I2C5_ SMBA - - OCTO SPIM_P2_ IO2 - - FMC_A2 TIM23_ CH3 - EVENT OUT PF3 - - - - - - - - - OCTO SPIM_P2_ IO3 - - FMC_A3 TIM23_ CH4 - EVENT OUT PF4 - - - - - - - - - OCTO SPIM_P2_ CLK - - FMC_A4 - - EVENT OUT PF5 - - - - - - - - - OCTO SPIM_P2_ NCLK - - FMC_A5 - - EVENT OUT PF6 - TIM16_ CH1 FDCAN3_ RX - - SPI5_ NSS SAI1_SD_ B UART7_ RX SAI4_SD_ B - OCTO SPIM_P1_ IO3 - - TIM23_ CH1 - EVENT OUT PF7 - TIM17_ CH1 FDCAN3_ TX - - SPI5_ SCK SAI1_ MCLK_B UART7_ TX SAI4_ MCLK_B - OCTO SPIM_P1_ IO2 - - TIM23_ CH2 - EVENT OUT PF8 - TIM16_ CH1N - - - SPI5_ MISO SAI1_SCK _B UART7_ RTS/ UART7_ DE SAI4_SCK TIM13_CH _B 1 OCTO SPIM_P1_ IO0 - - TIM23_ CH3 - EVENT OUT PF9 - TIM17_ CH1N - - - SPI5_ MOSI SAI1_FS_ B UART7_ CTS SAI4_FS_ B OCTO SPIM_P1_ IO1 - - TIM23_ CH4 - EVENT OUT TIM14_CH 1 Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port F AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port DS13313 Rev 1 Port F SYS AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS PF10 - TIM16_BK IN SAI1_D3 - PSSI_ D15 - - - - OCTO SPIM_P1_ CLK SAI4_D3 - - DCMI_ D11/PSSI _D11 LCD_D E EVENT OUT PF11 - - - - - SPI5_ MOSI - - - OCTO SPIM_P1_ NCLK SAI4_SD_ B - FMC_ NRAS DCMI_ D12/PSS I_D12 TIM24_ CH1 EVENT OUT PF12 - - - - - - - - - OCTO SPIM_P2_ DQS - - FMC_A6 - TIM24_ CH2 EVENT OUT PF13 - - - DFSDM1 _DATIN6 I2C4_ SMBA - - - - - - - FMC_A7 - TIM24_ CH3 EVENT OUT PF14 - - - DFSDM1 _CKIN6 I2C4_ SCL - - - - - - - FMC_A8 - TIM24_ CH4 EVENT OUT PF15 - - - - I2C4_ SDA - - - - - - - FMC_A9 - - EVENT OUT Pinouts, pin descriptions and alternate functions 83/226 Table 8. STM32H723 pin alternate functions (continued) STM32H723xE/G AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS 84/226 PG0 - - - - - - - - - OCTO SPIM_P2_ IO4 - UART9_RX FMC_A10 - - EVENT OUT PG1 - - - - - - - - - OCTO SPIM_P2_ IO5 - UART9_TX FMC_A11 - - EVENT OUT PG2 - - - TIM8_ BKIN - - - - - - - TIM8_BKIN _COMP12 FMC_A12 - TIM24_ ETR EVENT OUT PG3 - - - TIM8_ BKIN2 - - - - - - - TIM8_ BKIN2_ COMP12 FMC_A13 TIM23_ ETR - EVENT OUT PG4 - TIM1_BKI N2 - - - - - - - - - TIM1_ BKIN2_ COMP12 FMC_A14/ FMC_BA0 - - EVENT OUT PG5 - TIM1_ ETR - - - - - - - - - - FMC_A15/ FMC_BA1 - - EVENT OUT PG6 - TIM17_ BKIN - - - - - - - - OCTO SPIM_P1_ NCS - FMC_NE3 DCMI_D 12/PSSI_ D12 LCD_R 7 EVENT OUT PG7 - - - - - - SAI1_ MCLK_A USART6 _CK - OCTO SPIM_P2_ DQS - - FMC_INT DCMI_D 13/PSSI_ D13 LCD_ CLK EVENT OUT PG8 - - - TIM8_ ETR - SPI6_ NSS/I2S 6_WS - USART6 _RTS/ USART6 _DE SPDIFRX1 _IN3 - - ETH_PPS_ OUT FMC_ SDCLK - LCD_G 7 EVENT OUT PG9 - - FDCAN3_ TX - - SPI1_ MISO/I2S 1_SDI - USART6 _RX OCTO SPDIFRX1 SPIM_P1_ _IN4 IO6 SAI4_FS_ B SDMMC2_ D0 FMC_NE2/ FMC_NCE DCMI_ VSYNC/ PSSI_ RDY - EVENT OUT Pinouts, pin descriptions and alternate functions DS13313 Rev 1 Port G AF1 STM32H723xE/G Table 8. STM32H723 pin alternate functions (continued) AF0 Port SYS AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 CEC/ DCMI/ CRS/ DFSDM1/ FDCAN1/2 DFSDM1 PSSI/ DFSDM1/I SDMMC1 FMC/ ETH/I2C4/ CEC/ LPUART1/ /FMC/ /LCD/ DFSDM1 2C4/5/ /SPI2/I2S LCD/ LCD/MDIO FMC/ FDCAN3/ FDCAN3/ SAI4/ LCD/ LPTIM2/ /I2C1/2/3/ OCTO 2/SPI3/ OCTO S/OCTOSP LPTIM1/ PDM_ SPI1/I2S SDMMC1/ OCTO 3/4/5/ 4/5/ SPIM_P1/ I2S3/ SPIM_P1/ IM_P1/ SAI4/TIM1 SAI1/ 1/SPI2/ SPDIFRX1 SPIM_P1/ LPUART LPTIM2/ SAI1/ SPI6/ OTG1_FS/ SDMMC2/ 6/17/TIM1 TIM3/4/5/1 I2S2/SPI /SPI6/ 2/SAI4/ 1/OCTO OCTO SPI3/ UART7/ OTG1_HS/ SWPMI1/ x/TIM2x 2/15 3/I2S3/ UART4/5/ SDMMC2/ SPIM_P1 SPIM_P1 I2S3/ USART1/ SAI4/ TIM1x/TIM SPI4/5/6 8 SPDIFRX1 /2/TIM8 /TIM15/ UART4 2/3/6 SDMMC2/ 8/UART7/9/ /TIM13/14 USART1/ TIM8 USART10 10 AF12 AF13 AF14 AF15 FMC/LCD/ MDIOS/ OCTOSPI M_P1/ SDMMC1/ TIM1x/ TIM8 COMP/ DCMI/ PSSI/ LCD/ TIM1x/ TIM23 LCD/ TIM24/ UART5 SYS SDMMC2_ D1 FMC_NE3 DCMI_ D2/PSSI _D2 LCD_B 2 EVENT OUT OCTO SPDIFRX1 SPIM_P2_ _IN1 IO7 SDMMC2_ D2 ETH_MII_ TX_EN/ ETH_RMII_ TX_EN - DCMI_ D3/PSSI _D3 LCD_B 3 EVENT OUT USART6 _RTS/ USART6 _DE SPDIFRX1 _IN2 LCD_B4 SDMMC2_ D3 ETH_MII_ TXD1/ETH _RMII_TXD 1 FMC_NE4 TIM23_ CH1 LCD_B 1 EVENT OUT - USART6 _CTS/ USART6 _NSS - - SDMMC2_ D6 ETH_MII_ TXD0/ETH _RMII_TXD 0 FMC_A24 TIM23_ CH2 LCD_R 0 EVENT OUT SPI6_ MOSI/I2S 6_SDO - USART6 _TX - OCTO SPIM_P1_ IO7 SDMMC2_ D7 ETH_MII_ TXD1/ETH _RMII_TXD 1 FMC_A25 TIM23_ CH3 LCD_B 0 EVENT OUT - - - USART6 _CTS/ USART6 _NSS - OCTO SPIM_P2_ DQS - USART10_ CK FMC_NCA S DCMI_D 13/PSSI_ D13 - EVENT OUT - - - - - - - - - - - - EVENT OUT - - - - - - - - - - - - EVENT OUT - - FDCAN3_ RX OCTO SPIM_P2 _IO6 - SPI1_ NSS/I2S 1_WS - - PG11 - LPTIM1_ IN2 - - USART1 0_RX SPI1_ SCK/I2S 1_CK - - PG12 - LPTIM1_ IN1 - OCTO SPIM_P2 _NCS USART1 0_TX SPI6_ MISO/I2S 6_SDI - PG13 TRACE D0 LPTIM1_ OUT - - USART1 0_CTS/ USART1 0_NSS SPI6_ SCK/I2S 6_CK PG14 TRACE D1 LPTIM1_ ETR - - USART1 0_RTS/ USART1 0_DE PG15 - - - - PH0 - - - PH1 - - - - LCD_G3 STM32H723xE/G SAI4_SD_ B PG10 Port G DS13313 Rev 1 Port H AF1 Pinouts, pin descriptions and alternate functions 85/226 Table 8. STM32H723 pin alternate functions (continued) Electrical characteristics 6 6.1 STM32H723xE/G Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Figure 8. Pin loading conditions Figure 9. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 86/226 DS13313 Rev 1 MS19010V2 STM32H723xE/G Power supply scheme Figure 10. Power supply scheme VCAP IOs D3 domain (System logic, EXTI, IO logic Peripherals, RAM) Power switch VSS Power switch Core domain (VCORE) LDO voltage regulator VDDLDO Level shifter 6.1.6 Electrical characteristics D2 domain (peripherals, RAM) D1 domain (CPU, peripherals, RAM) Flash VSS VDD domain VDD VBAT charging HSI, CSI, HSI48, HSE, PLLs Backup domain Backup VBKP regulator VSW VBAT Power switch Power switch LSI, LSE, RTC, Wakeup logic, backup IO logic registers, Reset BKUP IOs VSS Backup RAM VSS VDD33USB USB FS IOs VDDA Analog domain REF_BUF VREF+ ADC, DAC VREF+ VREF- VREF- OPAMP, Comparator VSSA 1. Refer to application note AN5419 "Getting started with STM32H723/733, STM32H725/735 and STM32H730 Value Line hardware development" for the possible power scheme and connected capacitors. DS13313 Rev 1 87/226 206 Electrical characteristics 6.1.7 STM32H723xE/G Current consumption measurement Figure 11. Current consumption measurement scheme LDO ON IDD_VBAT VBAT IDD VDD VDDLDO VDDA 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics, Table 10: Current characteristics, and Table 11: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 9. Voltage characteristics Symbols Ratings Min Max Unit VDDX - VSS(1) External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT) -0.3 4.0 V Input voltage on FT_xxx pins VSS-0.3 Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4) V Input voltage on TT_xx pins VSS-0.3 4.0 V Input voltage on BOOT0 pin VSS 9.0 V VSS-0.3 4.0 V Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins - 50 mV VIN(2) Input voltage on any other pins |VDDX| |VSSx-VSS| 1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 88/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics 4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled. Table 10. Current characteristics Symbols Ratings Max IVDD (1) Total current into sum of all VDD power lines (source) 620 IVSS Total current out of sum of all VSS ground lines (sink)(1) 620 IVDD IVSS IIO I(PIN) IINJ(PIN) (3)(4) IINJ(PIN) Maximum current into each VDD power pin (source)(1) 100 (1) 100 Maximum current out of each VSS ground pin (sink) Output current sunk by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(2) 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 -5/+0 Injected current on PA4, PA5 -0/0 Total injected current (sum of all I/Os and control pins)(5) Unit mA 25 1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 9: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 11. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Industrial temperature range 6 DS13313 Rev 1 Value Unit - 65 to +150 C 125 89/226 206 Electrical characteristics STM32H723xE/G 6.3 Operating conditions 6.3.1 General operating conditions Table 12. General operating conditions Symbol Parameter VDD Standard operating voltage VDDLDO Supply voltage for the internal regulator VDD33USB Standard operating voltage, USB domain VDDA Analog operating voltage Operating conditions Min Typ Max - 1.62(1) - 3.6 VDDLDO VDD 1.62(1) - 3.6 3.0 - 3.6 0 - 3.6 ADC or COMP used 1.62 - DAC used 1.8 - OPAMP used 2.0 - VREFBUF used 1.8 - 0 - -0.3 - VDD+0.3 0 - 9 USB used USB not used ADC, DAC, OPAMP, COMP, VREFBUF not used TT_xx I/O BOOT0 VIN Internal regulator ON (LDO)(3) VCORE Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins 90/226 3.6 V All I/O except BOOT0 and TT_xx -0.3 - Min(VDD, VDDA, VDD33USB) +3.6V < 5.5V(2) VOS3 0.95 1.0 1.05 VOS2 1.05 1.10 1.15 VOS1 1.15 1.21 1.26 VOS0 1.30 1.36 1.40 VOS3 0.98 1.03 1.08 VOS2 1.08 1.13 1.18 VOS1 1.18 1.23 1.28 VOS0 1.33 1.38 1.40 I/O Input voltage DS13313 Rev 1 Unit V STM32H723xE/G Electrical characteristics Table 12. General operating conditions (continued) Symbol fCPU fACLK fHCLK fPCLK Operating conditions Parameter Arm(R) Cortex(R)-M7 clock frequency AXI clock frequency AHB clock frequency APB clock frequency Ambient temperature for temperature range 3 TA(5) Ambient temperature for temperature range 6 Min Typ Max VOS3 - - 170 VOS2 - - 300 VOS1 - - 400 VOS0 - - 520 VOS0 and CPU_FREQ_BOOST - - 550 VOS3 - - 85 VOS2 - - 150 VOS1 - - 200 VOS0 - - 275 VOS3 - - 85 VOS2 - - 150 VOS1 - - 200 VOS0 - - 275 VOS3 - - 42.5(4) VOS2 - - 75 VOS1 - - 100 VOS0 - - 137.5 Maximum power dissipation -40 125 Maximum power dissipation -40 85 Low-power dissipation(6) -40 105 Unit MHz C 1. When RESET is released, the functionality is guaranteed down to VPDRmax or down to the specified VDDmin when the PDR is OFF. The PDR can only be switched OFF though the PDR_ON pin that not available in all packages. 2. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table. 3. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO). 4. This value corresponds to the maximum APB clock frequency when at least one peripheral is enabled. 5. The device junction temperature must be kept below maximum TJ indicated in Table 13: Supply voltage and maximum temperature configuration and the maximum temperature. 6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). Table 13. Supply voltage and maximum temperature configuration Power scale VOS0 VCORE source LDO External (Bypass) Max. TJ (C) 105 DS13313 Rev 1 Min. VDD(V) Min. VDDLDO (V) 1.7 1.7 1.62 - 91/226 206 Electrical characteristics STM32H723xE/G Table 13. Supply voltage and maximum temperature configuration (continued) Power scale VOS1 VOS2 or VOS3 SVOS4/SVOS5 VCORE source Max. TJ (C) LDO Min. VDDLDO (V) 1.62 1.62 - - 1.62 1.62 - - 125 2 2 105 1.62 1.62 125 1.62 - 125 External (Bypass) LDO 125 External (bypass) LDO External (Bypass) 6.3.2 Min. VDD(V) VCAP external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 14. Two external capacitors can be connected to VCAP pins. Figure 12. External capacitor CEXT C ESR R Leak MS19044V2 1. Legend: ESR is the equivalent series resistance. Table 14. VCAP operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F(2)(3) ESR ESR of external capacitor < 100 m 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated. 3. 92/226 If a third VCAP pin is available on the package, it must be connected to the other VCAP pins but no additional capacitor is required. DS13313 Rev 1 STM32H723xE/G 6.3.3 Electrical characteristics Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 15. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD tVDDA tVDDUSB Parameter Min Max VDD rise time rate 0 VDD fall time rate 10 VDDA rise time rate 0 VDDA fall time rate 10 VDDUSB rise time rate 0 VDDUSB fall time rate 10 DS13313 Rev 1 Unit s/V 93/226 206 Electrical characteristics 6.3.4 STM32H723xE/G Embedded reset and power control block characteristics The parameters given in Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 16. Reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tRSTTEMPO(1) Reset temporization after BOR0 released - - 377 550 s VPOR/PDR Power-on/power-down reset threshold Rising edge(1) 1.62 1.67 1.71 Falling edge 1.58 1.62 1.68 VBOR1 Brown-out reset threshold 1 2.04 2.10 2.15 1.95 2.00 2.06 VBOR2 Brown-out reset threshold 2 2.34 2.41 2.47 2.25 2.31 2.37 VBOR3 Brown-out reset threshold 3 2.63 2.70 2.78 2.54 2.61 2.68 VPVD0 Programmable Voltage Detector threshold 0 Rising edge 1.90 1.96 2.01 1.81 1.86 1.91 VPVD1 Programmable Voltage Detector threshold 1 Rising edge 2.05 2.10 2.16 1.96 2.01 2.06 VPVD2 Programmable Voltage Detector threshold 2 Rising edge 2.19 2.26 2.32 2.10 2.15 2.21 VPVD3 Programmable Voltage Detector threshold 3 Rising edge 2.35 2.41 2.47 2.25 2.31 2.37 VPVD4 Programmable Voltage Detector threshold 4 Rising edge 2.49 2.56 2.62 2.39 2.45 2.51 VPVD5 Programmable Voltage Detector threshold 5 Rising edge 2.64 2.71 2.78 2.55 2.61 2.68 VPVD6 Programmable Voltage Detector threshold 6 Rising edge 2.78 2.86 2.94 2.69 2.76 2.83 VPOR/PDR Hysteresis voltage for Power-on/power-down reset Hysteresis in Run mode - 43.00 - Vhyst_BOR_PVD Hysteresis voltage for BOR Hysteresis in Run mode - 100 - IDD_BOR_PVD(1) BOR and PVD consumption from VDD - - - 0.630 IDD_POR_PVD POR and PVD consumption from VDD - 0.8 - 1.200 94/226 Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge in Run mode V mV A DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 16. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.49 VAVM_3 Analog voltage detector for VDDA threshold 3 Rising edge 2.74 2.83 2.91 2.64 2.72 2.80 Vhyst_VDDA Hysteresis of VDDA voltage detector - - 100 - mV IDD_PVM PVM consumption from VDD(1) - - - 0.25 A IDD_VDDA Voltage detector consumption on VDDA(1) - - 2.5 A Falling edge Falling edge Falling edge Falling edge Resistor bridge Unit V 1. Guaranteed by design. 6.3.5 Embedded reference voltage characteristics The parameters given in Table 17 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 17. Embedded reference voltage Symbol VREFINT tS_vrefint(1)(2) (3) tS_vbat(2) tstart_vrefint(2) Irefbuf(2) VREFINT(2) Tcoeff(2) VDDcoeff(2) Parameter Conditions Min Typ Max Unit -40C < TJ < TJmax 1.180 1.216 1.255 V ADC sampling time when reading the internal reference voltage - 4.3 - - VBAT sampling time when reading the internal VBAT reference voltage - 9 - - Start time of reference voltage buffer when ADC is enable - - - 4.4 VDD = 3.3 V 9 13.5 23 A -40C < TJ < TJmax - 5 15 mV Average temperature coefficient - 20 70 ppm/C 3.0 V < VDD < 3.6 V - 10 1370 ppm/V Internal reference voltages Reference Buffer consumption for ADC Internal reference voltage spread over the temperature range Average temperature coefficient Average Voltage coefficient DS13313 Rev 1 s 95/226 206 Electrical characteristics STM32H723xE/G Table 17. Embedded reference voltage (continued) Symbol Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. Parameter Unit % VREFINT The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 18. Internal reference voltage calibration values Symbol Parameter Raw data acquired at temperature of 30 C, VDDA = 3.3 V VREFIN_CAL 6.3.6 Memory address 1FF1 E860 - 1FF1 E861 Embedded USB regulator characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 19. USB regulator characteristics Symbol Parameter Conditions Min Typ Max Unit VREGOUTV33V Regulated output voltage - 3 - 3.6 V IOUT Output current load sinked by USB block - - - 20 mA TWKUP Wakeup time - - 120 170 us 6.3.7 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a CoreMark code. 96/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in analog input mode. * All peripherals are disabled except when explicitly mentioned. * The Flash memory access time is adjusted with the minimum wait states number, depending on the fACLK frequency (refer to the table "Number of wait states according to CPU clock (frcc_c_ck) frequency and VCORE range" available in the reference manual). * When the peripherals are enabled, the AHB clock frequency is the CPU frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2. The parameters given in the below tables are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 12: General operating conditions. DS13313 Rev 1 97/226 206 Electrical characteristics STM32H723xE/G Table 20. Typical and maximum current consumption in Run mode, code with data processing running from ITCM(1) Max(2) Symbol Parameter Conditions VOS0(3) VOS0 VOS1 All peripherals disabled VOS2 IDD Supply current in Run mode VOS3 VOS0 (3) VOS0 All peripherals enabled VOS1 VOS2 VOS3 frcc_c_ck (MHz) Typ 550 TJ = 25 C TJ = 85 C TJ = 105 C TJ = 125 C 145 170 260 330 - 520 135 160 260 320 - 520 135 160 260 320 - 480 125 150 250 310 - 450 115 150 240 300 - 400 105 130 230 290 - 400 90.5 110 170 220 280 300 69.5 84 150 200 260 300 63 74 130 170 220 280 58 69 120 160 210 216 45.5 56 110 150 200 200 42 53 110 140 200 170 32.5 40 80 110 160 168 32 40 79 110 160 144 28 36 75 110 150 60 13.5 21 61 90 140 25 6.9 14 54 83 130 550 215 250 360 430 - 520 205 240 350 420 - 520 205 240 350 420 - 400 160 190 300 370 - 400 135 160 230 290 360 300 105 130 200 250 330 300 95 110 170 210 280 280 88 100 160 210 270 170 49 58 110 140 190 1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case. 2. Guaranteed by characterization results, unless otherwise specified. 3. CPU_FREQ_BOOST is enabled. 98/226 DS13313 Rev 1 Unit mA STM32H723xE/G Electrical characteristics Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON(1) Max(2) Symbol Parameter Conditions VOS0(3) VOS0 VOS1 All peripherals disabled IDD Supply current in Run mode VOS2 VOS3 VOS0 (3) VOS0 All peripherals enabled VOS1 VOS2 VOS3 frcc_c_ck (MHz) Typ 550 TJ = 25 C TJ = 85 C TJ = 105 C TJ = 125 C 145 170 270 330 - 520 140 170 260 320 - 520 140 170 260 320 - 400 110 140 230 290 - 400 92 110 180 220 290 300 71 86 150 200 260 300 64 75 130 170 220 280 59 70 120 160 210 216 46.5 - - - - 200 42.5 53 110 140 200 180 36 43 83 120 160 170 33.5 41 81 110 160 168 33 - - - - 144 29 - - - - 60 14 - - - - 25 6.85 - - - - 550 220 250 360 430 - 520 210 240 350 420 - 520 210 240 350 420 - 400 160 190 300 370 - 400 140 160 240 290 360 300 105 130 200 250 330 300 96 110 170 210 280 280 89 110 160 210 270 170 50 59 110 140 190 Unit mA 1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case. 2. Guaranteed by characterization results, unless otherwise specified. 3. CPU_FREQ_BOOST is enabled. DS13313 Rev 1 99/226 206 Electrical characteristics STM32H723xE/G Table 22. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF(1) Symbol Parameter Conditions VOS0(2) VOS0 All peripherals disabled VOS1 VOS2 IDD VOS3 Supply current in Run mode VOS0(2) VOS0 All peripherals enabled VOS1 VOS2 VOS3 frcc_c_ck (MHz) Typ 550 99 520 95 520 95 400 76.5 400 66.5 300 51.5 300 47.5 280 43.5 170 24.5 550 170 520 165 520 165 400 130 400 115 300 87 300 79 280 73.5 170 41 Unit mA 1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case. 2. CPU_FREQ_BOOST is enabled. 100/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 23. Typical consumption in Run mode and corresponding performance versus code position Conditions Symbol Coremark Typ ITCM 550 2777 145 52.2 FLASH 550 2777 145 52.2 AXI SRAM 550 2777 145 52.2 SRAM 1 550 2777 150 54.0 SRAM 4 550 2777 145 FLASH 550 923 99 107.3 AXI SRAM 550 1271 105 82.6 SRAM 1 550 790 96.5 122.2 SRAM 4 550 723 89.5 123.8 Peripheral All peripherals disabled, cache ON Supply current in Run mode IDD All peripherals disabled cache OFF IDD/ Coremark frcc_c_c k (MHz) Parameter Code Unit Unit A/ Coremark 52.2 mA Table 24. Typical current consumption in Autonomous mode Symbol Parameter IDD Supply current in Autonous mode Conditions(1) frcc_c_c k (MHz) Typ Run, DStop VOS3 64 3.6 Run, DStandby VOS3 64 2.6 Unit mA 1. System in Run mode, CPU domain in DStop. Table 25. Typical current consumption in Sleep mode Max(1) Symbol Parameter Conditions VOS0 (2) VOS0 IDD(Sleep) Supply current in Sleep mode All peripherals disabled VOS1 VOS2 VOS3 frcc_c_ck (MHz) Typ 550 TJ = 25 C TJ = 85 C 36 - - - - 520 33.5 60 170 240 - 520 33.5 60 170 240 - 400 27 52 160 230 - 400 22.5 39 110 170 240 300 18.5 34 110 160 240 300 16.5 28 85 130 190 170 9.7 21 78 120 190 170 8.5 17 61 96 150 TJ = TJ = 105 C 125 C Unit mA 1. Guaranteed by characterization results. 2. CPU_FREQ_BOOST is enabled. DS13313 Rev 1 101/226 206 Electrical characteristics STM32H723xE/G Table 26. Typical current consumption in Stop mode Max(1) Symbol IDD(Stop) Parameter Conditions Typ Flash memory in low power mode Supply current in Stop and DStop modes Flash memory in normal mode TJ = 25 C TJ = 85 C TJ = TJ = 105 C 125 C SVOS5 0.52 3.7 26 44 72 SVOS4 0.81 6.1 39 64 110 SVOS3 1.15 8.6 51 82 130 SVOS5 0.535 3.7 26 44 72 SVOS4 0.96 6.2 39 64 110 SVOS3 1.45 8.8 51 83 130 Unit mA 1. Guaranteed by characterization results. Table 27. Typical current consumption in Standby mode(1) Typ(2) Conditions Symbol IDD (Standby) Parameter Supply current in Standby mode, IWDG OFF Max at 3.6 V(3) Backup SRAM RTC and LSE(4) 1.65 V 2.4 V 3 V 3.3 V TJ = 25 C TJ = 85 C TJ = 105 C TJ = 125 C OFF OFF TBD TBD TBD TBD TBD TBD TBD TBD ON OFF 3.5 3.7 4 4.3 7.7 39 75 140 OFF ON TBD TBD TBD TBD - - - - ON ON TBD TBD TBD TBD - - - - Unit A 1. TBD stands for "to be defined". 2. PDR is OFF for VDD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by additional 1.2 A. 3. Guaranteed by characterization results. 4. The LSE is in Low-drive mode. Table 28. Typical and maximum current consumption in VBAT mode(1) Conditions Symbol IDD (VBAT) Parameter Supply current in VBAT mode TJ = TJ = TJ = 2 TJ = 105 125 5 C 85 C C C Back-up SRAM RTC and LSE(3) 1.2 V 2V 3V 3.3 V OFF OFF TBD TBD TBD TBD TBD TBD TBD TBD ON OFF 1.45 1.6 1.75 1.85 4 28 53 91 OFF ON TBD TBD TBD TBD - - - - ON ON - - - - - - - - 1. TBD stands for "to be defined". 2. Guaranteed by characterization results. 3. The LSE is in Low-drive mode. 102/226 Max at 3.6 V(2) Typ DS13313 Rev 1 STM32H723xE/G Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 49: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption, the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDx x f SW x C L where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DS13313 Rev 1 103/226 206 Electrical characteristics 6.3.8 STM32H723xE/G Wakeup time from low-power modes The wakeup times given in Table 29 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 29. Low-power mode wakeup timings Max(1) Symbol Parameter Conditions Typ(1) tWUSLEEP(3) Wakeup from Sleep - 14.00 15.00 SVOS3, HSI, Flash memory in Normal mode 4.6 6.2 SVOS3, HSI, Flash memory in low-power mode 12.4 17.4 SVOS4, HSI, Flash memory in Normal mode 15.5 21.1 SVOS4, HSI, Flash memory in low-power mode 23.3 31.8 SVOS5, HSI, Flash memory in Normal mode 39.1 52.6 SVOS5, HSI, Flash memory in low-power mode 39.1 52.7 SVOS3, CSI, Flash memory in Normal mode 30.0 41.6 SVOS3, CSI, Flash memory in low power mode 40.6 55.0 SVOS4, CSI, Flash memory in Normal mode 41.0 55.4 SVOS4, CSI, Flash memory in low-power mode 51.5 68.8 SVOS5, CSI, Flash memory in Normal mode 67.3 89.5 SVOS5, CSI, Flash memory in low-power mode 67.2 89.5 - 400.0 504.3 tWUSTOP(3) tWUSTDBY(3) Wakeup from Stop mode Wakeup from Standby mode (2) 1. Guaranteed by characterization results. 2. The maximum values have been measured at -40 C, in worst conditions. 3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first 104/226 DS13313 Rev 1 Unit CPU clock cycles s STM32H723xE/G 6.3.9 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 49: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 13. Table 30. High-speed external user clock characteristics(1) Symbol Parameter Min Typ Max Unit fHSE_ext User external clock source frequency 4 25 50 MHz 0.7VDD - VDD VSS - 0.3VSS 7 - - VSW OSC_IN amplitude (VHSEH - VHSEL) VDC OSC_IN input voltage tW(HSE) OSC_IN high or low time V ns 1. Guaranteed by design. Figure 13. High-speed external clock source AC timing diagram VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32 ai17528b DS13313 Rev 1 105/226 206 Electrical characteristics STM32H723xE/G Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 49: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 14. Table 31. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDD - VDD VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDD OSC32_IN high or low time - 250 - - tw(LSEH) tw(LSEL) V ns 1. Guaranteed by design. Figure 14. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32 ai17529b 106/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 32. 4-50 MHz HSE oscillator characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - 4 - 50 MHz RF Feedback resistor - - 200 - k During startup(3) - - 4 VDD=3 V, Rm=30 CL=10 pF at 4 MHz - 0.35 - VDD=3 V, Rm=30 CL=10 pF at 8 MHz - 0.40 - VDD=3 V, Rm=30 CL=10 pF at 16 MHz - 0.45 - VDD=3 V, Rm=30 CL=10 pF at 32 MHz - 0.65 - VDD=3 V, Rm=30 CL=10 pF at 48 MHz - 0.95 - IDD(HSE) HSE current consumption mA Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V tSU(4) Start-up time VDD is stabilized - 2 - ms 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DS13313 Rev 1 107/226 206 Electrical characteristics STM32H723xE/G Figure 15. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF Bias controlled gain OSC_OU T STM32 ai17530b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 33. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 33. Low-speed external user clock characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - - 32.768 - kHz LSEDRV[1:0] = 00, Low drive capability - 290 - LSEDRV[1:0] = 01, Medium Low drive capability - 390 - LSEDRV[1:0] = 10, Medium high drive capability - 550 - LSEDRV[1:0] = 11, High drive capability - 900 - LSEDRV[1:0] = 00, Low drive capability - - 0.5 LSEDRV[1:0] = 01, Medium Low drive capability - - 0.75 LSEDRV[1:0] = 10, Medium high drive capability - - 1.7 LSEDRV[1:0] = 11, High drive capability - - 2.7 VDD is stabilized - 2 - IDD Gmcritmax tSU(3) LSE current consumption Maximum critical crystal gm Startup time nA A/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 108/226 DS13313 Rev 1 STM32H723xE/G Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 16. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fHSE OSC32_IN 32.768 kHz resonator RF Bias controlled gain OSC32_OUT STM32 CL2 ai17531c 1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.10 Internal clock source characteristics The parameters given in Table 34 to Table 36 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. 48 MHz high-speed internal RC oscillator (HSI48) Table 34. HSI48 oscillator characteristics Symbol fHSI48 TRIM(2) Parameter Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 47.5(1) 48 48.5(1) MHz - - 0.175 0.250 % 32 steps 4.70 5.6 - % - 45 - 55 % TJ=-40 to 125 C -4.5 - 3.5 % VDD=3 to 3.6 V - 0.025 0.05 VDD=1.62 V to 3.6 V - 0.05 0.1 HSI48 frequency USER trimming step USER TRIM COVERAGE(3) USER TRIMMING coverage DuCy(HSI48)(2) Duty Cycle ACCHSI48_REL(3)(4) Accuracy of the HSI48 oscillator over temperature (factory calibrated) VDD(HSI48)(2)(4) HSI48 oscillator frequency drift with VDD(5) (the reference is 3.3 V) % tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 s IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 A NT jitter(2) Next transition jitter Accumulated jitter on 28 cycles(6) - - 0.15 - ns PT jitter(2) Paired transition jitter Accumulated jitter on 56 cycles(6) - - 0.25 - ns 1. Guaranteed by test in production. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. fHSI = ACCHSI48_REL + VDD. DS13313 Rev 1 109/226 206 Electrical characteristics STM32H723xE/G 5. These values are obtained by using the formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or (Freq(3.6 V) - Freq(1.62 V)) / Freq(1.62 V). 6. Jitter measurements are performed without clock source activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 35. HSI oscillator characteristics(1) Symbol fHSI TRIM Parameter HSI frequency HSI user trimming step DuCy(HSI) Duty cycle VDD (HSI) HSI oscillator frequency drift over VDD (the reference is 3.3 V) TEMP(HSI) HSI oscillator frequency drift over temperature (the reference is 64 MHz) tsu(HSI) HSI oscillator start-up time tstab(HSI) HSI oscillator stabilization time IDD(HSI) HSI oscillator power consumption Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 63.7(2) 64 64.3(2) MHz Trimming is not a multiple of 32 - 0.24 0.32 Trimming is 128, 256 and 384 -5.2 -1.8 - Trimming is 64, 192, 320 and 448 -1.4 -0.8 - Other trimming are a multiple of 32 (not including multiple of 64 and 128) -0.6 -0.25 - - 45 - 55 % VDD=1.62 to 3.6 V -0.12 - 0.03 % TJ=-20 to 105 C -1(3) - 1(3) TJ=-40 to TJmax C -2(3) - 1(3) - - 1.4 2 at 1% of target frequency - 4 8 at 5% of target frequency - - 4 - - 300 400 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. 110/226 DS13313 Rev 1 % % s A STM32H723xE/G Electrical characteristics 4 MHz low-power internal RC oscillator (CSI) Table 36. CSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 3.96(2) 4 4.04(2) MHz Trimming is not a multiple of 16 - 0.40 0.75 Trimming is a multiple of 32 -4.75 -2.75 0.75 Other trimming values not multiple of 16 (excluding multiple of 32) -0.43 0.00 0.75 - 45 - 55 TJ = 0 to 85 C -3.7(3) - 4.5(3) TJ = -40 to 125 C -11(3) - 7.5(3) VDD = 1.62 to 3.6 V -0.06 - 0.06 % CSI oscillator startup time - - 1 2 s tstab(CSI) CSI oscillator stabilization time (to reach 3% of fCSI) - - - 4 cycle IDD(CSI) CSI oscillator power consumption - - 23 30 A Min Typ Max Unit VDD = 3.3 V, TJ = 25 C 31.4(1) 32 32.6(1) TJ = -40 to 110 C, VDD = 1.62 to 3.6 V 29.76(2) - 33.6(2) TJ = -40 to 125 C, VDD = 1.62 to 3.6 V 29.4(2) - 33.6(2) fCSI CSI frequency TRIM CSI trimming step DuCy(CSI) Duty cycle TEMP (CSI) CSI oscillator frequency drift over temperature VDD (CSI) CSI oscillator frequency drift over VDD tsu(CSI) % % % 1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 37. LSI oscillator characteristics Symbol fLSI tsu(LSI)(3) Parameter LSI frequency Conditions LSI oscillator startup time - - 80 130 tstab(LSI)(3) LSI oscillator stabilization time (5% of final value) - - 120 170 IDD(LSI)(3) LSI oscillator power consumption - - 130 280 kHz s nA 1. Guaranteed by test in production. 2. Guaranteed by characterization results. 3. Guaranteed by design. DS13313 Rev 1 111/226 206 Electrical characteristics 6.3.11 STM32H723xE/G PLL characteristics The parameters given in Table 38, Table 41 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 38. PLL1 characteristics (wide VCO frequency range)(1) Symbol fPLL_IN fPLL_P_OUT fVCO_OUT tLOCK Parameter Conditions Min Typ Max Unit PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % PLL multiplier output clock P VOS0 1.5 - 550 VOS1 1.5 - 400(2) VOS2 1.5 - 300(2) VOS3 1.5 - 170(2) - 192 - 836(3) Normal mode 15 50 150(3) Sigma-delta mode (CKIN 8 MHz) 25 65 170 fVCO_OUT = 192 MHz - 51 - fVCO_OUT = 400 MHz - 19 - fVCO_OUT = 560 MHz - 10 - fVCO_OUT = 800 MHz - 9 - fVCO_OUT = 192 MHz - 38 - fVCO_OUT = 560 MHz - 8 - fVCO_OUT = 800 MHz - 7 - fVCO_OUT = 192 MHz - 0.15 - fVCO_OUT = 400 MHz - 0.14 - fVCO_OUT = 832 MHz - 0.16 - fVCO_OUT = 192 MHz - 0.17 - fVCO_OUT = 500 MHz - 0.08 - fVCO_OUT = 836 MHz - 0.06 - PLL VCO output PLL lock time Cycle-to-cycle jitter(4) fPLL_OUT = fVCO_OUT/100 Period jitter Jitter Normal mode (CKIN = 2 MHz) Long term jitter Sigma-delta mode (CKIN = 16 MHz) 112/226 (2) DS13313 Rev 1 MHz s ps STM32H723xE/G Electrical characteristics Table 38. PLL1 characteristics (wide VCO frequency range)(1) (continued) Symbol Parameter Conditions fVCO_OUT = 560 MHz IDD(PLL) PLL power consumption fVCO_OUT = 192 MHz Min Typ Max Unit VDDA 530 557 670 VCORE 1190 1285 6300 VDDA 260 286 513 VCORE 309 377 5700 A 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Guaranteed by characterization results. 4. Integer mode only. Table 39. PLL1 characteristics (medium VCO frequency range)(1) Symbol fPLL_IN fPLL_OUT fVCO_OUT tLOCK Parameter Conditions Min Typ Max Unit PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % VOS0 1.17 - 210 VOS1 1.17 - 210 VOS2 1.17 - 210 VOS3 1.17 - 200 - 150 - 420 - 60(2) 100(2) PLL multiplier output clock P, Q, R PLL VCO output Normal mode PLL lock time Cycle-to-cycle Sigma-delta mode jitter(3) - Jitter Period jitter Long term jitter fPLL_OUT = 50 MHz Normal mode fVCO_OUT = 420 MHz I(PLL) PLL power consumption on VDD fVCO_OUT = 150 MHz DS13313 Rev 1 forbidden fVCO_OUT = 150 MHz - 145 - fVCO_OUT = 300 MHz - 91 - fVCO_OUT = 400 MHz - 64 - fVCO_OUT = 420 MHz - 63 - fVCO_OUT = 150 MHz - 55 - fVCO_OUT = 400 MHz - 30 - fVCO_OUT = 400 MHz - 0.3 - VDD - 440 1150 VCORE - 530 - VDD - 180 500 VCORE - 200 - MHz s ps -ps % A 113/226 206 Electrical characteristics STM32H723xE/G 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. Table 40. PLL2 and PLL3 characteristics (wide VCO frequency range)(1) Symbol fPLL_IN fPLL_OUT Parameter Conditions Min Typ Max Unit PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % VOS0 1.5 - 550(2) VOS1 1.5 - 400(2) VOS2 1.5 - 300(2) PLL multiplier output clock P, Q, R VOS3 1.5 - 170(2) - 192 - 960(3) Normal mode - 50 150(3) Sigma-delta mode (fPLL_IN 8 MHz) - 58 166(3) fVCO_OUT = 192 MHz - 134 - fVCO_OUT = 200 MHz - 134 - fVCO_OUT = 400 MHz - 76 - fVCO_OUT = 800 MHz - 39 - fVCO_OUT PLL VCO output tLOCK PLL lock time Cycle-to-cycle jitter(4) Jitter Long term jitter IDD(PLL)(3) PLL power consumption Normal mode (fPLL_IN = 2 MHz) fVCO_OUT = 560 MHz - 0.2 - Normal mode (fPLL_IN = 16 MHz) fVCO_OUT = 560 MHz - 0.8 - Sigma-delta mode (fPLL_IN = 2 MHz) fVCO_OUT = 560 MHz - 0.2 - Sigma-delta mode (fPLL_IN = 16 MHz) fVCO_OUT = 560 MHz - 0.8 - VDD - 590 1500 VCORE - 720 - VDD - 180 600 VCORE - 280 - fVCO_OUT = 836 MHz fVCO_OUT = 192 MHz s ps % 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 114/226 MHz DS13313 Rev 1 A STM32H723xE/G Electrical characteristics 3. Guaranteed by characterization results. 4. Integer mode only. Table 41. PLL2 and PLL3 characteristics (medium VCO frequency range)(1) Symbol fPLL_IN fPLL_OUT Parameter Conditions Min Typ Max Unit PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % VOS0 1.17 - 210 MHz VOS1 1.17 - 210 - VOS2 1.17 - 210 - VOS3 1.17 - 200 - - 150 - 420 - Normal mode - 60 100(2) PLL multiplier output clock P, Q, R fVCO_OUT PLL VCO output tLOCK PLL lock time Sigma-delta mode Cycle-to-cycle jitter(3) Jitter Period jitter fVCO_OUT = 150 MHz - 145 - fVCO_OUT = 200 MHz - 91 - fVCO_OUT = 400 MHz - 64 - fVCO_OUT = 420 MHz - 63 - - 55 - - 30 - fVCO_OUT = 400 MHz - 0.3 - VDD - 440 1150 VCORE - 530 - VDD - 180 500 VCORE - 200 - fPLL_OUT = 50 MHz fVCO_OUT = 150 MHz fVCO_OUT = 400 MHz Long term jitter IDD(PLL) PLL power consumption on VDD forbidden Normal mode fVCO_OUT = 420 MHz fVCO_OUT = 150 MHz s ps ps % A 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. DS13313 Rev 1 115/226 206 Electrical characteristics 6.3.12 STM32H723xE/G Memory characteristics Flash memory The characteristics are given at TJ = -40 to 125 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 42. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Unit Write / Erase 8-bit mode - 6.5 - Write / Erase 16-bit mode - 11.5 - Write / Erase 32-bit mode - 20 - Write / Erase 64-bit mode - 35 - Min(1) Typ Max(1) mA Table 43. Flash memory programming Symbol tprog tERASE tME Parameter Conditions Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Sector (128 Kbytes) erase time Program/erase parallelism x 16 - 1.8 3.6 Program/erase parallelism x 32 - Program/erase parallelism x 8 - 3 26 Program/erase parallelism x 16 - 8 16 Program/erase parallelism x 32 - 6 12 Program/erase parallelism x 64 - 5 10 1.62 - 3.6 1.8 - 3.6 Word (266 bits) programming time Mass erase time (1 Mbyte) Unit s s Program parallelism x 8 Vprog Programming voltage Program parallelism x 16 Program parallelism x 32 Program parallelism x 64 V 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 10K erase operations. Table 44. Flash memory endurance and data retention Symbol NEND tRET 116/226 Parameter Conditions Min(1) Unit kcycles Endurance TJ = -40 to +125 C 10 Data retention 1 kcycle at TA = 85 C 30 10 kcycles at TA = 55 C 20 DS13313 Rev 1 Years STM32H723xE/G Electrical characteristics 1. Guaranteed by characterization results. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 45. They are based on the EMS levels and classes defined in application note AN1709 "EMC design guide for STM8, STM32 and Legacy MCUs ". Table 45. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, TA = 25 C, Voltage limits to be applied on any I/O pin to induce LQFP176, conforming to a functional disturbance IEC 61000-4-2 3B VFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance 5A VDD = 3.3 V, TA = 25 C, LQFP176, conforming to IEC 61000-4-4 As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) DS13313 Rev 1 117/226 206 Electrical characteristics STM32H723xE/G Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015 "Software techniques for improving microcontrollers EMC performance"). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 46. EMI characteristics Symbol Parameter Conditions Max vs. [fHSE/fCPU] Monitored frequency band Unit 8/550 MHz SEMI 6.3.14 VDD = 3.6 V, TA = 25 C, LQFP176 package, Peak level conforming to IEC61967-2 0.1 to 30 MHz 14 30 to 130 MHz 20 130 MHz to 1 GHz 27 1 GHz to 2 GHz 17 EMI Level 4 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards. Table 47. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Electrostatic discharge TA = 25 C conforming to voltage (human body model) ANSI/ESDA/JEDEC JS-001 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS-002 1. Guaranteed by characterization results. 118/226 DS13313 Rev 1 Maximum Unit value(1) Packages Class All packages 2 2000 All LQFP packages C1 250 All BGA and WLCSP packages C2a 500 V STM32H723xE/G Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 48. Electrical sensitivities Symbol LU 6.3.15 Parameter Conditions Class Conforming to JESD78, TJ = TJMax Static latchup class II level A I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49: I/O static characteristics are derived from tests performed under the conditions summarized in Table 12: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Note: For information on GPIO configuration, refer to application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com. Table 49. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3VDD(1) - - 0.4VDD-0.1 BOOT0 I/O input low level voltage - - 0.19VDD+0.1 I/O input high level voltage except BOOT0 0.7VDD(1) - - 0.47VDD+ 0.25(2) - - 0.17VDD+ 0.6(2) - - - 250 - - 200 - I/O input low level voltage except BOOT0 VIL VIH I/O input low level voltage except BOOT0 I/O input high level voltage except BOOT0 1.62 V<VDDIOx<3.6 V 1.62 V<VDDIOx<3.6 V BOOT0 I/O input high level voltage VHYS (2) TT_xx, FT_xxx and NRST I/O input hysteresis 1.62 V< VDDIOx <3.6 V BOOT0 I/O input hysteresis DS13313 Rev 1 Unit (2) V (2) V mV 119/226 206 Electrical characteristics STM32H723xE/G Table 49. I/O static characteristics (continued) Symbol Parameter Condition Min Typ Max - - +/-250 Max(VDDXXX) < VIN 5.5 V (4)(5)(8) - - 1500 0< VIN Max(VDDXXX)(8) - - +/- 350 Max(VDDXXX) < VIN 5.5 V (4)(5)(8) - - 5000(6) 0< VIN Max(VDDXXX) (8) - - +/-250 0< VIN VDDIOX - - 15 0< VIN Max(VDDXXX) FT_xx Input leakage current Ileak (3) (2) FT_u IO TT_xx Input leakage current VPP (BOOT0 alternate function) RPU Weak pull-up equivalent resistor(7) RPD Weak pull-down equivalent resistor(7) CIO I/O pin capacitance (8) VDDIOX < VIN 9 V VIN=VSS nA 35 30 40 50 k VIN=VDD (8) - 30 40 50 - 5 - 1. Compliant with CMOS requirements. 2. Guaranteed by design. 3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ileak_max = 10 A + [number of I/Os where VIN is applied on the pad] Ilkg(Max). 4. All FT_xx IO except FT_lu, FT_u and PC3. 5. VIN must be less than Max(VDDXXX) + 3.6 V. 6. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be disabled. 7. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 8. Max(VDDXXX) is the maximum value of all the I/O supplies. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 17. 120/226 Unit DS13313 Rev 1 pF STM32H723xE/G Electrical characteristics Figure 17. VIL/VIH for all I/Os except BOOT0 3 2.5 2 S req Voltage CMO TLL requirement: VIHmin = 2 V 0.7V D in= t: V IHm en uirem D +0.25 =0.47VDD on VIHmin ulati d on sim 1.5 Base -0.1 =0.4VDD max lation VIL n simu V DD o .3 d 0 e = s Ba max ment: VIL require CMOS TLL requirement: VILmin = 0.8 V 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 MSv46121V3 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 10). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 10). DS13313 Rev 1 121/226 206 Electrical characteristics STM32H723xE/G Output voltage levels Unless otherwise specified, the parameters given in Table 50: Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Table 51: Output voltage characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. All I/Os are CMOS and TTL compliant. Table 50. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1) Symbol Parameter Conditions(3) Min Max Output low level voltage CMOS IIO = 8 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage CMOS port(2) IIO = -8 mA 2.7 V VDD 3.6 V VDD-0.4 - Output low level voltage TTL port(2) IIO = 8 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage TTL port(2) IIO = -8 mA 2.7 V VDD 3.6 V 2.4 - VOL(3) Output low level voltage IIO = 20 mA 2.7 V VDD 3.6 V - 1.3 VOH(3) Output high level voltage IIO = -20 mA 2.7 V VDD 3.6 V VDD-1.3 - VOL(3) Output low level voltage IIO = 4 mA 1.62 V VDD 3.6 V - 0.4 VOH (3) Output high level voltage IIO = -4 mA 1.62 VVDD<3.6 V VDD--0.4 - IIO = 20 mA 2.3 V VDD3.6 V - 0.4 IIO = 10 mA 1.62 V VDD 3.6 V - 0.4 Unit port(2) VOL VOH VOL(3) VOH (3) VOLFM+(3) Output low level voltage for an FTf I/O pin in FM+ mode V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. 122/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 51. Output voltage characteristics for PC13, PC14, PC15 and PI8(1) Conditions(3) Min Max Output low level voltage CMOS port(2) IIO = 3 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage CMOS port(2) IIO = -3 mA 2.7 V VDD 3.6 V VDD-0.4 - Output low level voltage TTL port(2) IIO = 3 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage TTL port(2) IIO = -3 mA 2.7 V VDD 3.6 V 2.4 - VOL(2) Output low level voltage IIO = 1.5 mA 1.62 V VDD 3.6 V - 0.4 VOH(2) Output high level voltage IIO = -1.5 mA 1.62 V VDD 3.6 V VDD-0.4 - Symbol VOL VOH VOL(3) VOH (2) Parameter Unit V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. DS13313 Rev 1 123/226 206 Electrical characteristics STM32H723xE/G Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.7 V. Table 52. Output timing characteristics (HSLV OFF)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) 124/226 Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 2.7 V VDD3.6 V - 12 C=50 pF, 1.62 VVDD2.7 V - 3 C=30 pF, 2.7 VVDD3.6 V - 12 C=30 pF, 1.62 VVDD2.7 V - 3 C=10 pF, 2.7 VVDD3.6 V - 16 C=10 pF, 1.62 VVDD2.7 V - 4 C=50 pF, 2.7 V VDD3.6 V - 16.6 C=50 pF, 1.62 VVDD2.7 V - 33.3 C=30 pF, 2.7 VVDD3.6 V - 13.3 C=30 pF, 1.62 VVDD2.7 V - 25 C=10 pF, 2.7 VVDD3.6 V - 10 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 60 C=50 pF, 1.62 VVDD2.7 V - 15 C=30 pF, 2.7 VVDD3.6 V - 80 C=30 pF, 1.62 VVDD2.7 V - 15 C=10 pF, 2.7 VVDD3.6 V - 110 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 5.2 C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 2.7 VVDD3.6 V - 4.2 C=30 pF, 1.62 VVDD2.7 V - 7.5 C=10 pF, 2.7 VVDD3.6 V - 2.8 C=10 pF, 1.62 VVDD2.7 V - 5.2 DS13313 Rev 1 Unit MHz ns MHz ns STM32H723xE/G Electrical characteristics Table 52. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 VVDD3.6 V - 85 C=50 pF, 1.62 VVDD2.7 V(4) - 35 - 110 C=30 pF, 1.62 VVDD2.7 V - 40 C=10 pF, 2.7 VVDD3.6 V(4) - 166 C=10 pF, 1.62 VVDD2.7 V(4) - 100 - 3.8 (4) (4) Fmax(2) Maximum frequency 10 C=30 pF, 2.7 VVDD3.6 V (4) (4) C=50 pF, 2.7 VVDD3.6 V (4) C=50 pF, 1.62 VVDD2.7 V tr/tf(3) Output high to low level fall time and output low to high level rise time - 6.9 V(4) - 2.8 C=30 pF, 1.62 VVDD2.7 V(4) - 5.2 C=10 pF, 2.7 VVDD3.6 V(4) - 1.8 Vv - 3.3 Vv - 100 C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 C=50 pF, 2.7 VVDD3.6 C=50 pF, 1.62 VVDD2.7 V(4) Fmax(2) Maximum frequency 11 - 50 C=30 pF, 2.7 VVDD3.6 Vv - 133 C=30 pF, 1.62 VVDD2.7 V(4) - 66 C=10 pF, 2.7 VVDD3.6 V(4) - 220 C=10 pF, 1.62 VVDD2.7 V(4) - 85 V(4) - 3.3 V(4) - 6.6 V(4) - 2.4 C=30 pF, 1.62 VVDD2.7 V(4) - 4.5 C=10 pF, 2.7 VVDD3.6 V(4) - 1.5 V(4) - 2.7 C=50 pF, 2.7 VVDD3.6 C=50 pF, 1.62 VVDD2.7 tr/tf(3) Output high to low level fall time and output low to high level rise time C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 Unit MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. DS13313 Rev 1 125/226 206 Electrical characteristics STM32H723xE/G Output buffer timing characteristics (HSLV option enabled) Table 53. Output timing characteristics (HSLV ON)(1) Speed Symbol Fmax (2) Parameter Maximum frequency 00 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 10 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 11 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 1.62 VVDD2.7 V - 10 C=10 pF, 1.62 VVDD2.7 V - 10 C=50 pF, 1.62 VVDD2.7 V - 11 C=30 pF, 1.62 VVDD2.7 V - 9 C=10 pF, 1.62 VVDD2.7 V - 6.6 C=50 pF, 1.62 VVDD2.7 V - 50 C=30 pF, 1.62 VVDD2.7 V - 58 C=10 pF, 1.62 VVDD2.7 V - 66 C=50 pF, 1.62 VVDD2.7 V - 6.6 C=30 pF, 1.62 VVDD2.7 V - 4.8 C=10 pF, 1.62 VVDD2.7 V - 3 C=50 pF, 1.62 VVDD2.7 V(4) - 55 C=30 pF, 1.62 VVDD2.7 V(4) - 80 C=10 pF, 1.62 VVDD2.7 V(4) - 133 C=30 pF, 1.62 VVDD2.7 V(4) - 5.8 C=30 pF, 1.62 VVDD2.7 V(4) - 4 C=30 pF, 1.62 VVDD2.7 V(4) - 2.4 C=30 pF, 1.62 VVDD2.7 V(4) - 60 C=30 pF, 1.62 VVDD2.7 V(4) - 90 C=30 pF, 1.62 VVDD2.7 V(4) - 175 C=30 pF, 1.62 VVDD2.7 V(4) - 5.3 C=30 pF, 1.62 VVDD2.7 V(4) - 3.6 (4) - 1.9 C=30 pF, 1.62 VVDD2.7 V Unit MHz ns MHz ns MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. 126/226 DS13313 Rev 1 STM32H723xE/G 6.3.16 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49: I/O static characteristics). Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 54. NRST pin characteristics Symbol RPU(2) Parameter Conditions Min Typ Max Unit VIN = VSS 30 40 50 1.71 V < VDD < 3.6 V - - 50 1.71 V < VDD < 3.6 V 350 - - 1.62 V < VDD < 3.6 V 1000 - - Weak pull-up equivalent resistor(1) VF(NRST)(2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse ns 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 18. Recommended NRST pin protection VDD External reset circuit (1) RPU NRST (2) Internal Reset Filter 0.1 F STM32 ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset is not taken into account by the device. 6.3.17 FMC characteristics Unless otherwise specified, the parameters given in Table 55 to Table 68 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS0. DS13313 Rev 1 127/226 206 Electrical characteristics STM32H723xE/G Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics. Asynchronous waveforms and timings Figure 19 through Figure 21 represent asynchronous waveforms and Table 55 through Table 62 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * Capacitive load CL = 30 pF In all timing tables, the TKERCK is the fmc_ker_ck clock period. Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 128/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min tw(NE) FMC_NE low time 3Tfmc_ker_ck-1 tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5 tw(NOE) FMC_NOE low time 2Tfmc_ker_ck -1 2Tfmc_ker_ck+1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 2Tfmc_ker_ck - tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck+14 - tsu(Data_NOE) Data to FMC_NOEx high setup time 13 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - - 4 - Tfmc_ker_ck+1 tv(NADV_NE) FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time Max Unit 3Tfmc_ker_ck+1 ns 1. Guaranteed by characterization results. Table 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 7Tfmc_ker_ck-1 7Tfmc_ker_ck+1 tw(NOE) FMC_NOE low time 5Tfmc_ker_ck-1 5Tfmc_ker_ck +1 tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck- 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +9 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck+12 - ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle. DS13313 Rev 1 129/226 206 Electrical characteristics STM32H723xE/G Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) FMC_NADV (1) tw(NADV) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 130/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 3Tfmc_ker_ck -1 3Tfmc_ker_ck + 1 tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-1 Tfmc_ker_ck tw(NWE) FMC_NWE low time Tfmc_ker_ck -0.5 Tfmc_ker_ck+0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - tv(A_NE) FMC_NEx low to FMC_A valid - 1 th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck -0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck -0.5 - tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 2 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 5 tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 1 Unit ns 1. Guaranteed by characterization results. Table 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max tw(NE) FMC_NE low time 8Tfmc_ker_ck -1 8Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time 6Tfmc_ker_ck -1 6Tfmc_ker_ck+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck+13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+12 - Unit ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle. DS13313 Rev 1 131/226 206 Electrical characteristics STM32H723xE/G Figure 21. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 132/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 59. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck -1 4Tfmc_ker_ck +1 tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck 2Tfmc_ker_ck +0.5 ttw(NOE) FMC_NOE low time Tfmc_ker_ck -1 Tfmc_ker_ck+1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 4.0 tw(NADV) FMC_NADV low time Tfmc_ker_ck -0.5 Tfmc_ker_ck +1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) Tfmc_ker_ckk -4 - th(A_NOE) Address hold time after FMC_NOE high Tfmc_ker_ck -0.5 - tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +14 - tsu(Data_NOE) Data to FMC_NOE high setup time 13 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 60. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 8Tfmc_ker_ck -1 8Tfmc_ker_ck +1 tw(NOE) FMC_NWE low time 5Tfmc_ker_ck -1 5Tfmc_ker_ck +1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +9 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck +12 - Unit ns 1. Guaranteed by characterization results. DS13313 Rev 1 133/226 206 Electrical characteristics STM32H723xE/G Table 61. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck -1 4Tfmc_ker_ck tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck -1 Tfmc_ker_ck +0.5 tw(NWE) FMC_NWE low time 2Tfmc_ker_ck -0.5 2Tfmc_ker_ck +0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck -0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 1 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 5.0 tw(NADV) FMC_NADV low time Tfmc_ker_ck -0.5 Tfmc_ker_ck + 1 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) Tfmc_ker_ck -4.5 - th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck - 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results. Table 62. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max tw(NE) FMC_NE low time 9Tfmc_ker_ck -1 9Tfmc_ker_ck tw(NWE) FMC_NWE low time 7Tfmc_ker_ck -0.5 7Tfmc_ker_ck +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck +9 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck +12 - 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle. 134/226 DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Synchronous waveforms and timings Figure 22 through Figure 25 represent synchronous waveforms and Table 63 through Table 66 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable * MemoryType = FMC_MemoryType_CRAM * WriteBurst = FMC_WriteBurst_Enable * CLKDivision = 1 * DataLatency = 1 for NOR Flash, DataLatency = 0 for PSRAM, CL = 30 pF In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values: * For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 137 MHz at CL = 20 pF * For 1.8 V<VDD<1.9 V: maximum FMC_CLK = 100 MHz at CL = 20 pF * For 1.62 V<VDD<1.8 V: maximumFMC_CLK = 88 MHz at CL = 15 pF Figure 22. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) FMC_NEx t d(CLKL-NADVL) td(CLKH-NExH) td(CLKL-NADVH) FMC_NADV td(CLKL-AV) td(CLKH-AIV) FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE t d(CLKL-ADV) FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH) AD[15:0] th(CLKH-ADV) tsu(ADV-CLKH) D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-ADV) D2 th(CLKH-NWAITV) th(CLKH-NWAITV) th(CLKH-NWAITV) MS32757V1 DS13313 Rev 1 135/226 206 Electrical characteristics STM32H723xE/G Table 63. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period 2Tfmc_ker_ck -0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3 td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Tfmc_ker_ck+1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low 1.62 V <VDD < 3.6 V td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1.62 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 1 5.5 2 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2.5 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck +1 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 - tsu(NWAIT- FMC_NWAIT valid before FMC_CLK high 3 - FMC_NWAIT valid after FMC_CLK high 2.5 - CLKH) th(CLKH-NWAIT) 1. Guaranteed by characterization results. 136/226 - DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Figure 23. Synchronous multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:16] td(CLKH-NWEH) td(CLKL-NWEL) FMC_NWE td(CLKL-ADIV) td(CLKL-ADV) FMC_AD[15:0] td(CLKL-Data) td(CLKL-Data) AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH) FMC_NBL MS32758V1 DS13313 Rev 1 137/226 206 Electrical characteristics STM32H723xE/G Table 64. Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck -0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 3 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0...2) Tfmc_ker_ck +1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low 1.62 V <VDD < 3.6 V td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1.62 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 1 5.5 2.0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x =16...25) Tfmc_ker_ck - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5 t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +1 - td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 - 1. Guaranteed by characterization results. 138/226 - DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Figure 24. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FMC_D[15:0] FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) D1 tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-DV) D2 th(CLKH-NWAITV) t h(CLKH-NWAITV) th(CLKH-NWAITV) MS32759V1 DS13313 Rev 1 139/226 206 Electrical characteristics STM32H723xE/G Table 65. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period 2Tfmc_ker_ck -0.5 - t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Tfmc_ker_ck+1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low 1.62 V <VDD < 3.6 V td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1.62 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 1 5.5 2.0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 2.5 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck+1 - tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 - 1. Guaranteed by characterization results. 140/226 - DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Figure 25. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) td(CLKL-Data) D1 FMC_D[15:0] D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 DS13313 Rev 1 141/226 206 Electrical characteristics STM32H723xE/G Table 66. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter Min Max t(CLK) FMC_CLK period 2Tfmc_ker_ck -0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Tfmc_ker_ck+1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low 1.62 V <VDD < 3.6 V td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1.62 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 2.7 V <VDD < 3.6 V 1 5.5 2 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+0.5 - tsu(NWAIT- FMC_NWAIT valid before FMC_CLK high 3 - FMC_NWAIT valid after FMC_CLK high 2.5 - CLKH) th(CLKH-NWAIT) 1. Guaranteed by characterization results. 142/226 - DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics NAND controller waveforms and timings Figure 26 through Figure 29 represent synchronous waveforms, and Table 67 and Table 68 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration and a capacitive load (CL) of 30 pF: * COM.FMC_SetupTime = 0x01 * COM.FMC_WaitSetupTime = 0x03 * COM.FMC_HoldSetupTime = 0x02 * COM.FMC_HiZSetupTime = 0x01 * ATT.FMC_SetupTime = 0x01 * ATT.FMC_WaitSetupTime = 0x03 * ATT.FMC_HoldSetupTime = 0x02 * ATT.FMC_HiZSetupTime = 0x01 * Bank = FMC_Bank_NAND * MemoryDataWidth = FMC_MemoryDataWidth_16b * ECC = FMC_ECC_Enable * ECCPageSize = FMC_ECCPageSize_512Bytes * TCLRSetupTime = 0 * TARSetupTime = 0 In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 26. NAND controller waveforms for read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE td(ALE-NOE) th(NOE-ALE) FMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32767V1 DS13313 Rev 1 143/226 206 Electrical characteristics STM32H723xE/G Figure 27. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MS32768V1 Figure 28. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 144/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Figure 29. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 67. Switching characteristics for NAND Flash read cycles(1) Symbol Parameter Min Max tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck+0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - - 3Tfmc_ker_ck +0.5 4Tfmc_ker_ck -1 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low th(NOE-ALE) FMC_NWE high to FMC_ALE invalid Unit ns 1. Guaranteed by characterization results. Table 68. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter Min Max tw(NWE) FMC_NWE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck +0.5 tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck +1.5 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck - 5 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck +0.5 th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck - 0.5 - Unit ns 1. Guaranteed by characterization results. DS13313 Rev 1 145/226 206 Electrical characteristics STM32H723xE/G SDRAM waveforms and timings In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: * For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 95 MHz at 20 pF * For 1.8 V<VDD<1.9 V: maximum FMC_CLK = 90 MHz at 20 pF * For 1.62 V<DD<1.8 V: maximum FMC_CLK = 85 MHz at 15 pF Figure 30. SDRAM read access waveforms (CL = 1) FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS th(SDCLKL_NCAS) td(SDCLKL_NCAS) FMC_SDNCAS FMC_SDNWE tsu(SDCLKH_Data) FMC_D[31:0] th(SDCLKH_Data) Data1 Data2 Datai Datan MS32751V2 146/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 69. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck +0.5 tsu(SDCLKH _Data) Data input setup time 3 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.0 td(SDCLKL- SDNE) Chip select valid time - 1.5(2) th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 2.0 th(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - Unit ns 1. Guaranteed by characterization results. 2. Using PC2_C I/O adds 4.5 ns to this timing. Table 70. LPSDR SDRAM read timings(1) Symbol Parameter Min Max Unit tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck+0.5 tsu(SDCLKH_Data) Data input setup time 3 - th(SDCLKH_Data) Data input hold time 2.5 - td(SDCLKL_Add) Address valid time - 2 td(SDCLKL_SDNE) Chip select valid time - 1.5(2)(3) th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 2 th(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - ns 1. Guaranteed by characterization results. 2. Using PC2 I/O adds 4 ns to this timing. 3. Using PC2_C I/O adds 16.5 ns to this timing. DS13313 Rev 1 147/226 206 Electrical characteristics STM32H723xE/G Figure 31. SDRAM write access waveforms FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] th(SDCLKL_NRAS) td(SDCLKL_NRAS) FMC_SDNRAS td(SDCLKL_NCAS) th(SDCLKL_NCAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_SDNCAS FMC_SDNWE td(SDCLKL_Data) Data1 FMC_D[31:0] Data2 Datai Datan th(SDCLKL_Data) td(SDCLKL_NBL) FMC_NBL[3:0] MS32752V2 Table 71. SDRAM Write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck+0.5 td(SDCLKL _Data) Data output valid time - 2 th(SDCLKL _Data) Data output hold time 0.5 - td(SDCLKL_Add) Address valid time - 2 td(SDCLKL_SDNWE) SDNWE valid time - 2 th(SDCLKL_SDNWE) SDNWE hold time 0 - td(SDCLKL_ SDNE) Chip select valid time - 1.5(2) th(SDCLKL-_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 2 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - 1. Guaranteed by characterization results. 2. Using PC2_C I/O adds 4.5 ns to this timing. 148/226 DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Table 72. LPSDR SDRAM Write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period td(SDCLKL _Data) Data output valid time - 2 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2 th(SDCLKL-SDNWE) SDNWE hold time 0 (2)(3) Unit 2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck+0.5 td(SDCLKL- SDNE) Chip select valid time - th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 2 td(SDCLKL-SDNCAS) SDNCAS hold time 0.5 - 1.5 ns 1. Guaranteed by characterization results. 2. Using PC2 I/O adds 4 ns to this timing. 3. Using PC2_C I/O adds 16.5 ns to this timing. 6.3.18 Octo-SPI interface characteristics Unless otherwise specified, the parameters given in Table 73 and Table 75 for OCTOSPI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.5 V * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics. Table 73. OCTOSPI characteristics in SDR mode(1)(2) Symbol F(CLK) Parameter OCTOSPI clock frequency Conditions Min Typ Max 1.71 V < VDD < 3.6 V, VOS0, CLOAD = 15 pF - - 92 1.71 V < VDD < 3.6 V, VOS0, CLOAD =20 pF - - 90 2.7 V < VDD < 3.6 V, VOS0, CLOAD = 20 pF - - 140 DS13313 Rev 1 Unit MHz 149/226 206 Electrical characteristics STM32H723xE/G Table 73. OCTOSPI characteristics in SDR mode(1)(2) (continued) Symbol tw(CKH) tw(CKL) tw(CKH) tw(CKL) ts(IN)(3) th(IN) (3) Parameter Conditions OCTOSPI clock high and low PRESCALER[7:0] = n time, even division = 0,1,3,5 Min Typ Max t(CK)/2 - t(CK)/2+1 t(CK)/2-1 - t(CK)/2 - (n/2)*t(CK)/ (n+1)+1 - (n/2+1)*t(CK) /(n+1) - (n/2)*t(CK)/ (n+1) OCTOSPI clock high and low PRESCALER[7:0] = n time, odd division = 2,4,6,8 (n/2+1)*t(CK)/ (n+1)-1 Data input setup time - 3.0 - Data input hold time - 1.5 - - tv(OUT) Data output valid time - - 0.5 1(4) th(OUT) Data output hold time - 0 - - Unit ns 1. All values apply to Octal and Quad-SPI mode. 2. Guaranteed by characterization results. 3. Delay block bypassed. 4. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value. Figure 32. OCTOSPI SDR read/write timing diagram tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tv(OUT) Data output th(OUT) D0 D1 ts(IN) Data input D0 D2 th(IN) D1 D2 MSv36878V1 150/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 74. OCTOSPI characteristics in DTR mode (no DQS)(1)(2) Symbol FCK(3) tw(CKH) tw(CKL) tw(CKH) tw(CKL) tsr(IN) tsf(IN)(5) thr(IN) thf(IN)(5) Parameter OCTOSPI clock frequency OCTOSPI clock high and low time, even division Conditions Min Typ Max 1.71 V < VDD < 3.6 V, VOS0, CLOAD = 15 pF - - 90(4) 1.71 V < VDD < 3.6 V, VOS0, CLOAD = 20 pF - - 87(4) 2.7 V < VDD < 3.6 V, VOS0, CLOAD = 20 pF - - 110 t(CK)/2 - t(CK)/2+1 t(CK)/2-1 - t(CK)/2 (n/2)*t(CK)/ (n+1) - (n/2)*t(CK)/ (n+1)+1 (n/2+1)*t(CK)/( n+1) - 1 - (n/2+1)* t(CK)/(n+1) 3.0 - - PRESCALER[7:0] = n = 0,1,3,5 OCTOSPI clock high and low time, odd division PRESCALER[7:0] = n = 2,4,6,8 Data input setup time - Unit MHz ns Data input hold time tvr(OUT) tvf(OUT) Data output valid time thr(OUT) thf(OUT) Data output hold time - 1.50 - - DHQC = 0 - 6 7(6) DHQC = 1, Prescaler = 1,2 ... - tpclk/4+ 1 tpclk/4+1.25 DHQC = 0 4.5 - - DHQC = 1, Prescaler = 1,2 ... tpclk/4 - - (6) 1. All values apply to Octal and Quad-SPI mode. 2. Guaranteed by characterization results. 3. DHQC must be set to reach the mentioned frequency. 4. Using PC2 or PC3 I/O in the data bus decreases the frequency to 47 MHz. 5. Delay block bypassed. 6. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value. Figure 33. OCTOSPI DTR mode timing diagram tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 tsf(IN) thf(IN) Data input D0 D1 D4 D5 tsr(IN) thr(IN) D2 D3 D4 D5 MSv36879V1 DS13313 Rev 1 151/226 206 Electrical characteristics STM32H723xE/G Table 75. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus(1) Symbol FCK(2)(3) tw(CKH) tw(CKL) tw(CKH) tw(CKL) Parameter OCTOSPI clock frequency OCTOSPI clock high and low time, even division OCTOSPI clock high and low time, odd division Conditions Min Typ Max 2,7 V < VDD < 3.6 V, VOS0, CLOAD = 20 pF - - 100 1.71 V < VDD < 3.6 V, VOS0, CLOAD = 20 pF - - 100(4) t(CK)/2 - t(CK)/2+1 t(CK)/2-1 - t(CK)/2 (n/2)*t(CK)/ (n+1) - (n/2)*t(CK)/ (n+1)+1 (n/2+1)*t(CK)/( n+1)-1 - (n/2+1)*t(CK)/ (n+1) PRESCALER[7:0] = n = 0,1,3,5 PRESCALER[7:0] = n = 2,4,6,8 MHz tv(CK) Clock valid time - - - t(CK)+1 th(CK) Clock hold time - t(CK)/2 - - VODr(CK) CK,CK crossing level on CK rising edge VDD = 1.8 V 922 - 1229 VODf(CK) CK,CK crossing level on CK falling edge VDD = 1.8 V 1000 - 1277 tw(CS) Chip select high time - 3*t(CK) - - tv(DQ) Data input vallid time - 0 - - tv(DS) Data strobe input valid time - 0 - - th(DS) Data strobe input hold time - 0 - - tv(RWDS) Data strobe output valid time - - - 3 x t(CK) Rising edge 0 - - Falling edge 0 - - Rising edge 1 - - Falling edge 1 - (5) tsr(DQ) tsf(DQ) thr(DQ) thf(DQ) tvr(OUT) tvf(OUT) Data input setup time Data input hold time Data output valid time rising edge Data output valid time falling edge thr(OUT) Data output hold time rising edge thf(OUT) Data output hold time falling edge ns ns mV DHQC = 0 - 6 DHQC = 1, Prescaler = 1,2... - tpclk/4+ 1 tpclk/4+1.25 DHQC = 0 - 5.5 6(5) DHQC = 1, Prescaler = 1,2... - tpclk/4+ 0.5 tpclk/4+0.75 DHQC = 0 4.5 - - DHQC = 1, Prescaler = 1,2... tpclk/4 - - DHQC = 0 4.5 - - DHQC = 1, Prescaler = 1,2... tpclk/4 - - 1. Guaranteed by characterization results. 152/226 Unit DS13313 Rev 1 7 (5) (5) ns STM32H723xE/G Electrical characteristics 2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns. 3. Activating DHQC is mandatory to reach this frequency 4. Using PC2 or PC3 I/O on data bus decreases the frequency to 47 MHz. 5. Using PC2 or PC3 I/O on the data bus adds 4 ns to this timing value. Figure 34. OCTOSPI Hyperbus clock timing diagram tr(CK) tw(CKH) t(CK) tw(CKL) tf(CK) VOD(CK) CK MSv47732V2 Figure 35. OCTOSPI Hyperbus read timing diagram tw(CS) CS# tv(CK) th(CK) t ACC= Initial Access CK tv(RWDS) tv(DS) th(DS) RWDS tv(OUT) DQ[7:0] 47:40 39:32 th(OUT) 31:24 23:16 Latency Count 15:8 7:0 Command-Address tv(DQ) ts(DQ) th(DQ) Dn A Dn+1 A Dn B Dn+1 B Memory drives DQ[7:0] and RWDS Host drives DQ[7:0] and Memory drives RWDS MSv47733V2 DS13313 Rev 1 153/226 206 Electrical characteristics STM32H723xE/G Figure 36. OCTOSPI Hyperbus write timing diagram tw(CS) CS# Read Write Recovery Access Latency tv(CK) th(CK) CK tv(RWDS) High = 2x Latency Count tv(OUT) th(OUT) tv(OUT) th(OUT) Low = 1x Latency Count RWDS Latency Count DQ[7:0] tv(OUT) th(OUT) 47:40 31:24 39:32 23:16 15:8 Dn A 7:0 Command-Address Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and RWDS Host drives DQ[7:0] and Memory drives RWDS MSv47734V2 6.3.19 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 76 for Delay Block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: Table 76. Delay Block characteristics 6.3.20 Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 900 1300 1900 ps t Unit Delay - 28 33 41 - 16-bit ADC characteristics Unless otherwise specified, the parameters given in Table 77, Table 78 and Table 79 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 12: General operating conditions. Table 77. 16-bit ADC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage for ADC ON - 1.62 - 3.6 Positive reference voltage VDDA 2 V 1.62 - VREF+ VDDA VREF- Negative reference voltage 154/226 VDDA < 2 V VDDA - VSSA DS13313 Rev 1 Unit V STM32H723xE/G Electrical characteristics Table 77. 16-bit ADC characteristics(1)(2) (continued) Symbol fADC Parameter ADC clock frequency Conditions 0.12 - 50 0.12 - 25 BOOST = 01 0.12 - 12.5 BOOST = 00 - - 6.25 fADC = 36 MHz SMP = 1.5 - - 3.60 Resolution = 16 bits fADC = 37 MHz SMP = 2.5 - - 3.35 Resolution = 14 bits fADC = 50 MHz SMP = 2.5 - - 5.00 fADC = 50 MHz SMP = 2.5 - - 5.50 1.62 V VDDA 3.6 V TJ = 90 C TJ = 125 C fADC = 50 MHz SMP = 1.5 - - 7.10 Resolution = 8 bits fADC = 50 MHz SMP = 1.5 - - 8.30 Resolution = 14 bits fADC = 49 MHz SMP = 1.5 - - 4.90 fADC = 50 MHz SMP = 1.5 - - 5.50 Resolution = 10 bits Resolution = 12 bits TJ = 140 C fADC = 50 MHz SMP = 1.5 - - 6.70 fADC = 50 MHz SMP = 1.5 - - 8.30 fADC = 32 MHz SMP = 2.5 - - 2.90 Resolution = 16 bits fADC = 31 MHz SMP = 2.5 - - 2.80 Resolution = 14 bits fADC = 33 MHz SMP = 2.5 - - 3.30 Resolution = 12 bits fADC = 39 MHz SMP = 2.5 - - 4.30 fADC = 48 MHz SMP = 2.5 - - 6.00 fADC = 50 MHz SMP = 2.5 - - 7.10 fADC = 37 MHz SMP = 2.5 - - 4.10 fADC = 46 MHz SMP = 2.5 - - 5.70 fADC = 50 MHz SMP = 2.5 - - 7.10 - - resolution = 14 bits - - resolution = 12 bits - - - - - - - - - - - - Resolution = 10 bits Resolution = 8 bits Resolution = 16 bits, VDDA >2.5 V Sampling rate for Fast channels Resolution = 10 bits TJ = 90 C TJ = 125 C Resolution = 8 bits Resolution = 12 bits Resolution = 10 bits TJ = 140 C Resolution = 8 bits Resolution = 16 bits Sampling rate for Slow channels, BOOST = 0, fADC = 10 MHz Max BOOST = 11 Resolution = 12 bits fs(3) Typ BOOST = 10 Resolution = 16 bits, VDDA >2.5 V Sampling rate for Direct channels Min resolution = 10 bits TJ = 90 C TJ = 125 C fADC = 10 MHz resolution = 8 bits resolution = 12 bits resolution = 10 bits TJ = 140 C resolution = 8 bits SMP = 1.5 Unit MHz MSps 1.00 tTRIG External trigger period Resolution = 16 bits - - 10 1/ fADC VAIN(4) Conversion voltage range - 0 - VREF+ V VCMIV Common mode input voltage - VREF/2 - 10% VREF/ 2 VREF/2 + 10% V DS13313 Rev 1 155/226 206 Electrical characteristics STM32H723xE/G Table 77. 16-bit ADC characteristics(1)(2) (continued) Symbol RAIN(5) Parameter External input impedance Conditions Min Typ Max Resolution = 16 bits, TJ = 125 C - - - - 170 Resolution = 14 bits, TJ = 125 C - - - - 435 Resolution = 12 bits, TJ =125 C - - - - 1,150 Resolution = 10 bits, TJ = 125 C - - - - 5,650 Resolution = 8 bits, TJ = 125 C - - - - 26,500 Unit CADC Internal sample and hold capacitor - - 4 - pF tADCVREG _STUP ADC LDO startup time - - 5 10 us tSTAB ADC Power-up time LDO already started 1 - - conver sion cycle tCAL Offset and linearity calibration time - 16,5010 1/fADC tOFF_ Offset calibration time - 1,280 1/fADC CAL CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 Trigger conversion latency regular injected channels aborting a regular conversion CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 tS Sampling time - 1.5 - 810.5 1/fADC tCONV Total conversion time (including sampling time) Resolution = N bits ts + 0.5 + N/2 - - 1/fADC tLATR tLATRINJ 156/226 Trigger conversion latency regular and injected channels without conversion abort DS13313 Rev 1 1/fADC 1/fADC STM32H723xE/G Electrical characteristics Table 77. 16-bit ADC characteristics(1)(2) (continued) Symbol Parameter ADC consumption on VDDA, BOOST=11, Differential mode IDDA_D (ADC) IDDA_SE (ADC) IDD (ADC) Conditions Min Typ Max Resolution = 16 bits, fADC = 25 MHz - - - 1,440 - Resolution = 14 bits, fADC = 30 MHz - - - 1,350 - Resolution = 12 bits, fADC = 40 MHz - - - 990 - ADC consumption on VDDA, BOOST=10, Differential mode, fADC = 25 MHz Resolution = 16 bits - - - 1,080 - Resolution = 14 bits - - - 810 - Resolution = 12 bits - - - 585 - ADC consumption on VDDA, BOOST=01, Differential mode, fADC = 12.5 MHz Resolution = 16 bits - - - 630 - Resolution = 14 bits - - - 432 - Resolution = 12 bits - - - 315 - ADC consumption on VDDA, BOOST=00, Differential mode, fADC = 6.25 MHz Resolution = 16 bits - - - 360 - Resolution = 14 bits - - - 270 - Resolution = 12 bits - - - 225 - ADC consumption on VDDA, BOOST=11, Single-ended mode Resolution = 16 bits, fADC=25 MHz - - - 720 - Resolution = 14 bits, fADC=30 MHz - - - 675 - Resolution = 12 bits, fADC=40 MHz - - - 495 - ADC consumption on VDDA, BOOST=10, Singl-ended mode, fADC = 25 MHz Resolution = 16 bits - - - 540 - Resolution = 14 bits - - - 405 - Resolution = 12 bits - - - 292.5 - ADC consumption on VDDA, BOOST=01, Single-ended mode, fADC = 12.5 MHz Resolution = 16 bits - - - 315 - Resolution = 14 bits - - - 216 - Resolution = 12 bits - - - 157.5 - ADC consumption on VDDA BOOST=00, Single-ended mode fADC=6.25 MHz Resolution = 16 bits - - - 180 - Resolution = 14 bits - - - 135 - Resolution = 12 bits - - - 112.5 - ADC consumption on VDD fADC=50 MHz - - - 400 - fADC=25 MHz - - - 220 - fADC=12.5 MHz - - - 180 - fADC=6.25 MHz - - - 120 - fADC=3.125 MHz - - - 80 - Unit A 1. Guaranteed by design. 2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches). DS13313 Rev 1 157/226 206 Electrical characteristics STM32H723xE/G 3. These values are valid for TFBGA100, UFBGA169 and UFBGA176+25 packages and one ADC. The values for other packages and multiple ADCs may be different. 4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA. 5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. Table 78. Minimum sampling time vs RAIN (16-bit ADC)(1)(2) Minimum sampling time (s) Resolution RAIN () Direct channels(3) 16 bits 47 7.37E-08 1.14E-07 1.72E-07 47 6.29E-08 9.74E-08 1.55E-07 68 6.84E-08 1.02E-07 1.58E-07 100 7.80E-08 1.12E-07 1.62E-07 150 9.86E-08 1.32E-07 1.80E-07 220 1.32E-07 1.61E-07 2.01E-07 47 5.32E-08 8.00E-08 1.29E-07 68 5.74E-08 8.50E-08 1.32E-07 100 6.58E-08 9.31E-08 1.40E-07 150 8.37E-08 1.10E-07 1.51E-07 220 1.11E-07 1.34E-07 1.73E-07 330 1.56E-07 1.78E-07 2.14E-07 470 2.16E-07 2.39E-07 2.68E-07 680 3.01E-07 3.29E-07 3.54E-07 47 4.34E-08 6.51E-08 1.08E-07 68 4.68E-08 6.89E-08 1.11E-07 100 5.35E-08 7.55E-08 1.16E-07 150 6.68E-08 8.77E-08 1.26E-07 220 8.80E-08 1.08E-07 1.40E-07 330 1.24E-07 1.43E-07 1.71E-07 470 1.69E-07 1.89E-07 2.13E-07 680 2.38E-07 2.60E-07 2.80E-07 1000 3.45E-07 3.66E-07 3.84E-07 1500 5.15E-07 5.35E-07 5.48E-07 2200 7.42E-07 7.75E-07 7.78E-07 3300 1.10E-06 1.14E-06 1.14E-06 14 bits 12 bits 10 bits 158/226 DS13313 Rev 1 Fast channels(4) Slow channels(5) STM32H723xE/G Electrical characteristics Table 78. Minimum sampling time vs RAIN (16-bit ADC)(1)(2) (continued) Minimum sampling time (s) Resolution 8 bits RAIN () Direct channels(3) 47 3.32E-08 5.10E-08 8.61E-08 68 3.59E-08 5.35E-08 8.83E-08 100 4.10E-08 5.83E-08 9.22E-08 150 5.06E-08 6.76E-08 9.95E-08 220 6.61E-08 8.22E-08 1.11E-07 330 9.17E-08 1.08E-07 1.32E-07 470 1.24E-07 1.40E-07 1.63E-07 680 1.74E-07 1.91E-07 2.12E-07 1000 2.53E-07 2.70E-07 2.85E-07 1500 3.73E-07 3.93E-07 4.05E-07 2200 5.39E-07 5.67E-07 5.75E-07 3300 8.02E-07 8.36E-07 8.38E-07 4700 1.13E-06 1.18E-06 1.18E-06 6800 1.62E-06 1.69E-06 1.68E-06 10000 2.36E-06 2.47E-06 2.45E-06 15000 3.50E-06 3.69E-06 3.65E-06 Fast channels(4) Slow channels(5) 1. Guaranteed by design. 2. Data valid at up to 130 C, with a 47 pF PCB capacitor, and VDDA=1.6 V. 3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance. 4. Fast channels correspond to PA6, PB1, PC4, PF11, PF13 for ADCx_INPx, and to PA7, PB0, PC5, PF12, PF14 for ADCx_INNx. 5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels. DS13313 Rev 1 159/226 206 Electrical characteristics STM32H723xE/G Table 79. 16-bit ADC accuracy(1)(2) Symbol Parameter Conditions(3) Direct channel ET Total undadjusted error Fast channel Slow channel Min Typ Max Single ended - +10/-20 - Differential - 15 - Single ended - +10/-20 - Differential - 15 - Single ended - 10 - 10 - Differential EO Offset error - - 10 - EG Gain error - - 15 - Single ended - +3/-1 - Differential - +4.5/-1 - Single ended - 11 - Differential - 7 - Single ended - 13 - Differential - 7 - Single ended - 10 - Differential - 6 - Single ended - 12.2 - Differential - 13.2 - Single ended - 75.2 - Differential - 81.2 - Single ended - 77.0 - Differential - 81.0 - Single ended - 87 - Differential - 90 - ED Differential linearity error Direct channel EL Integral linearity error Fast channel Slow channel ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Unit LSB Bits dB 1. Guaranteed by characterization results for BGA packages. The values for LQFP packages might differ. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V, BOOST=11 and 16-bit mode. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) does not affect the ADC accuracy. 160/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Figure 37. ADC accuracy characteristics (12-bit resolution) [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 7 V SSA 4093 4094 4095 4096 VDDA ai14395c 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 38. Typical connection diagram using the ADC STM32 VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL1 A 12-bit converter C ADC(1) ai17534b 1. Refer to Table 77 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DS13313 Rev 1 161/226 206 Electrical characteristics STM32H723xE/G General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39 or Figure 40, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+(1) 1 F // 100 nF VDDA 1 F // 100 nF VSSA/VREF+(1) MSv50648V1 1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA, respectively. Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) STM32 VREF+/VDDA(1) 1 F // 100 nF VREF-/VSSA(1) MSv50649V1 1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA, respectively. 162/226 DS13313 Rev 1 STM32H723xE/G 6.3.21 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 80, Table 81 and Table 82 are derived from tests performed under the ambient temperature and VDDA supply voltage conditions summarized in Table 12: General operating conditions. In Table 80, Table 81 and Table 82, fADC refers to fadc_ker_ck. Table 80. 12-bit ADC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max VDDA Analog power supply for ADC ON - 1.62 - 3.6 VREF+ (3) Positive reference voltage VDDA VREF+ 1.62 - VDDA VREF- Negative reference voltage - VSSA - - fADC ADC clock frequency 1,62 V VDDA 3.6 V 1.5 - 75 - - 5 - - 4 - - 3.33 Resolution = 12 bits fADC = 75 MHz Continuous 2.4 V VDDA 3.6 V and Discontinuous 1.6V VDDA 3.6 V mode(5) -40 C TJ 130 C Resolution = 10 bits fS(4) fADC = 50 MHz(6) 1.6 V VDDA 3.6 V fADC = 38 MHz(6) - - 2.53 1.6V VDDA 3.6V fADC = 75 MHz - - 5.77 - - 4.46 - 3.23 2.4 V VDDA 3.6 V -40 C TJ 130 C Single mode Sampling rate for Direct channels Resolution = 8 bits Continuous and Discontinuous mode(5) SMP = 2.5 fADC = 42 MHz(6) - 1.6V VDDA 3.6V fADC = 75 MHz - - 6.82 - - 6.09 -40 C TJ 130 C Single mode Resolution = 6 bits fADC = 58 MHz(6) 1.6V VDDA 3.6V 2.4 V VDDA 3.6 V Continuous and Discontinuous mode(5) SMP = 2.5 fADC = 67 MHz(6) MSPS SMP = 2.5 1.6V VDDA 3.6V fADC = 48 MHz(6) - - 4.36 1.6V VDDA 3.6V fADC = 75 MHz - - 8.33 - - 8.33 - - 6.11 2.4 V VDDA 3.6 V -40 C TJ 130 C Single mode 1.6V VDDA 3.6V DS13313 Rev 1 fADC = 75 MHz(6) fADC = 55 MHz(6) V MHz 2.4 V VDDA 3.6 V Single mode Continuous and Discontinuous mode(5) fADC = 60 MHz Unit SMP = 2.5 163/226 206 Electrical characteristics STM32H723xE/G Table 80. 12-bit ADC characteristics(1)(2) (continued) Symbol Parameter Conditions Resolution = 12 bits fADC = 65 MHz Continuous 2.4 V VDDA 3.6 V and Discontinuous 1.6V VDDA 3.6V mode(5) -40 C TJ 130 C Resolution = 10 bits fS(4) Resolution = 8 bits (continued) - - 2.13 fADC = 75 MHz - - 5.77 - - 2.77 -40 C TJ 130 C fADC = 36 MHz(6) SMP = 2.5 1.6V VDDA 3.6V fADC = 30 MHz(6) - - 2.31 1.6V VDDA 3.6V fADC = 75 MHz - - 6.82 - - 4.00 -40 C TJ 130 C fADC =44 MHz(6) SMP = 2.5 fADC = 35 MHz(6) - - 3.18 1.6V VDDA 3.6V fADC = 75 MHz - - 8.33 - - 6.22 - - 4.66 - - 1.00 - - 1.28 - - 1.63 - - 2.08 -40 C TJ 130 C fADC = 56 MHz(6) SMP = 2.5 fADC = 42 MHz(6) -40 C TJ 130 C - Resolution = 6 bits fADC = 15 MHz(6) SMP = 2.5 tTRIG External trigger period Resolution = 12 bits - - 15 VAIN Conversion voltage range - 0 - VREF+ VCMIV Common mode input voltage - VREF /2- 10% VREF /2 VREF/2 + 10% Resolution = 12 bits, TJ = 125 C - - 220 RAIN External input impedance Resolution = 10 bits, TJ = 125 C - - 2100 Resolution = 8 bits, TJ = 125 C - - 12000 Resolution = 6 bits, TJ = 125 C - - 80000 (7) 164/226 DS13313 Rev 1 Unit MSPS 1.6V VDDA 3.6V Resolution = 12 bits Resolution = 8 bits 3.87 1.6V VDDA 3.6V 2.4 V VDDA 3.6 V - - 1.73 1.6V VDDA 3.6V Resolution = 10 bits - - Single mode Sampling rate for slow channels 4.33 - Single mode Resolution = 6 bits - fADC = 26 MHz(6) 2.4 V VDDA 3.6 V Continuous and Discontinuous mode(5) - 1.6V VDDA 3.6V 2.4 V VDDA 3.6 V Continuous and Discontinuous mode(5) Max fADC = 32 MHz(6) Single mode Sampling rate for fast channels (VIN[0:5]) SMP = 2.5 Typ 2.4 V VDDA 3.6 V Single mode Continuous and Discontinuous mode(5) fADC = 58 MHz Min 1/fADC V STM32H723xE/G Electrical characteristics Table 80. 12-bit ADC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit CADC Internal sample and hold capacitor - - 5 - pF ADC LDO startup time - - 5 10 s tSTAB ADC powerup time LDO already started 1 - - conversion cycle tOFF_ Offset calibration time - 135 - - Trigger conversion latency for regular and injected channels without aborting the conversion CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 Trigger conversion latency for regular and injected channels when a regular conversion is aborted CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 tADCV REG_ STUP CAL tLATR tLATR INJ 1/fADC tS Sampling time - 2.5 - 640.5 tCONV Total conversion time (including sampling time) N-bits resolution tS + 0.5 + N - - ADC consumption IDDA_ on VDDA and VREF, D(ADC) Differential mode IDDA_ SE (ADC) IDD (ADC) ADC consumption on VDDA and VREF, Singleended mode ADC consumption on VDD per fADC fS= 5 MSPS - 430 - fS = 1 MSPS - 133 - fS = 0.1 MSPS - 51 - fS= 5 MSPS - 350 - fS = 1 MSPS - 122 - fS = 0.1 MSPS - 47 - - - 2.4 - A A/ MHz 1. Guaranteed by design. 2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches). 3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA. 4. Guaranteed by characterization for BGA and CSP packages. The values for LQFP packages may be different. DS13313 Rev 1 165/226 206 Electrical characteristics STM32H723xE/G 5. The conversion of the first element in the group is excluded. 6. fADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy sampling periods, the maximum frequency is fADC value * SMPy / 2.5 with a limitation to 75 MHz. 7. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified. Table 81. Minimum sampling time vs RAIN (12-bit ADC)(1)(2) Resolution 12 bits 10 bits 166/226 RAIN () Minimum sampling time (s) Direct channels(3) Fast channels(4) Slow channels(5) 47 5.55E-08 7.04E-08 1.03E-07 68 5.76E-08 7.22E-08 1.05E-07 100 6.17E-08 7.65E-08 1.07E-07 150 7.02E-08 8.45E-08 1.13E-07 220 8.59E-08 1.00E-07 1.22E-07 330 1.11E-07 1.26E-07 1.41E-07 470 1.46E-07 1.61E-07 1.69E-07 680 1.98E-07 2.17E-07 2.25E-07 47 4.90E-08 6.06E-08 8.77E-08 68 5.07E-08 6.27E-08 8.95E-08 100 5.41E-08 6.67E-08 9.22E-08 150 6.18E-08 7.50E-08 9.59E-08 220 7.51E-08 8.70E-08 1.04E-07 330 9.46E-08 1.07E-07 1.17E-07 470 1.22E-07 1.34E-07 1.42E-07 680 1.63E-07 1.77E-07 1.86E-07 1000 2.27E-07 2.42E-07 2.43E-07 1500 3.27E-07 3.40E-07 3.35E-07 2200 4.53E-07 4.86E-07 4.73E-07 3300 6.56E-07 6.93E-07 6.72E-07 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Table 81. Minimum sampling time vs RAIN (12-bit ADC)(1)(2) (continued) Resolution 8 bits 6 bits RAIN () Minimum sampling time (s) Direct channels(3) Fast channels(4) Slow channels(5) 47 4.35E-08 5.31E-08 7.36E-08 68 4.47E-08 5.48E-08 7.47E-08 100 4.72E-08 5.79E-08 7.63E-08 150 5.33E-08 6.35E-08 7.88E-08 220 6.26E-08 7.26E-08 8.47E-08 330 7.84E-08 8.80E-08 9.48E-08 470 9.80E-08 1.07E-07 1.14E-07 680 1.28E-07 1.39E-07 1.43E-07 1000 1.76E-07 1.88E-07 1.90E-07 1500 2.49E-07 2.66E-07 2.64E-07 2200 3.50E-07 3.63E-07 3.63E-07 3300 5.09E-07 5.27E-07 5.24E-07 4700 7.00E-07 7.28E-07 7.09E-07 6800 9.84E-07 1.03E-06 1.00E-06 10000 1.43E-06 1.48E-06 1.44E-06 15000 2.10E-06 2.18E-06 2.11E-06 47 3.79E-08 4.58E-08 5.74E-08 68 3.88E-08 4.69E-08 5.81E-08 100 4.09E-08 4.89E-08 5.93E-08 150 4.48E-08 5.25E-08 6.14E-08 220 5.07E-08 5.81E-08 6.58E-08 330 6.04E-08 6.79E-08 7.46E-08 470 7.37E-08 8.10E-08 8.60E-08 680 9.31E-08 1.01E-07 1.04E-07 1000 1.23E-07 1.32E-07 1.34E-07 1500 1.71E-07 1.82E-07 1.82E-07 2200 2.39E-07 2.50E-07 2.49E-07 3300 3.43E-07 3.57E-07 3.49E-07 4700 4.72E-07 4.92E-07 4.81E-07 6800 6.65E-07 6.89E-07 6.68E-07 10000 9.54E-07 9.88E-07 9.54E-07 15000 1.40E-06 1.45E-06 1.39E-06 1. Guaranteed by design. 2. Data valid up to 130 C, with a 22 pF PCB capacitor and VDDA = 1.62 V. DS13313 Rev 1 167/226 206 Electrical characteristics STM32H723xE/G 3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance. 4. Fast channels correspond to ADCx_INx[0:5]. 5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels. Table 82. 12-bit ADC accuracy(1)(2) Symbol Parameter Conditions Direct channel ET Total unadjusted error Fast channel Slow channel Min Typ Max Single ended - 3.5 5 Differential - 2.5 3 Single ended - 3.5 5 Differential - 2.5 3 Single ended - 3.5 5 Differential - 2.5 3 +/-2 +/-5 EO Offset error - - EG Gain error - - Single ended - ED Differential linearity error +/0.75 Differential - +/-0.5 +1.25 /-1 Single ended - +/-1 +/-2.5 Differential - +/-1 +/-2 Single ended - +/-1 +/-2.5 Differential - +/-1 +/-2 Single ended - +/-1 +/-2.5 Differential - +/-1 +/-2 Direct channel EL Integral linearity error Fast channel Slow channel TBD (3) +1.5/- LSB 1 Effective number of bits Single ended - 11.2 - ENOB Differential - 11.5 - Single ended - 68.9 - SINAD Signal-tonoise and distortion ratio Differential - 71.1 - SNR Signal-tonoise ratio Single ended - 69.1 - Differential - 71.4 - Total harmonic distortion Single ended - -79.6 - THD Differential - -81.8 - 168/226 DS13313 Rev 1 Unit bits dB STM32H723xE/G Electrical characteristics 1. Guaranteed by characterization for BGA packages. The maximum values are preliminary data. The values for LQFP packages may be different. 2. ADC DC accuracy values are measured after internal calibration in Continuous and Discontinuous mode. 3. TBD stands for "to be defined". 6.3.22 DAC characteristics Table 83. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.8 VDD = 2.0 V - - 18.7 DAC output buffer OFF - - 50 pF Sample and Hold mode - 0.1 1 F DAC output buffer ON 0.2 - VDDA -0.2 V DAC output buffer OFF 0 - VREF+ 0.5 LSB - 2.05 3 1 LSB - 1.97 2.87 2 LSB - 1.67 2.84 4 LSB - 1.66 2.78 8 LSB - 1.65 2.7 Normal mode, DAC output buffer OFF, 1LSB CL=10 pF - 1.7 2 Normal mode, DAC output buffer ON, CL 50 pF, RL = 5 - 5 7.5 2 5 -80 -28 RL Resistive Load DAC output buffer ON RO Output Impedance RBON Output impedance sample and hold mode, output buffer ON DAC output buffer ON RBOFF Output impedance sample and hold mode, output buffer OFF DAC output buffer OFF CL CSH VDAC_OUT Capacitive Load Voltage on DAC_OUT output Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes tSETTLING when DAC_OUT reaches the final value of 0.5LSB, 1LSB, 2LSB, 4LSB, 8LSB) DAC output buffer OFF Normal mode, DAC output buffer ON, CL 50 pF, RL 5 Wakeup time from off state (setting the ENx bit in the DAC Control tWAKEUP(2) register) until the final value of 1LSB is reached Normal mode, DAC output buffer OFF, CL 10 pF DC VDDA supply rejection ratio Normal mode, DAC output buffer ON, CL 50 pF, RL = 5 PSRR DS13313 Rev 1 Unit V k k k s s - dB 169/226 206 Electrical characteristics STM32H723xE/G Table 83. DAC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max MODE<2:0>_V12=100/101 (BUFFER ON) - 0.7 2.6 tSAMP Sampling time in Sample and Hold mode CL=100 nF (code transition between the lowest input code and the highest input code when DAC_OUT reaches the 1LSB final value) MODE<2:0>_V12=110 (BUFFER OFF) - 11.5 18.7 MODE<2:0>_V12=111 (INTERNAL BUFFER OFF) - 0.3 0.6 Unit ms (3) s Ileak Output leakage current - CIint Internal sample and hold capacitor - 1.8 2.2 2.6 pF tTRIM Middle code offset trim time Minimum time to verify the each code 50 - - s Voffset Middle code offset for 1 trim code step VREF+ = 3.6 V - 850 - VREF+ = 1.8 V - 425 - No load, middle code (0x800) - 360 - No load, worst code (0xF1C) - 490 - No load, middle/ worst code (0x800) - 20 - - 360*TON/ (TON+TOFF) - No load, middle code (0x800) - 170 - No load, worst code (0xF1C) - 170 - No load, middle/ worst code (0x800) - 160 - Sample and Hold mode, Buffer ON, CSH=100 nF (worst code) - 170*TON/ (TON+TOFF) - Sample and Hold mode, Buffer OFF, CSH=100 nF (worst code) - 160*TON/ (TON+TOFF) - DAC output buffer ON IDDA(DAC) DAC quiescent consumption from VDDA DAC output buffer OFF Sample and Hold mode, CSH=100 nF DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ DAC output buffer OFF 1. Guaranteed by design unless otherwise specified. 170/226 DS13313 Rev 1 (4) (4) (4) nA V A STM32H723xE/G Electrical characteristics 2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value). 3. Refer to Table 49: I/O static characteristics. 4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more details. Table 84. DAC accuracy(1) Symbol Parameter Conditions Min Typ Max DNL Differential non linearity(2) DAC output buffer ON -2 - 2 DAC output buffer OFF -2 - 2 - Monotonicity 10 bits - - - DAC output buffer ON, CL 50 pF, RL 5 -4 - 4 DAC output buffer OFF, CL 50 pF, no RL -4 - 4 VREF+ = 3.6 V - - 12 VREF+ = 1.8 V - - 25 DAC output buffer OFF, CL 50 pF, no RL - - 8 DAC output buffer OFF, CL 50 pF, no RL - - 5 VREF+ = 3.6 V - - 5 VREF+ = 1.8 V - - 7 DAC output buffer ON,CL 50 pF, RL 5 - - 1 DAC output buffer OFF, CL 50 pF, no RL - - 1 DAC output buffer ON, CL 50 pF, RL 5 - - 30 INL Offset Integral non linearity(3) Offset error at code 0x800 (3) Offset1 Offset error at code 0x001(4) OffsetCal Offset error at code 0x800 after factory calibration Gain TUE TUECal SNR Gain error(5) Total unadjusted error DAC output buffer ON, CL 50 pF, RL 5 DAC output buffer ON, CL 50 pF, RL 5 - LSB LSB LSB % DAC output buffer OFF, CL 50 pF, no RL 12 - - 23 DAC output buffer ON,CL 50 pF, RL 5 , 1 kHz, BW = 500 KHz - 67.8 - DAC output buffer OFF, CL 50 pF, no RL,1 kHz, BW = 500 KHz - 67.8 - DS13313 Rev 1 LSB LSB Total unadjusted error DAC output buffer ON, CL 50 pF, after calibration RL 5 Signal-to-noise ratio(6) Unit LSB dB 171/226 206 Electrical characteristics STM32H723xE/G Table 84. DAC accuracy(1) (continued) Symbol THD SINAD ENOB Parameter Total harmonic distortion(6) Signal-to-noise and distortion ratio(6) Conditions Min Typ Max DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - -78.6 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - -78.6 - DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 67.5 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - 67.5 - DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 10.9 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - Effective number of bits Unit dB dB bits 10.9 - 1. Guaranteed by characterization results. 2. Difference between two consecutive codes minus 1 LSB. 3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON. 6. Signal is -0.5dBFS with Fsampling=1 MHz. Figure 41. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 172/226 DS13313 Rev 1 STM32H723xE/G 6.3.23 Electrical characteristics Voltage reference buffer characteristics Table 85. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode, VDDA = 3.3 V VDDA Analog supply voltage Degraded mode(2) Normal mode at 30 C, Iload = 100 A VREFBUF _OUT Voltage Reference Buffer Output, at 30 C, Iload= 100 A Degraded Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.10 VSCALE = 011 1.62 - 1.80 VSCALE = 000 2.4980 2.5000 2.5035 VSCALE = 001 2.0460 2.0490 2.0520 VSCALE = 010 1.8010 1.8040 1.8060 VSCALE = 011 1.4995 1.5015 1.5040 VSCALE = 000 VDDA- 150 mV - VDDA VSCALE = 001 VDDA- 150 mV - VDDA VSCALE = 010 VDDA- 150 mV - VDDA VSCALE = 011 VDDA- 150 mV - VDDA mode(2) Unit V TRIM Trim step resolution - - - 0.05 0.1 % CL Load capacitor - - 0.5 1 1.50 F esr Equivalent Serial Resistor of CL - - - - 2 ILOAD Static load current - - - - 4 mA Iline_reg Line regulation 2.8 V VDDA 3.6 V Iload = 500 A - 200 - Iload = 4 mA - 100 - Iload_reg Load regulation 500 A ILOAD 4 mA Normal mode - 50 - ppm/ mA Tcoeff Temperature coefficient - - Tcoeff VREFINT + 100 ppm/ C PSRR Power supply rejection -40 C < TJ < +130 C DC - - 60 - 100KHz - - 40 - DS13313 Rev 1 ppm/V dB 173/226 206 Electrical characteristics STM32H723xE/G Table 85. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA (VREFBUF) Parameter Conditions Start-up time Typ Max CL=0.5 F - - 300 - CL=1 F - - 500 - CL=1.5 F - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit s mA ILOAD = 0 A - - 15 25 ILOAD = 500 A - - 16 30 ILOAD = 4 mA - - 32 50 A 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage). 3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively. 6.3.24 Analog temperature sensor characteristics Table 86. Temperature sensor characteristics Symbol Parameter TL(1) (2) Avg_Slope V30(3) tstart_run tS_temp (1) Isens(1) Isensbuf(1) Min Typ Max Unit VSENSE linearity with temperature - - 3 C Average slope - 2 - mV/C Voltage at 30C 5 C - 0.62 - V Startup time in Run mode (buffer startup) - - 25.2 ADC sampling time when reading the temperature 9 - - Sensor consumption - 0.18 0.31 Sensor buffer consumption - 3.8 6.5 s A 1. Guaranteed by design. 2. Guaranteed by characterization results. 3. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Table 87. Temperature sensor calibration values Symbol 174/226 Parameter Memory address TS_CAL1 Temperature sensor raw data acquired value at 30 C, VDDA=3.3 V 0x1FF1 E820 -0x1FF1 E821 TS_CAL2 Temperature sensor raw data acquired value at 110 C, VDDA=3.3 V 0x1FF1 E840 - 0x1FF1 E841 DS13313 Rev 1 STM32H723xE/G 6.3.25 Electrical characteristics Digital temperature sensor characteristics Table 88. Digital temperature sensor characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fDTS(2) Output Clock frequency - 500 750 1150 kHz TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750 Hz/ C TJ = -40C to 30C -13 - 4 TJ = 30C to Tjmax -7 - 2 VOS2 0 - 0 VOS0, VOS1, VOS3 -1 - 1 TTOTAL_ERROR (2) Temperature offset measurement, all VOS C TVDD_CORE Additional error due to supply variation tTRIM Calibration time - - - 2 ms tWAKE_UP Wake-up time from off state until DTS ready bit is set - - 67 116.00 s IDDCORE_DTS DTS consumption on VDD_CORE - 8.5 30 70.0 A C 1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by characterization results. 6.3.26 Temperature and VBAT monitoring Table 89. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - K Q Ratio on VBAT measurement - 4 - - -10 - +10 % s (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input 9 - - VBAThigh High supply monitoring - 3.55 - VBATlow Low supply monitoring - 1.36 - V 1. Guaranteed by design. Table 90. VBAT charging characteristics Symbol RBC Parameter Battery charging resistor Condition Min Typ Max VBRS in PWR_CR3= 0 - 5 - 1.5 - VBRS in PWR_CR3= 1 DS13313 Rev 1 Unit K 175/226 206 Electrical characteristics STM32H723xE/G Table 91. Temperature monitoring characteristics Symbol 6.3.27 Parameter Min Typ Max TEMPhigh High temperature monitoring - 117 - TEMPlow Low temperature monitoring - -25 - Unit C Voltage booster for analog switch Table 92. Voltage booster for analog switch characteristics(1) Symbol VDD Parameter Condition Min Typ Max Unit - 1.62 2.6 3.6 V - - - 50 s 1.62 V VDD 2.7 V - - 125 2.7 V < VDD < 3.6 V - - 250 Supply voltage tSU(BOOST) Booster startup time IDD(BOOST) Booster consumption A 1. Guaranteed by characterization results. 6.3.28 Comparator characteristics Table 93. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 VIN Comparator input voltage range - 0 - VDDA V VBG Scaler input voltage - VSC Scaler offset voltage - - 5 10 mV BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.8 1 - - 140 250 High-speed mode - 2 5 Medium mode - 5 20 Ultra-low-power mode - 15 80 High-speed mode - 50 80 Medium mode - 0.5 0.9 Ultra-low-power mode - 2.5 7 High-speed mode - 50 120 Medium mode - 0.5 1.2 Ultra-low-power mode - 2.5 7 Full common mode range - 5 20 VDDA IDDA(SCALER) Parameter Scaler static consumption from VDDA tSTART_SCALER Scaler startup time tSTART Comparator startup time to reach propagation delay specification Propagation delay for 200 mV step with 100 mV overdrive tD (3) Voffset 176/226 Propagation delay for step > 200 mV with 100 mV overdrive only on positive inputs Comparator offset error DS13313 Rev 1 Unit (2) A s s ns s ns s mV STM32H723xE/G Electrical characteristics Table 93. COMP characteristics(1) (continued) Symbol Parameter Vhys Comparator hysteresis Conditions Min Typ Max No hysteresis - 0 - Low hysteresis 4 10 22 Medium hysteresis 8 20 37 High hysteresis 16 30 52 Static - 400 600 With 50 kHz 100 mV overdrive square signal - 800 - Static - 5 7 - 6 - Static - 70 100 With 50 kHz 100 mV overdrive square signal - 75 - Ultra-lowpower mode IDDA(COMP) Comparator consumption from VDDA Medium mode With 50 kHz 100 mV overdrive square signal High-speed mode Unit mV nA A 1. Guaranteed by design, unless otherwise specified. 2. Refer to Table 17: Embedded reference voltage. 3. Guaranteed by characterization results. 6.3.29 Operational amplifier characteristics Table 94. Operational amplifier characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25C, no load on output - - 1.5 Unit V VIOFFSET Input offset voltage All voltages and temperature, no load - - 2.5 VIOFFSET Input offset voltage drift - - 3.0 - TRIMOFFSETP TRIMLPOFFSETP Offset trim step at low common input voltage (0.1*VDDA) - - 1.1 1.5 TRIMOFFSETN TRIMLPOFFSETN Offset trim step at high common input voltage (0.9*VDDA) - - 1.1 1.5 ILOAD Drive current - - - 500 ILOAD_PGA Drive current in PGA mode - - - 270 mV V/C mV DS13313 Rev 1 A 177/226 206 Electrical characteristics STM32H723xE/G Table 94. Operational amplifier characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CLOAD Capacitive load - - - 50 pF CMRR Common mode rejection ratio - - 80 - dB PSRR Power supply rejection ratio CLOAD 50pf / RLOAD 4 k(2) at 1 kHz, Vcom=VDDA/2 50 66 - dB GBW Gain bandwidth for high supply range 200 mV Output dynamic range VDDA - 200 mV 4 7.3 12.3 MHz SR Slew rate (from 10% and 90% of output voltage) Normal mode - 3 - High-speed mode - 24 - AO Open loop gain 200 mV Output dynamic range VDDA - 200 mV 59 90 129 dB m Phase margin - - 55 - GM Gain margin - - 12 - dB VOHSAT High saturation voltage Iload=max or RLOAD=min, Input at VDDA VDDA -100 mV - - Low saturation voltage Iload=max or RLOAD=min, Input at 0 V - - 100 Normal mode CLOAD 50pf, RLOAD 4 k, follower configuration - 0.8 3.2 High speed mode CLOAD 50pf, RLOAD 4 k, follower configuration - 0.9 2.8 PGA gain = 2 -1 - 1 PGA gain = 4 -2 - 2 PGA gain = 8 -2.5 - 2.5 PGA gain = 16 -3 - 3 PGA gain = 2 -1 - 1 PGA gain = 4 -1 - 1 PGA gain = 8 -2 - 2 PGA gain = 16 -3 - 3 PGA gain = 2 -1 - 1 PGA gain = 4 -3 - 3 PGA gain = 8 -3.5 - 3.5 PGA gain = 16 -4 - 4 VOLSAT tWAKEUP Wake up time from OFF state Non inverting gain error value PGA gain Inverting gain error value External non-inverting gain error value 178/226 DS13313 Rev 1 V/s mV s % STM32H723xE/G Electrical characteristics Table 94. Operational amplifier characteristics(1) (continued) Symbol Parameter R2/R1 internal resistance values in non-inverting PGA mode(3) Rnetwork R2/R1 internal resistance values in inverting PGA mode(3) Delta R Conditions Min Typ Max PGA Gain=2 - 10/10 - PGA Gain=4 - 30/10 - PGA Gain=8 - 70/10 - PGA Gain=16 - 150/10 - PGA Gain = -1 - 10/10 - PGA Gain = -3 - 30/10 - PGA Gain = -7 - 70/10 - PGA Gain = -15 - 150/10 - - -15 - 15 Gain=2 - GBW/2 - Gain=4 - GBW/4 - Gain=8 - GBW/8 - Gain=16 - GBW/16 - Gain = -1 - 5.00 - Gain = -3 - 3.00 - Gain = -7 - 1.50 - Gain = -15 - 0.80 - - 140 - - 55 - - 570 1000 - 610 1200 Resistance variation (R1 or R2) PGA bandwidth for different non inverting gain PGA BW PGA bandwidth for different inverting gain en IDDA(OPAMP) Voltage noise density OPAMP consumption from VDDA at 1 KHz at 10 KHz Normal mode Highspeed mode output loaded with 4 k no Load, quiescent mode, follower Unit k/ k % MHz MHz nV/ Hz A 1. Guaranteed by design, unless otherwise specified. 2. RLOAD is the resistive load connected to VSSA or to VDDA. 3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1. DS13313 Rev 1 179/226 206 Electrical characteristics 6.3.30 STM32H723xE/G Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 95 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 12: General operating conditions. * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (DiFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM). Table 95. DFSDM measured timing Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock 1.62 < VDD < 3.6 V - - fSYSCLK SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0) - - 20 SPI mode (SITP[1:0] = 0,1), Internal clock mode (SPICKSEL[1:0] # 0) - - 20 1.62 < VDD < 3.6 V - - 20 Even division, CKOUTDIV = n, 1, 3, 5.. 45 50 55 Odd division, CKOUTDIV = n, 2, 4, 6.. (((n/2+1)/(n+1)) *100)-5 fCKIN (1/TCKIN) fCKOUT DuCyCKOUT 180/226 Input clock frequency Output clock frequency Output clock frequency duty cycle 1.62 < VDD < 3.6 V Unit MHz % DS13313 Rev 1 (((n/2+1)/(n+1)) (((n/2+1)/(n+1)) *100) *100)+5 STM32H723xE/G Electrical characteristics Table 95. DFSDM measured timing (continued) Symbol Parameter Conditions Min Typ Max Unit twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0) TCKIN/2-0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0) 2 - - th Data input hold time SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0) 1 - - TManchester Manchester data period (recovered clock period) Manchester mode (SITP[1:0] = 2,3), Internal clock mode (SPICKSEL[1:0] # 0) (CKOUTDIV+1) * TDFSDMCLK - (2*CKOUTDIV) * TDFSDMCLK ns DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT (SPICKSEL=0) tsu th twl twh tr tf tr tf SITP = 00 tsu th SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 tsu FSDM_DATINy SPI timing : SPICKSEL = 1, 2, 3 SPI timing : SPICKSEL = 0 Figure 42. Channel transceiver timing diagrams th twl twh SITP = 0 tsu th SITP = 1 DS13313 Rev 1 181/226 206 Electrical characteristics 6.3.31 STM32H723xE/G Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 96 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * DCMI_PIXCLK polarity: falling * DCMI_VSYNC and DCMI_HSYNC polarity: high * Data formats: 14 bits * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS0 Table 96. DCMI characteristics(1) Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 - DCMI_PIXCLK Pixel Clock input - 110 MHz Dpixel Pixel Clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input setup time 2 - th(HSYNC), th(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input hold time 1 - ns 1. Guaranteed by characterization results. Figure 43. DCMI timing diagram 1/DCMI_PIXCLK DCMI_PIXCLK tsu(HSYNC) th(HSYNC) DCMI_HSYNC tsu(VSYNC) th(HSYNC) DCMI_VSYNC tsu(DATA) th(DATA) DATA[0:13] MS32414V2 182/226 DS13313 Rev 1 STM32H723xE/G 6.3.32 Electrical characteristics Parallel synchronous slave interface (PSSI) characteristics Unless otherwise specified, the parameters given in Table 97 and Table 98 for PSSI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 12: General operating conditions. Table 97. PSSI transmit characteristics(1) Symbol Parameter Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK - 0.4 - PSSI_PDCK PSSI Clock input - 50 - 35(2) Dpixel PSSI Clock input duty cycle 30 70 tov(DATA) Data output valid time - - - - 10 14(2) toh(DATA) Data output hold time 4.5 - tov((DE) DE output valid time - 10 toh(DE) DE output hold time 4 - tsu(RDY) RDY input setup time 0 - th(RDY) RDY input hold time 0 - MHz % ns 1. Guaranteed by characterization results. 2. This value is obtained by using PA9, PA10 or PH4 I/O. Table 98. PSSI receive characteristics(1) Symbol Parameter Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK - 0.4 - PSSI_PDCK PSSI Clock input - 110 MHz Dpixel PSSI Clock input duty cycle 30 70 % tsu(DATA) Data input setup time 1.5 - th(DATA) Data input hold time 0.5 - tsu((DE) DE input setup time 2 - th(DE) DE input hold time 1 - tov(RDY) RDY output valid time - 15 toh(RDY) RDY output hold time 5.5 - ns 1. Guaranteed by characterization results. DS13313 Rev 1 183/226 206 Electrical characteristics 6.3.33 STM32H723xE/G LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 99 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity: low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS0 Table 99. LTDC characteristics(1) Symbol fCLK Parameter Min 2.7<VDD<3.6 V, 20 pF LTDC clock output frequency 2.7<VDD<3.6 V Max 150 - 133 LTDC clock output duty cycle 45 55 tw(CLKH), tw(CLKL) Clock High time, low time tw(CLK)//2-0.5 tw(CLK)/2+0.5 th(DATA) tv(HSYNC), tv(VSYNC), tv(DE) th(HSYNC), th(VSYNC), th(DE) 2.7<VDD<3.6 V Data output valid time 1.62<VDD<3.6 V Data output hold time HSYNC/VSYNC/DE output valid time - % 2.0 2.5/6.5(2) 0 - 2.7<VDD<3.6 V - 1.5 1.62<VDD<3.6 V - 2.0 0 - HSYNC/VSYNC/DE output hold time MHz 90/76.5(2) 1.62<VDD<3.6 V DCLK tv(DATA) Unit ns 1. Guaranteed by characterization results. 2. This value is valid when PA[9], PA[10], PA[11], PA[12], PA[15], PB[11], PH[4], PJ[8], PJ[9], PJ[10], PJ[11], PK[0], PK[1] or PK[2] is used. 184/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Figure 44. LCD-TFT horizontal timing diagram tCLK LCD_CLK LCD_VSYNC tv(HSYNC) tv(HSYNC) LCD_HSYNC th(DE) tv(DE) LCD_DE tv(DATA) LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] Pixel Pixel 1 2 Pixel N th(DATA) HSYNC Horizontal width back porch Active width Horizontal back porch One line MS32749V1 Figure 45. LCD-TFT vertical timing diagram tCLK LCD_CLK tv(VSYNC) tv(VSYNC) LCD_VSYNC LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] M lines data VSYNC Vertical width back porch Active width Vertical back porch One frame MS32750V1 DS13313 Rev 1 185/226 206 Electrical characteristics 6.3.34 STM32H723xE/G Timer characteristics The parameters given in Table 100 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 100. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 275 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 137.5 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 240 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 275 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2. 6.3.35 Low-power timer characteristics The parameters given in Table 101 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 101. LPTIMx characteristics(1)(2) Symbol tres(TIM) fLPTIMxCLK fEXT ResTIM Parameter Min Max Unit Timer resolution time 1 - tTIMxCLK Timer kernel clock 0 137.5 Timer external clock frequency on Input1 and Input2 0 fLPTIMxCLK/2 Timer resolution - 16 bit - 65536 tTIMxCLK tMAX_COUNT Maximum possible count 1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers. 2. Guaranteed by design. 186/226 DS13313 Rev 1 MHz STM32H723xE/G 6.3.36 Electrical characteristics Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual revision 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s * Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. I 2C The timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below: Table 102. Minimum i2c_ker_ck frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog Filtre ON DNF=0 8 Analog Filtre OFF DNF=1 9 Analog Filtre ON DNF=0 17 Analog Filtre OFF DNF=1 16 Unit MHz - The SDA and SCL I/O requirements are met with the following restrictions: * The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but still present. * The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load CLoad supported in Fm+, which is given by these formulas: tr(SDA/SCL)=0.8473xRPxCLoad RP(min)= (VDD-VOL(max))/IOL(max) Where RP is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 103. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by analog filter 50(2) 80(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. DS13313 Rev 1 187/226 206 Electrical characteristics STM32H723xE/G 3. Spikes with widths above tAF(max) are not filtered. USART interface characteristics Unless otherwise specified, the parameters given in Table 104 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART). Table 104. USART characteristics(1) Symbol Parameter Conditions Master mode, 1.62 V < VDD < 3.6 V fCK USART clock frequency Slave receiver mode, 1.62 V < VDD < 3.6 V Slave transmitter mode, 1.62 V < VDD < 3.6 V Slave transmitter mode, 2.5 V < VDD < 3.6 V Min Typ Max 17.0 - 45.0 MHz 27.0 - 37.0 tsu(NSS) NSS setup time Slave mode tker+1 - - th(NSS) NSS hold time Slave mode 2 - - tw(SCKH), tw(SCKL) CK high and low time Master mode 1/fCK/2-2 1/fCK/2 1/fCK/2+2 tsu(RX) Data input setup time Master mode 16 - - Slave mode 1.0 - - th(RX) Data input hold time Master mode 0 - - Slave mode 2.0 - - Slave mode, , 1.62 V < VDD < 3.6 V - 12.0 18 Slave mode, , 2.5 V < VDD < 3.6 V - 12.0 13.5 Master mode - 0.5 1 Slave mode 9 - - Master mode 0 - - tv(TX) th(TX) Data output valid time Data output hold time 1. Guaranteed by characterization results. 188/226 DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Figure 46. USART timing diagram in Master mode High NSS input SCK Output SCK Output tc(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(RX) RX INPUT tr(SCK)/tf(SCK) BIT6 IN MSB IN LSB IN th(RX) TX OUTPUT BIT1 OUT MSB OUT tv(TX) LSB OUT th(TX) MSv65386V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 47. USART timing diagram in Slave mode NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(TX) tw(SCKL) First bit OUT TX output tv(TX) th(TX) Next bits OUT tf(SCK) tdis(TX) Last bit OUT th(RX) tsu(RX) RX input First bit IN Next bits IN Last bit IN MSv65387V1 DS13313 Rev 1 189/226 206 Electrical characteristics STM32H723xE/G SPI interface characteristics Unless otherwise specified, the parameters given in Table 105 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 105. SPI characteristics(1)(2) Symbol fSCK Parameter SPI clock frequency Conditions Min Typ Max Master mode, 2.7 V < VDD < 3.6 V, SPI1, 2, 3 125 Master mode, 1.62 V < VDD < 3.6 V, SPI1, 2, 3 80/66(3) Master mode, 1.62 V < VDD < 3.6 V, SPI4, 5, 6 68.5 Slave receiver mode, 1.62 V < VDD < 3.6 V, SPI1, 2, 3 - - 100 Slave receiver mode, 1.62 V < VDD < 3.6 V, SPI4, 5, 6 68.5 Slave mode transmitter/full duplex, 2.7 V < VDD < 3.6 V 45 Slave mode transmitter/full duplex, 1.62 V < VDD < 3.6 V 42.5/31(4) tsu(NSS) NSS setup time Slave mode 2 - - th(NSS) NSS hold time Slave mode 1 - - Master mode /2-1(5) tw(SCKH), tw(SCKL) 190/226 SCK high and low time DS13313 Rev 1 tSCK tSCK/2(5) tSCK /2+1(5) Unit MHz - STM32H723xE/G Electrical characteristics Table 105. SPI characteristics(1)(2) (continued) Symbol tsu(MI) tsu(SI) Parameter Data input setup time th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 2.5 - - Slave mode 1 - - Master mode 3 - - Slave mode 1.5 - - Unit ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode, 2.7 V < VDD < 3.6 V - 7.5 11 Slave mode, 1.62 V < VDD < 3.6 V - 7.5 12/16(4) Master mode, 1.62 V < VDD < 3.6 V - 1 1.5/5.5(6) Slave mode 7 - - Master mode 0.5 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time ns 1. Guaranteed by characterization results. 2. The values given in the above table might be degraded when PC3_C/PC2_C I/Os are used (not available on all packages). 3. This value is obtained by using PA9 or PA12 I/O. 4. This value is obtained by using PC2 or PJ11 I/O. 5. tSCK = tker_ck * baud rate prescaler. 6. This value is obtained by using PC3 or PJ10 I/O. Figure 48. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) First bit OUT MISO output th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 DS13313 Rev 1 191/226 206 Electrical characteristics STM32H723xE/G Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 50. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 192/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics I2S Interface characteristics Unless otherwise specified, the parameters given in Table 106 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,WS). Table 106. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max - 50 Master transmitter - 50/40(2) Master receiver - 50/40(2) Slave transmitter - 41.5/31(3) Slave receiver - 50 - 2/6(4) 1 - 3 - 1 - Master receiver 2.5 - Slave receiver 1 - Master receiver 3 - Slave receiver 1.5 - Slave transmitter (after enable edge) - 12/16(3) tv(SD_MT) Master transmitter (after enable edge) - 2/6(5) th(SD_ST) Slave transmitter (after enable edge) 6.5 - Master transmitter (after enable edge) 0.5 - - fMCK I2S main clock output tv(WS) WS valid time th(WS) WS hold time tsu(WS) WS setup time th(WS) WS hold time tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Master mode Slave mode Data input setup time Data input hold time tv(SD_ST) Data output valid time Data output hold time th(SD_MT) Unit MHz ns 1. Guaranteed by characterization results. 2. This value is obtained when PA9 or PA12 are used. 3. This value is obtained when PC2 is used. 4. This value is obtained when PA11 or PA15 are used. DS13313 Rev 1 193/226 206 Electrical characteristics STM32H723xE/G 5. This value is obtained when PC3 is used. Figure 51. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 52. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 194/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 107 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * IO Compensation cell activated. * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 107. SAI characteristics(1) Symbol Parameter Conditions Min Max fMCK SAI Main clock output - - 50 Master transmitter, 2.7 V VDD 3.6 V - 45 Master transmitter, 1.62 V VDD 3.6 V - 32 Master receiver, 1.62 V VDD 3.6 V - 32 Slave transmitter, 2.7 V VDD 3.6 V - 47.5 Slave transmitter, 1.62 V VDD 3.6 V - 41.5 Slave receiver, 1.62 V VDD 3.6 V - 50 fCK SAI clock frequency(2) DS13313 Rev 1 Unit MHz 195/226 206 Electrical characteristics STM32H723xE/G Table 107. SAI characteristics(1) (continued) Symbol Parameter tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Conditions Min Max Master mode, 2.7 V VDD 3.6 V - 11 Master mode, 1.62 V VDD 3.6 V - 15.5 Slave mode 2.5 - Master mode 6 - Slave mode 0.5 - Master receiver 3 - Slave receiver 3.5 - Master receiver 3.5 - Slave receiver 0 - Slave transmitter (after enable edge), 2.7 V VDD 3.6 V - 10.5 Slave transmitter (after enable edge), 1.62 V VDD 3.6 V - 12 Slave transmitter (after enable edge) 6.5 - Master transmitter (after enable edge), 2.7 V VDD 3.6 V - 10.5 Master transmitter (after enable edge), 1.62 V VDD 3.6 V - 14.5 Master transmitter (after enable edge) 6 - Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time Unit ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. Figure 53. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) Slot n+2 th(SD_MR) Slot n MS32771V1 196/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Figure 54. SAI slave timing waveforms 1/fSCK SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) th(FS) tsu(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 MDIO characteristics Unless otherwise specified, the parameters given in Table 108 for the MDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * I/O Compensation cell activated. * Measurement points are done at CMOS levels: 0.5VDD * HSLV activated when VDD 2.7 V * VOS level set to VOS0 Table 108. MDIO Slave timing parameters Symbol Parameter Min Typ Max Unit FMDC Management Data Clock - - 30 MHz td(MDIO) Management Data Iput/output output valid time 8 10 18 tsu(MDIO) Management Data Iput/output setup time 1 - - th(MDIO) Management Data Iput/output hold time 1 - - DS13313 Rev 1 ns 197/226 206 Electrical characteristics STM32H723xE/G Figure 55. MDIO Slave timing diagram tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 109 and Table 110 for SDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Table 109. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 120 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time 8.5 9.5 - tW(CKH) Clock high time 8.5 9.5 - fPP =52MHz ns CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode tISU Input setup time HS - 2.5 - - tIH Input hold time HS - 0.5 - - Input valid window (variable window) - 1.5 - - tIDW (3) ns CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode 198/226 tOV Output valid time HS - - 5.5 6 tOH Output hold time HS - 4.5 - - DS13313 Rev 1 ns STM32H723xE/G Electrical characteristics Table 109. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD - 1.5 - tIHD Input hold time SD - 0.5 - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD - - 1 1 tOHD Output hold default time SD - 0 - - ns 1. Guaranteed by characterization results. 2. Above 100 MHz, CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 110. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 85 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time 8.5 9.5 - tW(CKH) Clock high time 8.5 9.5 - fPP =52 MHz ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS - 1.5 - - tIH Input hold time HS - 1.5 - - Input valid window (variable window) - 3.5 - - tIDW (3) ns CMD, D outputs (referenced to CK) in eMMC mode tOVD Output valid time HS - - 6 6.5 tOHD Output hold time HS - 5.5 - - ns 1. Guaranteed by characterization results. 2. CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. DS13313 Rev 1 199/226 206 Electrical characteristics STM32H723xE/G Figure 56. SDIO high-speed mode Figure 57. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Figure 58. DDR mode tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tvf(OUT) Data output thr(OUT) IO0 tvr(OUT) IO1 IO2 thf(OUT) IO3 tsf(IN) thf(IN) Data input IO0 IO1 IO4 IO5 tsr(IN) thr(IN) IO2 IO3 IO4 IO5 MSv36879V3 200/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics USB OTG_FS characteristics Unless otherwise specified, the parameters given in Table 112 for ULPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=20 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Table 111. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit VDD33US USB transceiver operating voltage - 3.0(1) - 3.6 V RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600 RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 ZDRV Output driver impedance(2) Driver high and low 28 36 44 B 1. The USB functionality is ensured down to 2.7 V. However, not all USB electrical characteristics are degraded in the 2.7 to 3.0 V voltage range. 2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. USB OTG_HS characteristics Unless otherwise specified, the parameters given in Table 112 for ULPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=20 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. DS13313 Rev 1 201/226 206 Electrical characteristics STM32H723xE/G Table 112. Dynamics characteristics: USB ULPI(1) Symbol Parameter Condition Min Typ Max tSC Control in (ULPI_DIR , ULPI_NXT) setup time - 5.5 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 0 - - tSD Data in setup time - 2.5 - - tHD Data in hold time - 0 - - 2.7 V < VDD < 3.6 V, CL = 20 pF - 6.0 8.0 1.71 V < VDD < 3.6 V , CL = 15 pF - 6.0 12 tDC/tDD Control/Datal output delay Unit ns 1. Guaranteed by characterization results. Figure 59. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC Control out (ULPI_STP) tDC tDD data out (8-bit) ai17361c 202/226 DS13313 Rev 1 STM32H723xE/G Electrical characteristics Ethernet interface characteristics Unless otherwise specified, the parameters given in Table 113, Table 114 and Table 115 for SMI, RMII and MII are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL=20 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics: Table 113. Dynamics characteristics: Ethernet MAC signals for SMI (1) Symbol Parameter Min Typ Max tMDC MDC cycle time( 2.5 MHz) 400 400 403 Td(MDIO) Write data valid time 0.5 1.5 4 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization results. Figure 60. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 DS13313 Rev 1 203/226 206 Electrical characteristics STM32H723xE/G Table 114. Dynamics characteristics: Ethernet MAC signals for RMII (1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 2 - - tsu(CRS) Carrier sense setup time 1.5 - - tih(CRS) Carrier sense hold time 1.5 - - td(TXEN) Transmit enable valid delay time 8 0 10.5 td(TXD) Transmit data valid delay time 7 8 9.5 Unit ns 1. Guaranteed by characterization results. Figure 61. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b Table 115. Dynamics characteristics: Ethernet MAC signals for MII (1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2.0 - - tih(RXD) Receive data hold time 2.0 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1.5 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 9.0 11 19 td(TXD) Transmit data valid delay time 8.5 10 19 1. Guaranteed by characterization results. 204/226 DS13313 Rev 1 Unit ns STM32H723xE/G Electrical characteristics Figure 62. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668b JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 116 and Table 117 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 12: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS0 Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics: Table 116. Dynamics JTAG characteristics Symbol Fpp 1/tc(TCK) Parameter TCK clock frequency Conditions Min Typ Max 2.7V <VDD< 3.6 V - - 37 1.62 <VDD< 3.6 V - - 27.5 Unit MHz tisu(TMS) TMS input setup time - 2.5 - - tih(TMS) TMS input hold time - 1 - - tisu(TDI) TDI input setup time - 1.5 - - - tih(TDI) TDI input hold time - 1 - - - tov(TDO) TDO output valid time 2.7V <VDD< 3.6 V - 8 13.5 - 1.62 <VDD< 3.6 V - 8 18 - toh(TDO) TDO output hold time - 7 - - - DS13313 Rev 1 205/226 206 Electrical characteristics STM32H723xE/G Table 117. Dynamics SWD characteristics Symbol Fpp 1/tc(SWCLK) Parameter SWCLK clock frequency Conditions Min Typ Max 2.7V <VDD< 3.6 V - - 71 1.62 <VDD< 3.6 V - - 52.5 Unit MHz tisu(SWDIO) SWDIO input setup time - 2.5 - - - tih(SWDIO) SWDIO input hold time - 1 - - - 2.7V <VDD< 3.6 V - 8.5 14 - - 8.5 19 - 8 - - - tov(SWDIO) SWDIO output valid time 1.62 <VDD< 3.6 V toh(SWDIO) SWDIO output hold time - Figure 63. JTAG timing diagram tc(TCK) TCK tsu(TMS/TDI) th(TMS/TDI) tw(TCKL) tw(TCKH) TDI/TMS tov(TDO) toh(TDO) TDO MSv40458V1 Figure 64. SWD timing diagram tc(SWCLK) SWCLK tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH) SWDIO (receive) tov(SWDIO) toh(SWDIO) SWDIO (transmit) MSv40459V1 206/226 DS13313 Rev 1 Package information 7 STM32H723xE/G Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. 7.1 LQFP100 package information LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package. Figure 65. LQFP100 package outline 0.25 mm c A1 A A2 SEATING PLANE C GAUGE PLANE D L D1 A1 K ccc C L1 D3 51 75 50 100 26 PIN 1 1 IDENTIFICATION 25 e 1. Drawing is not to scale. 208/226 E E3 E1 b 76 DS13313 Rev 1 1L_ME_V5 STM32H723xE/G Package information Table 118. LQPF100 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS13313 Rev 1 209/226 224 Package information STM32H723xE/G Figure 66. LQFP100 package recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. 210/226 DS13313 Rev 1 STM32H723xE/G Package information Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 67. LQFP100 marking example (package top view) Product identification(1) STM32H723 VGT6 Revision code R Date code Y WW Pin 1 indentifier MSv53061V3 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13313 Rev 1 211/226 224 Package information 7.2 STM32H723xE/G TFBGA100 package information TFBGA100 is a 100-ball, 8 x 8 mm, 0.8 mm pitch, thin fine-pitch ball grid array package. ddd C Figure 68. TFBGA100 package outline SEATING PLANE B A1 ball index A1 ball area identifier D1 e A A2 A1 C F E E1 G A B C D E F G H J K D e A 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW b (100 BALLS) eee C A B fff C TOP VIEW A08Q_ME_V1 1. Drawing is not to scale. 212/226 DS13313 Rev 1 STM32H723xE/G Package information Table 119. TFBGA100 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 69. TFBGA100 package recommended footprint Dpad Dsm A08Q_FP_V1 1. Dimensions are expressed in millimeters. DS13313 Rev 1 213/226 224 Package information STM32H723xE/G Table 120. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm Device marking for TFBGA100 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 70. TFBGA100 marking example (package top view) Product identification(1) STM32H723 Revision code VGH6 R Date code Y Ball A1identifier WW MSv53063V2 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 214/226 DS13313 Rev 1 STM32H723xE/G LQFP144 package information LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package. Figure 71. LQFP144 package outline SEATING PLANE c A1 A2 C A 0.25 mm GAUGE PLANE D L D1 K A1 ccc C L1 D3 108 73 109 72 E 37 144 PIN 1 E1 E3 b 7.3 Package information 1 36 IDENTIFICATION e 1A_ME_V4 1. Drawing is not to scale. DS13313 Rev 1 215/226 224 Package information STM32H723xE/G Table 121. LQFP144 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 216/226 DS13313 Rev 1 STM32H723xE/G Package information Figure 72. LQFP144 package recommended footprint 108 109 73 1.35 72 0.35 0.5 19.9 17.85 22.6 144 37 1 36 19.9 22.6 ai14905e 1. Dimensions are expressed in millimeters. DS13313 Rev 1 217/226 224 Package information STM32H723xE/G Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 73. LQFP144 marking example (package top view) Product identification(1) ES32H723ZGT6 Revision code R Date code Y WW Pin 1 identifier MSv53065V2 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 218/226 DS13313 Rev 1 STM32H723xE/G 7.4 Package information UFBGA144 package information UFBGA144 is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package. Figure 74. UFBGA144 package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y M 12 1 BOTTOM VIEW Ob (144 balls) O eee M Z Y X O fff M Z TOP VIEW A0AS_ME_V2 1. Drawing is not to scale. Table 122. UFBGA144 package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.320 0.0091 0.0110 0.0126 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DS13313 Rev 1 219/226 224 Package information STM32H723xE/G Table 122. UFBGA144 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 75. UFBGA144 package recommended footprint Dpad Dsm BGA_WLCSP_FT_V1 Table 123. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) Dimension 220/226 Recommended values Pitch 0.50 mm Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DS13313 Rev 1 STM32H723xE/G Package information Device marking for UFBGA144 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 76. UFBGA144 marking example (package top view STM32H Product identification(1) 723ZGI6 Revision code Date code Y WW R Ball A1 identifier MSv53067V2 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS13313 Rev 1 221/226 224 Package information 7.5 STM32H723xE/G Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 124. Thermal characteristics Symbol JA JB JC 222/226 Definition Thermal resistance junction-ambient Thermal resistance junction-board Thermal resistance junction-case Parameter Value Thermal resistance junction-ambient LQFP100 - 14 x 14 mm /0.5 mm pitch 43.8 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm /0.8 mm pitch 43.2 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 44.8 Thermal resistance junction-ambient UFBGA144 - 7 x 7 mm /0.5 mm pitch TBD Thermal resistance junction-ambient LQFP100 - 14 x 14 mm /0.5 mm pitch 19.8 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm /0.8 mm pitch 24.8 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 24.4 Thermal resistance junction-ambient UFBGA144 - 7 x 7 mm /0.5 mm pitch TBD Thermal resistance junction-ambient LQFP100 - 14 x 14 mm /0.5 mm pitch 7.3 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm /0.8 mm pitch 13.2 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 7.4 Thermal resistance junction-ambient UFBGA144 - 7 x 7 mm /0.5 mm pitch TBD DS13313 Rev 1 Unit C/W C/W C/W STM32H723xE/G 7.5.1 Package information Reference documents * JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. * For information on thermal management, refer to application note "Thermal management guidelines for STM32 applications" (AN5036) available from www.st.com. DS13313 Rev 1 223/226 224 Ordering information 8 STM32H723xE/G Ordering information Example: STM32 H 723 V G T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 723 = STM32H723 Pin count V = 100 pins Z = 144 pins Flash memory size E = 512 Kbytes G = 1024 Kbytes Package T = LQFP ECOPACK2 I = UFBGA pitch 0.5 mm ECOPACK2 H = TFBGA ECOPACK2 Temperature range 6 = Industrial temperature range -40 to 85 C Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 224/226 DS13313 Rev 1 STM32H723xE/G 9 Revision history Revision history Table 125. Document revision history Date Revision 10-Jul-2020 1 Changes Initial release. DS13313 Rev 1 225/226 225 STM32H723xE/G IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2020 STMicroelectronics - All rights reserved 226/226 DS13313 Rev 1