; AUSTIN SEMICONDUCTOR, ING. M5C2561 883C Feels] We Mm telat Y\' SRAM 256Kx1SRAM jy AVAILABLE AS MILITARY SPECIFICATIONS * SMD 5962-88725 , 5962-88544 * MIL-STD-883 FEATURES e Ultra high speed: 12, 15ns High speed: 20, 25, 35 and 45ns Battery backup: 2V data retention * Low power standby * High-performance, low-power, CMOS double-metal process Single +5V (10%) power supply * Easy memory expansion with CE e All inputs and output are TTL compatible OPTIONS MARKING Timing 12ns access (Contact factory) -12 15ns access (Contact factory) -15 20ns access (Contact factory) -20 25ns access (Contact factory) -25 35ns access -35 45ns access -45 55ns access ~55* 70ns access -70* * Packages Ceramic DIP (300 mil) C No. 106 Ceramic LCC EC No. 204 * 2V data retention, low power standby L Electrical characteristics ident.cal to those provided for the 45ns access devices, GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high- speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon tech- nology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE) on all organi- zations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The x1 configu- ration features separate data input and output. PIN ASSIGNMENT (Top View) 24-Pin DIP UVce DAI JA16 LAI5 DA JAi3 Nar Oat DA10 allio 1sfag wei hee 13141516 17 VssU12 13UCE is aioe Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. The L version provides an approximate 50 percent reduction in CMOS standby current (Issc2) over the stan- dard version. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. MT5C2561 883C REV 397 DS000002 Austin Semiconductor. Inc reserves the ngnt to change products ar specifications without notice.AUSTIN SEMICONDUCTOR. INC. MT5C2561 883C 256K x 1 SRAM FUNCTIONAL BLOCK DIAGRAM Vcc GND A A_ oe D A) 6 5 N A 8 262,144-BIT Fe , | o |} memory array [2 > Q } Ty = oO A oO = _ a lo CE A OE A >| (LSB) iO = C FA COLUMN DECODER DOWN tf tt ttttt tt A A A A A A TRUTH TABLE MODE CE WE OUTPUT POWER STANDBY H x HIGH-Z STANDBY READ L H Q ACTIVE WRITE L L HIGH-Z ACTIVE MT5C2561 683C 1 4 0 Austin Semiconductor, Inc . reserves the right to change products or specifications without natice REV. 97 = Dsoc0002hee MT5C2561 883C 256K x 1 SRAM AUSTIN SEMICONDUCTOR, ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- a Voltage on Any Input Relative to Vss.. mum Ratings may cause permanent damage to the device. Voltage on Vcc Supply Ri Relative to Ves. -1V to +7V This is a stress rating only and functional operation of the Voltage Applied to Q... cceatenee _.-1V to +7V device at these or any other conditions above those indi- Storage Temperature ..0......... cee ceesceeeeenees 65C to +150C cated in the operational sections of this specification is not Power Dissipation. .....cc0..ccsscesessesesssesseeesecenresneseeeseceens 1W implied. Exposure to absolute maximum rating conditions Short Circuit Output Current 0... cscceeseeececneeeeee 50mA for extended periods may affect reliability. Lead Temperature (soldering 10 seconds).............. +260C Junction Temperature 0.0... cceesceseeeseceettnecneneenenes +175C ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (55C < Tg < 125C; Voc = 5V + 10%) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.2 Vec+1.0 Vv 1 Input Low (Logic 0) Voltage Vit -0.5 0.8 Vv 1,2 Input Leakage Current OV < Vin < Vcc Iu 5 5 pA Output Leakage Current Output Disabled Lo 5 5 pA OV < VouT < Vcc Output High Voltage low = -4.0MA Vou 2.4 Vv 1 Output Low Voltage lot = 8.0MA VoL 0.4 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL | -15 | -20 | -25 | -35 | -45 UNITS NOTES Power Supply CE < Vit; Veco = MAX Current: Operating f = MAX = 1/'RC (MIN) lec 165 | 150 | 135 | 120 | 115 mA 3 Output Open Power Supply CE = Vin; Vcc = MAX Current: Standby f = MAX = 1/'RC (MIN) IsBT1 50 40 35 30 30 mA Output Open CE 2 Vin, All Other Inputs < Vit or > Vin, Vcc = MAX Ispt2 25 25 25 25 25 mA f=0Hz CE 2 Vec -0.2V; Vec = MAX Vit < Vss +0.2V Issc2 5 5 5 5 5 mA Vin > Vec -0.2V; f= 0 Hz L Version Only Ispc2 4 4 4 4 4 mA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input Capacitance Ty, = 25C, f= 1MHz Ci 8 pF 4 Output Capacitance Vcc = 5V Co 8 pF 4 neces BB3C 1 -1 1 Aushin Semiconductor, Inc reserves the nght to change products or specifications ewilnout notice BSo00002ALSTIN SEMICONDUC FOR, ING pe Re 256K x 1 SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C < Tg < 125C; Vec = 5V + 10%) 15 -20 -25 35 -45 DESCRIPTION SYM | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES READ Cycle READ cycle time 'RC 15 20 25 35 45 ns Address access time AA 15 20 25 35 45 ns Chip Enable access time ACE 15 20 25 35 45 ns Output hold from address change OH 2 2 2 2 2 ns Chip Enable to output in Low-Z 'LZCE}] 2 2 2 2 2 ns 7 Chip disable to output in High-Z 'HZCE 8 9 10 14 15 ns 6, 7 Chip Enable to power-up time 'PU 0) 0 0 0 0 ns 4 Chip disable to power-down time PD 15 20 25 35 45 ns 4 WRITE Cycle WRITE cycie time wc 15 20 25 35 45 ns Chip Enable to end of write tcw | 12 15 18 20 25 ns Address valid to end of write AW 12 15 18 20 25 ns Address setup time AS 0 0 0 0 0 ns Address hold from end of write 'AH 2 2 2 2 2 ns WRITE pulse width twP 12 16 17 20 25 ns Data setup time ps 7 10 12 15 20 ns Data hold time 'DH 0 0 0 0 0 ns Write disable to output in Low-Z LZWE] 2 2 2 2 2 ns 7 Write Enable to output in High-Z HZWE 7 0 10 0 11 0 14 0 15 ns 6,7 MTscase1 999 1-12 Austin Semiconductor ine reserves the ght te change products or specifications without notice bBsoooGd2ihe) OF/40) BIR 15161 56K x i SRAM AUSTIN SF CONDUCTOR, ING AC TEST CONDITIONS *8V +5V Input pulse levels ...... eect eeeereeees Vss to 3V Q 480 a 480 Input rise and fall times ........c. eee eee cree 5ns 255 30 pF 255 5 pF Input timing reference level oo... eee 1.5V Output reference level oo... cette 1.5V P / Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD Output load 0... ee eesereereeee See figures 1 and 2 EQUIVALENT EQUIVALENT NOTES 1. All voltages referenced to Vss (GND). 7. Atany given temperature and voltage condition, 2. -3V for pulse width < 20ns. HZCE is less than LZCE and HZWE is less than 3. Icc is dependent on output loading and cycle rates. LZWE, The specified value applies with the output unloaded, 8. WE is HIGH for READ cycle. 9. Device is continuously selected. Chip enable is held in and f = _ Hz. its active stat (RC (MIN) its active state. a 4. This parameter is guaranteed but not tested. 10. Address valid Peele or coincident with latest 5. Test conditions as specified with the output loading pocaurnang, chip enable. rs : 11. RC = READ cycle time. as shown in Fig. 1 unless otherwise noted. 2 Chi ble (CE) and wri ble (WE oo. 6. 'HZCE and HZWE are specified with CL = 5 pF as in - Chip enable (CE) and write enable (WE) can initiate Fig. 2. Transition is measured + 500mV typical from steady state voltage, allowing for actual tester RC time constant. and terminate a WRITE cycle. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Vcc for Retention Data VbrR 2 _ Vv Data Retention Current CE 2 (Vcc - 0.2V)|Vcc = 2V|_ Iccor 500 LA VIN > (Vcc - 0.2V) or<0.2V Vcc = 3V 800 yA Chip Deselect to Data CDR 0 ns 4 Retention Time Operation Recovery Time 'R tRC ns 4,11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE Voc \ 4.5V tcoR DR >eVv KOR 4.5VY tr = ZI WH. DON'T CARE UNDEFINED MTSC2361 ag3c REY 337 Dsoeo00002 Austin Semiconductor inc reserves the ght Io change products or specifications without soliceAUSTIN SEMICONDUCTOR. INC. MYSC2561 883C 256K x 1 SRAM READ CYCLE NO. 18 tac | ADDR | Rh. VALID taa tOH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2 7.8.10 tac CE K, / tACE tLZCE Q HIGH-Z DATA VALID DON'T CARE RY UNDEFINED MT5C2561 883C 4 -4 4 Austin Semiconductor, inc , reserves Ihe night to change products of specifications without notice REV 3/97 Dsoo0002AUSTIN SEMICONDUC TOR. INC. MT5C2561 883C 256K x 1 SRAM ADDR ADDR WRITE CYCLE NO. 1 "2 (Chip Enable Controlled) two tas | tcw taH HOO rey UN U AO OONN Gs OOS POOOVO OO HIGH-Z WRITE CYCLE NO. 27.72 (Write Enable Controlled) two tos DATA VALID DON'T CARE Rad UNDEFINED MT5C2561 883C 1-15 Austin. Semiconductor Inc , reservas the right to change products or srecih cations withioul nonceAUSTIN SEMICONDUCTOR, INC. MT5C2561 883C 256K x 1 SRAM | ELECTRICAL TEST REQUIREMENTS SUBGROUPS MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table |} INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, BA, 10 (Method 5004) FINAL ELECTRICAL TEST PARAMETERS 1*, 2,3, 77, 8,9, 10, 11 (Method 5004) GROUP A TEST REQUIREMENTS 1, 2, 3, 4**, 7, 8,9, 10, 11 (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1,2, 3, 7,8, 9, 10, 11 (Method 5005) * PDA applies to subgroups 1 and 7. * Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. MTSC2561 883C 1 -1 6 Austin Semiconductor Inc. reserves the ngril fo change products or specifications without nobce REV 397 Dsaocce