FINAL COM'L: -7/10/12/15/20, Q-12/15/20 MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 IND: -12/14/18/24 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 64 Macrocells Peripheral Component Interconnect (PCI) compliant 7.5 ns tPD Commercial 12 ns tPD Industrial 32 Outputs 133 MHz fCNT 4 "PAL22V16" blocks with buried macrocells 38 Inputs; 210A Inputs have built-in pull-up resistors Pin-compatible with MACH110, MACH111, MACH211, and MACH215 64 Flip-flops; 2 clock choices GENERAL DESCRIPTION The MACH210 is a member of the high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL22V16" structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides regis- tered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. Publication# 14128 Rev. I Issue Date: May 1995 Amendment /0 BLOCK DIAGRAM I/O0-I/O7 I0-I1, I3-I4 I/O8-I/O15 8 I/O Cells 8 I/O Cells 8 8 8 Macrocells Macrocells 8 8 8 Macrocells 2 Macrocells OE OE 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator 22 4 22 Switch Matrix 22 22 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator OE OE Macrocells 8 8 I/O Cells 2 Macrocells 8 Macrocells 8 8 Macrocells 8 2 I/O Cells 8 8 I/O24-I/O31 I/O16-I/O23 CLK0/I2, CLK1/I5 14128I-1 2 MACH210-7/10/12/15/20, Q-12/15/20 CONNECTION DIAGRAM Top View I/O0 GND 4 2 3 I/O29 I/O28 I/O2 I/O1 5 I/O31 I/O30 I/O3 6 VCC I/O4 PLCC 1 44 43 42 41 40 I/O5 I/O6 7 39 I/O27 8 38 I/O7 I0 9 37 I/O26 I/O25 10 I/O24 CLK1/I5 I1 11 36 35 GND 12 34 GND CLK0/I2 13 33 I4 I/O8 I/O9 14 32 I3 15 31 I/O10 I/O11 16 30 I/O23 I/O22 29 I/O21 17 I/O20 I/O18 I/O19 I/O16 I/O17 GND VCC I/O14 I/O15 I/O12 I/O13 18 19 20 21 22 23 24 25 26 27 28 14128I-2 Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215. MACH210-7/10/12/15/20, Q-12/15/20 3 CONNECTION DIAGRAM Top View 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 TQFP 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 4 MACH210-7/10/12/15/20, Q-12/15/20 14128I-3 ORDERING INFORMATION Commercial Products Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 210A -7 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors 210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors, Quarter Power OPERATING CONDITIONS C = Commercial (0C to +70C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD Valid Combinations MACH210A-7 MACH210A-10 MACH210A-12 MACH210-12 MACH210-15 MACH210-20 MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 JC, VC Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations or to check on newly released combinations. JC MACH210-7/10/12/15/20, Q-12/15/20 (Com'l) 5 ORDERING INFORMATION Industrial Products Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 210A -12 J OPTIONAL PROCESSING Blank = Standard Processing FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors OPERATING CONDITIONS I = Industrial (-40C to +85C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -12 = 12 ns tPD -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD Valid Combinations MACH210A-12 MACH210A-14 MACH210-14 MACH210-18 MACH210-24 6 I JI Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations or to check on newly released combinations. MACH210-12/14/18/24 (Ind) FUNCTIONAL DESCRIPTION The MACH210 consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACH210A inputs and I/O pins have built-in pull-up resistors. While it is always a good design practice to tie unused pins high, the 210A pull-up resistors provide design security and stability in the event that unused pins are left disconnected. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation Macrocell Output Buried M0 M1 M2 M3 M4 M5 The PAL Blocks Each PAL block in the MACH210 (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent "PAL22V16" with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACH210 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array The MACH210 product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset. The Logic Allocator The logic allocator in the MACH210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 The Macrocell The MACH210 has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flipflop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. MACH210-7/10/12/15/20, Q-12/15/20 7 The I/O Cell PCI Compliance The I/O cell in the MACH210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. The MACH210A-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH210A-7/10's predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. 8 MACH210-7/10/12/15/20, Q-12/15/20 0 4 8 12 16 20 24 28 32 36 40 43 Output Enable Output Enable Asynchronous Reset Asynchronous Preset Output Macro cell M0 I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O 2 Buried Macro cell M1 2 Output Macro cell M2 2 Buried Macro cell M3 0 2 C0 C1 Output Macro cell M4 2 C2 C3 Buried Macro cell M5 2 C5 C6 Switch Matrix C7 C8 Logic Allocator C4 C9 Output Macro cell M6 2 Buried Macro cell M7 2 Output Macro cell M8 2 C10 C11 Buried Macro cell M9 2 C12 C13 Output Macro cell M10 2 C14 C15 63 Buried Macro cell M11 2 Output Macro cell M12 2 Buried Macro cell M13 2 Output Macro cell M14 2 Buried Macro cell M15 2 8 12 16 20 24 28 32 36 40 43 CLK1 4 CLK0 0 16 8 14128I-4 Figure 1. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 9 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V Commercial (C) Devices DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -160 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = 5.0 V, f = 25 MHz, TA = 25C (Note 4) V 0.5 2.0 V V -30 130 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 10 MACH210A-7 (Com'l) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit VCC = 5.0 V, TA = 25C, 6 pF f = 1 MHz 8 pF Max Unit 7.5 ns SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol -7 Parameter Description Min tPD Input, I/O, or Feedback to Combinatorial Output tS Setup Time from Input, I/O or Feedback to Clock tH 5.5 ns 6.5 ns 0 ns Register Data Hold Time tCO Clock to Output tWL Clock Width 5 tWH External Feedback fMAX D-Type T-Type Maximum Frequency Internal Feedback (fCNT) ns LOW 3 ns HIGH 3 ns D-Type 100 MHz T-Type 91 MHz D-Type 133 MHz T-Type 125 MHz 166.7 MHz 5.5 ns 0 ns No Feedback tSL Setup Time from Input, I/O, or Feedback to Gate tHL Latch Data Hold Time tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL 6 3 Input Register Clock Width tWICH fMAXIR Maximum Input Register Frequency ns ns 9.5 11 ns ns D-Type 9 ns T-Type 10 ns LOW 3 ns HIGH 3 ns 166.7 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2 ns tIGO Input Latch Gate to Combinatorial Output 12 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate MACH210A-7 (Com'l) 7.5 ns 11 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued) Parameter Symbol tIGS -7 Parameter Description Min Max Unit Input Latch Gate to Output Latch Setup 10 ns tWIGL Input Latch Gate Width LOW 3 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 11.5 ns tAR Asynchronous Reset to Registered or Latched Output 12 ns tARW Asynchronous Reset Width 8 ns tARR Asynchronous Reset Recovery Time 8 ns tAP Asynchronous Preset to Registered or Latched Output 12 ns tAPW Asynchronous Preset Width 8 ns tAPR Asynchronous Preset Recovery Time 8 ns tEA Input, I/O, or Feedback to Output Enable 7.5 ns tER Input, I/O, or Feedback to Output Disable 7.5 ns Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 12 MACH210A-7 (Com'l) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH IIL Input HIGH Leakage Current Input LOW Leakage Current VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5V, TA = 25C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V -30 135 0.8 V 10 -100 A A 10 A -100 A -160 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH210A-10/12 (Com'l) 13 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX -10 Min Max Parameter Description Maximum Frequency (Note 1) 12 1/(tS + tCO) tSL Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 7 ns T-Type 7.5 8 ns 0 5 5 6 6 ns ns D-Type 80 66.7 MHz T-Type 74 62.5 MHz D-Type 100 83.3 MHz T-Type 91 76.9 MHz 100 83.3 MHz 6.5 7 ns 0 0 ns Input Register Setup Time 2 2 Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup Input Register Clock Width fMAXIR Maximum Input Register Frequency 10 6 12 tSIR Input Register Hold Time ns LOW HIGH 5 tHIR ns 8 7 tICO ns 6.5 1/(tS + tH) tHL Unit D-Type 6 tWICL tWICH ns 14 2 ns ns 2 13 ns ns 15 ns D-Type 10 12 ns T-Type 11 13 ns LOW HIGH 5 5 6 6 ns ns 100 83.3 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2 2 ns tHIL Input Latch Hold Time 2 2 ns tIGO Input Latch Gate to Combinatorial Output 14 17 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 19 ns tSLL tIGS 14 10 0 Internal Feedback (fCNT) No Feedback -12 Min Max Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 8.5 9 ns Input Latch Gate to Output Latch Setup 11 13 ns MACH210A-10/12 (Com'l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -10 Min Max Parameter Symbol Parameter Description Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 16 ns Asynchronous Reset to Registered or Latched Output 25 16 ns tARW Asynchronous Reset Width (Note 1) 10 tARR Asynchronous Reset Recovery Time (Note 1) 10 tAP Asynchronous Preset to Registered or Latched Output 6 Unit tWIGL tAR 5 -12 Min Max ns 12 ns 8 15 ns 16 ns tAPW Asynchronous Preset Width (Note 1) 10 12 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 8 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 10 12 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 10 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Com'l) 15 ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . -40C to +85C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH IIL Input HIGH Leakage Current Input LOW Leakage Current VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5V, TA = 25C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V -30 135 0.8 V 10 -100 A A 10 A -100 A -160 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 16 MACH210A-12/14 (Ind) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX -12 Min Max Parameter Description Maximum Frequency (Note 1) 12 14.5 ns 8 8.5 ns T-Type 9 10 ns 0 7.5 1/(tS + tCO) Unit D-Type 0 Internal Feedback (fCNT) No Feedback -14 Min Max ns 10 ns LOW HIGH 6 6 7.5 7.5 ns ns D-Type 64 53 MHz T-Type 59 50 MHz D-Type 80 61.5 MHz T-Type 72.5 57 MHz 80 66.5 MHz 1/(tS + tH) tSL Setup Time from Input, I/O, or Feedback to Gate 8 8.5 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 8.5 6 Input Register Setup Time 2.5 3 tHIR Input Register Hold Time Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 7.5 14.5 tSIR tICO 12 ns 17 2.5 ns ns 3 16 ns ns 18 ns D-Type 12 14.5 ns T-Type 13 16 ns LOW HIGH 6 6 7.5 7.5 ns ns 80 66.5 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2.5 2.5 ns tHIL Input Latch Hold Time 3 3 ns tIGO Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL tIGS 17 20.5 ns 19.5 23 ns Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 10.5 11 ns Input Latch Gate to Output Latch Setup 13.5 16 ns MACH210A-12/14 (Ind) 17 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -12 Min Max Parameter Symbol Parameter Description Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 17 19.5 ns Asynchronous Reset to Registered or Latched Output 19.5 19.5 ns tARW Asynchronous Reset Width (Note 1) 12 tARR Asynchronous Reset Recovery Time (Note 1) 12 tAP Asynchronous Preset to Registered or Latched Output 7.5 Unit tWIGL tAR 6 -14 Min Max ns 14.5 ns 10 18 ns 19.5 ns tAPW Asynchronous Preset Width (Note 1) 12 14.5 ns tAPR Asynchronous Preset Recovery Time (Note 1) 12 10 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 14.5 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 14.5 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 18 MACH210A-12/14 (Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL -10 A 10 A -10 A -160 mA 2.4 Unit V 0.5 2.0 V V Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -30 ICC Supply Current (Typical) VCC = 5V, TA = 25C, f = 25 MHz (Note 4) 120 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH210-12/15/20 (Com'l) 19 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width Maximum Frequency (Note 1) 1/(tS + tCO) 15 20 Unit ns 10 13 ns T-type 8 11 14 ns 0 0 0 ns 6 6 10 6 6 12 8 8 ns ns ns D-type 66.7 50 40 MHz T-type 62.5 47.6 38.5 MHz D-type 83.3 66.6 50 MHz T-type 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate 7 10 13 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 10 6 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 11 6 14 12 8 17 15 22 18 ns ns 23 ns ns D-type 12 15 20 ns T-type 13 16 21 ns LOW HIGH 6 6 6 6 8 8 ns ns 83.3 83.3 62.5 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 9 12 15 ns Input Latch Gate to Output Latch Setup 13 16 21 ns tIGS 20 12 -20 Min Max 7 8 Internal Feedback (fCNT) No Feedback -15 Min Max D-type LOW HIGH External Feedback fMAX -12 Min Max Parameter Description MACH210-12/15/20 (Com'l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -12 Min Max Parameter Symbol Parameter Description tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches tAR 6 -15 Min Max 6 16 Asynchronous Reset to Registered or Latched Output -20 Min Max 8 19 16 ns 24 20 Unit 25 ns ns tARW Asynchronous Reset Width (Note 1) 12 15 20 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 16 20 25 ns tAPW Asynchronous Preset Width (Note 1) 12 tAPR Asynchronous Preset Recovery Time (Note 1) 8 tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns 15 20 10 ns 15 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210-12/15/20 (Com'l) 21 ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Ambient Temperature With Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL -10 A 10 A -10 A -160 mA Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5 V, TA = 25C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V -30 120 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 22 MACH210-14/18/24 (Ind) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX -14 Min Max Parameter Description Maximum Frequency (Note 1) 14.5 18 Setup Time from Input, I/O, or Feedback to Gate ns T-type 10 13.5 17 ns 0 10 10 ns ns D-type 53 40 32 MHz T-type 50 38 30.5 MHz D-type 61.5 53 38 MHz T-type 57 44 34.5 MHz 66.5 66.5 50 MHz 8.5 12 16 ns 0 tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2.5 3 0 12 7.5 tICS Input Register Clock to Output Register Setup tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency ns 7.5 7.5 Gate to Output (Note 3) Input Register Clock to Combinatorial Output ns 14.5 7.5 7.5 Latch Data Hold Time Input Register Hold Time 0 12 LOW HIGH tHL tHIR ns 16 tGO tICO Unit 12 1/(tWL + tWH) tSL 24 8.5 10 1/(tS + tCO) -24 Min Max D-type 0 Internal Feedback (fCNT) No Feedback -18 Min Max 0 13.5 7.5 17 10 20.5 2.5 ns ns 4 22 ns ns 26.5 2.5 3.5 18 ns 14.5 ns 28 ns D-type 14.5 18 24 ns T-type 16 19.5 25.5 ns LOW HIGH 7.5 7.5 7.5 7.5 10 10 ns ns 66.5 66.5 50 MHz 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2.5 2.5 2.5 ns tHIL Input Latch Hold Time 3 3.5 4 ns tIGO Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 11 14.5 18 ns tIGS Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches MACH210-14/18/24 (Ind) 20.5 24 30 ns 23 26.5 32.5 ns 19.5 23 29 ns 23 SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) -14 Min Max Parameter Symbol Parameter Description tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) tARR Asynchronous Reset Recovery Time (Note 1) tAP Asynchronous Preset to Registered or Latched Output -18 Min Max 19.5 -24 Min Max 24 30 Unit ns 14.5 18 24 ns 10 12 18 ns 19.5 24 30 ns tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 24 MACH210-14/18/24 (Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -160 mA ICC Supply Current (Typical) VCC = 5 V, TA = 25C, f = 25 MHz (Note 4) V 0.5 2.0 V V -30 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH210AQ-12 (Com'l) 25 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD -12 Parameter Description Min Input, I/O, or Feedback to Combinatorial Output tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output tWL tWH Clock Width fMAX 12 Internal Feedback (fCNT) ns 12 ns T-type 13 ns 0 ns ns LOW HIGH 6 6 ns ns D-type 55.6 MHz T-type 52.6 MHz D-type 83.3 MHz T-type 76.9 MHz 83.3 MHz No Feedback 26 Unit D-type 6 External Feedback Maximum Frequency (Note 1) Max tSL Setup Time from Input, I/O, or Feedback to Gate 12 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2.5 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 7 6 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency ns ns 14 17 ns ns D-type 15 ns T-type 16 ns LOW HIGH 6 6 ns ns 83.3 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2.5 ns tIGO Input Latch Gate to Combinatorial Output 19 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 20 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 13 ns tIGS Input Latch Gate to Output Latch Setup 16 ns MACH210AQ-12 (Com'l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol -12 Parameter Description Min tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Max 6 Unit ns 18 24 ns tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) 19 ns tARR Asynchronous Reset Recovery Time (Note 1) 19 ns 24 ns tAP Asynchronous Preset to Registered or Latched Output tAPW Asynchronous Preset Width (Note 1) 19 ns ns tAPR Asynchronous Preset Recovery Time (Note 1) 19 ns tEA Input, I/O, or Feedback to Output Enable 12 ns tER Input, I/O, or Feedback to Output Disable 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Com'l) 27 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH IIL Input HIGH Leakage Current Input LOW Leakage Current VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5V, TA = 25C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V -30 45 0.8 V 10 -100 A A 10 A -100 A -160 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 28 MACH210AQ-15/20 (Com'l) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX -15 Min Max Parameter Description Maximum Frequency (Note 1) 15 20 1/(tS + tH) ns 13 17 ns T-type 14 18 ns 0 7 1/(tS + tCO) Unit D-type 0 Internal Feedback (fCNT) No Feedback -20 Min Max ns 8 ns LOW HIGH 6 6 8 8 ns ns D-type 50 40 MHz T-type 47.6 38.4 MHz D-type 58.8 45.4 MHz T-type 55.5 43.4 MHz D-type 76.9 58.8 MHz T-type 71.4 55.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 13 17 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 8 6 8 8 17 ns ns 22 ns tSIR Input Register Setup Time 2 2 ns tHIR Input Register Hold Time 2.5 3 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 18 23 ns D-type 17 22 ns T-type 18 23 ns LOW HIGH 6 6 8 8 ns ns 83.3 62.5 MHz 2 ns 1/(tWICL + tWICH) tSIL Input Latch Setup Time 2 2.5 tHIL Input Latch Hold Time tIGO Input Latch Gate to Combinatorial Output 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 22 27 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 15 19 ns Input Latch Gate to Output Latch Setup 18 23 ns tIGS MACH210AQ-15/20 (Com'l) 3 ns 29 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -15 Min Max Parameter Symbol Parameter Description Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 19 24 ns Asynchronous Reset to Registered or Latched Output 25 30 ns tARW Asynchronous Reset Width (Note 1) 20 tARR Asynchronous Reset Recovery Time (Note 1) 20 tAP Asynchronous Preset to Registered or Latched Output 8 Unit tWIGL tAR 6 -20 Min Max ns 25 ns 25 25 ns 30 ns tAPW Asynchronous Preset Width (Note 1) 20 25 ns tAPR Asynchronous Preset Recovery Time (Note 1) 20 25 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 30 MACH210AQ-15/20 (Com'l) ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Ambient Temperature With Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . -0.5 V to VCC+ 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . . . . . . . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC Supply Current (Typical) VCC = 5 V, TA = 25C, f = 25 MHz (Note 4) Typ Max Unit V 0.5 2.0 V V 0.8 -30 45 V 10 A -100 A 10 A -100 A -160 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH210AQ-18/24 (Ind) 31 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25C, 6 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width Maximum Frequency (Note 1) 24 1/(tS + tCO) 1/(tS + tH) Unit ns D-type 16 20.5 ns T-type 17 22 ns 0 0 ns 8.5 Internal Feedback (fCNT) No Feedback -24 Min Max 18 LOW HIGH External Feedback fMAX -18 Min Max Parameter Description 7.5 7.5 10 10 10 ns ns ns D-type 40 32 MHz T-type 38 30.5 MHz D-type 47 36 MHz T-type 44 34.5 MHz D-type 61.5 47 MHz T-type 57 47 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 16 20.5 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW 10 tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2.5 2.5 ns tHIR Input Register Hold Time 3.5 4 ns 7.5 tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 20.5 ns T-type 22 28 ns LOW HIGH 7.5 7.5 10 10 ns ns 66.5 50 MHz 2.5 ns 2.5 3.5 Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate ns 26.5 Input Latch Setup Time Input Latch Hold Time 28 ns 20.5 tSIL tHIL 26.5 22 ns ns D-type 1/(tWICL + tWICH) tIGO 10 10 4 ns 24 30 ns 26.5 32.5 ns 18 23 ns tIGS Input Latch Gate to Output Latch Setup 22 28 ns tWIGL Input Latch Gate Width LOW 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 32 MACH210AQ-18/24 (Ind) 23 29 ns SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) -18 Min Max Parameter Symbol Parameter Description tAR Asynchronous Reset to Registered or Latched Output -24 Min Max 30 36 Unit ns tARW Asynchronous Reset Width (Note 1) 24 30 ns tARR Asynchronous Reset Recovery Time (Note 1) 24 30 ns tAP Asynchronous Preset to Registered or Latched Output 30 36 ns tAPW Asynchronous Preset Width (Note 1) 24 30 ns tAPR Asynchronous Preset Recovery Time (Note 1) 24 30 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210AQ-18/24 (Ind) 33 TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25C IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 .2 .4 .6 .8 1.0 -40 -60 -80 14128I-5 Output, LOW IOH (mA) 25 1 2 3 4 5 VOH (V) -3 -2 -1 -25 -50 -75 -100 -125 -150 14128I-6 Output, HIGH II (mA) 20 VI (V) -2 -1 -20 1 2 3 4 5 -40 -60 -80 -100 14128I-7 Input 34 MACH210-7/10/12/15/20, Q-12/15/20 TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C MACH210A 150 MACH210 125 100 75 ICC (mA) MACH210AQ 50 25 0 0 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) 14128I-8 The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210-7/10/12/15/20, Q-12/15/20 35 TYPICAL THERMAL CHARACTERISTICS Measured at 25C ambient. These parameters are not tested. Parameter Symbol Typ Parameter Description jc Thermal impedance, junction to case ja Thermal impedance, junction to ambient jma Thermal impedance, junction to ambient with air flow TQFP PLCC Unit 11.3 15 C/W 41 40 C/W 200 lfpm air 35 36 C/W 400 lfpm air 33.7 33 C/W 600 lfpm air 32.6 31 C/W 800 lfpm air 32 29 C/W Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 36 MACH210-7/10/12/15/20, Q-12/15/20 SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 14128I-9 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS VT tH tSL Gate VT Clock tHL tCO Registered Output VT tPDL tGO Latched Out VT VT 14128I-11 14128I-10 Registered Output Latched Output (MACH 2, 3, and 4) tWH Clock Gate VT tGWS tWL 14128I-13 14128I-12 Clock Width Gate Width (MACH 2, 3, and 4) Registered Input VT tSIR Input Register Clock Registered Input VT tHIR Input Register Clock VT tICO Combinatorial Output VT 14128I-14 Registered Input (MACH 2 and 4) VT tICS Output Register Clock VT 14128I-15 Input Register to Output Register Setup (MACH 2 and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical. MACH210-7/10/12/15/20, Q-12/15/20 37 SWITCHING WAVEFORMS Latched In VT tSIL tHIL Gate VT tIGO Combinatorial Output VT 14128I-16 Latched Input (MACH 2 and 4) tPDLL Latched In VT Latched Out Input Latch Gate VT tIGOL tSLL tIGS VT Output Latch Gate 14128I-17 Latched Input and Output (MACH 2, 3, and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical. 38 MACH210-7/10/12/15/20, Q-12/15/20 SWITCHING WAVEFORMS tWICH Clock Input Latch Gate VT VT tWICL tWIGL 14128I-19 14128I-18 Input Register Clock Width (MACH 2 and 4) Input Latch Gate Width (MACH 2 and 4) tARW tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAR Registered Output tAP Registered Output VT VT tARR Clock tAPR Clock VT VT 14128I-20 14128I-21 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH - 0.5V VOL + 0.5V VT 14128I-22 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical. MACH210-7/10/12/15/20, Q-12/15/20 39 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 14128I-23 Commercial Specification tPD, tCO tEA tER CL S1 R1 R2 Closed Measured Output Value 1.5 V Z H: Open Z L: Closed 35 pF H Z: Open L Z: Closed 5 pF 1.5 V 300 390 H Z: VOH - 0.5 V L Z: VOL + 0.5 V *Switching several outputs simultaneously should be avoided for accurate measurement. 40 MACH210-7/10/12/15/20, Q-12/15/20 fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC LOGIC REGISTER tS t CO tS fMAX Internal (fCNT) fMAX External; 1/(tS + tCO) LOGIC REGISTER CLK CLK REGISTER REGISTER tS tSIR fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL) LOGIC tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 14128I-24 MACH210-7/10/12/15/20, Q-12/15/20 41 ENDURANCE CHARACTERISTICS The MACH families are manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol tDR N 42 Parameter Description Min Units Test Conditions 10 Years Max Storage Temperature Min Pattern Data Retention Time 20 Years Max Operating Temperature Max Reprogramming Cycles 100 Cycles Normal Programming Conditions MACH210-7/10/12/15/20, Q-12/15/20 INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC 100 k 1 k VCC ESD Protection Input VCC VCC 100 k 1 k Preload Circuitry Feedback Input 14128I-25 I/O MACH210-7/10/12/15/20, Q-12/15/20 43 POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the Parameter Symbol wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 s tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC Power 4V tPR Registered Output tS Clock tWL 14128I-26 Power-Up Reset Waveform 44 MACH210-7/10/12/15/20, Q-12/15/20 USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. Preloaded HIGH D In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. Q1 Q AR Preloaded HIGH The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. D Q2 Q AR While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. On Preload Mode Off Q1 AR Q2 Figure 2. Preload/Reset Conflict 14128I-27 Set All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. Reset Figure 3. Combinatorial Latch 14128I-28 MACH210-7/10/12/15/20, Q-12/15/20 45 PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 .042 .056 .062 .083 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF TOP VIEW 50 .009 .015 .090 .120 .165 .180 SEATING PLANE SIDE VIEW MACH210-7/10/12/15/20, Q-12/15/20 16-038-SQ PL 044 DA78 6-28-94 ae PHYSICAL DIMENSIONS* PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters) 44 1 11.80 12.20 9.80 10.20 9.80 10.20 11.80 12.20 11 - 13 0.95 1.05 1.20 MAX 1.00 REF. 0.30 0.45 0.80 BSC 11 - 13 16-038-PQT-2_AH PQT 44 5-4-95 ae *For reference only. BSC is an ANSI standard for Basic Space Centering. MACH210-7/10/12/15/20, Q-12/15/20 51