Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 8
1Publication Order Number:
MC10H141/D
MC10H141
Four−Bit Universal Shift
Register
Description
The MC10H141 is a four−bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K part with
100% improvement in propagation delay and operation frequency and
no increase in power supply current.
Features
•Shift frequency, 250 MHz Min
•Power Dissipation, 425 mW Typical
•Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
•Voltage Compensated
•MECL 10K Compatible
•Pb−Free Packages are Available*
L
HQ2
n32n
H
Parallel Entry
Stop Shift Q0n
Figure 1. Pin Assignment
VCC1
Q2
Q3
C
DR
D3
S2
VEE
VCC2
Q1
Q0
DL
D0
D1
S1
D2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Table 1. TRUTH TABLE
SELECT OPERATING
MODE
OUTPUTS
S1 S2 Q1n + 1Q2n + 1Q3n + 1
LL
* Outputs as exist after pulse appears at “C” input with
input conditions as shown (Pulse Positive transition of
clock input).
D0 D1 D2 D3
H Shift Right* Q1nQ2nQ3nDR
H L Shift Left* DL Q0nQ1nQ2n
Q1n
Q0n + 1
Pin assignment is for Dual−in−Line Package.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
CDIP−16
L SUFFIX
CASE 620A
MARKING DIAGRAMS*
PDIP−16
P SUFFIX
CASE 648
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
16
1
16
1
MC10H141P
AWLYYWWG
1
16
MC10H141L
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
PLLC−20
FN SUFFIX
CASE 775
20 110H141G
AWLYYWW
120
MC10H141
http://onsemi.com
2
Table 2. MAXIMUM RATINGS
Symbol Characteristic Rating Unit
VEE Power Supply (VCC = 0) −8.0 to 0 Vdc
VIInput Voltage (VCC = 0) 0 to VEE Vdc
Iout Output Current − Continuous
− Surge
50
100
mA
TAOperating Temperature Range 0 to +75 °C
Tstg Storage Temperature Range − Plastic
− Ceramic
−55 to +150
−55 to +165
°C
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 3. ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5% (Note 1)
0°25°75°
Symbol Characteristic Min Max Min Max Min Max Unit
IEPower Supply Current −112 −102 −112 mA
IinH Input Current High
Pins 5,6,9,11,12,13
Pins 7,10
Pin 4
−
−
−
405
416
510
−
−
−
255
260
320
−
−
−
255
260
320
mA
IinL Input Current Low 0.5 −0.5 −0.3 −mA
VOH High Output Voltage −1.02 −0.84 −0.98 −0.81 −0.92 −0.735 Vdc
VOL Low Output Voltage −1.95 −1.63 −1.95 −1.63 −1.95 −1.60 Vdc
VIH High Input Voltage −1.17 −0.84 −1.13 −0.81 −1.07 −0.735 Vdc
VIL Low Input Voltage −1.95 −1.48 −1.95 −1.48 −1.95 −1.45 Vdc
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained. Outputs are terminated through a 50 W resistor to −2.0 V.
Table 4. AC PARAMETERS
tpd Propagation Delay 1.0 2.0 1.0 2.0 1.1 2.1 ns
thold Hold Time −
Data, Select
1.0 −1.0 −1.0 −ns
tset Set−up Time
Data
Select
1.5
3.0
−
−
1.5
3.0
−
−
1.5
3.0
−
−
ns
trRise Time 0.5 2.4 0.5 2.4 0.5 2.4 ns
tfFall Time 0.5 2.4 0.5 2.4 0.5 2.4 ns
fshift Shift Frequency 250 −250 −250 −MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
MC10H141
http://onsemi.com
3
LOGIC DIAGRAM
PARALLEL ENTER
SHIFT RIGHT
SHIFT LEFT
HOLD
DQ
C
1 OF 4
DECODER
D3
DL
S1
DR
C
Q3
VCC1 = PIN 1
SCC2 = PIN 16
V
EE = PIN 8
S2
D2 D1 D0
Q2 Q1 Q0
DQ
C
DQ
C
DQ
C
APPLICATION INFORMATION
The MC10H141 is a four−bit universal shift register
which performs shift left, or shift right, serial/parallel in, and
serial/parallel out operations with no external gating. Inputs
S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip−flops shift
information on the positive edge of the clock. The four
operations are stop shift, shift left, shift right, and parallel
entry of data. The other six inputs are all data type inputs;
four for parallel entry data, and one for shifting in from the
left (DL) and one for shifting in from the right (DR).
ORDERING INFORMATION
Device Package Shipping†
MC10H141FN PLLC−20 46 Units / Rail
MC10H141FNG PLLC−20
(Pb−Free)
46 Units / Rail
MC10H141FNR2 PLLC−20 500 / Tape & Reel
MC10H141FNR2G PLLC−20
(Pb−Free)
500 / Tape & Reel
MC10H141L CDIP−16 25 Unit / Rail
MC10H141P PDIP−16 25 Unit / Rail
MC10H141PG PDIP−16
(Pb−Free)
25 Unit / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC10H141
http://onsemi.com
4
PACKAGE DIMENSIONS
−M−
−N−
−L−
Y BRK
W
V
D
D
S
L−M
M
0.007 (0.180) N S
T
S
L−M
M
0.007 (0.180) N S
T
S
L−M
S
0.010 (0.250) N S
T
XG1
B
U
Z
VIEW D−D
20 1
S
L−M
M
0.007 (0.180) N S
T
S
L−M
M
0.007 (0.180) N S
T
S
L−M
S
0.010 (0.250) N S
T
C
G
VIEW S
E
J
R
Z
A
0.004 (0.100)
−T−SEATING
PLANE
S
L−M
M
0.007 (0.180) N S
T
S
L−M
M
0.007 (0.180) N S
T
H
VIEW S
K
K1
F
G1
20 LEAD PLLC
CASE 775−02
ISSUE E
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M,
1982.
2. DIMENSIONS IN INCHES.
3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM −T−, SEATING PLANE.
5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER
THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.385 0.395 9.78 10.03
B0.385 0.395 9.78 10.03
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.019 0.33 0.48
G0.050 BSC 1.27 BSC
H0.026 0.032 0.66 0.81
J0.020 −−− 0.51 −−−
K0.025 −−− 0.64 −−−
R0.350 0.356 8.89 9.04
U0.350 0.356 8.89 9.04
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y−−− 0.020 −−− 0.50
Z2 10 2 10
G1 0.310 0.330 7.88 8.38
K1 0.040 −−− 1.02 −−−
____
MC10H141
http://onsemi.com
5
PACKAGE DIMENSIONS
CDIP−16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620A−01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
5 THIS DRAWING REPLACES OBSOLETE
CASE OUTLINE 620−10.
F
E
N
K
C
SEATING
PLANE
A
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.750 0.785 19.05 19.93
B0.240 0.295 6.10 7.49
C−−− 0.200 −−− 5.08
D0.015 0.020 0.39 0.50
E0.050 BSC 1.27 BSC
F0.055 0.065 1.40 1.65
G0.100 BSC 2.54 BSC
H0.008 0.015 0.21 0.38
K0.125 0.170 3.18 4.31
L0.300 BSC 7.62 BSC
M0 15 0 15
N0.020 0.040 0.51 1.01
____
A
B
A
B
16
1
9
8
G
16X D
B
M
0.25 (0.010) T
T
16X J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
MC10H141
http://onsemi.com
6
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
MC10H141/D
MECL 10H and MECL 10K are trademarks of Motorola, Inc.
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
