Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 LP8728-Q1 Quad-Output Step-Down DC/DC Converter 1 Features 3 Description * The LP8728-Q1 is a quad-output Power Management Unit (PMU), optimized for low-power FPGAs, microprocessors, and DSPs for automotive applications. This device integrates four highly efficient step-down DC/DC converters into one package. Each converter has high current capability and separate controls which allows flexibility to use the device in multiple applications. All the converters operate above the AM band with a fixed 3.2-MHz switching frequency. Each buck converter's high-side switch turnon time is phase shifted to minimize input current spikes. 1 * * * * * * LP8728-Q1 is an Automotive Grade Product that is AECQ-100 Grade 1 Qualified Four High Efficiency Step-Down DC/DC Converters: - 93% Peak Efficiency (VIN = 5 V, VOUT 3.3 V) - Max Output Current 1 A - Forced PWM Operation - Soft-Start Control - VOUT1 = 3.3 V - VOUT2 = 1.25 V - VOUT3 = 1.8 V or 2.65 V (pin selectable) - VOUT4 = 1.8 V Separate Enable Inputs for each Converter Control Separate Power Good Outputs for each Converter Output Overcurrent and Input Overvoltage Protection Overtemperature Protection Undervoltage Lockout (UVLO) 2 Applications * * * * * The protection features include output short-circuit protection, switch current limits, input overvoltage protection, input undervoltage lockout, and thermal shutdown functions. During start-up, the device controls the output slew rate to minimize output voltage overshoot and the input inrush current. Device Information(1) PART NUMBER LP8728-Q1 PACKAGE BODY SIZE (NOM) WQFN (28) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space FPGA, DSP Core Power Processor Power for Mobile Devices Peripheral I/O Power Automotive Safety Cameras Automotive Infotainment space space space space space Simplified Schematic VIN Efficiency VIN 10 F VIN_B1 AVDD 1 F 100 1.5 H VIN 10 F VIN_B2 VDDIO 1.5 H VOUT2 10 F SW_B2 FB_B2 LP8728 PG_B1 PG_B3 Micro Controller VIN 10 F VIN_B3 PG_B2 1.5 H PG_B4 SW_B3 EN_B1 FB_B3 VOUT3 10 F VIN_B4 VIN EN_B2 EN_B3 10 F GND_B3 GND_B4 GND_B2 AGND DEFSEL GND_B1 EN_B4 1.5 H SW_B4 FB_B4 VOUT4 80 EFFICIENCY (%) FB_B1 1 F 90 VOUT1 10 F SW_B1 BYP 70 60 50 40 3.3V 30 2.65V 20 1.8V 10 1.25V 0 0 100 200 300 400 500 600 700 OUTPUT CURRENT (mA) 800 900 1000 C000 10 F 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 5 6 7 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... System Characteristics ............................................. Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Example .................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 Device Support .................................................... Related Documentation......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2014) to Revision B Page * Changed simplified schematic circuit drawing to correct pin placements for SW_B3 and SW_B4 ...................................... 1 * Added ESD Ratings table to replace Handling Ratings ......................................................................................................... 5 * Changed typical application circuit drawing to correct pin placements for SW_B3 and SW_B4 ........................................ 15 Changes from Original (August 2013) to Revision A * 2 Page Added Device Information and Handling Ratings tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout , Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section. ............. 1 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 5 Pin Configuration and Functions WQFN (RSG) Package 28 Pins VIN_B2 SW_B2 GND_B2 GND_B1 SW_B1 VIN_B1 EN_B1 TOP VIEW 7 6 5 4 3 2 1 PIN 1 ID FB_B2 8 28 FB_B1 EN_B2 9 27 PG_B1 PG_B2 10 26 AVDD DEFSEL 11 25 BYP PG_B3 12 24 AGND EN_B3 13 23 PG_B4 FB_B3 14 22 FB_B4 18 19 20 21 SW_B4 VIN_B4 EN_B4 SW_B3 17 GND_B4 16 GND_B3 15 VIN_B3 DAP Pin Functions PIN NUMBER NAME TYPE DESCRIPTION 1 EN_B1 D/I 2 VIN_B1 P Enable Buck 1 Positive power supply input for Buck 1 3 SW_B1 P Switch node for Buck 1 4 GND_B1 G Power ground for Buck 1 5 GND_B2 G Power ground for Buck 2 6 SW_B2 P Switch node for Buck 2 7 VIN_B2 P Positive power supply input for Buck 2 Feedback pin for Buck 2. Referenced against AGND. 8 FB_B2 A 9 EN_B2 D/I Enable Buck 2 10 PG_B2 D/O Open-drain Power Good output for Buck 2 11 DEFSEL D/I Buck 3 output voltage selection pin 12 PG_B3 D/O Open-drain Power Good output for Buck 3 13 EN_B3 D/I Enable buck 3 14 FB_B3 A Feedback pin for Buck 3. Referenced against AGND. 15 VIN_B3 P Positive power supply input for Buck 3 16 SW_B3 P Switch node for Buck 3 17 GND_B3 G Power ground for Buck 3 18 GND_B4 G Power ground for Buck 4 19 SW_B4 P Switch node for Buck 4 20 VIN_B4 P Positive power supply input for Buck 4 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 3 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Pin Functions (continued) PIN 4 TYPE DESCRIPTION NUMBER NAME 21 EN_B4 D/I 22 FB_B4 A 23 PG_B4 D/O 24 AGND G Analog ground 25 BYP A Internal 1.8-V supply voltage capacitor pin. A ceramic low ESR 1-F capacitor should be connected from this pin to AGND. The BYP voltage is generated internally, do not supply or load this pin externally. Analog positive power supply pin (VIN level) 26 AVDD P 27 PG_B1 D/O 28 FB_B1 A DAP Die Attachment Pad Enable Buck 4 Feedback pin for Buck 4. Referenced against AGND. Open-drain Power Good output for Buck 4 Open-drain Power Good output for Buck 1 Feedback pin for Buck 1. Referenced against AGND. Exposed die attachment pad should to be connected to GND plane with thermal vias to improve the thermal performance of the system. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VIN Voltage on power pins (AVDD, VIN_Bx) VFB Voltage on feedback pins (FB_Bx) (1) MIN MAX -0.3 6 -0.3 6 UNIT VSW Voltage on buck converter switch pins (SW_Bx) (GND_Bx - 0.2 V) to (VIN_Bx + 0.2 V) with 6 V max VDIG Voltage on digital pins (PG_Bx, EN_Bx, DEFSEL) (AGND - 0.2V) to (AVDD + 0.2 V) with 6 V max VBYP Voltage on BYP pin TJ(MAX) Maximum operating junction temperature (2) -0.3 2 Maximum lead temperature (Soldering) Tstg (1) (2) (3) See Storage temperature V 150 C 150 C (3) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150C (typ.) and disengages at TJ = 130C (typ.). For detailed soldering specifications and information, please refer to Texas Instruments Application Note Leadless Leadframe Package (LLP) SNOA401. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 2000 Charged-device model (CDM), per AEC Q100-011 750 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN (1) Input voltage on AVDD, VIN_B1, VIN_B2, VIN_B3 and VIN_B4 Pins (2) TA Operating ambient temperature COUT Effective output capacitance during operation. Min value over TA -40C to 125C. CIN Effective input capacitance during operation. 4.5 V VIN_Bx 5.5 V. Min value over TA -40C to 125C. L Effective inductance during operation Min value over TA -40C to 125C. (1) (2) MIN NOM MAX 4.5 5 5.5 V 125 C -40 5 10 2.5 10 0.47 1.5 UNIT 12 F 2 All voltage values are with respect to network ground terminal. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (RJA), as given by the following equation: TA(max) = TJ(max) - (RJA x PD(max)) 6.4 Thermal Information LP8728-Q1 THERMAL METRIC (1) WQFN (RSG) UNIT 28 PINS RJA (1) (2) Junction-to-ambient thermal resistance (2) 36.3 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Calculated using 4-layer standard JEDEC thermal test board with 5 thermal vias between the die attach pad in the first copper layer and second copper layer. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 5 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com 6.5 Electrical Characteristics (1) (2) Unless otherwise noted, VIN = 5 V, typical values apply for TA = 25C, and minimum/maximum limits apply over junction temperature range, TJ = -40C to 125C. PARAMETER TEST CONDITIONS ISHDN Shutdown supply current into power connections EN_Bx = 0 V IOP Operating current All buck-converters active, IOUT = 0 mA MIN TYP MAX 1 6 20 UNIT A mA LOGIC INPUTS (EN_Bx, DEFSEL) VIL Input low level 0.4 V VIH Input high level 1.6 RPD_DI EN_Bx and DEFSEL internal pulldown resistance 300 TH_MIN Minimum EN_Bx high time 1 ms TL_MIN Minimum EN_Bx low time 10 s V 520 820 k LOGIC OUTPUTS (PG_Bx) VOL Output low level RPU Recommended pull-up resistor ISINK = 3 mA 0.4 V 10 k BUCK CONVERTERS VOUT1 Output voltage for Buck 1 Fixed voltage 3.3 V VOUT2 Output voltage for Buck 2 Fixed voltage 1.25 V DEFSEL = 1 2.65 DEFSEL = 0 1.8 VOUT3 Output voltage for Buck 3 VOUT4 Output voltage for Buck 4 VFB_Bx Output voltage accuracy Fixed voltage V 1.8 -3% V 3% Line regulation 4.5 V VIN_Bx 5.5 V ILOAD = 10 mA 3 mV Load regulation VIN = 5 V 100 mA ILOAD 900 mA 3 mV IOUT Output current DC load TA = 25C. FSW Switching frequency GBW Gain bandwidth ILIMITP High side switch current limit ILIMITN Low side switch current limit Reverse current 500 RDSONP Pin-pin resistance for PFET IOUT = 200 mA 210 300 m RDSONN Pin-pin resistance for NFET IOUT = 200 mA 140 240 m ILK_SW Switch pin leakage current VOUT = 1.8V 1 A RPD_FB Pull-down resistor from FB_Bx pin to GND Only active when converter disabled. All limits apply for TA = 25C. 100 KRAMP Slew rate control DEFSEL from 0 to 1 TSTART Start-up time Time from first EN_Bx high to start of switching KSTART Soft-start VOUT slew rate VOUT 3.03 3.2 1200 1500 1000 mA 3.37 MHz 300 40 70 kHz 1800 mA mA 10 mV/s 420 s 18 mV/s VOLTAGE MONITORING VPG Power good threshold voltage VOVP (1) (2) 6 Input overvoltage protection trigger point Power good threshold for voltage rising 93.5% 96% 98% Power good threshold for voltage falling 91% 93% 95% 5.5 5.7 5.9 Voltage monitored on AVDD Pin, voltage rising Hysteresis 80 V mV All voltage values are with respect to network ground terminal. Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ = 25C. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 Electrical Characteristics(1)(2) (continued) Unless otherwise noted, VIN = 5 V, typical values apply for TA = 25C, and minimum/maximum limits apply over junction temperature range, TJ = -40C to 125C. PARAMETER TEST CONDITIONS Input undervoltage lockout (UVLO) turn-on threshold. VUVLO MIN TYP Voltage monitored on AVDD Pin, voltage falling MAX UNIT V 4.35 Hysteresis 80 mV THERMAL SHUTDOWN AND MONITORING TSD Threshold, temperature rising Thermal shutdown 150 Hysteresis C 20 6.6 System Characteristics (1) (2) (3) Typical values apply for TA = 25C. Unless otherwise noted, VIN = 5 V. PARAMETER TEST CONDITIONS (1) (2) (3) MAX UNIT 70 mV IOUT 90% max load 10% max load, 1s load step 70 mV Line transient response VIN_Bx stepping 4.5V 5.5V tr = tf = 10 s, IOUT = 400 mA 20 mV Output voltage ripple COUT ESR = 10 m, IOUT = 200 mA 10 mVPP VOUT TYP IOUT 10% max load 90% max load, 1s load step Load transient response VRIPPLE MIN Efficiency VOUT = 3.3 V, IOUT = 300 mA 94% VOUT = 2.65 V, IOUT = 300 mA 92% VOUT = 1.8 V, IOUT = 300 mA 89% VOUT = 1.2 V, IOUT = 300 mA 85% All voltage values are with respect to network ground terminal. Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ = 25C. System Characteristics are highly dependent on external components and PCB layout. System Characteristics are verified using inductor type: TOKO MDT2520-CN1R5M, input and output capacitor type: MuRata GRM21BR71A106KE51L. 6.7 Typical Characteristics 100 3280 90 3260 80 3240 70 3220 3200 60 fSW (Hz) EFFICIENCY (%) Unless otherwise noted, VIN = 5 V, TA = 25C 50 3180 3160 40 3.3V 30 2.65V 20 1.8V 3100 10 1.25V 3080 3140 3120 0 3060 0 100 200 300 400 500 600 700 800 OUTPUT CURRENT (mA) 900 1000 -60 Figure 1. Efficiency vs Output Current -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) C000 140 C012 Figure 2. Switching Frequency vs Temperature Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 7 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 3.33 3.33 3.32 3.32 3.31 3.31 VOUT1 (V) VOUT1 (V) Unless otherwise noted, VIN = 5 V, TA = 25C 3.30 3.29 3.28 3.29 +125C 3.28 +125C +25C +25C 3.27 3.30 3.27 -40C -40C 3.26 3.26 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IOUT1 (A) 4.4 4.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 1.26 1.26 1.25 1.25 VOUT2 (V) 1.27 1.24 1.23 5.6 C007 1.24 1.23 1.22 +125C +25C 1.21 +125C +25C 1.21 -40C -40C 1.20 1.20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IOUT2 (A) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 SUPPLY VOLTAGE (V) C008 Figure 5. Buck2 Load Regulation with 1.25-V Setting C009 Figure 6. Buck2 Line Regulation with 1.25-V Setting 5.0 25 + 125C 4.0 + 85C 3.5 + 25C 3.0 - 40C 24 SUPPLY CURRENT (mA) 4.5 ISHDN (A) 5.5 Figure 4. Buck1 Line Regulation 1.27 1.22 2.5 2.0 23 22 21 20 19 18 - 40C 17 + 25C 0.5 16 + 125C 0.0 15 1.5 1.0 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 SUPPLY VOLTAGE (V) 5.5 5.6 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 SUPPLY VOLTAGE (V) C010 Figure 7. Shutdown Current Consumption 8 5.4 SUPPLY VOLTAGE (V) Figure 3. Buck1 Load Regulation VOUT2 (V) 4.6 C006 5.3 5.4 5.5 5.6 C011 Figure 8. Active Mode Current Consumption (All Bucks Active) Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LP8728 has four integrated high-efficiency buck converters. Each buck converter has individual enable input and power good output pins. When the first enable pin is pulled high there is a 420-s start-up delay when the device wakes up from shutdown mode and all internal reference blocks are started up. Once reference blocks have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during start-up. Once a buck output reaches 96% (typ.) of the desired output voltage, the powergood pin is pulled high (see Figure 9). When at least one buck core is active, the remaining buck converters will start up without any start-up delay. If the output voltage drops below 93% (typ.) of desired voltage due to, for example, an overload condition, the corresponding power-good pin is pulled low. The power-good signal is always held low for at least 50 ms. When the enable pin is pulled low, the corresponding buck converter's power good signals are set low, and the buck converter is instantly shut down. An output capacitor is then discharged through an internal 70- (typ.) pull-down resistor. The pull-down resistor is connected between buck feedback pin and ground and is only active when the enable pin is set low. When all enable signals are pulled low, the LP8728-Q1 enters a low-current shutdown mode. 7.2 Functional Block Diagram VIN AVDD 1 F VIN_B1 VIN BYP 10 F LDO 1 F Buck1 (Active Pulldown) Oscillator FB_B1 SW_B1 1.5 H VOUT1 UVLO 10 F Reference Voltage VIN_B2 Thermal Shutdown VIN 10 F OTP Buck2 (Active Pulldown) PG_B1 FB_B2 SW_B2 1.5 H VOUT2 10 F PG_B2 PG_B3 VIN_B3 VIN 10 F PG_B4 Buck3 (Active Pulldown) DEFSEL Control Logic FB_B3 SW_B3 EN_B1 1.5 H VOUT3 10 F EN_B2 VIN_B4 EN_B3 VIN 10 F Buck4 (Active Pulldown) EN_B4 FB_B4 SW_B4 1.5 H VOUT4 GND_B4 GND_B3 GND_B2 GND_B1 AGND 10 F Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 9 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com 7.3 Feature Description 7.3.1 Buck Information The buck converters are operated in forced PWM mode. Even with light load a minimum switching pulse is generated with every switching cycle. Each buck converter's high-side switch turn-on time is phase shifted to minimize the input current ripple (see Figure 20). 7.3.1.1 Features The following features are supported for all converters: * * * * * * Synchronous rectification Current mode feedback loop with PI compensator Forced PWM operation Soft start Power-good output Overvoltage comparator In addition to the aforementioned features, buck3 output voltage can be selected with the DEFSEL pin. If the DEFSEL pin is pulled low, VOUT3 is set to 1.8 V. If DEFSEL is pulled high, VOUT3 is set to 2.65 V. 96% 93% Active pulldown VOUTx Overload condition 5% EN_Bx PG_Bx TSTART 50ms TRAMP Figure 9. Buck Converter Start-up And Shutdown 7.3.2 Thermal Shutdown (TSD) Thermal shutdown function shuts down all buck regulators if the device's junction temperature TJ rises above 150C (typ.). All power-good signals are pulled low 5 ms before buck regulators are shut down. Once TJ falls below 130C (typical), the LP8728 will automatically start up the buck regulators. There is a 2-second safety delay included in the restart function. Buck regulators are not restarted until 2 seconds have elapsed after TJ falls below 130C (typical). To minimize the inrush current during restarting, regulators are started in a buck1 buck2 buck3 buck4 sequence. A 500-s delay is included between each buck start-up. 150C Junction Temperature TJ 130C TSD (Internal Signal) PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 2s 500us 500us 500us Figure 10. TSD Timing Diagram 10 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 Feature Description (continued) 7.3.3 Undervoltage Lockout (UVLO) Undervoltage lockout pulls the PG_Bx pins low if the input voltage drops below 4.35 V (typical) (Figure 11). PG_Bx pins are always held low for at least 50 ms. Once an undervoltage condition has lasted for 5 ms, all buck converters are shut down. Buck converters are restarted once the input voltage rises above UVLO level. If an undervoltage condition has lasted more than 5 ms, but less than 50 ms, PG_Bx pins are released high once 50 ms has elapsed and corresponding output voltage has settled. If an overvoltage condition has lasted more than 50 ms, power-good signals are released high once corresponding output voltage has settled. If an undervoltage condition lasts less than 5 ms, the buck converters are not shut down. Even in this case PG_Bx pins are held low for 50 ms. Regulators are always restarted in a buck1 buck2 buck3 buck4 sequence. A 500-s delay is included between each buck start-up. 5.0V VIN 4.35V UVLO PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms Figure 11. UVLO Operation 7.3.4 Overvoltage Protection (OVP) Overvoltage protection protects the device in case of an overvoltage condition. If input voltage exceeds 5.7 V (typical), all PG_Bx pins are pulled low. PG_Bx pins are always held low for at least 50 ms. Once the PG_Bx pins are pulled low, the system has 5 ms time to power down. After over-voltage condition has lasted for 5 ms, all buck converters are shut down. Buck converters are restarted once input voltage falls below 5.62 V (typical). Regulators are started in a buck1 buck2 buck3 buck4 sequence. A 500-s delay is included between each buck start-up. If an overvoltage condition lasted more than 5 ms, but less than 50 ms, the PG_Bx pins are released high once 50 ms has elapsed and corresponding output voltage has settled (Figure 12). Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 11 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Feature Description (continued) VIN 5.7V OVP PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 500s 500s 500s 50 ms Figure 12. OVP Duration Less Than 50 ms If an overvoltage condition has lasted more than 50 ms, power-good signals are released high once corresponding output voltage has settled. Regulators are started in a buck1 buck2 buck3 buck4 sequence. A 500-s delay is included between each buck start-up (Figure 13). If an overvoltage condition has lasted less than 5 ms, buck converters are not shut down. Even in this case the PG_Bx pins are held low for 50 ms. NOTE Since regulators are allowed to operate for 5 ms during overvoltage condition it is the system designer's responsibility to verify that input voltage doesn't exceed limits stated in Absolute Maximum Ratings. Exceeding these limits may cause permanent damage to the device. VIN 5.7V OVP PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 50 ms 500s 500s 500s Figure 13. OVP Duration More Than 50 ms 12 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 7.4 Device Functional Modes 7.4.1 Shutdown Mode When all EN_Bx inputs are low device is in Shutdown mode. This is a low-power mode when all buck-regulators and all internal blocks are disabled. 7.4.2 Active Mode When the first enable pin is pulled high there is a 420-s start-up delay when the device wakes up from Shutdown Mode and all internal reference blocks are started up. Once reference blocks have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during start-up. Once a buck output reaches 96% (typ.) of the desired output voltage, the power-good pin is pulled high. When at least one buck converter is active device is in Active Mode. When device is in Active Mode, the remaining buck converters will start up without any start-up delay when EN_Bx pin is pulled high. When EN_Bx pin is set low the corresponding buck converter will shut down. When all EN_Bx pins are set low LP8728 shuts down all internal reference blocks and enters Shutdown Mode. If output voltage of a buck regulator falls below 93% (typ.) of desired voltage due to, for example, an overload condition, the corresponding power good pin is pulled low. Once output voltage rises back above 96% (typ.) of desired voltage power good pin is set back high. Power good signal is held low for at least 50 ms. If UVLO, OVP or TSD fault occurs during normal operation, all power good pins are pulled low. Once fault condition has lasted for 5 ms all buck converters are shut down. Once fault condition has ended buck converters are restarted in a buck1 buck2 buck3 buck4 power-up sequence. A 500-s delay is included between each buck start-up. In case of TSD fault there is a 2 second safety delay before power up sequence. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 13 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) Shutdown Mode EN_Bx = HIGH & VIN > UVLO Reference Startup (420 s typ) Reference Shutdown Normal Operation All EN_Bx pins are LOW Buck_X Startup Buck_X Shutdown EN_Bx = HIGH All EN_Bx pins not LOW EN_Bx = LOW Power-up Sequence Active Mode Fault > 5 ms Fault < 5 ms Fault UVLO, OVP or TSD Fault VOUTX falls below power good threshold PG_Bx is pulled low Figure 14. Device Functional Modes 14 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP8728-Q1 is a quad-output Power Management Unit (PMU), optimized for low-power FPGAs, microprocessors, and DSPs. 8.2 Typical Application Figure 15 shows an example of typical application. Micro controller controls each buck converter with separated enable signal. All four power good signals are connected to micro controller with a separated pull-up resistors. If only one master power good signal is required all power good signals can be connected in parallel and pulled up with a single pull-up resistor. VOUT3 voltage can be selected with DEFSEL input. If VOUT3 control is not required during operation output voltage can be selected by connecting DEFSEL pin to VDDIO or to GND. VIN VIN 10 F VIN_B1 AVDD 1 F 1.5 H VOUT1 10 F SW_B1 BYP FB_B1 1 F VIN 10 F VIN_B2 VDDIO 1.5 H VOUT2 10 F SW_B2 FB_B2 LP8728 PG_B1 PG_B3 Micro Controller VIN 10 F VIN_B3 PG_B2 1.5 H PG_B4 SW_B3 EN_B1 FB_B3 VOUT3 10 F EN_B2 VIN VIN_B4 EN_B3 10 F GND_B3 GND_B4 GND_B2 AGND DEFSEL GND_B1 EN_B4 1.5 H SW_B4 FB_B4 VOUT4 10 F Figure 15. LP8728-Q1 Typical Application Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 15 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 8.2.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Input voltage range (VIN) 4.5 V to 5.5 V Buck converter output current 1 A maximum Buck converter input capacitance 10 F, 6.3 V Buck converter output capacitance 10 F, 6.3 V Buck converter inductor 1.5 H, 1.5 A AVDD pin bypass capacitor 1 F, 6.3 V BYP pin bypass capacitor 1 F, 6.3 V 8.2.2 Detailed Design Procedure 8.2.2.1 Inductor The four converters operate with 1.5-H inductors. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor directly influences the efficiency of the converter. Therefore, an inductor with the lowest possible DC resistance should be selected for the highest efficiency. The inductor should have a saturation current rating equal or higher than the high-side switch current limit (1500 mA). To minimize radiated noise shielded inductor should be used. The inductor should be connected to the SW pin as close to the IC as possible. 8.2.2.2 Input and Output Capacitors Because buck converters have a discontinuous input current, a low ESR input capacitor is required for best input-voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10-F ceramic input capacitor on its input pin VIN_Bx. The input capacitor capacitance can be increased without any limit for better input voltage filtering. A small 100-nF capacitor can be used in parallel to minimize high-frequency interferences. Input capacitors should be placed as close to VIN_Bx pins as possible. Routing from input capacitor to VIN_Bx pins should be done on top layer without using any vias. An output capacitor with a typical value of 10 F is recommended for each converter. Ceramic capacitors with low ESR value have lowest output voltage ripple and are recommended. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied DC voltage (DC bias effect). The capacitance value can fall below half of the nominal capacitance. This needs to be taken into consideration and, if necessary, use a capacitor with higher value or higher voltage rating. Table 1. Recommended External Components COMPONENT DESCRIPTION VALUE TYPE EXAMPLE CIN_B1,2,3,4 Buck regulator input capacitor 10 F Ceramic, 10 V, X7R MuRata, GRM21BR71A106KE51L COUT_B1,2,3,4 Buck regulator output capacitor 10 F Ceramic, 10 V, X7R MuRata, GRM21BR71A106KE51L CAVDD AVDD pin input capacitor 1 F Ceramic, 10 V, X7R MuRata, GRM188R71A105KA61D CBYP Internal LDO bypass capacitor 1 F Ceramic, 10 V, X7R MuRata, GRM188R71A105KA61D Buck regulator inductor 1.5 H ISAT >1.5 A, DCR < 100 m TOKO MDT2520-CN1R5M LSW1,2,3 16 4 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 8.2.3 Application Curves EN_B1 VOUT1 100mV/div PG_B1 SW_B1 5V/div Inductor current 500mA/div VOUT1 1V/div 200s/div 100s/div C001 C012 Figure 16. Short-Circuit Waveforms Figure 17. Start-up Delay VOUT1 50mV/div VOUT1 50mV/div VIN 1V/div IOUT 500mA/div 10s/div 40s/div C013 C014 IOUT from 0 mA to 1A VIN from 4.5 V To 5.5 V Figure 18. Load Transient Response Figure 19. Line Transient Response SW1 SW2 SW3 SW4 80ns/div C013 Figure 20. Switch Turnon Phase Shifting 9 Power Supply Recommendations The LP8728-Q1 is designed to operate from an input voltage supply range between 4.5 V and 5.5 V. This input supply must be well regulated and capable to supply the required input current. If the input supply is located far from the LP8728-Q1 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 17 LP8728-Q1 SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 www.ti.com 10 Layout 10.1 Layout Guidelines * * * * * * * * AVDD and BYP pins must by bypassed to ground. 1-F ceramic capacitor is recommended. Place the capacitor close to AVDD, BYP and AGND pins. AGND pin must bo be tied to the PCB ground plane. Use multiple vias to minimize the inductance. AVDD pin must be connected to PCB VIN plane. Use multiple vias to minimize the inductance. Place the buck converter input capacitors as close to buck input voltage and buck ground pins as possible. Place the buck converter output capacitors and inductors so that the buck converter switching loops can be routed on top layer. Try to minimize the area of the switching loops. Keep the trace width from switch pin to inductor wide enough to withstand the switching currents. Avoid any excess copper on the switch pin to minimize switch pin capacitance. Connect the exposed thermal pad to ground plane with multiple thermal vias. Avoid routing digital signals directly under the switching loops to avoid interferences. 10.2 Layout Example L2 VOUT2 Vias to VIN plane L1 Vias to GND plane COUT2 COUT1 CIN2 CIN1 VOUT1 Vias to VIN plane EN_B1 VIN_B1 SW_B1 GND_B1 GND_B2 FB_B2 FB_B1 PG_B3 AGND EN_B3 PG_B4 FB_B3 FB_B4 Connect thermal pad to GND plane using multiple vias Vias to VIN plane CBYP CIN EN_B4 VIN_B4 BYP SW_B4 DEFSEL GND_B4 AVDD GND_B3 PG_B1 SW_B3 EN_B2 PG_B2 VIN_B3 Route to controller SW_B2 VIN_B2 Route to Controller on internal layers CIN3 CIN4 COUT3 COUT4 Route to Controller on internal layers Vias to VIN plane VOUT3 VOUT4 L3 Vias to GND plane L4 Figure 21. Layout Example 18 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972B - AUGUST 2013 - REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Related Documentation Texas Instruments Application Note 1187 Leadless Leadframe Package (LLP) (SNOA401). See Using the LP8728EVM Evaluation Module (SNVU231) for more information about LP8728 evaluation module. 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 19 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2018 PACKAGING INFORMATION Orderable Device Status (1) LP8728QSQE-A/NOPB ACTIVE Package Type Package Pins Package Drawing Qty WQFN RSG 28 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 125 8728Q-A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 2-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP8728QSQE-A/NOPB Package Package Pins Type Drawing WQFN RSG 28 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.3 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-May-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8728QSQE-A/NOPB WQFN RSG 28 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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