LP8728
FB_B1
SW_B1 VOUT1
FB_B2
SW_B2 VOUT2
FB_B3
SW_B3 VOUT3
FB_B4
SW_B4 VOUT4
1.5 µH
AGND
GND_B1
GND_B2
GND_B3
GND_B4
EN_B1
EN_B2
EN_B3
EN_B4
PG_B1
PG_B2
PG_B3
PG_B4
Micro
Controller
DEFSEL
AVDD
BYP
VIN VIN
VIN_B1
VIN
VIN_B2
VIN
VIN
VIN_B3
VIN_B4
VDDIO
1 µF
1 µF 10 µF
1.5 µH
1.5 µH
1.5 µH
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400 500 600 700 800 900 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
3.3V
2.65V
1.8V
1.25V
C000
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LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
LP8728-Q1 Quad-Output Step-Down DC/DC Converter
1 Features 3 Description
The LP8728-Q1 is a quad-output Power Management
1• LP8728-Q1 is an Automotive Grade Product that Unit (PMU), optimized for low-power FPGAs,
is AECQ-100 Grade 1 Qualified microprocessors, and DSPs for automotive
• Four High Efficiency Step-Down DC/DC applications. This device integrates four highly
Converters: efficient step-down DC/DC converters into one
package. Each converter has high current capability
– 93% Peak Efficiency (VIN =5V,VOUT 3.3 V) and separate controls which allows flexibility to use
– Max Output Current 1 A the device in multiple applications. All the converters
– Forced PWM Operation operate above the AM band with a fixed 3.2-MHz
– Soft-Start Control switching frequency. Each buck converter's high-side
switch turnon time is phase shifted to minimize input
– VOUT1 = 3.3 V current spikes.
– VOUT2 = 1.25 V The protection features include output short-circuit
– VOUT3 = 1.8 V or 2.65 V (pin selectable) protection, switch current limits, input overvoltage
– VOUT4 = 1.8 V protection, input undervoltage lockout, and thermal
• Separate Enable Inputs for each Converter shutdown functions. During start-up, the device
controls the output slew rate to minimize output
Control voltage overshoot and the input inrush current.
• Separate Power Good Outputs for each Converter
• Output Overcurrent and Input Overvoltage Device Information(1)
Protection PART NUMBER PACKAGE BODY SIZE (NOM)
• Overtemperature Protection LP8728-Q1 WQFN (28) 5.00 mm x 5.00 mm
• Undervoltage Lockout (UVLO) (1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications space
• FPGA, DSP Core Power space
• Processor Power for Mobile Devices space
• Peripheral I/O Power space
• Automotive Safety Cameras
• Automotive Infotainment space
space
Simplified Schematic Efficiency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Feature Description................................................. 10
1 Features.................................................................. 17.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 18 Application and Implementation ........................ 15
3 Description............................................................. 18.1 Application Information............................................ 15
4 Revision History..................................................... 28.2 Typical Application ................................................. 15
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 17
6 Specifications......................................................... 510 Layout................................................................... 18
6.1 Absolute Maximum Ratings ...................................... 510.1 Layout Guidelines ................................................. 18
6.2 ESD Ratings.............................................................. 510.2 Layout Example .................................................... 18
6.3 Recommended Operating Conditions....................... 511 Device and Documentation Support................. 19
6.4 Thermal Information.................................................. 511.1 Device Support .................................................... 19
6.5 Electrical Characteristics........................................... 611.2 Related Documentation......................................... 19
6.6 System Characteristics ............................................. 711.3 Trademarks........................................................... 19
6.7 Typical Characteristics.............................................. 711.4 Electrostatic Discharge Caution............................ 19
7 Detailed Description.............................................. 911.5 Glossary................................................................ 19
7.1 Overview ................................................................... 912 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 9Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2014) to Revision B Page
• Changed simplified schematic circuit drawing to correct pin placements for SW_B3 and SW_B4 ...................................... 1
• Added ESD Ratings table to replace Handling Ratings ......................................................................................................... 5
• Changed typical application circuit drawing to correct pin placements for SW_B3 and SW_B4 ........................................ 15
Changes from Original (August 2013) to Revision A Page
• Added Device Information and Handling Ratings tables, Feature Description,Device Functional Modes,Application
and Implementation,Power Supply Recommendations,Layout ,Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section.............. 1
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Product Folder Links: LP8728-Q1
1
DAP
PIN 1 ID
234567
212019
18171615
8
9
10
11
12
13
14
28
27
26
25
24
23
22
FB_B1
PG_B4
EN_B4
PG_B2
EN_B2 PG_B1
FB_B4
FB_B2
DEFSEL
EN_B1
AVDD
BYP
AGND
FB_B3
GND_B3
SW_B3
VIN_B3
EN_B3
VIN_B4
SW_B4
GND_B4
GND_B2
SW_B2
VIN_B2
PG_B3
VIN_B1
SW_B1
GND_B1
TOP VIEW
LP8728-Q1
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SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
5 Pin Configuration and Functions
WQFN (RSG) Package
28 Pins
Pin Functions
PIN TYPE DESCRIPTION
NUMBER NAME
1 EN_B1 D/I Enable Buck 1
2 VIN_B1 P Positive power supply input for Buck 1
3 SW_B1 P Switch node for Buck 1
4 GND_B1 G Power ground for Buck 1
5 GND_B2 G Power ground for Buck 2
6 SW_B2 P Switch node for Buck 2
7 VIN_B2 P Positive power supply input for Buck 2
8 FB_B2 A Feedback pin for Buck 2. Referenced against AGND.
9 EN_B2 D/I Enable Buck 2
10 PG_B2 D/O Open-drain Power Good output for Buck 2
11 DEFSEL D/I Buck 3 output voltage selection pin
12 PG_B3 D/O Open-drain Power Good output for Buck 3
13 EN_B3 D/I Enable buck 3
14 FB_B3 A Feedback pin for Buck 3. Referenced against AGND.
15 VIN_B3 P Positive power supply input for Buck 3
16 SW_B3 P Switch node for Buck 3
17 GND_B3 G Power ground for Buck 3
18 GND_B4 G Power ground for Buck 4
19 SW_B4 P Switch node for Buck 4
20 VIN_B4 P Positive power supply input for Buck 4
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Pin Functions (continued)
PIN TYPE DESCRIPTION
NUMBER NAME
21 EN_B4 D/I Enable Buck 4
22 FB_B4 A Feedback pin for Buck 4. Referenced against AGND.
23 PG_B4 D/O Open-drain Power Good output for Buck 4
24 AGND G Analog ground
25 BYP A Internal 1.8-V supply voltage capacitor pin. A ceramic low ESR 1-μF capacitor should
be connected from this pin to AGND. The BYP voltage is generated internally, do not
supply or load this pin externally.
26 AVDD P Analog positive power supply pin (VIN level)
27 PG_B1 D/O Open-drain Power Good output for Buck 1
28 FB_B1 A Feedback pin for Buck 1. Referenced against AGND.
DAP Die Attachment Pad Exposed die attachment pad should to be connected to GND plane with thermal vias
to improve the thermal performance of the system.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN Voltage on power pins (AVDD, VIN_Bx) –0.3 6
VFB Voltage on feedback pins (FB_Bx) –0.3 6
(GND_Bx – 0.2 V) to (VIN_Bx + 0.2 V) with 6 V
VSW Voltage on buck converter switch pins (SW_Bx) V
max
VDIG Voltage on digital pins (PG_Bx, EN_Bx, DEFSEL) (AGND – 0.2V) to (AVDD + 0.2 V) with 6 V max
VBYP Voltage on BYP pin –0.3 2
TJ(MAX) Maximum operating junction temperature(2) 150 °C
Maximum lead temperature (Soldering) See (3)
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and
disengages at TJ= 130°C (typ.).
(3) For detailed soldering specifications and information, please refer to Texas Instruments Application Note Leadless Leadframe Package
(LLP) SNOA401.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
VIN Input voltage on AVDD, VIN_B1, VIN_B2, VIN_B3 and VIN_B4 Pins 4.5 5 5.5 V
TAOperating ambient temperature(2) –40 125 °C
Effective output capacitance during operation.
COUT 5 10 12
Min value over TA–40°C to 125°C.
Effective input capacitance during operation. 4.5 V ≤VIN_Bx ≤5.5 V.
CIN 2.5 10 µF
Min value over TA–40°C to 125°C.
Effective inductance during operation
L 0.47 1.5 2
Min value over TA–40°C to 125°C.
(1) All voltage values are with respect to network ground terminal.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (RθJA), as given by the following equation: TA(max) = TJ(max) – (RθJA × PD(max))
6.4 Thermal Information LP8728-Q1
THERMAL METRIC(1) WQFN (RSG) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance (2) 36.3 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Calculated using 4-layer standard JEDEC thermal test board with 5 thermal vias between the die attach pad in the first copper layer and
second copper layer.
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6.5 Electrical Characteristics(1)(2)
Unless otherwise noted, VIN = 5 V, typical values apply for TA= 25°C, and minimum/maximum limits apply over junction
temperature range, TJ= –40°C to 125°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shutdown supply current into power
ISHDN EN_Bx = 0 V 1 6 μA
connections
IOP Operating current All buck-converters active, IOUT = 0 mA 20 mA
LOGIC INPUTS (EN_Bx, DEFSEL)
VIL Input low level 0.4 V
VIH Input high level 1.6 V
EN_Bx and DEFSEL internal pull-
RPD_DI 300 520 820 kΩ
down resistance
TH_MIN Minimum EN_Bx high time 1 ms
TL_MIN Minimum EN_Bx low time 10 µs
LOGIC OUTPUTS (PG_Bx)
VOL Output low level ISINK = 3 mA 0.4 V
RPU Recommended pull-up resistor 10 kΩ
BUCK CONVERTERS
VOUT1 Output voltage for Buck 1 Fixed voltage 3.3 V
VOUT2 Output voltage for Buck 2 Fixed voltage 1.25 V
DEFSEL = 1 2.65
VOUT3 Output voltage for Buck 3 V
DEFSEL = 0 1.8
VOUT4 Output voltage for Buck 4 Fixed voltage 1.8 V
VFB_Bx Output voltage accuracy –3% 3%
Line regulation 4.5 V ≤VIN_Bx ≤5.5 V ILOAD = 10 mA 3 mV
ΔVOUT Load regulation VIN = 5 V 100 mA ≤ILOAD ≤900 mA 3 mV
DC load
IOUT Output current 1000 mA
TA= 25°C.
FSW Switching frequency 3.03 3.2 3.37 MHz
GBW Gain bandwidth 300 kHz
ILIMITP High side switch current limit 1200 1500 1800 mA
ILIMITN Low side switch current limit Reverse current 500 mA
RDSONP Pin-pin resistance for PFET IOUT = 200 mA 210 300 mΩ
RDSONN Pin-pin resistance for NFET IOUT = 200 mA 140 240 mΩ
ILK_SW Switch pin leakage current VOUT = 1.8V 1 µA
Pull-down resistor from FB_Bx pin to Only active when converter disabled.
RPD_FB 40 70 100 Ω
GND All limits apply for TA= 25°C.
KRAMP Slew rate control DEFSEL from 0 to 1 10 mV/µs
Time from first EN_Bx high to start of
TSTART Start-up time 420 µs
switching
KSTART Soft-start VOUT slew rate 18 mV/µs
VOLTAGE MONITORING
Power good threshold for voltage rising 93.5% 96% 98%
VPG Power good threshold voltage Power good threshold for voltage falling 91% 93% 95%
Voltage monitored on AVDD Pin, V
5.5 5.7 5.9
Input overvoltage protection trigger voltage rising
VOVP point Hysteresis 80 mV
(1) All voltage values are with respect to network ground terminal.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ= 25°C.
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C000
C012
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SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
Electrical Characteristics(1)(2) (continued)
Unless otherwise noted, VIN = 5 V, typical values apply for TA= 25°C, and minimum/maximum limits apply over junction
temperature range, TJ= –40°C to 125°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Voltage monitored on AVDD Pin, V
4.35
Input undervoltage lockout (UVLO) voltage falling
VUVLO turn-on threshold. Hysteresis 80 mV
THERMAL SHUTDOWN AND MONITORING
Threshold, temperature rising 150
TSD Thermal shutdown °C
Hysteresis 20
6.6 System Characteristics(1)(2)(3)
Typical values apply for TA= 25°C. Unless otherwise noted, VIN = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT 10% max load →90% max load, 1- 70 mV
µs load step
Load transient response IOUT 90% max load →10% max load, 1-
ΔVOUT 70 mV
µs load step
VIN_Bx stepping 4.5V ↔5.5V tr = tf = 10
Line transient response 20 mV
µs, IOUT = 400 mA
VRIPPLE Output voltage ripple COUT ESR = 10 mΩ, IOUT = 200 mA 10 mVPP
VOUT = 3.3 V, IOUT = 300 mA 94%
VOUT = 2.65 V, IOUT = 300 mA 92%
ηEfficiency VOUT = 1.8 V, IOUT = 300 mA 89%
VOUT = 1.2 V, IOUT = 300 mA 85%
(1) All voltage values are with respect to network ground terminal.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ= 25°C.
(3) System Characteristics are highly dependent on external components and PCB layout. System Characteristics are verified using
inductor type: TOKO MDT2520-CN1R5M, input and output capacitor type: MuRata GRM21BR71A106KE51L.
6.7 Typical Characteristics
Unless otherwise noted, VIN = 5 V, TA= 25°C
Figure 1. Efficiency vs Output Current Figure 2. Switching Frequency vs Temperature
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C010
C011
C008
C009
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOUT1 (V)
IOUT1 (A)
+125°C
+25°C
-40°C
C006
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6
VOUT1 (V)
SUPPLY VOLTAGE (V)
+125°C
+25°C
-40°C
C007
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
Unless otherwise noted, VIN = 5 V, TA= 25°C
Figure 3. Buck1 Load Regulation Figure 4. Buck1 Line Regulation
Figure 5. Buck2 Load Regulation with 1.25-V Setting Figure 6. Buck2 Line Regulation with 1.25-V Setting
Figure 7. Shutdown Current Consumption Figure 8. Active Mode Current Consumption (All Bucks
Active)
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Control
Logic
EN_B1
Thermal
Shutdown
Oscillator
Reference
Voltage
OTP
UVLO
DEFSEL
PG_B1
VIN_B1
10 µF
FB_B1
1.5 µH
SW_B1
VIN
VOUT2
VOUT1
PG_B2
PG_B3
PG_B4
EN_B2
EN_B3
EN_B4
VIN
VIN
VIN
VOUT3
VOUT4
VIN
LDO
10 µF
Buck1
(Active Pulldown)
Buck2
(Active Pulldown)
VIN_B2
10 µF
FB_B2
1.5 µH
SW_B2
10 µF
Buck3
(Active Pulldown)
VIN_B3
10 µF
FB_B3
1.5 µH
SW_B3
10 µF
Buck4
(Active Pulldown)
VIN_B4
10 µF
FB_B4
1.5 µH
SW_B4
10 µF
AGND
AVDD
BYP
GND_B1
GND_B2
GND_B3
GND_B4
1 µF
1 µF
LP8728-Q1
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SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LP8728 has four integrated high-efficiency buck converters. Each buck converter has individual enable input
and power good output pins. When the first enable pin is pulled high there is a 420-µs start-up delay when the
device wakes up from shutdown mode and all internal reference blocks are started up. Once reference blocks
have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the
inrush current during start-up. Once a buck output reaches 96% (typ.) of the desired output voltage, the power-
good pin is pulled high (see Figure 9). When at least one buck core is active, the remaining buck converters will
start up without any start-up delay.
If the output voltage drops below 93% (typ.) of desired voltage due to, for example, an overload condition, the
corresponding power-good pin is pulled low. The power-good signal is always held low for at least 50 ms. When
the enable pin is pulled low, the corresponding buck converter's power good signals are set low, and the buck
converter is instantly shut down. An output capacitor is then discharged through an internal 70-Ω(typ.) pull-down
resistor. The pull-down resistor is connected between buck feedback pin and ground and is only active when the
enable pin is set low. When all enable signals are pulled low, the LP8728-Q1 enters a low-current shutdown
mode.
7.2 Functional Block Diagram
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VOUT1
VOUT2
VOUT3
VOUT4
Junction
Temperature TJ
TSD
(Internal Signal)
2s
500us 500us 500us
PG_B1
PG_B2
PG_B3
PG_B4
5 ms
130°C
150°C
96%
VOUTx
EN_Bx
PG_Bx
93%
Overload condition
5%
TSTART TRAMP 50ms
Active pulldown
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
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7.3 Feature Description
7.3.1 Buck Information
The buck converters are operated in forced PWM mode. Even with light load a minimum switching pulse is
generated with every switching cycle. Each buck converter's high-side switch turn-on time is phase shifted to
minimize the input current ripple (see Figure 20).
7.3.1.1 Features
The following features are supported for all converters:
• Synchronous rectification
• Current mode feedback loop with PI compensator
• Forced PWM operation
• Soft start
• Power-good output
• Overvoltage comparator
In addition to the aforementioned features, buck3 output voltage can be selected with the DEFSEL pin. If the
DEFSEL pin is pulled low, VOUT3 is set to 1.8 V. If DEFSEL is pulled high, VOUT3 is set to 2.65 V.
Figure 9. Buck Converter Start-up And Shutdown
7.3.2 Thermal Shutdown (TSD)
Thermal shutdown function shuts down all buck regulators if the device's junction temperature TJrises above
150°C (typ.). All power-good signals are pulled low 5 ms before buck regulators are shut down. Once TJfalls
below 130°C (typical), the LP8728 will automatically start up the buck regulators. There is a 2-second safety
delay included in the restart function. Buck regulators are not restarted until 2 seconds have elapsed after TJfalls
below 130°C (typical). To minimize the inrush current during restarting, regulators are started in a buck1 →
buck2 →buck3 →buck4 sequence. A 500-µs delay is included between each buck start-up.
Figure 10. TSD Timing Diagram
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VOUT1
VOUT2
VOUT3
VOUT4
VIN
UVLO
PG_B1
PG_B2
PG_B3
PG_B4
5.0V
4.35V
5 ms
LP8728-Q1
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SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
Feature Description (continued)
7.3.3 Undervoltage Lockout (UVLO)
Undervoltage lockout pulls the PG_Bx pins low if the input voltage drops below 4.35 V (typical) (Figure 11).
PG_Bx pins are always held low for at least 50 ms. Once an undervoltage condition has lasted for 5 ms, all buck
converters are shut down. Buck converters are restarted once the input voltage rises above UVLO level.
If an undervoltage condition has lasted more than 5 ms, but less than 50 ms, PG_Bx pins are released high once
50 ms has elapsed and corresponding output voltage has settled. If an overvoltage condition has lasted more
than 50 ms, power-good signals are released high once corresponding output voltage has settled. If an under-
voltage condition lasts less than 5 ms, the buck converters are not shut down. Even in this case PG_Bx pins are
held low for 50 ms.
Regulators are always restarted in a buck1 →buck2 →buck3 →buck4 sequence. A 500-µs delay is included
between each buck start-up.
Figure 11. UVLO Operation
7.3.4 Overvoltage Protection (OVP)
Overvoltage protection protects the device in case of an overvoltage condition. If input voltage exceeds 5.7 V
(typical), all PG_Bx pins are pulled low. PG_Bx pins are always held low for at least 50 ms. Once the PG_Bx
pins are pulled low, the system has 5 ms time to power down. After over-voltage condition has lasted for 5 ms,
all buck converters are shut down. Buck converters are restarted once input voltage falls below 5.62 V (typical).
Regulators are started in a buck1 →buck2 →buck3 →buck4 sequence. A 500-µs delay is included between
each buck start-up.
If an overvoltage condition lasted more than 5 ms, but less than 50 ms, the PG_Bx pins are released high once
50 ms has elapsed and corresponding output voltage has settled (Figure 12).
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VOUT1
VOUT2
VOUT3
VOUT4
VIN
OVP
500 s 500 s 500 sμ μ μ
PG_B1
PG_B2
PG_B3
PG_B4
5 ms
5.7V
50 ms
VOUT1
VOUT2
VOUT3
VOUT4
VIN
OVP
PG_B1
PG_B2
PG_B3
PG_B4
5 ms
5.7V
50 ms
500 sμ 500 sμ 500 sμ
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
Figure 12. OVP Duration Less Than 50 ms
If an overvoltage condition has lasted more than 50 ms, power-good signals are released high once
corresponding output voltage has settled. Regulators are started in a buck1 →buck2 →buck3 →buck4
sequence. A 500-µs delay is included between each buck start-up (Figure 13). If an overvoltage condition has
lasted less than 5 ms, buck converters are not shut down. Even in this case the PG_Bx pins are held low for 50
ms.
NOTE
Since regulators are allowed to operate for 5 ms during overvoltage condition it is the
system designer’s responsibility to verify that input voltage doesn’t exceed limits stated in
Absolute Maximum Ratings. Exceeding these limits may cause permanent damage to the
device.
Figure 13. OVP Duration More Than 50 ms
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
When all EN_Bx inputs are low device is in Shutdown mode. This is a low-power mode when all buck-regulators
and all internal blocks are disabled.
7.4.2 Active Mode
When the first enable pin is pulled high there is a 420-µs start-up delay when the device wakes up from
Shutdown Mode and all internal reference blocks are started up. Once reference blocks have settled, the
corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during
start-up. Once a buck output reaches 96% (typ.) of the desired output voltage, the power-good pin is pulled high.
When at least one buck converter is active device is in Active Mode. When device is in Active Mode, the
remaining buck converters will start up without any start-up delay when EN_Bx pin is pulled high. When EN_Bx
pin is set low the corresponding buck converter will shut down. When all EN_Bx pins are set low LP8728 shuts
down all internal reference blocks and enters Shutdown Mode.
If output voltage of a buck regulator falls below 93% (typ.) of desired voltage due to, for example, an overload
condition, the corresponding power good pin is pulled low. Once output voltage rises back above 96% (typ.) of
desired voltage power good pin is set back high. Power good signal is held low for at least 50 ms.
If UVLO, OVP or TSD fault occurs during normal operation, all power good pins are pulled low. Once fault
condition has lasted for 5 ms all buck converters are shut down. Once fault condition has ended buck converters
are restarted in a buck1 →buck2 →buck3 →buck4 power-up sequence. A 500-µs delay is included between
each buck start-up. In case of TSD fault there is a 2 second safety delay before power up sequence.
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LP8728-Q1
Normal Operation
EN_Bx = HIGH
& VIN > UVLO
Shutdown
Mode
Reference
Startup
(420 µs typ)
EN_Bx = HIGH
Active Mode
Buck_X
Startup
Buck_X
Shutdown
All EN_Bx pins
are LOW
EN_Bx = LOW
Reference
Shutdown
All EN_Bx pins
not LOW
VOUTX falls below
power good threshold
PG_Bx is pulled
low
Power-up
Sequence
Fault
UVLO, OVP or
TSD Fault
Fault < 5 ms
Fault > 5 ms
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
Device Functional Modes (continued)
Figure 14. Device Functional Modes
14 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: LP8728-Q1
LP8728
FB_B1
SW_B1 VOUT1
FB_B2
SW_B2 VOUT2
FB_B3
SW_B3 VOUT3
FB_B4
SW_B4 VOUT4
1.5 µH
AGND
GND_B1
GND_B2
GND_B3
GND_B4
EN_B1
EN_B2
EN_B3
EN_B4
PG_B1
PG_B2
PG_B3
PG_B4
Micro
Controller
DEFSEL
AVDD
BYP
VIN VIN
VIN_B1
VIN
VIN_B2
VIN
VIN
VIN_B3
VIN_B4
VDDIO
1 µF
1 µF 10 µF
1.5 µH
1.5 µH
1.5 µH
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
LP8728-Q1
www.ti.com
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8728-Q1 is a quad-output Power Management Unit (PMU), optimized for low-power FPGAs,
microprocessors, and DSPs.
8.2 Typical Application
Figure 15 shows an example of typical application. Micro controller controls each buck converter with separated
enable signal. All four power good signals are connected to micro controller with a separated pull-up resistors. If
only one master power good signal is required all power good signals can be connected in parallel and pulled up
with a single pull-up resistor. VOUT3 voltage can be selected with DEFSEL input. If VOUT3 control is not required
during operation output voltage can be selected by connecting DEFSEL pin to VDDIO or to GND.
Figure 15. LP8728-Q1 Typical Application
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LP8728-Q1
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range (VIN) 4.5 V to 5.5 V
Buck converter output current 1 A maximum
Buck converter input capacitance 10 µF, 6.3 V
Buck converter output capacitance 10 µF, 6.3 V
Buck converter inductor 1.5 µH, 1.5 A
AVDD pin bypass capacitor 1 µF, 6.3 V
BYP pin bypass capacitor 1 µF, 6.3 V
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor
The four converters operate with 1.5-µH inductors. The selected inductor has to be rated for its DC resistance
and saturation current. The DC resistance of the inductor directly influences the efficiency of the converter.
Therefore, an inductor with the lowest possible DC resistance should be selected for the highest efficiency. The
inductor should have a saturation current rating equal or higher than the high-side switch current limit (1500 mA).
To minimize radiated noise shielded inductor should be used. The inductor should be connected to the SW pin
as close to the IC as possible.
8.2.2.2 Input and Output Capacitors
Because buck converters have a discontinuous input current, a low ESR input capacitor is required for best
input-voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. Each
DC-DC converter requires a 10-µF ceramic input capacitor on its input pin VIN_Bx. The input capacitor
capacitance can be increased without any limit for better input voltage filtering. A small 100-nF capacitor can be
used in parallel to minimize high-frequency interferences. Input capacitors should be placed as close to VIN_Bx
pins as possible. Routing from input capacitor to VIN_Bx pins should be done on top layer without using any
vias.
An output capacitor with a typical value of 10 µF is recommended for each converter. Ceramic capacitors with
low ESR value have lowest output voltage ripple and are recommended.
Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the
increased applied DC voltage (DC bias effect). The capacitance value can fall below half of the nominal
capacitance. This needs to be taken into consideration and, if necessary, use a capacitor with higher value or
higher voltage rating.
Table 1. Recommended External Components
COMPONENT DESCRIPTION VALUE TYPE EXAMPLE
MuRata,
CIN_B1,2,3,4 Buck regulator input capacitor 10 µF Ceramic, 10 V, X7R GRM21BR71A106KE51L
MuRata,
COUT_B1,2,3,4 Buck regulator output capacitor 10 µF Ceramic, 10 V, X7R GRM21BR71A106KE51L
MuRata,
CAVDD AVDD pin input capacitor 1 µF Ceramic, 10 V, X7R GRM188R71A105KA61D
MuRata,
CBYP Internal LDO bypass capacitor 1 µF Ceramic, 10 V, X7R GRM188R71A105KA61D
LSW1,2,3 4 Buck regulator inductor 1.5 µH ISAT >1.5 A, DCR < 100 mΩTOKO MDT2520-CN1R5M
16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: LP8728-Q1
80ns/div
C013
SW1
SW2
SW3
SW4
10s/div
C013
VOUT1
50mV/div
IOUT
500mA/div
40s/div
C014
VOUT1
50mV/div
VIN
1V/div
200s/div
C001
VOUT1
100mV/div
SW_B1
5V/div
Inductor
current
500mA/div
100s/div
C012
EN_B1
PG_B1
VOUT1
1V/div
LP8728-Q1
www.ti.com
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
8.2.3 Application Curves
Figure 16. Short-Circuit Waveforms Figure 17. Start-up Delay
IOUT from 0 mA to 1A VIN from 4.5 V To 5.5 V
Figure 18. Load Transient Response Figure 19. Line Transient Response
Figure 20. Switch Turnon Phase Shifting
9 Power Supply Recommendations
The LP8728-Q1 is designed to operate from an input voltage supply range between 4.5 V and 5.5 V. This input
supply must be well regulated and capable to supply the required input current. If the input supply is located far
from the LP8728-Q1 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LP8728-Q1
FB_B1
PG_B1
PG_B4
FB_B4
AVDD
BYP
AGND
PG_B2
EN_B2
FB_B2
DEFSEL
FB_B3
EN_B3
PG_B3
EN_B1
GND_B2
SW_B2
VIN_B2
VIN_B1
SW_B1
GND_B1
EN_B4
GND_B3
SW_B3
VIN_B3
VIN_B4
SW_B4
GND_B4
CIN2
L2
COUT2
CIN1
COUT1
L1
COUT3
CIN3
COUT4
CIN4
L4L3
Route to
controller
Connect thermal pad
to GND plane using
multiple vias
VOUT1VOUT2
VOUT3 VOUT4
CBYP CIN
Route to
Controller on
internal layers
Route to
Controller on
internal layers
Vias to
VIN plane
Vias to
VIN plane
Vias to
VIN plane
Vias to
VIN plane
Vias to
GND plane
Vias to
GND plane
LP8728-Q1
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
• AVDD and BYP pins must by bypassed to ground. 1-µF ceramic capacitor is recommended. Place the
capacitor close to AVDD, BYP and AGND pins.
• AGND pin must bo be tied to the PCB ground plane. Use multiple vias to minimize the inductance.
• AVDD pin must be connected to PCB VIN plane. Use multiple vias to minimize the inductance.
• Place the buck converter input capacitors as close to buck input voltage and buck ground pins as possible.
• Place the buck converter output capacitors and inductors so that the buck converter switching loops can be
routed on top layer. Try to minimize the area of the switching loops.
• Keep the trace width from switch pin to inductor wide enough to withstand the switching currents. Avoid any
excess copper on the switch pin to minimize switch pin capacitance.
• Connect the exposed thermal pad to ground plane with multiple thermal vias.
• Avoid routing digital signals directly under the switching loops to avoid interferences.
10.2 Layout Example
Figure 21. Layout Example
18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: LP8728-Q1
LP8728-Q1
www.ti.com
SNVS972B –AUGUST 2013–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Documentation
Texas Instruments Application Note 1187 Leadless Leadframe Package (LLP) (SNOA401).
See Using the LP8728EVM Evaluation Module (SNVU231) for more information about LP8728 evaluation
module.
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LP8728-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP8728QSQE-A/NOPB ACTIVE WQFN RSG 28 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 8728Q-A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP8728QSQE-A/NOPB WQFN RSG 28 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP8728QSQE-A/NOPB WQFN RSG 28 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2018
Pack Materials-Page 2
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