FUNCTIONAL BLOCK DIAGRAM REF_SEL Rx AD9574 x1/x2 OUT1_P Rx OUT1_N MCLK_x REF_ACT REF_SW REF_FLO REF_FHI REFMON PPRx OUT0_P OUT0_N x1/x2 PFD/ CP LF LD LF PPR CONTROL VCO OUT2_P OUT2_N OUT3_P OUT3_N OUT4_P OUT4_N OUT5_P OUT5_N OUT6_P OUT6_N 07501-001 REF0_P REF0_N REF1_P REF1_N DIVIDERS Redundant input reference clock capability Reference monitoring function Fully integrated VCO/PLL core Jitter (rms) 0.234 ps rms jitter (10 kHz to 10 MHz) at 156.25 MHz 0.243 ps rms jitter (12 kHz to 20 MHz) at 156.25 MHz Input frequency: 19.44 MHz or 25 MHz Preset frequency translations Using a 19.44 MHz input reference 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz Using a 25 MHz input reference 25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS Integrated loop filter (requires a single external capacitor) 2 copies of reference clock output Device configuration via strapping pins (PPRx) Space-saving 7 mm x 7 mm 48-lead LFCSP 3.3 V operation REFERENCE MONITOR FEATURES REFERENCE SWITCH Data Sheet Ethernet/Gigabit Ethernet Clock Generator AD9574 Figure 1. APPLICATIONS Ethernet line cards, switches, and routers SATA and PCI express Low jitter, low phase noise clock generation GENERAL DESCRIPTION The AD9574 provides a multiple output clock generator function comprising a dedicated phase-locked loop (PLL) core optimized for Ethernet and gigabit Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The AD9574 also benefits other applications requiring low phase noise and jitter performance. Configuring the AD9574 for a particular application requires only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. Connecting an external 19.44 MHz or 25 MHz oscillator to one or both of the REF0_P/REF0_N or REF1_P/REF1_N reference inputs results in a set of output frequencies prescribed by the PPRx pins. Connecting a stable Rev. B clock source (8 kHz/10 MHz/19.44 MHz/25 MHz/38.88 MHz) to the monitor clock input enables the optional monitor circuit providing quality of service (QoS) status for REF0 or REF1. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a partially integrated loop filter (LF), a low phase noise voltage controlled oscillator (VCO), and feedback and output dividers. The divider values depend on the PPRx pins. The integrated loop filter requires only a single external capacitor connected to the LF pin. The AD9574 is packaged in a 48-lead 7 mm x 7 mm LFCSP, requiring only a single 3.3 V supply. The operating temperature range is -40C to +85C. Note that throughout this data sheet, OUT0 to OUT6, REF0, and REF1 refer to the respective channels, which consist of the differential pins, OUT0_P/OUT0_N to OUT6_P/OUT6_N, REF0_P/REF0_N, and REF1_P/REF1_N, respectively. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9574 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 21 Applications ....................................................................................... 1 PPRx Pins .................................................................................... 21 Functional Block Diagram .............................................................. 1 PPR0--Reference Clock Input Configuration ................... 22 General Description ......................................................................... 1 PPR1--Frequency Translation Settings .............................. 22 Revision History ............................................................................... 2 PPR2--OUT0 and OUT1 Configuration ........................... 23 Specifications..................................................................................... 3 PPR3--OUT4 and OUT5 Configuration ........................... 23 OUT0 Channel Absolute Clock Jitter ........................................ 3 PPR4--OUT6 Configuration ............................................... 24 OUT1 Channel Absolute Clock Jitter ........................................ 3 PPR5--Reference Monitor Threshold................................. 24 OUT2 and OUT3 Channels Absolute Clock Jitter................... 3 PPR6--Monitor Clock (MCLK_x) Input Configuration . 24 OUT4 and OUT5 Channels Absolute Clock Jitter................... 4 Dependency of PPR3 and PPR4 on PPR1 .......................... 24 OUT6 Channel Absolute Clock Jitter ........................................ 5 Power-On Reset (POR) ............................................................. 25 Clock Outputs (OUT0_x to OUT6_x)--Static ........................ 6 Reference Clock Inputs .............................................................. 27 Clock Outputs (OUT0_x to OUT6_x)--Dynamic .................. 6 Monitor Clock Input .................................................................. 27 Monitor Clock Inputs (MCLK_x)--Static ................................ 7 Reference Switching ................................................................... 27 Monitor Clock Inputs (MCLK_x)--Dynamic .......................... 8 Reference Monitor...................................................................... 27 Reference Inputs (REF0_x and REF1_x)--Static ..................... 8 PLL ............................................................................................... 28 Reference Inputs (REF0_x and REF1_x)--Dynamic .............. 8 Output Drivers ............................................................................ 29 Reference Switchover Output Disturbance ............................... 9 Output Clocks ............................................................................. 29 Control Pins .................................................................................. 9 Applications Information .............................................................. 30 Status Pins .................................................................................... 10 Dual Oscillator Reference Input Application ......................... 30 Power Supply and Dissipation .................................................. 10 Simple, Single Oscillator Reference Input Application ......... 31 Timing Specifications ................................................................ 11 Interfacing to CMOS Clock Outputs ....................................... 31 Timing Diagrams........................................................................ 12 Interfacing to LVDS and HSTL Clock Outputs ..................... 32 Absolute Maximum Ratings .......................................................... 13 Interfacing to HCSL Clock Outputs ........................................ 32 ESD Caution ................................................................................ 13 Power Supply............................................................................... 33 Pin Configuration and Function Descriptions ........................... 14 Typical Performance Characteristics ........................................... 17 Power and Grounding Considerations and Power Supply Rejection ...................................................................................... 33 Phase Noise and Voltage Waveforms ....................................... 17 Thermal Performance .................................................................... 34 Reference Switching Frequency and Phase Disturbance ...... 19 Outline Dimensions ....................................................................... 35 Terminology .................................................................................... 20 Ordering Guide .......................................................................... 35 Theory of Operation ...................................................................... 21 REVISION HISTORY 4/2017--Rev. A to Rev. B Change to Figure 20 ....................................................................... 21 Updated Outline Dimensions ....................................................... 35 Changes to Ordering Guide .......................................................... 35 1/2015--Rev. 0 to Rev. A Changes to Table 13 .......................................................................... 9 Changes to Note 1, Table 17 .......................................................... 13 Deleted Thermal Resistance Section and Table 18; Renumbered Sequentially ..................................................................................... 13 Changes to Power-On Reset (POR) Section ............................... 26 Added Figure 22; Renumbered Sequentially .............................. 26 Added Thermal Performance Section and Table 35 .................. 34 9/2014--Revision 0: Initial Version Rev. B | Page 2 of 35 Data Sheet AD9574 SPECIFICATIONS OUT0 CHANNEL ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25C, unless otherwise noted. Table 1. Parameter HIGH SPEED TRANSCEIVER LOGIC (HSTL) INTEGRATED JITTER 19.44 MHz Output 25 MHz Output 38.88 MHz Output 50 MHz Output 3.3 V CMOS INTEGRATED JITTER 19.44 MHz Output 25 MHz Output 38.88 MHz Output 50 MHz Output Min Typ Max Unit 0.196 0.179 1.943 1.523 ps rms ps rms ps rms ps rms 0.204 0.178 1.969 1.446 ps rms ps rms ps rms ps rms Test Conditions/Comments Jitter integration bandwidth = 12 kHz to 5 MHz Jitter integration bandwidth = 12 kHz to 5 MHz OUT1 CHANNEL ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25C, unless otherwise noted. Table 2. Parameter HSTL INTEGRATED JITTER 19.44 MHz Output 25 MHz Output 3.3 V CMOS INTEGRATED JITTER 19.44 MHz Output 25 MHz Output Min Typ Max Unit 0.175 0.153 ps rms ps rms 0.184 0.160 ps rms ps rms Test Conditions/Comments Jitter integration bandwidth = 12 kHz to 5 MHz Jitter integration bandwidth = 12 kHz to 5 MHz OUT2 AND OUT3 CHANNELS ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25C, unless otherwise noted. Frequency multiplier (x2) at PLL input enabled. Table 3. Parameter HSTL INTEGRATED JITTER Jitter Integration Bandwidth = 10 kHz to 10 MHz 155.52 MHz Output 156.25 MHz Output 160 MHz Output Jitter Integration Bandwidth = 12 kHz to 20 MHz 155.52 MHz Output 156.25 MHz Output 160 MHz Output Jitter Integration Bandwidth = 1.875 MHz to 20 MHz 155.52 MHz Output 156.25 MHz Output 160 MHz Output Min Typ Max Unit Test Conditions/Comments 0.244 0.234 1.290 ps rms ps rms ps rms Frequency multiplier (x2) at PLL input bypassed 0.470 0.243 1.329 ps rms ps rms ps rms Frequency multiplier (x2) at PLL input bypassed 0.409 0.100 1.257 ps rms ps rms ps rms Frequency multiplier (x2) at PLL input bypassed Rev. B | Page 3 of 35 AD9574 Data Sheet OUT4 AND OUT5 CHANNELS ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25C. Frequency multiplier (x2) at PLL input enabled unless otherwise indicated. Table 4. Parameter HSTL INTEGRATED JITTER Jitter Integration Bandwidth = 10 kHz to 10 MHz 38.88 MHz Output 77.76 MHz Output 80 MHz Output 100 MHz Output 125 MHz Output 160 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 12 kHz to 20 MHz 77.76 MHz Output 80 MHz Output 100 MHz Output 125 MHz Output 160 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 50 kHz to 80 MHz 312.5 MHz Output Jitter Integration Bandwidth = 1.875 MHz to 20 MHz 77.76 MHz Output 80 MHz Output 100 MHz Output 125 MHz Output 160 MHz Output 312.5 MHz Output HIGH SPEED CURRENT SINKING LOGIC (HCSL) INTEGRATED JITTER Jitter Integration Bandwidth = 10 kHz to 10 MHz 100 MHz Output 125 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 12 kHz to 20 MHz 100 MHz Output 125 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 50 kHz to 80 MHz 312.5 MHz Output Jitter Integration Bandwidth = 1.875 MHz to 20 MHz 100 MHz Output 125 MHz Output 312.5 MHz Output Min Typ Max Unit 0.251 0.245 1.267 ps rms ps rms ps rms 0.240 0.228 1.277 ps rms ps rms ps rms 0.234 ps rms 0.488 1.314 ps rms ps rms 0.252 0.233 1.321 ps rms ps rms ps rms 0.236 ps rms 0.389 ps rms 0.430 1.242 ps rms ps rms 0.115 0.089 1.248 ps rms ps rms ps rms 0.072 ps rms Test Conditions/Comments Input = crystal oscillator Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Input = crystal oscillator 0.238 0.226 0.240 ps rms ps rms ps rms 0.255 0.233 0.243 ps rms ps rms ps rms 0.445 ps rms 0.131 0.098 0.082 ps rms ps rms ps rms Rev. B | Page 4 of 35 Data Sheet AD9574 Parameter LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) INTEGRATED JITTER Jitter Integration Bandwidth = 10 kHz to 10 MHz 38.88 MHz Output 77.76 MHz Output 80 MHz Output Min Typ Max Unit 0.396 0.270 1.304 ps rms ps rms ps rms 0.247 0.234 1.314 ps rms ps rms ps rms 0.246 ps rms 0.529 1.360 ps rms ps rms 0.267 0.243 1.357 ps rms ps rms ps rms 0.249 ps rms 0.473 ps rms 0.474 1.289 ps rms ps rms 100 MHz Output 125 MHz Output 160 MHz Output 0.149 0.109 1.284 ps rms ps rms ps rms 312.5 MHz Output 0.082 ps rms 100 MHz Output 125 MHz Output 160 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 12 kHz to 20 MHz 77.76 MHz Output 80 MHz Output 100 MHz Output 125 MHz Output 160 MHz Output 312.5 MHz Output Jitter Integration Bandwidth = 50 kHz to 80 MHz 312.5 MHz Output Jitter Integration Bandwidth = 1.875 MHz to 20 MHz 77.76 MHz Output 80 MHz Output Test Conditions/Comments Input = crystal oscillator Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed Frequency multiplier (x2) at PLL input bypassed OUT6 CHANNEL ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25C, unless otherwise noted. Frequency multiplier (x2) at PLL input enabled. Cycle to cycle jitter magnitude varies with respect to the clock edge (rising or falling). Table 5 entries indicate jitter for the worst edge (rising or falling). The better edge typically offers a factor of 2 improvement over the tabulated jitter. Table 5. Parameter LVDS CYCLE TO CYCLE JITTER 66.6 MHz Output 133.3 MHz Output 1.8 V CMOS CYCLE TO CYCLE JITTER 66.6 MHz Output 133.3 MHz Output 3.3 V CMOS CYCLE TO CYCLE JITTER 33.3 MHz Output 66.6 MHz Output 133.3 MHz Output Min Typ Max Unit 210 353 ps p-p ps p-p 234 363 ps p-p ps p-p 28 207 360 ps p-p ps p-p ps p-p Test Conditions/Comments 1000 cycles 1000 cycles 1000 cycles Rev. B | Page 5 of 35 AD9574 Data Sheet CLOCK OUTPUTS (OUT0_x TO OUT6_x)--STATIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 6. Parameter HSTL (OUT0_x TO OUT5_x ONLY) Differential Output Voltage Swing Min Typ Max Unit 745 955 1235 mV Common-Mode Output Voltage HCSL (OUT4_x AND OUT5_x ONLY) Differential Output Voltage Swing 745 950 1010 mV 570 700 830 mV 295 360 430 mV 247 350 454 mV 1.125 1.25 50 1.375 50 24 mV V mV mA Output shorted to GND 0.1 V V ILOAD = 1 mA ILOAD = 1 mA 0.5 V V ILOAD = 10 mA ILOAD = 10 mA Common-Mode Output Voltage LVDS (OUT4_x TO OUT6_x ONLY) Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) 1.8 V CMOS (OUT6_x ONLY) Output High Voltage (VOH) Output Low Voltage (VOL) 3.3 V CMOS (OUT0_x, OUT1_x, AND OUT6_x ONLY) Output High Voltage (VOH) Output Low Voltage (VOL) 1 14 1.7 VDD1 - 0.5 Test Conditions/Comments 100 termination (differential) Magnitude of voltage across pins; output driver static Output driver static 50 from each output pin to GND Magnitude of voltage across pins; output driver static Output driver static 100 termination (differential) Magnitude of voltage across pins; output driver static VDD is the supply of all VDD_x pins. CLOCK OUTPUTS (OUT0_x TO OUT6_x)--DYNAMIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Rise and fall time measurement thresholds are 20% and 80% of the nominal low and high amplitude of the waveform. Table 7. Parameter HSTL (OUT1_x TO OUT5_x ONLY) OUT0_x and OUT1_x Output Rise Time, tRL Output Fall Time, tFL OUT2_x to OUT5_x Output Rise Time, tRP Output Fall Time, tFP Duty Cycle OUT0_x and OUT1_x Min Typ Max Unit 161 164 195 193 232 226 ps ps 114 111 144 143 175 177 ps ps 45 55 % OUT2_x to OUT5_x HCSL (OUT4_x AND OUT5_x ONLY) Output Rise Time, tRL Output Fall Time, tFL Duty Cycle 45 55 % 221 238 55 ps ps % Test Conditions/Comments 100 termination (differential) Measured differentially Measured differentially 195 188 45 206 211 Rev. B | Page 6 of 35 Assumes 50% reference input duty cycle; duty cycle specification does not apply to OUT0_x for 38.88 MHz and 50 MHz operation 50 from each output pin to GND Measured differentially Measured differentially Data Sheet Parameter LVDS (OUT4_x TO OUT6_x ONLY) OUT4_x, OUT5_x Output Rise Time, tRL Output Fall Time, tFL OUT6_x Output Rise Time, tRL Output Fall Time, tFL Duty Cycle OUT4_x, OUT5_x OUT6_x 1.8 V CMOS (OUT6_x ONLY) Output Rise Time, tRC Output Fall Time, tFC Duty Cycle 3.3 V CMOS (OUT0_x, OUT1_x, AND OUT6_x ONLY) Output Rise Time, tRC Output Fall Time, tFC Duty Cycle OUT0_x OUT1_x OUT6_x AD9574 Min Typ Max Unit Test Conditions/Comments 100 termination (differential) 151 152 193 195 238 242 ps ps Measured differentially Measured differentially 221 224 242 241 273 270 ps ps Measured differentially Measured differentially 55 55 % % 1.7 1.8 55 ns ns % 45 45 CLOAD = 10 pF 1.2 1.2 45 CLOAD = 10 pF 0.5 0.6 1.0 1.1 ns ns 45 55 % 45 45 55 55 % % Not applicable for 38.88 MHz and 50 MHz operation MONITOR CLOCK INPUTS (MCLK_x)--STATIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 8. Parameter DIFFERENTIAL INPUT MODE Common-Mode Internally Generated Bias Voltage Common-Mode Voltage Tolerance Differential Input Capacitance Differential Input Resistance SINGLE-ENDED INPUT CMOS MODE Hysteresis Input Resistance Input Capacitance Input High Voltage Input Low Voltage Min Typ Max 1.192 0.6 Unit Test Conditions/Comments V 1.5 V 2 5 pF k 230 1 2 mV M pF V V 2 1.2 Rev. B | Page 7 of 35 The acceptable common-mode range for a 200 mV p-p dc-coupled input signal AD9574 Data Sheet MONITOR CLOCK INPUTS (MCLK_x)--DYNAMIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 9. Parameter DIFFERENTIAL INPUT MODE Input Sensitivity Minimum Input Slew Rate Duty Cycle SINGLE-ENDED INPUT CMOS MODE Duty Cycle Min Typ Max Unit Test Conditions/Comments 100 50 40 Ensures proper device function when using a sinusoidal source 60 mV p-p V/s % 40 60 % REFERENCE INPUTS (REF0_x AND REF1_x)--STATIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 10. Parameter DIFFERENTIAL INPUT MODE Common-Mode Internally Generated Bias Voltage Common-Mode Voltage Tolerance Differential Input Capacitance Differential Input Resistance SINGLE-ENDED INPUT CMOS MODE Hysteresis Input Resistance Input Capacitance Input High Voltage Input Low Voltage Min Typ Max 1.218 0.650 Unit Test Conditions/Comments V 1.8 V 2 4.3 pF k 220 1 2 mV M pF V V 2 1.2 The acceptable common-mode range for a 200 mV p-p dc-coupled input signal REFERENCE INPUTS (REF0_x AND REF1_x)--DYNAMIC Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 11. Parameter DIFFERENTIAL INPUT MODE Input Sensitivity Minimum Input Slew Rate Duty Cycle PLL x2 Multiplier Bypass PLL x2 Multiplier Active OUT0 x2 Multiplier Active SINGLE-ENDED INPUT CMOS MODE Duty Cycle PLL x2 Multiplier Bypass PLL x2 Multiplier Active OUT0 x2 Multiplier Active Min Typ Max 200 100 Unit mV p-p V/s 40 40 40 60 60 60 % % % 40 40 40 60 60 60 % % % Rev. B | Page 8 of 35 Test Conditions/Comments Minimum limit imposed for jitter performance (when using a sinusoidal source, for example) Ensures OUT0_x duty cycle limits with OUT0 x2 multiplier enabled Data Sheet AD9574 REFERENCE SWITCHOVER OUTPUT DISTURBANCE Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 12. Parameter INSTANTANEOUS FREQUENCY (d/dt) DISTURBANCE DUE TO REFERENCE SWITCHOVER INSTANTANEOUS PHASE DISTURBANCE DUE TO REFERENCE SWITCHOVER Min Typ 250 Max 500 220 Unit ppm pk ps Test Conditions/Comments Applies only to PLL outputs; 1 ppm frequency offset between the REF0 and REF1 channels Applies to OUT0 and OUT1 with OUT0 x2 multiplier bypassed CONTROL PINS Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 13. Parameter INPUT CHARACTERISTICS REF_SEL Pin Logic 1 Voltage (VIH) Logic 0 Voltage (VIL) Logic 1 Current (IIH) Logic 0 Current (IIL) RESET Pin Logic 1 Voltage (VIH) Logic 0 Voltage (VIL) Logic 1 Current (IIH) Logic 0 Current (IIL) REFMON Pin Logic 1 Voltage (VIH) Logic 0 Voltage (VIL) Logic 1 Current (IIH) Logic 0 Current (IIL) PPR0 to PPR6 Pins PPRx State 0 PPRx State 1 PPRx State 2 PPRx State 3 PPRx State 4 PPRx State 5 PPRx State 6 PPRx State 7 Min Typ Max Unit 0.8 150 150 V V A A 0.8 350 350 V V A A 0.5 150 150 V V A A Test Conditions/Comments Internal 30 k pull-down resistor 2.0 2.0 VDD - 0.5 820 1800 3900 8200 820 1800 3900 8200 Rev. B | Page 9 of 35 VIH = VDD VIL = GND Internal 30 k pull-up resistor VIH = VDD VIL = GND Do not float this pin or toggle it during device operation; connect to a static Logic 0 or Logic 1 VIH = VDD VIL = GND Maximum resistor tolerance = 10% Pull-down to GND Pull-down to GND Pull-down to GND Pull-down to GND Pull-up to VDD Pull-up to VDD Pull-up to VDD Pull-up to VDD AD9574 Data Sheet STATUS PINS Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 14. Parameter OUTPUT CHARACTERISTICS LD Pin Logic 1 Voltage Logic 0 Voltage REF_ACT Pin Logic 1 Voltage Logic 0 Voltage REF_SW Pin Logic 1 Voltage Logic 0 Voltage REF_FHI Pin Logic 1 Voltage Logic 0 Voltage REF_FLO Pin Logic 1 Voltage Logic 0 Voltage Min Typ Max Unit 0.8 V V 0.8 V V 0.8 V V 2.0 2.0 2.0 Test Conditions/Comments ILOAD = 1 mA (source or sink) Internal 30 k pull-down resistor 2.0 0.8 V V 0.8 V V Internal 30 k pull-down resistor 2.0 POWER SUPPLY AND DISSIPATION Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. Table 15. Parameter POWER SUPPLY VOLTAGE POWER DISSIPATION Typical Configuration All Blocks Running Min 2.97 Typ 3.3 Max 3.63 Unit V Test Conditions/Comments 466 569 654 mW 579 698 803 mW PPR0 State 0 (REF0_x: 25 MHz, 3.3 V CMOS buffer; REF1_x: no connection) PPR1 State 0 (PLL input x2: off; OUT2: 156.25 MHz, HSTL; OUT3: 156.25 MHz, HSTL) PPR2 State 7 (OUT0: 25 MHz, HSTL, x2 off; OUT1: disabled) PPR3 State 0 (OUT4: 100 MHz, HSTL; OUT5: 125 MHz, HSTL) PPR4 State 5 (OUT6: 66.67 MHz, 3.3 V CMOS) PPR5 State 0 (reference monitor threshold: not applicable (25 ppm)) PPR6 State 0 (MCLK_x: no connection (19.44 MHz differential)) REFMON: GND PPR0 State 4 (REF0_x: 25 MHz, differential; REF1_x: 25 MHz, differential) PPR1 State 0 (PLL input x2: off; OUT2: 156.25 MHz, HSTL; OUT3: 156.25 MHz, HSTL) PPR2 State 2 (OUT0: 50 MHz, 3.3 V CMOS, x2 on; OUT1: 25 MHz, 3.3 V CMOS) PPR3 State 2 (OUT4: 100 MHz, HCSL; OUT5: 125 MHz, HSTL) PPR4 State 1 (OUT6: 133.33 MHz, 3.3 V CMOS) PPR5 State 6 (reference monitor threshold: 100 ppm) PPR6 State 4 (MCLK_x: 38.88 MHz, differential) REFMON: VDD Rev. B | Page 10 of 35 Data Sheet Parameter Minimal Power Configuration Incremental Power Dissipation Input Reference On/Off Single-Ended Differential Output Driver On/Off LVDS (at 312.5 MHz) HSTL (at 156.25 MHz) 1.8 V CMOS (at 66 MHz) 3.3 V CMOS (at 25 MHz) Other Blocks On/Off OUT0 x2 On/Off POWER SUPPLY CURRENT (ISUPPLY) Typical Configuration All Blocks Running Configuration Minimal Power Configuration 1 AD9574 Min 346 Typ 422 Max 486 Unit mW Test Conditions/Comments PPR0 State 0 (REF0_x: 19.44 MHz, 3.3 V CMOS buffer; REF1_x: 19.44 MHz, 3.3 V CMOS buffer) PPR1 State 4 (PLL input x2: off, OUT2: 155.52 MHz, HSTL; OUT3: 155.52 MHz, HSTL) PPR2 State 4 (OUT0: disabled; OUT1: disabled) PPR3 State 7 (OUT4: disabled; OUT5: disabled) PPR4 State 0 (OUT6: disabled) PPR5 State 0 (reference monitor threshold: not applicable (25 ppm) PPR6 State 1 (MCLK_x: no connection (19.44 MHz, 3.3 V CMOS buffer)) REFMON: GND Typical configuration; values show the change in power due to the indicated operation Applies to one reference clock input 0.23 20.5 0.30 25.1 0.36 30.0 mW mW 18.1 30.6 13.7 22.5 36.6 16.2 27.2 42.5 19.2 mW mW mW A single 1.8 V CMOS output with an 10 pF load 9.5 12.2 15.2 mW A single 3.3 V CMOS output with an 10 pF load 3.1 4.0 5.4 mW Total supply current for VDD_x pins1 in aggregate 157 195 172 212 180 221 mA mA For power dissipation with typical configuration settings For power dissipation with all blocks running configuration settings 117 128 134 mA For power dissipation with minimal power configuration settings VDD_x pins include VDD_REF0, VDD_REF1, VDD_OUT01, VDD_PLL, VDD_VCO, VDD_RFDIV, VDD_OUT6, VDD_OUT4, VDD_OUT5, VDD_OUT23, and VDD_MCLK. TIMING SPECIFICATIONS Typical is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. The indicated times assume the voltage applied to all 3.3 V power supply pins is within specification and stable. Table 16. Parameter MONITOR CLOCK INPUT TO REF_FHI/REF_FLO TIME fMCLK = 8 kHz fMCLK = 10 MHz fMCLK = 19.44 MHz fMCLK = 25 MHz fMCLK = 38.88 MHz Min Typ Max Unit 4200 3400 1800 1400 870 ms ms ms ms ms Test Conditions/Comments Elapsed time from the first rising edge of the monitor clock input signal to the valid reference status as indicated by the REF_FHI and REF_FLO pins (the active reference must be stable) Rev. B | Page 11 of 35 AD9574 Data Sheet Parameter OUTPUT READY TIME OUT0 to OUT1 Min OUT2 to OUT6 PPR1 State 0 PPR1 State 1 PPR1 State 2 PPR1 State 3 PPR1 State 4 PPR1 State 5 PPR1 State 6 PPR1 State 7 Typ Max Unit Test Conditions/Comments 0.2 ms Typical start-up time of the external crystal oscillator dominates the output ready time of the OUT0 and OUT1 channels Time interval from RESET pin = Logic 1 to LD pin = Logic 1 (PLL lock detection) 5.0 2.8 5.0 2.8 6.4 3.6 22.3 11.5 ms ms ms ms ms ms ms ms TIMING DIAGRAMS DIFFERENTIAL SINGLE-ENDED 80% 80% LVDS/HSTL/HCSL CMOS 10pF LOAD tFC 07501-002 tRC tRL tFL Figure 3. LVDS, HSTL, HCSL Timing, Differential Figure 2. CMOS Timing, Single-Ended, 10 pF Load Rev. B | Page 12 of 35 07501-003 20% 20% Data Sheet AD9574 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 17. Parameter VDD_x to GND Junction Temperature1 Storage Temperature Range 1 Rating -0.3 V to +3.6 V 150C -65C to +150C See the Thermal Performance section for details on junction temperature. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 13 of 35 AD9574 Data Sheet AD9574 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VDD_OUT23 REF_FHI REF_FLO OUT5_N OUT5_P VDD_OUT5 VDD_OUT4 OUT4_P OUT4_N PPR3 PPR4 REFMON VDD_PLL LD LF LDO_BYP VDD_VCO VDD_RFDIV PPR6 RESET OUT6_N OUT6_P VDD_OUT6 PPR5 13 14 15 16 17 18 19 20 21 22 23 24 REF0_P 1 REF0_N 2 VDD_REF0 3 VDD_REF1 4 REF1_N 5 REF1_P 6 PPR2 7 VDD_OUT01 8 OUT0_N 9 OUT0_P 10 OUT1_P 11 OUT1_N 12 07501-004 48 47 46 45 44 43 42 41 40 39 38 37 REF_SEL PPR0 MCLK_N MCLK_P REF_ACT REF_SW VDD_MCLK PPR1 OUT3_N OUT3_P OUT2_P OUT2_N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED DIE PAD MUST BE CONNECTED TO THE POWER SUPPLY COMMON (GND). Figure 4. Pin Configuration Table 18. Pin Function Descriptions Pin No. 1 Mnemonic REF0_P Input/Output Input 2 REF0_N Input 3 VDD_REF0 Input Pin Type Configurable clock input Configurable clock input Power 4 VDD_REF1 Input Power 5 REF1_N Input 6 REF1_P Input 7 PPR2 Input Configurable clock input Configurable clock input Control 8 VDD_OUT01 Input Power 9 OUT0_N Output 10 OUT0_P Output 11 OUT1_P Output 12 OUT1_N Output 13 14 15 VDD_PLL LD LF Input Output Input/Output Configurable clock output Configurable clock output Configurable clock output Configurable clock output Power 3.3 V CMOS Analog 16 LDO_BYP Output Analog Description Reference Clock Input 0, Positive. Configurable via PPR0 (Pin 47). Reference Clock Input 0, Negative. Configurable via PPR0 (Pin 47). 3.3 V Input Supply for Reference Clock Input 0 (REF0_x). This pin supplies the single-ended input receiver and internal low dropout (LDO) regulator for the differential receiver. 3.3 V Input Supply for Reference Clock Input 1 (REF1_x). This pin supplies the single-ended input receiver and internal LDO regulator for the differential receiver. Reference Clock Input 1, Negative. Configurable via PPR0 (Pin 47). Reference Clock Input 1, Positive. Configurable via PPR0 (Pin 47). Pin Program Reader 2. Connect a resistor to this pin to configure the OUT0 and OUT1 channels (see the PPR2--OUT0 and OUT1 Configuration section for more information). 3.3 V Supply. 3.3 V input for the CMOS drivers of OUT0_x and OUT1_x and the source for an internal 1.8 V LDO regulator for the differential drivers of OUT0_x and OUT1_x. Clock Output 0, Negative. Configurable via PPR2 (Pin 7). Clock Output 0, Positive. Configurable via PPR2 (Pin 7). Clock Output 1, Positive. Configurable via PPR2 (Pin 7). Clock Output 1, Negative. Configurable via PPR2 (Pin 7). 3.3 V Input to the Internal LDO Regulator for the PLL. PLL Lock Detector Status. Logic 0 = unlocked; Logic 1 = locked. Loop Filter. Connect a capacitor or series RC network (see Table 32) from this pin to LDO_BYP (Pin 16). LDO Bypass. Connect a 470 nF capacitor from this pin to GND. Rev. B | Page 14 of 35 Data Sheet AD9574 Pin No. 17 18 19 Mnemonic VDD_VCO VDD_RFDIV PPR6 Input/Output Input Input Input Pin Type Power Power Control 20 RESET Input 3.3 V CMOS 21 OUT6_N Output 22 OUT6_P Output 23 VDD_OUT6 Input Configurable clock output Configurable clock output Power 24 PPR5 Input Control 25 REFMON Input Control 26 PPR4 Input Control 27 PPR3 Input Control 28 OUT4_N Output 29 OUT4_P Output 30 VDD_OUT4 Input Configurable clock output Configurable clock output Power 31 VDD_OUT5 Input Power 32 OUT5_P Output 33 OUT5_N Output 34 REF_FLO Output Configurable clock output Configurable clock output 3.3 V CMOS 35 REF_FHI Output 3.3 V CMOS 36 VDD_OUT23 Input Power 37 OUT2_N Output 38 OUT2_P Output 39 OUT3_P Output 40 OUT3_N Output 41 PPR1 Input Configurable clock output Configurable clock output Configurable clock output Configurable clock output Control 42 VDD_MCLK Input Power Description 3.3 V Supply. 3.3 V input to the internal LDO regulator for the VCO. 3.3 V Supply. 3.3 V input to the internal LDO regulator for the VCO RF dividers. Pin Program Reader 6. Connect a resistor to this pin to configure the MCLK_x input (see the PPR6--Monitor Clock (MCLK_x) Input Configuration section for more information). Reset. Logic 0 (GND) initializes the device to its default state (see the PPRx Pins section for details). This pin has an internal 30 k pull-up resistor. Clock Output 6, Negative. Configurable via PPR4 (Pin 26). Clock Output 6, Positive. Configurable via PPR4 (Pin 26). 3.3 V Supply. 3.3 V input for the CMOS drivers of OUT6_x and the source for an internal 1.8 V LDO regulator for the 1.8 V CMOS drivers and differential drivers of OUT6_x. Pin Program Reader 5. Connect a resistor to this pin to configure the reference clock frequency error threshold (see the PPR5--Reference Monitor Threshold section for more information). Reference Frequency Monitor Enable/Disable. Do not float this pin or toggle it during device operation. Connect it to a static Logic 0 or Logic 1. Pin Program Reader 4. Connect a resistor to this pin to configure the OUT6 channel (see the PPR4--OUT6 Configuration section for more information). Pin Program Reader 3. Connect a resistor to this pin to configure the OUT4 and OUT5 channels (see the PPR3--OUT4 and OUT5 Configuration section for more information). Clock Output 4, Negative. Configurable via PPR3 (Pin 27). Clock Output 4, Positive. Configurable via PPR3 (Pin 27). 3.3 V Supply. 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT4_x. 3.3 V Supply. 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT5_x. Clock Output 5, Positive. Configurable via PPR3 (Pin 27). Clock Output 5, Negative. Configurable via PPR3 (Pin 27). Low Reference Frequency Status Indicator. A Logic 1 indicates that the reference frequency is below the lower threshold limit (see the Reference Monitor section for details). This pin is an open-drain output with an internal 30 k pull-down resistor. High Reference Frequency Status Indicator. A Logic 1 indicates that the reference frequency is above the upper threshold limit (see the Reference Monitor section for details). This pin is an open-drain output with an internal 30 k pull-down resistor. 3.3 V Supply. 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT2_x and OUT3_x. Clock Output 2, Negative (HSTL). Configurable via PPR2 (Pin 7). Clock Output 2, Positive (HSTL). Configurable via PPR2 (Pin 7). Clock Output 3, Positive (HSTL). Configurable via PPR2 (Pin 7). Clock Output 3, Negative (HSTL). Configurable via PPR2 (Pin 7). Pin Program Reader 1. Connect a resistor to this pin to select a predefined frequency translation configuration (see the PPR1--Frequency Translation Settings section for more information). 3.3 V Supply. 3.3 V input for Reference Monitor Clock 0 (MCLK_x). This pin supplies the single-ended input receiver and internal LDO regulator for the differential receiver. Rev. B | Page 15 of 35 AD9574 Data Sheet Pin No. 43 Mnemonic REF_SW Input/Output Output Pin Type 3.3 V CMOS 44 REF_ACT Output 3.3 V CMOS 45 MCLK_P Input 46 MCLK_N Input 47 PPR0 Input Configurable monitor clock input Configurable monitor clock input Control 48 REF_SEL Input 3.3 V CMOS EP Input GND Description Reference Switchover Status Indicator. This pin indicates when the device is in the process of switching references (see the Reference Monitor section for more information). Reference Active Status Indicator. This pin indicates whether REF0 or REF1 is the active reference (see the Reference Monitor section for more information). Reference Monitor Clock Normal Input. Configurable via PPR6 (Pin 18). Reference Monitor Clock Complementary Input. Configurable via PPR6 (Pin 18). Pin Program Reader 0. Connect a resistor to this pin to configure the reference clock inputs (see the PPR0--Reference Clock Input Configuration section for more information). Reference Clock Select. The pin selects Input Reference Clock 0 or Input Reference Clock 1 as the internal reference clock source (Logic 0 or Logic 1, respectively). This pin has an internal 30 k pull-down resistor. Exposed Pad. The exposed die pad must be connected to the power supply common (GND). Rev. B | Page 16 of 35 Data Sheet AD9574 TYPICAL PERFORMANCE CHARACTERISTICS PHASE NOISE AND VOLTAGE WAVEFORMS VDD = nominal, TA = 25C. The only enabled output channels are those indicated in the figure captions. The phase noise plots (see Figure 5 to Figure 9) show the Taitien XO A0145-L-006-3 phase noise normalized to the output frequency. The voltage waveform plots (see Figure 10 to Figure 16) embody ac coupling to the measurement instrument. -110 -100 HSTL CMOS 3.3V TAITIEN XO A0145-L-006-3 RMS JITTER HSTL: 0.197ps CMOS: 0.195ps INTEGRATION BANDWIDTH: 12kHz TO 20MHz -130 -140 -150 -160 HSTL TAITIEN XO A0145-L-006-3 -120 -130 -140 -150 10k 1k 100k 1M 10M FREQUENCY OFFSET (Hz) -170 100 PHASE NOISE (dBc/Hz) HSTL HCSL TAITIEN XO A0145-L-006-3 -140 -150 HSTL TAITIEN XO A0145-L-006-3 -120 -130 -140 -150 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -170 100 07501-006 1k 1k 100k 10k 1M 100M 10M FREQUENCY OFFSET (Hz) Figure 6. Phase Noise (OUT4)--fOUT4 = 100 MHz, fOUT5 = 125 MHz 07501-009 -160 Figure 9. Phase Noise (OUT5)--fOUT4 = 100 MHz, fOUT5 = 125 MHz 1.25 -90 25MHz RMS JITTER HSTL: 0.230ps HCSL: 0.245ps LVDS: 0.254ps INTEGRATION BANDWIDTH: 12kHz TO 20MHz -110 0.75 -120 -130 -140 HSTL HCSL LVDS TAITEN XO A0145-L-006-3 10k 100k 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 1M 10M FREQUENCY OFFSET (Hz) 100M 07501-007 1k 312.5MHz 1.00 OUTPUT VOLTAGE (V) -100 -1.25 0 5 10 15 20 25 30 TIME (ns) 35 40 45 Figure 10. Output Waveform, HSTL (25 MHz, 312.5 MHz) Figure 7. Phase Noise (OUT4)--fOUT4 = 312.5 MHz Rev. B | Page 17 of 35 50 07501-010 PHASE NOISE (dBc/Hz) -120 -130 RMS JITTER HSTL: 0.228ps INTEGRATION BANDWIDTH: 12kHz TO 20MHz -110 -160 PHASE NOISE (dBc/Hz) 100M 10M -100 RMS JITTER HSTL: 0.245ps HCSL: 0.244ps INTEGRATION BANDWIDTH: 12kHz TO 20MHz -110 -160 100 1M Figure 8. Phase Noise (OUT2)--fOUT2 = 156.25 MHz -100 -150 100k 10k FREQUENCY OFFSET (Hz) Figure 5. Phase Noise (OUT0)--fOUT0 = 25 MHz -170 100 1k 07501-008 -160 07501-005 -170 100 RMS JITTER HSTL: 0.234ps INTEGRATION BANDWIDTH: 12kHz TO 20MHz -110 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -120 AD9574 Data Sheet 1.00 0.5 100MHz 312.5MHz 66.67MHz 312.5MHz 0.4 0.75 0.3 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.50 0.25 0 -0.25 0.2 0.1 0 -0.1 -0.2 -0.50 -0.3 -0.75 0 1 2 3 4 5 6 7 8 9 10 11 12 13 TIME (ns) -0.5 07501-011 -1.00 0 5 10 15 20 25 30 TIME (ns) Figure 11. Output Waveform, HCSL (100 MHz, 312.5 MHz) 07501-014 -0.4 Figure 14. Output Waveform, LVDS (66.67 MHz, 312.5 MHz) 1.0 2.5 1.5 0.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.0 66.67MHz, 2pF_P 66.67MHz, 2pF_N 0 66.67MHz, 10pF_P 66.67MHz, 10pF_N -0.5 1.0 0.5 25MHz, 2pF_P 0 25MHz, 10pF_P 25MHz, 2pF_N -0.5 25MHz, 10pF_N -1.0 -1.5 5 10 15 20 25 30 TIME (ns) -2.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 TIME (ns) Figure 12. Output Waveform, 1.8 V CMOS (66.67 MHz) 07501-315 0 07501-012 -2.0 -1.0 Figure 15. Output Waveform, 3.3 V CMOS (25 MHz) 2.5 1.0 133.3MHz, 2pF_P 133.3MHz, 10pF_P 133.3MHz, 2pF_N 133.3MHz, 10pF_N 2.0 OUTPUT VOLTAGE (V) 133.3MHz, 2pF_P 133.3MHz, 2pF_N 0 133.3MHz, 10pF_P 133.3MHz, 10pF_N -0.5 1.0 0.5 0 -0.5 -1.0 -2.0 -2.5 -1.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 TIME (ns) 14 0 5 10 15 TIME (ns) Figure 16. Output Waveform, 3.3 V CMOS (133.3 MHz) Figure 13. Output Waveform, 1.8 V CMOS (133.3 MHz) Rev. B | Page 18 of 35 20 07501-316 -1.5 07501-013 OUTPUT VOLTAGE (V) 1.5 0.5 Data Sheet AD9574 REFERENCE SWITCHING FREQUENCY AND PHASE DISTURBANCE 50000 45000 40000 35000 30000 25000 20000 15000 5000 0 -5000 -10000 -15000 -20000 -25000 -30000 -35000 -40000 -45000 -1.5 2.0 -1 PPM REFERENCE FREQUENCY OFFSET RELATIVE PHASE (Degrees) 1.5 -0.5 0.5 1.5 RELATIVE PHASE (Degrees) 10 DEGREES 3 2 1 0 -1 -2 -3 -4 -5 -6 0.1 RELATIVE TIME (s) 0.2 0.3 07501-115 1 DEGREE = 17.78ps 0 -0.1 0 0.1 0.2 0.3 Figure 19. Reference Switchover Phase Disturbance for OUT0 at 25 MHz with Output x2 Multiplier Bypassed (PPR0 = 0, PPR1 = 1, PPR2 = 3, PPR3 = 2, PPR4 = 1, PPR5 = 7, PPR6 = 7) 6 -0.1 -1.0 RELATIVE TIME (s) 7 -7 -0.2 -0.5 1 DEGREE = 111.1ps 2.5 Figure 17. Reference Switchover Frequency Disturbance for OUT2 at 156.25 MHz (PPR0 = 0, PPR1 = 1, PPR2 = 2, PPR3 = 0, PPR4 = 0, PPR5 = 0, PPR6 = 2) 5 0 -2.0 -0.2 RELATIVE TIME (s) 4 1.5 DEGREES 0.5 07501-215 +1 PPM REFERENCE FREQUENCY OFFSET 1.0 -1.5 07501-113 FREQUENCY DEVIATION (Hz) VDD = nominal, TA = 25C. The only enabled output channels are those indicated in the figure captions. The reference switchover phase disturbance plots (see Figure 18 and Figure 19) each show a collection of output phase variations due to approximately 250 reference switching events between two references with a frequency offset of approximately 2 ppm. Each reference switch event (initiated by toggling the REF_SEL pin) occurs at a random phase offset between the two references. The plots demonstrate the tightly controlled phase disturbance at the output as a result of the reference switching logic seeking the optimal moment to switch references. Figure 18. Reference Switchover Phase Disturbance for OUT3 at 156.25 MHz (PPR0 = 0, PPR1 = 1, PPR2 = 3, PPR3 = 2, PPR4 = 1, PPR5 = 7, PPR6 = 7) Rev. B | Page 19 of 35 AD9574 Data Sheet TERMINOLOGY Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution. This phase jitter leads to the energy of the sine wave spreading out in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Phase Noise When the total power contained within some interval of offset frequencies (for example, 12 kHz to 20 MHz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. B | Page 20 of 35 Data Sheet AD9574 OUT0_P OUT0_N OUT1_P OUT1_N THEORY OF OPERATION 10 9 11 12 3.3V CMOS REF0_P 1 REF0_N 2 HSTL HSTL x2 37 OUT2_N 16 A HSTL REF. SWITCH REF_SEL 48 38 OUT2_P 3.3V CMOS 39 OUT3_P 40 OUT3_N A MCLK_P LVDS/HCSL/HSTL 45 MCLK_N 46 REFERENCE FREQUENCY MONITOR REF_ACT PLL 1/2, 1, 5/2, 5 REFMON 25 44 REF_SW 43 PFD LOCK DET REF_FHI 35 2488MHz 2500MHz 2560MHz CP LOOP FILTER 29 OUT4_P 28 OUT4_N 2, 4, 5, 8, 16 4 32 OUT5_P VCO 5 50, 64, 100, 128, 256, 512 LVDS/HCSL/HSTL 33 OUT5_N 3.3V CMOS REF_FLO 34 1.8V CMOS REF1_P 6 22 OUT6_P LVDS AD9574 REF1_N 5 3.75 2 2 21 OUT6_N RESET 1.8V CMOS PPR CONTROL 26 24 19 20 PPR1 PPR2 PPR3 PPR4 PPR5 PPR6 RESET 14 15 07501-015 27 LF 7 LD 41 PPR0 3.3V CMOS 47 Figure 20. Detailed Block Diagram OVERVIEW Figure 20 shows a block diagram of the AD9574. The AD9574 accepts a 19.44 MHz or 25 MHz reference clock at the REF0_x and/or REF1_x inputs. It also accepts a 0.008 MHz, 10 MHz, 19.44 MHz, 25 MHz, or 38.88 MHz monitor input clock at the MCLK_x input. The monitor input clock serves as a stable frequency reference for the internal reference frequency monitor of the device. The input clock receivers provide differential or single-ended input configurations. The AD9574 provides up to seven output channel clocks (OUT0 to OUT6). The OUT0 and OUT1 channels provide a replica of the REF0 or REF1 channel frequency with a frequency doubling option for OUT0. The OUT2 through OUT6 channels provide various output frequencies by means of an integrated PLL and divider chains. The output clock drivers provide for a variety of modes including LVDS, HSTL, HCSL, 1.8 V CMOS, and 3.3 V CMOS, although not all modes are available at every output. The integrated PLL provides the necessary frequency translations. The divider block at the input to the PLL consists of a x2 multiplier, a divide-by-5, and a multiplexer configured to provide the four possible divide values (1/2, 1, 5/2, or 5), as shown in Figure 20. PPRx PINS The AD9574 makes use of seven PPRx pins to configure the device. Internal circuitry scans the PPRx pins for the presence of resistor terminations and configures the device accordingly. A PPRx pin scan occurs automatically as part of the power-on reset sequence (see the Power-On Reset (POR) section) or following assertion of the RESET pin. Each PPRx pin controls a specific function or functional block within the device (see Table 19). The configuration of a functional block depends on the scanned state of the corresponding PPRx pin. The scan of a PPRx pin identifies one of eight possible states based on an external pull-up or pull-down resistor (maximum 10% tolerance) per Table 20. Rev. B | Page 21 of 35 AD9574 Data Sheet Table 19. PPRx Pin Function Assignments PPR0--Reference Clock Input Configuration Mnemonic PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 Pin No. 47 41 7 27 26 24 The PPR0 pin controls the configuration of the reference clock inputs (REF0_x and REF1_x). The selected PPR0 state applies to both references (REF0_x and REF1_x). Table 21 associates each PPR0 state with a particular reference input configuration. PPR6 19 Function Assignment Reference input configuration Frequency translation settings OUT0 and OUT1 channel configuration OUT4 and OUT5 channel configuration OUT6 channel configuration Reference clock frequency monitor error threshold Monitor clock (MCLK_x) input configuration Device programming consists of connecting the appropriate value programming resistors to the PPRx pins and terminating the resistors to VDD or GND (per Table 20). For example, Figure 21 shows how to program PPR0 to State 3. Table 20. PPRx State PPRx State 0 1 2 3 4 5 6 7 Resistance 820 1.8 k 3.9 k 8.2 k 820 1.8 k 3.9 k 8.2 k PPR0 State 0 1 2 3 4 5 6 7 Reference Clock Input Configuration Single-ended 3.3 V CMOS buffer Not applicable Not applicable Not applicable Differential Not applicable Not applicable Not applicable PPR1--Frequency Translation Settings Terminus GND GND GND GND VDD VDD VDD VDD The PPR1 pin allows the user to select from a predefined set of frequency translation groups per Table 22 (with all frequency entries in MHz). The frequency translations apply to the OUT4 and OUT5 channels with respect to the reference frequency (fREF) at the REF0_x or REF1_x inputs. This also establishes the frequency at the OUT2 and OUT3 channels, as shown in Table 22. Note that the frequency translation associated with each PPRx state relies on one of three possible VCO frequencies shown in Table 22. The x2 column in Table 22 indicates the status of the x2 multiplier associated with the divider at the input to the PLL (as explained in the Overview section). The PLL bandwidth column indicates the -3 dB closed-loop bandwidth of the PLL. AD9574 The frequency group for a given PPR1 state defines a pair of OUT4 and OUT5 frequencies. The frequency pair associated with a PPR1 state may apply to the OUT4 or OUT5 channel in any combination. For example, although PPR1 State 0 defines both 100 MHz and 125 MHz output frequencies, OUT4 and OUT5 may be any pairing of the two frequencies: 100 MHz at both output channels, 100 MHz on OUT4 and 125 MHz at OUT5, 125 MHz at OUT4 and 100 MHz at OUT5, or 125 MHz at both output channels. The specific OUT4 and OUT5 frequency assignments depend on the state of PPR3 (see Table 24). See the Output Clocks section for details for the specific frequency translations on a per output basis. 47 07501-016 PPR0 8.2k Table 21. PPR0--Reference Input Options Figure 21. PPRx Programming Resistor Example For details regarding the device configuration based on the scanned PPRx states, see the description of each PPRx pin in the following sections. Table 22. PPR1--Frequency Translation Options PPR1 State 0 1 2 3 4 5 6 7 fREF (MHz) 25 25 25 25 19.44 19.44 25 25 OUT4/OUT5 Frequency (MHz) 100, 125 100,125 125, 312.5 125, 312.5 38.88, 77.76 38.88, 77.76 80, 160 80, 160 x2 Bypass Active Bypass Active Bypass Active Bypass Active PLL Bandwidth (MHz) 0.7 0.6 0.7 0.6 0.6 0.6 0.3 0.6 Rev. B | Page 22 of 35 fVCO 2500 2500 2500 2500 2488 2488 2560 2560 OUT2/OUT3 Frequency (MHz) 156.25 156.25 156.25 156.25 155.52 155.52 160 160 Data Sheet AD9574 PPR2--OUT0 and OUT1 Configuration PPR3--OUT4 and OUT5 Configuration The PPR2 pin allows the user to select from a predefined set of configurations for the OUT0 and OUT1 channels per Table 23. The output configuration includes the type of output driver and a frequency scale factor that indicates whether the output frequency is the same or twice the input reference frequency. See the Output Drivers section for details regarding output driver types. The PPR3 pin allows the user to select from a predefined set of configurations for the OUT4 and OUT5 channels per Table 24. The output configuration includes the frequency (in MHz) and type of output driver assignment (see the Output Drivers section for details regarding output driver types). Note that the state of PPR1 (frequency translation options) determines the frequency pair available for assignment to the OUT4 and OUT5 channels. Table 23. PPR2--OUT0/OUT1 Options OUT0 PPR2 State 0 1 2 3 4 5 6 7 Driver HSTL HSTL 3.3 V CMOS 3.3 V CMOS Disabled 3.3 V CMOS HSTL HSTL OUT1 Scale 1 2 2 1 Not applicable 1 2 1 Driver HSTL HSTL 3.3 V CMOS 3.3 V CMOS Disabled Disabled Disabled Disabled Scale 1 1 1 1 Not applicable Not applicable Not applicable Not applicable Table 24. PPR3--OUT4/OUT5 Options PPR1 0 or 1 2 or 3 4 or 5 6 or 7 PPR State PPR3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Driver HSTL HCSL HCSL LVDS HSTL LVDS HSTL Disabled HSTL LVDS HCSL HSTL LVDS HCSL LVDS HCSL HSTL LVDS LVDS HSTL HSTL LVDS Disabled Disabled HSTL LVDS LVDS Disabled LVDS HSTL Disabled Disabled OUT4 fOUT4 (MHz) 100 100 100 125 125 100 100 Not applicable 312.5 312.5 312.5 312.5 312.5 312.5 312.5 125 38.88 38.88 38.88 38.88 77.76 77.76 Not applicable Not applicable 80 80 80 Not applicable 80 80 Not applicable Not applicable Rev. B | Page 23 of 35 Driver HSTL HCSL HSTL LVDS HSTL HCSL HSTL Disabled HSTL LVDS HCSL HSTL LVDS HCSL HSTL HCSL HSTL LVDS LVDS HSTL HSTL LVDS HSTL Disabled HSTL HSTL LVDS HSTL LVDS HSTL HSTL Disabled OUT5 fOUT5 (MHz) 125 100 125 125 125 100 100 Not applicable 312.5 312.5 312.5 125 125 125 125 125 77.76 77.76 38.88 38.88 77.76 77.76 38.88 Not applicable 80 80 160 80 80 160 160 Not applicable AD9574 Data Sheet PPR4--OUT6 Configuration PPR6--Monitor Clock (MCLK_x) Input Configuration The PPR4 pin allows the user to select from a predefined set of configurations for the OUT6 channel per Table 25. The output configuration includes the frequency (MHz) and type of output driver assignment (see the Output Drivers section for details regarding output driver types). Note that the PPR4 assignments share a dependency with the state of PPR1 (frequency translation options) in that the OUT6 channel is disabled for PPR1 State 2 through State 7. The PPR6 pin controls the configuration of the MCLK_x inputs, which includes a combination of both frequency (MHz) and input type (see the Monitor Clock Input section for details regarding MCLK_x input types). Table 27 associates each PPR6 state with a particular MCLK_x input configuration. Table 25. PPR4--OUT6 Options PPR State PPR4 0 1 2 3 4 5 6 7 2 to 7 0 to 7 PPR1 0 or 1 Driver Disabled 3.3 V CMOS 1.8 V CMOS LVDS LVDS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Disabled OUT6 fOUT6 (MHz) Not applicable 133.3 133.3 133.3 66.67 66.67 66.67 33.33 Not applicable PPR5--Reference Monitor Threshold The PPR5 pin controls the range of the frequency error threshold associated with the reference frequency monitor (see the Reference Monitor section) per Table 26. The threshold has units of parts per million (ppm) relative to the nominal input reference frequency (19.44 MHz or 25 MHz). Table 27. PPR6--MCLK_x Input Options PPR6 State 0 1 2 3 4 5 6 7 MCLK_x Input Configuration Differential Single-ended 3.3 V CMOS buffer Single-ended 3.3 V CMOS buffer Differential Differential Differential Single-ended 3.3 V CMOS buffer Differential Dependency of PPR3 and PPR4 on PPR1 PPR1 defines the input reference frequency, configures the internal PLL to yield certain OUT2 and OUT3 frequencies and establishes the state of the x2 multiplier at the input of the PLL (bypass/active). PPR3 and PPR4 affect the frequency and output driver of the OUT4, OUT5, and OUT6 channels, but with a dependency on the state of PPR1, as summarized in Table 28. With regard to Table 28, the user may select any PPR3 state and any PPR4 state for a given PPR1 state (that is, PPR3 and PPR4 are completely independent of one another). Table 26. PPR5--Reference Monitor Threshold Options PPR5 State 0 1 2 3 4 5 6 7 fMCLK (MHz) 19.44 19.44 0.008 0.008 38.88 25 10 10 Threshold (ppm) 25 25 10 10 50 50 100 100 Rev. B | Page 24 of 35 Data Sheet AD9574 Table 28. PPR1, PPR3, and PPR4 Dependencies1 PPR1 State 0 1 fREF (MHz) 25 25 PLL x2 Bypass Active OUT2/OUT3 Frequency (MHz) 156.25 156.25 2 3 25 25 Bypass Active 156.25 156.25 4 5 19.44 19.44 Bypass Active 155.52 155.52 6 7 25 25 Bypass Active 160 160 1 PPR3 State 0 1 OUT4 Frequency (MHz) Driver 100 HSTL 100 HCSL OUT5 Frequency (MHz) Driver 125 HSTL 100 HCSL PPR4 State 0 1 2 100 HCSL 125 HSTL 2 3 4 5 125 125 100 LVDS HSTL LVDS 125 125 100 LVDS HSTL HCSL 3 4 5 6 100 HSTL 100 HSTL 6 7 N/A Disabled N/A Disabled 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 312.5 312.5 312.5 312.5 312.5 312.5 312.5 125 38.88 38.88 38.88 38.88 77.76 77.76 N/A N/A 80 80 80 N/A 80 80 N/A N/A HSTL LVDS HCSL HSTL LVDS HCSL LVDS HCSL HSTL LVDS LVDS HSTL HSTL LVDS Disabled Disabled HSTL LVDS LVDS Disabled LVDS HSTL Disabled Disabled 312.5 312.5 312.5 125 125 125 125 125 77.76 77.76 38.88 38.88 77.76 77.76 38.88 N/A 80 80 160 80 80 160 160 N/A HSTL LVDS HCSL HSTL LVDS HCSL HSTL HCSL HSTL LVDS LVDS HSTL HSTL LVDS HSTL Disabled HSTL HSTL LVDS HSTL LVDS HSTL HSTL Disabled 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 OUT6 Frequency (MHz) Driver N/A Disabled 133.3 3.3 V CMOS 133.3 1.8 V CMOS 133.3 LVDS 66.67 LVDS 66.67 3.3 V CMOS 66.67 1.8 V CMOS 33.33 3.3 V CMOS N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A Disabled N/A means not applicable. POWER-ON RESET (POR) Applying power to the AD9574 causes an internal power-on reset (POR) event. A POR event allows the device to initialize to a known state at power-up by initiating a scan of the PPRx pins (see the PPRx Pins section). In general, the AD9574 follows an orderly power-on sequence beginning with the POR circuit detecting a valid 3.3 V supply. This activates the internal LDO regulators. Detection of valid LDO voltages by the POR circuit triggers a PPRx scan sequence, which results in the configuration of the input reference receivers. Assuming the presence of the active reference, the reference signal appears at the input to the PLL and at the OUT0 and OUT1 channels. With a reference signal applied to the input of the PLL, the VCO calibration sequence initiates. Assuming a valid input reference signal, the PLL eventually locks to the reference signal as indicated by assertion of the LD pin. This lock enables the prescale dividers at the output of the VCO, which starts the output drivers toggling (that is, those output drivers enabled per the PPRx settings). Rev. B | Page 25 of 35 AD9574 Data Sheet To ensure maximum operational robustness, the power-on initialization sequence shown in Figure 22 is recommended. The power supply initialization loop assumes the user can monitor the VDD supply voltages applied to the device. The chip level reset loop assumes the user can monitor the state of the lock detect pin (LD, Pin 14) and assert the RESET pin (Pin 20) under software control. The variables RST_COUNT, time, and PLL_TO denote quantities maintained in the power-on initialization software routine of the user. The RESET count (RST_COUNT) represents an integer counter implemented in the software to track the number of times the RESET pin is asserted under software control. Time is a variable implemented in the software to track elapsed time. The PLL timeout (PLL_TO) variable is implemented in the software to indicate the maximum amount of time allowed for the PLL to lock following an assertion of the RESET pin. Note that the value of PLL_TO depends on the selected PPR state. See Table 16 in the Timing Specifications section to determine the appropriate value for the PLL_TO variable. START USER POWER SUPPLIES INITIALIZATION LOOP APPLY VDD (ALL DOMAINS) NO VDD SETTLED? YES APPLY REFERENCE CLOCK(S) (REF0 / REF1) CHIP LEVEL RESET LOOP RST_COUNT = 0 ISSUE A PIN LEVEL RESET RST_COUNT = RST_COUNT + 1 START TIMEOUT CLOCK: TIME = 0 PLL LOCK DETECT POLLING LOOP NO LD PIN = LOGIC 1 NO TIMEOUT CLOCK: TIME > PLL_TO NO YES RST_COUNT >0 YES RAISE FLAG FOR DEBUGGING 07501-122 YES END Figure 22. Recommended Power-On Initialization Sequence Rev. B | Page 26 of 35 Data Sheet AD9574 REFERENCE CLOCK INPUTS The REF0 and REF1 input channels provide for two operating modes based on the scanned state of PPR0. Note that the resulting mode applies to both the REF0 and REF1 channels. That is, independent input mode selection is not an option. In single-ended 3.3 V CMOS buffer mode, the user may connect a 3.3 V clock source directly to the positive reference input pin (REF0_P, for example). Note that in single-ended mode, it is best to connect a 0.1 nF capacitor from the negative input pin (REF0_N, for example) to GND. In differential mode, the user may connect a differential clock driver to the two reference input pins (REF0_P and REF0_N, for example). Note that differential operation requires ac coupling, that is, a series connected 0.1 nF capacitor from each output of an external differential clock driver to the corresponding reference input pin. This mode also supports a single-ended 1.8 V CMOS clock source by connecting the source to either of the reference input pins (REF0_P or REF0_N, for example). Connect the unused input pin to GND via a 0.1 nF capacitor. MONITOR CLOCK INPUT The MCLK_x pins are the monitor clock inputs and are intended to accept a stable frequency reference source. The MCLK_x pins are configurable as either single-ended 3.3 V CMOS or differential. The monitor clock accepts a fixed frequency of 0.008 MHz, 10 MHz, 19.44 MHz, 25 MHz, or 38.88 MHz. Note that the monitor clock input frequency and receiver configuration depend on the scanned state of PPR6 (see the PPR6--Monitor Clock (MCLK_x) Input Configuration section for details). A stable monitor clock frequency source supports the operation of the reference monitor (see the Reference Monitor section). Because the reference monitor relies on the precision and stability of the monitor clock input signal, the user must ensure the frequency accuracy of the monitor clock source. REFERENCE SWITCHING The AD9574 provides for manual reference switching capability. Although the on-board reference monitor provides the user with information regarding the status of the input references, the device does not provide for automatic reference switchover as a result of status changes. Rather, the REF_SEL pin provides the user with manual reference switchover control. A Logic 0 on the REF_SEL pin informs the internal reference switching logic to make REF0 the active reference, whereas a Logic 1 makes REF1 the active reference. The switch to a new active reference does not occur instantaneously with a corresponding change of state on the REF_SEL pin. Instead, the reference switching logic notes the request for a reference switch and waits for the opportune moment to make the physical switch. This functionality ensures a minimal frequency disturbance on the output clocks associated with the integrated PLL (the OUT2 through OUT6 channels). The reference switching logic provides information about which reference channel (REF0 or REF1) is the currently active reference via the REF_ACT output pin. The REF_ACT pin is Logic 0 when REF0 is the active reference and Logic 1 when REF1 is the active reference. Furthermore, the reference switching logic indicates when the device is in the process of performing a reference switchover via the REF_SW pin (that is, REF_SW is Logic 1 when a reference switch is in progress). The REF_SW pin assumes a Logic 1 state when REF_SEL changes states and returns to a Logic 0 state when the device completes the reference switchover process. See the Reference Switching section for additional information. Changing the state of the REF_SEL pin triggers the internal state machine to perform the reference switching process. Confirm (via the REF_ACT pin) that the device has switched to the desired reference before a subsequent change of the REF_SEL pin. Changing the state of the REF_SEL pin before the internal state machine completes the reference switching process may cause undesired results. Because the reference switching logic waits for an optimal switchover point rather than switching immediately, there is the rare possibility that either or both references happen to fail (resulting in a loss of reference (LOR) fault condition) just after the user requests a reference switchover (via the REF_SEL pin), but before the switching logic identifies the optimal switchover point. In such an instance, the LOR condition associated with either reference causes the internal state machine to stall and the device fails to switch references, thereby retaining the currently active reference. If the currently active reference fails, the device loses lock, thereby necessitating a device reset. If the requested reference fails, the device retains the currently active reference, but switches to the requested reference if it becomes available. Note that as long as a reference remains in an LOR condition, the state machine remains stalled. Only a device reset makes the state machine disregard the initial request to switch references. The REF_SEL pin determines which reference is the active reference any time device power is cycled or the user asserts the RESET pin. REFERENCE MONITOR An on-board reference frequency monitor provides the user with a means to validate the frequency accuracy of the active reference channel (REF0 or REF1) in real time. The REFMON pin enables or disables the reference monitoring function (Logic 1 or Logic 0, respectively). Apply a static and valid Logic 0 or Logic 1 level to the REFMON pin. Do not allow the REFMON pin to float. Do not toggle the REFMON pin during device operation. When enabled, the reference monitor continuously tests the frequency of the active reference by comparing it to the frequency of the MCLK_x signal. The result of this comparison appears on the REF_FHI and REF_FLO pins per Table 29. Rev. B | Page 27 of 35 AD9574 Data Sheet The above or below frequency decision threshold of the monitor is 10 ppm, 25 ppm, 50 ppm, or 100 ppm per the scanned value of PPR5 (see the PPR5--Reference Monitor Threshold section). Following a power-up or RESET, the reference monitor indicates an indeterminate (see Table 29) condition until enough time elapses to make a valid decision (see the monitor clock input to REF_FHI/REF_FLO time parameter in Table 16). The monitoring process begins when the following two conditions are met: the REFMON pin is Logic 1 and a valid signal is present at the MCLK_x pins. Within the time specified by the monitor clock input to REF_FHI/REF_FLO time parameter (per Table 16), the reference monitor indicates the results on the reference monitor status pins, REF_FHI/REF_FLO (per Table 29). The REF_FHI and REF_FLO pins are open-drain with internal pull-down resistors allowing wire-OR'ed operation. That is, both pins can be connected together to yield a single in tolerance or out of tolerance indication. With a wire-OR'ed connection, however, it is not possible to discern whether the reference frequency is above or below the tolerance threshold. Table 29. Reference Frequency Monitor Status REF_FHI 0 0 1 1 REF_FLO 0 1 0 1 Active Reference Status Frequency within tolerance threshold Frequency below tolerance threshold Frequency above tolerance threshold Indeterminate or fault condition In addition to its frequency monitoring function, the reference monitor also checks for the presence of a clock signal at the REF0_x, REF1_x, and MCLK_x inputs. The absence of a clock signal results in an internal LOR indication for that particular clock input. Note that LOR indication occurs when the input frequency is below approximately 1 MHz. The one exception is for fMCLK = 8 kHz, for which an LOR indication occurs if fMCLK is below approximately 6.1 kHz. An LOR condition may cause the REF_FHI and REF_FLO pins to indicate an indeterminate state (a Logic 1 on both the REF_FHI and REF_FLO pins). See the Reference Switching section for details regarding LOR conditions that occur during a reference switching operation. PLL The PLL consists of six functional elements. * * * * * * Frequency prescaler PFD Charge pump Loop filter VCO Feedback divider The AD9574 automatically configures the six functional elements based on the prevailing PPRx settings. The prescaler is shown functionally as a programmable divider in Figure 20. It actually consists of a x2 frequency multiplier, a divideby-5 block, and multiplexers to yield the necessary frequency divide ratios per Table 30. Table 30. PLL Frequency Prescaler x2 Active Bypassed Active Bypassed /5 Bypassed Bypassed Active Active Frequency Division 1/2 (same as multiply by 2) 1 5/2 5 Table 31. REF_FHI and REF_FLO Status1 REFMON 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MCLK_x Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable LOR OK OK OK OK OK OK OK REF_SEL 0 0 1 1 Not applicable Not applicable Not applicable Not applicable 0 0 1 1 Not applicable Not applicable Not applicable REF_SW2 0 0 0 0 1 1 1 Not applicable 0 0 0 0 1 1 1 REF0_x LOR OK Not applicable Not applicable LOR Not applicable OK Not applicable LOR OK Not applicable Not applicable LOR Not applicable OK OK means the signal is present. For REF_SW = 1, LOR means a transition to a LOR condition while the device is in the process of a reference switchover. 3 REF_Fx refers to the combined state of the REF_FHI and REF_FLO pins per Table 29. 1 2 Rev. B | Page 28 of 35 REF1_x Not applicable Not applicable LOR OK Not applicable LOR OK Not applicable Not applicable Not applicable LOR OK Not applicable LOR OK REF_Fx3 11 00 11 00 11 11 00 11 11 00, 01, or 10 11 00, 01, or 10 11 11 00, 01, or 10 Data Sheet AD9574 The PFD, charge pump, and loop filter work together to tune the VCO output frequency according to the phase difference of the clock edges at the input to the PFD. The closed-loop configuration gradually causes the phase difference at the PFD input to settle near zero and the VCO output frequency to settle to a value of N times the PFD input frequency (N is the feedback divider value). Based on the PPRx pin settings, the AD9574 automatically selects the value of N and the prescaler value to yield one of three VCO frequencies (2488 MHz, 2500 MHz, or 2560 MHz) per Table 22. The loop filter consists of a partially integrated third-order RC network with an external network connected between the LF and LDO_BYP pins. The external network consists of a 1 nF or 2 nF capacitor or a series connected 2 nF capacitor, C, and 4.75 k resistor, R (see Table 32). The loop filter components, charge pump current, feedback divider, and VCO gain define the bandwidth of the PLL according to Table 22. The device automatically adjusts the internal components per the PPRx settings to maintain an approximately constant loop bandwidth. OUTPUT DRIVERS The output channels of the AD9574 offer the flexibility of a variety of drive formats, including HSTL, HCSL, LVDS, and CMOS. Each channel offers a subset of these formats (see Table 33). Table 33. Output Drive Formats Format Output Channel 0 1 2 3 4 5 6 HSTL Yes Yes Yes Yes Yes Yes No 3.3 V Yes Yes No No No No Yes CMOS 1.8 V No No No No No No Yes Table 34. Output Frequencies INTEGRATED LOOP FILTER VCO LF fREF 25 0 25 50 1 25 19.44 19.44 19.44 07501-017 EXTERNAL COMPONENTS LDO_BYP LVDS No No No No Yes Yes Yes The seven output clock channels (OUT0 through OUT6) provide two different frequency translation functions. OUT0 and OUT1 offer a replica of the reference frequency (with a frequency doubling option for OUT0), whereas OUT2 through OUT6 offer rational frequency translations by means of an integrated integer-N PLL. Table 34 shows a summary of the available frequencies for each output channel (in units of MHz). The indicated reference to output frequency translations depends on the results of a PPRx scan (see the PPRx Pins section for details). External Components C = 1 nF C = 2 nF C = 1 nF C = 2 nF C = 1 nF C = 2 nF C = 2 nF in series with R = 4.75 k C = 2 nF in series with R = 4.75 k Figure 23 is a diagram of the loop filter portion of the PLL. CHARGE PUMP HCSL No No No No Yes Yes No OUTPUT CLOCKS Table 32. External Loop Filter Components PPR1 State 0 1 2 3 4 5 6 7 The OUT2 through OUT6 channels are static (outputs do not toggle) while the PLL is unlocked (that is, while the LD pin is Logic 0). Figure 23. PLL Loop Filter Detail The AD9574 also provides a digital lock detect output signal at the LD pin, which indicates (active high) when the device considers the PFD input phase differential to have stabilized near zero. 1 N/A means not applicable. Rev. B | Page 29 of 35 Output (MHz) 2 3 4 156.25 156.25 100 125 312.5 80 160 155.52 155.52 38.88 77.76 5 100 125 312.5 80 160 38.88 77.76 6 33.33 66.67 133.3 N/A1 AD9574 Data Sheet APPLICATIONS INFORMATION DUAL OSCILLATOR REFERENCE INPUT APPLICATION required. The FPGA also controls the on/off state of the reference oscillators, which provides for shutting down a faulty reference or for keeping a redundant reference turned off until needed. The general configuration of the AD9574 is set via a group of resistors that establish the desired PPRx states. Although Figure 24 shows XOs with differential outputs, singleended XOs can be substituted by connecting the XO output to the REFx_P pin and a 0.1 nF capacitor from the REFx_N pin to GND. Figure 24 depicts a typical application diagram using two crystal oscillators (XOs) as the reference inputs. A stable oscillator source supplies the MCLK_x inputs and serves as the timing reference for the on-board reference monitoring function. A field-programmable gate array (FPGA) handles the control interface for monitoring the status of the references and the PLL (lock detector) and for switching between references as PROGRAMMING RESISTORS PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 PPR6 3.3V 47 41 7 27 26 24 19 10 OUT0_P x1/x2 PPR CONTROL 9 1 REF0_N 2 REF1_P 6 REF1_N 5 MCLK_P 45 MCLK_N 46 REF_SEL 48 REFMON 25 REF_FHI 35 REF_FLO 34 33 OUT5_N REF_ACT 44 22 OUT6_P REF_SW 43 Rx 38 OUT2_P AD9574 37 OUT2_N 39 OUT3_P x1/x2 PFD/ CP LF VCO 40 OUT3_N REFERENCE MONITOR 29 OUT4_P 28 OUT4_N 32 OUT5_P 21 OUT6_N 14 15 16 LD LF LDO_BYP FPGA 1nF Figure 24. Dual Oscillator Reference Input Application Diagram Rev. B | Page 30 of 35 470nF 07501-018 STABLE REFERENCE 12 OUT1_N DIVIDERS XO 11 OUT1_P Rx XO ON/OFF CONTROL OUT0_N REF0_P Data Sheet AD9574 INTERFACING TO CMOS CLOCK OUTPUTS Apply the following general guidelines when using the singleended 1.8 V or 3.3 V CMOS clock output drivers. Design point-to-point nets such that a driver has only one receiver on the net, if possible. This allows simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. CMOS 10 60.4 1.0 INCH MICROSTRIP 5pF GND Figure 25. Series Termination of CMOS Output Termination at the far end of the printed circuit board (PCB) trace is a second option. The CMOS outputs of the AD9574 do not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in Figure 26. Ensure that the impedance of the far end termination network matches the PCB trace impedance and provides the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. 3.3V CMOS 10 50 100 100 5pF 07501-021 Figure 27 depicts a simple application using a single crystal oscillator as the reference input with minimal reference monitoring functionality. The wire-OR'ed REF_FHI and REF_FLO connection in conjunction with REF_MON tied to GND (REF_MON = 0; see Table 31) yields a LOR function indicating only that REF0 is present (or not); that is, there is no specific indication of high or low frequency status. The LOR and LD signals can notify a controller (not shown) of a reference failure or an unlocked PLL condition. The general configuration of the AD9574 is set via a group of resistors that establish the desired PPRx states. Although Figure 27 shows an XO with differential outputs, a single-ended XO can be substituted by connecting the XO output to the REF0_P pin and a 0.1 nF capacitor from the REF0_N pin to GND. The value of the series termination depends on the board design and timing requirements (typically 10 to 100 ). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity. 07499-015 SIMPLE, SINGLE OSCILLATOR REFERENCE INPUT APPLICATION Figure 26. CMOS Output with Far End Termination Rev. B | Page 31 of 35 AD9574 Data Sheet PROGRAMMING RESISTORS PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 PPR6 3.3V 47 41 7 27 26 24 19 PPR CONTROL 10 OUT0_P x1/x2 9 REF0_N 2 OUT0_N 11 OUT1_P Rx 12 OUT1_N REF1_P 6 REF1_N 5 MCLK_P 45 MCLK_N 46 REF_SEL 48 REFMON 25 REF_FHI 35 REF_FLO 34 33 OUT5_N REF_ACT 44 22 OUT6_P REF_SW 43 38 OUT2_P AD9574 Rx 37 OUT2_N 39 OUT3_P x1/x2 PFD/ CP LF VCO 40 OUT3_N REFERENCE MONITOR 29 OUT4_P 28 OUT4_N 32 OUT5_P 21 OUT6_N 14 15 16 LD LF LDO_BYP 07501-019 LOR 1 DIVIDERS XO REF0_P LD 1nF 470nF Figure 27. Single Oscillator Reference Input Application Diagram HCSL LVDS and HSTL both employ a differential output driver. The recommended termination circuit for LVDS and HSTL drivers appears in Figure 28. RECEIVER 50 INDEPENDENT UNCOUPLED 50 TRANSMISSION LINES 50 Figure 29. HCSL Output Termination 100 Figure 28. LVDS or HSTL Output Termination See the AN-586 Application Note for more information about LVDS. INTERFACING TO HCSL CLOCK OUTPUTS HCSL 10 TO 30 INDEPENDENT UNCOUPLED 50 TRANSMISSION LINES 10 TO 30 HCSL uses a differential open-drain architecture. The opendrain architecture necessitates the use of an external termination resistor. Figure 29 shows the typical method for interfacing to HCSL drivers. Rev. B | Page 32 of 35 50 RECEIVER 50 Figure 30. Alternate HCSL Output Termination 07501-024 RECEIVER In some cases, the fast switching capability of HCSL drivers results in overshoot and ringing. The alternative HCSL interface shown in Figure 30 can mitigate this problem via a small series resistor, typically in the 10 to 30 range. 07501-022 HSTL/LVDS DRIVER INDEPENDENT UNCOUPLED 50 TRANSMISSION LINES 07501-023 INTERFACING TO LVDS AND HSTL CLOCK OUTPUTS Data Sheet AD9574 POWER SUPPLY The AD9574 requires a power supply of 3.3 V 10%. The Specifications section gives the performance expected from the AD9574 with the power supply voltage within this range. The absolute maximum range of -0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VDD_x pins. Follow good engineering practice in the layout of power supply traces and the ground plane of the PCB. Bypass the power supply on the PCB with adequate capacitance (>10 F). Bypass the AD9574 with adequate capacitors (0.1 F) at all power pins as close as possible to the device. The layout of the AD9574 evaluation board is a good example of how to route power supply traces and where to place bypass capacitors. POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. The exposed metal pad on the AD9574 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the pad must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9574; therefore, this GND connection provides a good thermal path to a larger heat dissipation area, such as a ground plane on the PCB. Rev. B | Page 33 of 35 AD9574 Data Sheet THERMAL PERFORMANCE Table 35. Thermal Parameters for the 48-Lead, 7 mm x 7 mm LFCSP Symbol JA JB JC JT JT JT 8 9 Thermal Characteristic Using a JEDEC 51-7 Plus JEDEC 51-5 2S2P Test Board8 Junction to ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction to board thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-8 (still air) Junction to case thermal resistance (die-to-heat sink) per MIL-Standard 883, Method 1012.1 Junction to top of package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) Junction to top of package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction to top of package characterization parameter, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Value9 32.6 18.7 3.5 0.3 0.4 0.6 Unit C/W C/W C/W C/W C/W C/W The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. The AD9574 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value as indicated in Table 35. PD is the power dissipation (see Table 15). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Rev. B | Page 34 of 35 Data Sheet AD9574 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.23 0.18 PIN 1 INDICATOR 37 36 48 1 0.50 BSC 4.25 4.10 SQ 3.95 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-005092 SEATING PLANE 0.45 0.40 0.35 24 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 03-27-2017-B 7.10 7.00 SQ 6.90 Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body and 0.75 mm Package Height (CP-48-5) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9574BCPZ AD9574BCPZ-REEL7 AD9574/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2014-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07501-0-4/17(B) Rev. B | Page 35 of 35 Package Option CP-48-5 CP-48-5