3-Channel, Integrated Ultralow Power Solution with Dual Buck Regulators and Load Switch ADP5310 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP5310 TO MCU EN1 SW1 CHANNEL 1 PGND1 BUCK REGULATOR FB1 (800mA) PWRGD PVIN1 - + - + VIN = 2.7V TO 15V C1 10F MLCC FROM MCU PVIN2 NC SYNC/ MODE L1 4.7H CHANNEL 2 SW2 ULTRALOW POWER PGND2 BUCK REGULATOR FB2 (50mA/300mA) CHANNEL 3 LOAD SWITCH EN3 VREG VOUT1 C3 10F MLCC L2 4.7H R1 R2 VOUT3 VOUT3 AGND VOUT2 C4 10F MLCC C5 220nF MLCC 13008-001 FROM MCU 2 x LiMnO2 Wide input voltage range: 2.7 V to 15.0 V 700 nA quiescent current when EN1 = SYNC/MODE = low 1.5% output accuracy over full temperature range in PWM mode 600 kHz (or 1.2 MHz) switching frequency with optional synchronization input from 400 kHz to 1.4 MHz Channel 1: 800 mA buck regulator Automatic PSM/PWM or forced PWM mode via factory fuse 100% duty cycle operation mode Adjustable/fixed output options via factory fuse Power-good flag Channel 2: ultralow power buck regulator Selectable hysteresis or PWM operation mode Output current up to 50 mA in hysteresis mode, 300 mA in PWM mode with 100% duty cycle operation mode Low noise at 0.8 V reference in PWM mode Adjustable/fixed output voltage options via factory fuse Channel 3: high-side load switch Low RDS(ON) of 494 m at VOUT3 = 2.5 V Quick output discharge (QOD) option UVLO, OCP, and TSD protection 16-lead TSSOP_EP package -40C to +125C operational junction temperature C6 1F Figure 1. APPLICATIONS Energy (gas and water) metering Portable and battery-powered equipment Medical applications Keep-alive power supplies GENERAL DESCRIPTION The ADP5310 combines dual buck regulators and one load switch in a 16-lead TSSOP_EP package that meets demanding performance and board space requirements. The device enables direct connection to a wide input voltage range of 2.7 V to 15.0 V, allowing the use of multiple alkaline/NiMH or lithium cells and other power sources. The buck regulator in Channel 1 uses a current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient performance, which provides up to 800 mA of output current. The automatic PWM/pulse skipping mode (PSM) control scheme achieves excellent efficiency in light output current. A power-good signal indicates that the output of Channel 1 is within 92% of its nominal value. An ultralow power buck regulator is integrated in Channel 2 with the SYNC/MODE pin to control its operation mode. When SYNC/MODE is set to low, the buck regulator operates in hysteresis Rev. A mode, which draws only 700 nA of quiescent current to regulate the output under zero load and provides up to 50 mA of output current. Hysteresis mode helps achieve excellent efficiency at less than 1 mW and can work as a keep-alive power supply in a batterypowered system. When the SYNC/MODE pin is set to high, the buck regulator switches to a traditional constant frequency PWM control scheme to provide low output ripple for noise sensitive applications, and the buck regulator provides up to 300 mA of output current in PWM mode. Channel 3 integrates a high-side load switch that operates from 1.65 V to 5.5 V with its input connected to the output of Channel 2. The load switch provides power domain isolation and extends battery operation time. Other key safety features of the ADP5310 include overcurrent protection (OCP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5310 is rated for the -40C to +125C junction temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5310 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start ...................................................................................... 19 Applications ....................................................................................... 1 Startup with Precharged Output .............................................. 19 Typical Application Circuit ............................................................. 1 100% Duty Operation ................................................................ 19 General Description ......................................................................... 1 Active Discharge ......................................................................... 20 Revision History ............................................................................... 2 Power-Good Function ............................................................... 20 Detailed Functional Block Diagram .............................................. 3 Load Switch ................................................................................. 20 Specifications..................................................................................... 4 Thermal Shutdown .................................................................... 20 Buck Regulators and Load Switch Specifications..................... 5 Applications Information .............................................................. 21 Absolute Maximum Ratings............................................................ 7 External Component Selection ................................................ 21 Thermal Resistance ...................................................................... 7 Selecting the Inductor ................................................................ 21 ESD Caution .................................................................................. 7 Output Capacitor........................................................................ 21 Pin Configuration and Function Descriptions ............................. 8 Input Capacitor ........................................................................... 21 Typical Performance Characteristics ............................................. 9 Adjustable Output Voltage Programming .............................. 22 Theory of Operation ...................................................................... 18 Efficiency ..................................................................................... 22 Buck Regulator Operation Modes............................................ 18 Recommended Buck External Components .......................... 22 Adjustable and Fixed Output Voltages .................................... 19 Capacitor Selection .................................................................... 24 Undervoltage Lockout (UVLO) ............................................... 19 Circuit Board Layout Recommendations ............................... 24 Enable and Shutdown Features................................................. 19 Typical Application Circuits .......................................................... 25 Internal Linear Regulator (VREG) ........................................... 19 Factory Programmable Options ................................................... 26 Oscillator and Synchronization ................................................ 19 Outline Dimensions ....................................................................... 28 Current Limit .............................................................................. 19 Ordering Guide .......................................................................... 28 Short-Circuit Protection ............................................................ 19 REVISION HISTORY 11/2016--Rev. 0 to Rev. A Moved Circuit Board Layout Recommendations Section and Figure 57................................................................................... 24 Changes to Ordering Guide .......................................................... 28 4/2015--Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADP5310 DETAILED FUNCTIONAL BLOCK DIAGRAM ADP5310 VIN PVIN1 DRIVER CHANNEL 1 P_ILIMIT VIN 1.2A RDS(ON) x kr 300mA/k r IMIN SW1 N_ILIMIT VIN CONTROL LOGIC RDS(ON) x kr -0.5A (PWM) 0A (PSM) PWM VIN SLOPE COMPENSATION DRIVER PSM 0.808V 0.8V 1.2V EN1 0.4V PGND1 FB1 0.736V 0.696V PWRGD 0.8V V TO I FB1 SOFT START PVIN1 PVIN2 LDO 1.2V CH1 UVLO 2.55V 2.4V BAND GAP BIAS AND CONTROL LOGIC VREG 1.2V 0.4V CH2 CH1 1.2MHz OSC S/H OSC CH2 SYNC SYNC/MODE CH2 VIN PVIN2 DRIVER CHANNEL 2 P_ILIMIT VIN 0.6A RDS(ON) x kr 300mA/k r IMIN SW2 N_ILIMIT VIN CONTROL LOGIC RDS(ON) x kr -0.5A (PWM) 0A (PSM) PWM VIN SLOPE COMPENSATION DRIVER PSM 0.808V 0.8V PGND2 FB2 0.8V V TO I SOFT START CHANNEL 3 VOUT3 DRIVER Figure 2. Rev. A | Page 3 of 28 13008-002 1.2V 0.4V EN3 ADP5310 Data Sheet SPECIFICATIONS VIN = 6 V, VREG = 3.9 V, TJ = -40C to +125C for minimum and maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current Standby Operation PWM Operation UNDERVOLTAGE LOCKOUT UVLO Threshold Rising Falling Hysteresis OSCILLATOR CIRCUIT Switching Frequency Feedback (FB) Threshold of Frequency Fold SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNC High Level Threshold SYNC Low Level Threshold SYNC Pulse On Time Range EN1 and EN3 Input High Level Threshold Input Low Level Threshold Input Leakage Current INTERNAL POWER GOOD Internal Power-Good Threshold Internal Power-Good Hysteresis Internal Power-Good Rising Delay Internal Power-Good Falling Delay Leakage Current for PWRGD Pin Output Low Voltage for PWRGD Pin INTERNAL REGULATOR VREG Output Voltage THERMAL SHUTDOWN Threshold Hysteresis Symbol VIN Min 2.7 Typ Max 15.0 Unit V Test Conditions/Comments PVIN1 and PVIN2 pins PVIN1 and PVIN2 pins 700 1850 nA 700 3800 nA IQ3 UVLO 1.4 1.65 mA -40C TJ +85C, EN1 = SYNC/MODE = low -40C TJ +125C, EN1 = SYNC/MODE = low EN1 = SYNC/MODE = high PVIN2 pin VUVLO_RISING VUVLO_FALLING VHYS 2.55 2.40 150 2.75 V V mV IQ1 2.15 For Channel 1 and Channel 2, PWM mode fSW 1050 525 VOSC_FOLD SYNCCLOCK SYNCCLOCK SYNCHIGH SYNCLOW SYNCON 400 800 1.2 80 VIH VIL ILEAKAGE 1.2 VPWRGD(RISE) VPWRGD(HYS) tPWRGD_RISE 88 tPWRGD_FALL IPWRGD_LEAKAGE VPWRGD_LOW VREG TSHDN THYS 1200 600 0.3 3.6 92 5 16 1350 675 kHz kHz V 800 1400 0.4 1/fSW - 150 kHz kHz V V ns 0.4 300 V V nA 1 10 50 40 100 % % Clock cycles s nA mV 3.9 4.2 V 135 15 Rev. A | Page 4 of 28 96 C C fSW = 600 kHz fSW = 1.2 MHz IPWRGD = 100 A Data Sheet ADP5310 BUCK REGULATORS AND LOAD SWITCH SPECIFICATIONS VIN = 6 V, VREG = 3.9 V, TJ = -40C to +125C for minimum and maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 2. Parameter CHANNEL 1 SYNC BUCK REGULATOR Supply Voltage Range Rating Output Current FB1 Pin in PWM Mode Fixed Output Options Fixed Output Accuracy Adjustable Output Voltage Range Adjustable Feedback Voltage Adjustable Feedback Voltage Accuracy FB1 Pin in PSM Mode Threshold Accuracy from Active Mode to Skip Mode Hysteresis of Threshold Accuracy from Active Mode to Skip Mode Feedback Bias Current SW1 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold Minimum On Time Soft Start Time COUT Discharge Switch On Resistance CHANNEL 2 SYNC BUCK REGULATOR Supply Voltage Range Rating Output Current Hysteresis Mode PWM Mode Mode Transition Transition Delay from Hysteresis Mode to PWM Mode FB2 Pin in PWM Mode Fixed Output Options Symbol Min VIN1 IOUT 2.7 VOUT1_FIX VFB1_FIX VOUT1_ADJ VFB1 VFB1_ADJ VFB1_PSM Typ Max Unit Test Conditions/Comments 15.0 V mA PVIN1 pin 1.2 5.0 V Factory trim, 3 bits (adjustable, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 2.85 V, 3.3 V, 5.0 V) -1.5 0.8 +1.5 PVIN1 Adjustable voltage option Adjustable voltage option TJ = 25C 0C TJ 85C -40C TJ +125C 800 -0.55 +0.55 % V V % -1.2 -1.5 +1.0 +1.5 % % -1.5 +1.5 % 0.800 VFB1_PSM(PSM) 1 IFB1 % 0.1 A Adjustable voltage option RDS(ON)1H 472 690 m Pin to pin measurement RDS(ON)1L 438 725 m Pin to pin measurement 1260 38 350 287 1450 70 mA ns s ITH(ILIM1) tMIN_ON1 tSS1 RDIS1 1000 VIN2 2.7 15.0 V Factory trim, 1 bit (350 s, 2800 s) PVIN2 pin IOUT_HYS IOUT_PWM 50 300 mA mA THYS_TO_PWM 8 Clock cycles SYNC/MODE goes logic high from logic low Factory trim, 8 bits (adjustable, 1.2 V to 3.6 V in 50 mV steps, and 3.6 V to 5.0 V in 100 mV steps) VOUT2_FIX 1.2 5.0 V Fixed Output Accuracy Adjustable Output Voltage Range VFB2_FIX VOUT2_ADJ -1.5 0.8 +1.5 PVIN2 % V Adjustable Feedback Voltage VFB2 0.800 Rev. A | Page 5 of 28 V Adjustable voltage option (note that Channel 3 has no use in this setting) Adjustable voltage option ADP5310 Parameter Adjustable Feedback Voltage Accuracy Data Sheet Symbol VFB2_ADJ Min -0.55 Typ -1.2 -1.5 Feedback Bias Current Feedback Resistor to GND FB2 Pin in Hysteresis Mode Threshold Accuracy from Active Mode to Standby Mode Hysteresis of Threshold Accuracy from Active Mode to Standby Mode SW2 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit Threshold in PWM Mode Peak Inductor Current in Hysteresis Mode Minimum On Time Soft Start Time COUT Discharge Switch On Resistance CHANNEL 3 LOAD SWTICH Supply Voltage Range FB2 to VOUT3 On Resistance IFB2_ADJ IFB2_FIX VFB2_HYS 15 57 -1.5 Max +0.55 Unit % Test Conditions/Comments TJ = 25C +1.0 +1.5 200 % % nA M 0C TJ 85C -40C TJ +125C Adjustable voltage option Fixed voltage option +1.5 % VFB2_HYS(HYS) 1 RDS(ON)2H 868 1250 m Pin to pin measurement RDS(ON)2L 893 1360 m Pin to pin measurement 600 730 mA SYNC/MODE = high mA SYNC/MODE = low ITH(ILIM2) 450 IL2 300 tMIN_ON2 tSS2 36 350 RDIS2 282 VIN3 RDS(ON)3 1.65 % 70 ns s Factory trim, 1 bit (350 s, 2800 s) 382 430 494 5.5 550 615 700 V m m m FB2 pin VOUT3 = 5.0 V, ILOAD3 = 50 mA VOUT3 = 3.3 V, ILOAD3 = 50 mA VOUT3 = 2.5 V, ILOAD3 = 50 mA 16 s VOUT3 = 2.5 V, CLOAD3 = 1 F, factory trim, 2 bits (3 s, 12 s, 48 s, 192 s) VOUT3 TIME Turn On Rise Time tRISE3 12 COUT Discharge Switch On Resistance RDIS3 286 Rev. A | Page 6 of 28 Data Sheet ADP5310 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter PVIN1, PVIN2 to PGNDx SW1, SW2 to PGNDx VREG to PGNDx EN1, EN3, SYNC/MODE, PWRGD to AGND FB1, FB2 to AGND VOUT3 to PGNDx PGND1, PGND2 to AGND Storage Temperate Range Operational Junction Temperature Range JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating -0.3 V to +17 V -0.3 V to PVIN + 0.3 V -0.3 V to +6 V -0.3 V to +17 V Table 4. Thermal Resistance Package Type 16-Lead TSSOP_EP -0.3 V to +6 V -0.3 V to +6 V -0.3 V to +0.3 V -65C to +150C -40C to +125C ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 7 of 28 JA 39.14 JC 2.59 Unit C/W ADP5310 Data Sheet PVIN1 1 16 SW1 PVIN2 2 15 PGND1 NC 3 14 EN1 ADP5310 13 FB1 TOP VIEW (Not to Scale) 12 PWRGD FB2 6 11 SYNC/MODE VOUT3 7 10 VREG 8 9 AGND SW2 4 PGND2 EN3 5 NOTES 1. NC = NO CONNECT. 2. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. 13008-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 Mnemonic PVIN1 PVIN2 NC SW2 PGND2 FB2 VOUT3 EN3 AGND VREG SYNC/MODE 12 13 14 15 16 PWRGD FB1 EN1 PGND1 SW1 EPAD Description Power Input of Channel 1. This pin must be connected to PVIN2. Power Input of Channel 2 and Internal Linear Regulator. No Connect. This pin is not internally connected. Leave this pin floating. Switching Node Output of Channel 2. Power Ground of Channel 2. Feedback Sensing Input of Channel 2. Power Output of Channel 3. Enable Input of Channel 3. Analog Ground. Output of the Internal Linear Regulator. Connect a 1.0 F ceramic capacitor between this pin and ground. Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 400 kHz to 1.4 MHz. PWM or Hysteresis Mode Selection Pin of Channel 2 (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. Power-Good Signal Output. This open-drain output is the power-good signal of Channel 1. Feedback Sensing Input of Channel 1. Enable Input of Channel 1. Power Ground of Channel 1. Switching Node Output of Channel 1. Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal dissipation. Rev. A | Page 8 of 28 Data Sheet ADP5310 TYPICAL PERFORMANCE CHARACTERISTICS 90 100 80 90 70 80 70 EFFICIENCY (%) 60 50 40 30 40 10 100 1000 10 Figure 4. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 1.2 V 0 0.1 90 80 80 70 70 EFFICIENCY (%) 90 50 40 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 10 0.1 1 10 100 1000 LOAD CURRENT (mA) 100 50 40 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 Figure 5. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 2.5 V 1000 60 30 10 0.1 13008-005 20 10 Figure 7. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 1.8 V 100 60 1 LOAD CURRENT (mA) 100 30 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 13008-007 1 LOAD CURRENT (mA) EFFICIENCY (%) 50 1 10 100 1000 LOAD CURRENT (mA) 13008-008 10 0 0.1 60 30 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 13008-004 EFFICIENCY (%) VIN = 6 V, VOUT1 = 4 V, VOUT2 = 3 V, L1 = 4.7 H, L2 = 6.8 H, CIN = COUT = 10 F, fSW = 1.2 MHz, TA = 25C, unless otherwise noted. Figure 8. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 3.3 V 90 100 80 90 70 EFFICIENCY (%) 70 60 50 40 50 40 30 20 VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 1 10 LOAD CURRENT (mA) 100 1000 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V 10 13008-006 30 20 0.1 60 Figure 6. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 5 V Rev. A | Page 9 of 28 0 0 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) Figure 9. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 1.2 V 13008-009 EFFICIENCY (%) 80 Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 30 40 0 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) 10 0 0 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) Figure 10. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 1.8 V 13008-013 0 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 13008-010 10 Figure 13. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 2.5 V 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 30 60 50 40 30 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 10 0 0 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) 20 0 0 100 200 300 400 500 600 700 Figure 14. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 5 V 80 75 85 80 70 75 65 70 65 60 EFFICIENCY (%) 55 50 45 40 35 30 60 55 50 45 40 35 30 25 0.01 0.1 1 LOAD CURRENT (mA) 10 100 20 15 10 0.001 13008-012 15 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 25 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V 20 800 LOAD CURRENT (mA) Figure 11. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 3.3 V 10 0.001 VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 10 13008-011 20 13008-014 EFFICIENCY (%) 50 30 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 EFFICIENCY (%) 60 Figure 12. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.2 V 0.01 0.1 1 LOAD CURRENT (mA) 10 100 13008-015 EFFICIENCY (%) ADP5310 Figure 15. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.8 V Rev. A | Page 10 of 28 ADP5310 95 95 90 85 80 90 75 70 75 85 65 60 55 50 45 40 35 30 25 20 15 0.001 0.1 1 10 100 LOAD CURRENT (mA) 65 60 55 50 45 40 35 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 0.01 70 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 30 25 20 0.001 Figure 16. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 2.5 V 0.01 0.1 1 10 100 LOAD CURRENT (mA) 13008-019 EFFICIENCY (%) 80 13008-016 EFFICIENCY (%) Data Sheet Figure 19. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 3.3 V 80 95 90 70 85 80 60 EFFICIENCY (%) EFFICIENCY (%) 75 70 65 60 55 50 40 30 50 30 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) 10 0 13008-017 35 0 90 70 80 60 70 EFFICIENCY (%) 100 80 30 150 200 250 300 Figure 20. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 1.2 V 90 40 100 LOAD CURRENT (mA) Figure 17. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 5 V 50 50 13008-020 VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 40 60 50 40 30 10 0 0 50 100 150 200 250 300 LOAD CURRENT (mA) VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 10 0 0 50 100 150 200 250 300 LOAD CURRENT (mA) Figure 21. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 2.5 V Figure 18. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 1.8 V Rev. A | Page 11 of 28 13008-021 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 13008-018 EFFICIENCY (%) VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 45 Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 40 10 10 50 100 150 200 250 0 13008-022 0 0 VIN = 6V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 300 LOAD CURRENT (mA) 0 50 100 150 200 250 300 LOAD CURRENT (mA) Figure 22. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 3.3 V 13008-025 VIN = 5V VIN = 7.2V VIN = 9V VIN = 12V VIN = 15V 20 Figure 25. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 5 V 1.8 2000 1500 1000 500 -40C +25C +85C +125C 0 3 5 7 9 11 13 15 VIN (V) Figure 23. Quiescent Current, Hysteresis Mode vs. VIN, EN1 = SYNC/MODE = Low 1.7 1.6 1.5 1.4 1.3 1.2 1.0 2 801 FEEDBACK VOLTAGE (mV) 804 798 6 10 8 12 14 16 Figure 26. Quiescent Current, PWM Mode, EN1 = SYNC/MODE = High 802 800 4 VIN (V) 806 802 -40C +25C +125C 1.1 13008-026 QUIESCENT CURRENT, PWM MODE (mA) 2500 13008-023 QUIESCENT CURRENT, HYSTERESIS MODE (nA) 50 30 30 FEEDBACK VOLTAGE (mV) 60 800 799 798 797 796 FB2 FB1 ACTIVE MODE TO SKIP MODE SKIP MODE TO ACTIVE MODE -40 0 25 TEMPERATURE (C) 85 125 796 13008-024 794 Figure 24. Channel 1 Feedback Voltage of PSM Mode vs. Temperature -40 0 25 TEMPERATURE (C) 85 125 13008-027 EFFICIENCY (%) ADP5310 Figure 27. Channel 2 Feedback Voltage of PWM Mode vs. Temperature Rev. A | Page 12 of 28 Data Sheet ADP5310 812 900 800 806 804 802 800 798 700 600 500 400 300 796 -40C +25C +125C ACTIVE MODE TO STANDBY MODE STANDBY MODE TO ACTIVE MODE -40 0 25 85 200 13008-028 794 125 TEMPERATURE (C) 2 8 10 12 14 16 Figure 31. Channel 1 High-Side RDS(ON)1H vs. VIN 900 1600 800 1400 600 500 400 300 100 2 4 6 8 10 12 14 16 VIN (V) 1000 800 600 400 -40C +25C +125C 200 1200 -40C +25C +125C 200 2 4 6 10 8 12 14 16 VIN (V) Figure 29. Channel 1 Low-Side RDS(ON)1L vs. VIN 13008-032 HIGH-SIDE RDS(ON)2H (m) 700 13008-029 Figure 32. Channel 2 High-Side RDS(ON)2H vs. VIN 900 1600 800 LOAD SWITCH RDS(ON)3 (m) 1400 1200 1000 800 600 400 -40C +25C +125C 2 4 6 8 10 12 14 VIN (V) 16 600 500 400 300 -40C +25C +125C 200 13008-030 200 700 Figure 30. Channel 2 Low-Side RDS(ON)2L vs. VIN 100 1.5 2.5 3.5 4.5 VIN (V) Figure 33. Channel 3 Load Switch RDS(ON)3 vs. VIN Rev. A | Page 13 of 28 5.5 13008-033 LOW-SIDE RDS(ON)1L (m) 6 VIN (V) Figure 28. Channel 2 Feedback Voltage of Hysteresis Mode vs. Temperature LOW-SIDE RDS(ON)2L (m) 4 13008-031 808 HIGH-SIDE RDS(ON)1H (m) FEEDBACK VOLTAGE (mV) 810 Data Sheet 1300 1300 1250 1250 1200 1150 1100 1050 1200 1150 1100 1050 -40 0 25 85 125 TEMPERATURE (C) 1000 13008-034 1000 -40C +25C +125C 4 10 12 14 16 Figure 37. Channel 1 Peak Current Limit vs. VIN 620 640 620 580 560 540 520 500 600 580 560 540 520 500 -40C +25C +125C 480 0 25 85 125 TEMPERATURE (C) 460 4 1275 2.60 1250 SWITCHING FREQUENCY (kHz) 1300 2.64 2.56 2.52 2.48 2.44 2.40 2.36 RISING FALLING 0 25 85 125 TEMPERATURE (C) 14 16 1225 1200 1175 1150 1125 1100 -40C +25C +125C 1075 13008-036 -40 12 10 Figure 38. Channel 2 Peak Current Limit vs. VIN 2.68 2.28 8 VIN (V) Figure 35. Channel 2 Peak Current Limit vs. Temperature 2.32 6 1050 2 4 6 8 10 12 VIN (V) Figure 39. Switching Frequency vs. VIN Figure 36. UVLO Threshold, Rising and Falling, vs. Temperature Rev. A | Page 14 of 28 14 16 13008-039 -40 13008-035 480 13008-038 PEAK CURRENT LIMIT (A) 600 PEAK CURRENT LIMIT (A) 8 VIN (V) Figure 34. Channel 1 Peak Current Limit vs. Temperature UVLO THRESHOLD (V) 6 13008-037 PEAK CURRENT LIMIT (A) PEAK CURRENT LIMIT (A) ADP5310 Data Sheet ADP5310 T VOUT1 (AC) T SW2 1 SW1 1 3 3 VOUT2 (AC) VOUT2 (AC) 2 IL2 4 4 W B CH2 5.00mV CH4 5.00V W M 1.00s A CH3 T 30.20% 4.80V B CH1 5.00V M 10.0s A CH1 W CH3 50.0mV BW CH4 200mA BW T 20.80% 2.40V 13008-043 CH1 10.0mV CH3 10.0V 13008-040 SW2 B Figure 43. Channel 2 Output Ripple of Hysteresis Mode Figure 40. Steady Waveform of PWM Mode T T VIN 1 VOUT1 SW1 SW2 1 VOUT2 2 VOUT3 2 3 3 4 B W CH2 2.00V CH4 2.00V B W B W M 200s A CH2 T 50.00% 3.32V CH1 5.00V CH3 5.00V BW Figure 41. Soft Start Waveform CH2 5.00V 3.00V Figure 44. Synchronization to 1 MHz T T VIN 1 M 1.00s A CH3 T 50.40% 13008-044 CH1 2.00V CH3 2.00V 13008-041 SYNC/MODE VIN VOUT2 (AC) 1 VOUT2 (AC) 3 3 IL2 IL2 7.20V 13008-042 B CH1 5.00V M 1.00ms A CH1 W CH3 50.0mV BW CH4 200mA BW T 20.20% B CH1 5.00V M 1.00ms A CH1 W CH3 10.0mV BW CH4 200mA BW T 20.20% 7.20V Figure 45. Channel 2 Line Transient in PWM Mode Figure 42. Channel 2 Line Transient in Hysteresis Mode Rev. A | Page 15 of 28 13008-045 4 4 ADP5310 Data Sheet T T VOUT2 (AC) VIN 2 1 VOUT1 (AC) 2 IOUT2 IL1 7.20V 13008-046 CH1 5.00V BW CH2 20.0mV BW M 1.00ms A CH1 CH4 500mA BW T 20.20% Figure 46. Channel 1 Line Transient in PWM Mode CH2 50.0mV BW M 100s A CH4 CH4 20.0mA BW T 70.40% -41.6mA 13008-049 4 4 Figure 49. Channel 2 Hysteresis Mode Load Transient (10 mA to 30 mA Load Step) T T VOUT1 (AC) VOUT2 (AC) 2 1 IOUT2 IOUT1 (AC) 4 B W CH4 500mA M 200s A CH4 T 20.40% 400mA Figure 47. Channel 1 Load Transient (0.2 A to 0.6 A Load Step) CH2 10.0mV BW M 100s A CH4 CH4 100mA BW T 70.40% 92.0mA 13008-050 CH1 200mV 13008-047 4 Figure 50. Channel 2 PWM Mode Load Transient (75 mA to 225 mA Load Step) T T VIN VIN VOUT1 VOUT2 SW1 SW2 2 1 CH1 1.00V BW CH3 5.00V CH2 1.00V BW M 400s A CH1 T 19.80% 3.40V 13008-048 3 CH1 1.00V CH3 2.00V CH2 1.00V BW M 400s A CH1 T 39.40% 4.36V Figure 51. Channel 2 100% Duty Operation in PWM Mode Figure 48. Channel 1 100% Duty Operation in PWM Mode Rev. A | Page 16 of 28 13008-051 3 Data Sheet ADP5310 T T SW2 VIN 2 2 IL2 4 VOUT2 VOUT2 (AC) SW2 3 1 SYNC/MODE 3 CH2 1.00V BW M 400s A CH1 T 39.40% 4.36V CH1 5.00V CH3 100mV CH2 5.00V CH4 500mA BW 1.80V Figure 54. Mode Transition from Hysteresis Mode to PWM Mode Figure 52. Channel 2 100% Duty Operation in Hysteresis Mode T T VOUT2 (AC) 1 M 4.00s A CH1 T 20.40% 13008-054 CH1 1.00V CH3 2.00V 13008-052 1 VOUT2 1 SW2 2 SW2 2 IL2 CH1 2.00V BW M 20.0s A CH1 CH2 5.00V CH4 200mA BW T 30.40% 2.12V 13008-053 4 IL2 CH1 2.00V BW Figure 53. Output Short M 20.0s A CH1 CH2 5.00V CH4 200mA BW T 50.20% Figure 55. Output Short Recovery Rev. A | Page 17 of 28 2.12V 13008-055 4 ADP5310 Data Sheet THEORY OF OPERATION The ADP5310 is an ultralow power management unit that combines dual buck regulators and one load switch in a 16-lead TSSOP_EP package to meet demanding performance and board space requirements. The device enables direct connection to the wide input voltage range of 2.7 V to 15 V, allowing the use of multiple alkaline/NiMH or lithium cells and other power sources. BUCK REGULATOR OPERATION MODES PWM Mode In PWM mode, the buck regulators in the ADP5310 operate at a fixed frequency that is set by an internal oscillator. At the start of each oscillator cycle, the high-side MOSFET switch turns on and sends a positive voltage across the inductor. The inductor current increases until the current sense signal exceeds the peak current threshold of the inductor that turns off the high-side MOSFET switch and turns on the low-side MOSFET. This places a negative voltage across the inductor, causing the inductor current to reduce. The low-side MOSFET stays on for the remainder of the cycle. PSM Mode The ADP5310 smoothly transitions to the variable frequency PSM mode of operation when the load current decreases below the pulse skipping threshold current, IMIN. For the peak current of the inductor based on the input and output voltages, the design of the IMIN value is based on the recommended inductor values. Deviating from the recommended inductor value for a particular output voltage results in shifting the PSM to PWM threshold and may result in the device entering discontinuous mode (DCM). As long as the required peak inductor current is above IMIN, the regulator remains in PWM mode. As the load decreases, the PSM circuitry prevents the peak inductor current from dropping below the PSM peak current value. This circuitry causes the regulator to supply more current to the output than the load requires, resulting in the output voltage increasing and the output of the internal compensation node of the error amplifier, VCOMP, decreasing. When the FB1 pin voltage rises above 1% of the nominal output voltage and the VCOMP node voltage is below a predetermined PSM threshold voltage level, the regulator enters skip mode. While in skip mode, the high-side and low-side switches and a majority of the circuitry are disabled to allow a low skip mode quiescent current as well as high efficiency performance. During skip mode, the output voltage decreases as the output capacitor discharges into the load. Fixed frequency operation starts when the FB1 voltage reaches the nominal output voltage. When the load requirement increases past the IMIN peak current level, the VCOMP node rises and the PWM control loop sets the duty cycle. While the device is entering and exiting skip mode, the PSM voltage ripple is larger than 1% because of the delay in the comparators. Hysteresis Mode In hysteresis mode, the buck regulator in the ADP5310 charges the output voltage slightly higher than its nominal output voltage with PWM pulses by regulating the constant peak inductor current. When the output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulator enters standby mode. In standby mode, the high-side and low-side MOSFET and a majority of the circuitry are disabled to allow a low quiescent current as well as high efficiency performance. During standby mode, the output capacitor supplies the energy into the load and the output voltage decreases until it falls below the hysteresis comparator lower threshold. The buck regulator wakes up and generates the PWM pulses to charge the output again. Because the output voltage occasionally enters standby mode and then recovers, the output voltage ripple in hysteresis mode is larger than the ripple in PWM mode. Mode Selection The buck regulator in Channel 1 uses the default automatic PSM/PWM mode for excellent light load efficiency. Current mode, constant frequency PWM mode can be programmed by the factory fuse for excellent stability and transient performance. The buck regulator in Channel 2 includes the SYNC/MODE pin, allowing configuration in hysteresis mode or PWM mode. When a logic high level is applied to the SYNC/MODE pin, the buck regulator in Channel 2 is forced to operate in PWM mode. In PWM mode, the regulator can supply up to 300 mA of output current. The regulator can provide lower output ripple and lower 1/f output noise in PWM mode, which benefits noise sensitive applications. When a logic low level is applied to the SYNC/MODE pin, the buck regulator in Channel 2 is forced to operate in hysteresis mode. In hysteresis mode, the regulator draws only 700 nA of quiescent current to regulate the output under zero load, which allows Channel 2 to act as a keep-alive power supply in a battery-powered system. In hysteresis mode, the regulator supplies up to 50 mA of output current with a relatively large output ripple compared to PWM mode. The user can alternate between hysteresis mode and PWM mode during operation. The flexible configuration capability during operation of the device enables efficient power management to meet high efficiency and low output ripple requirements when the system switches between active mode and standby mode. Rev. A | Page 18 of 28 Data Sheet ADP5310 ADJUSTABLE AND FIXED OUTPUT VOLTAGES The buck regulator in Channel 1 provides adjustable and fixed output voltage settings via the factory fuse. For the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage (0.8 V for Channel 1). The buck regulator in Channel 2 provides adjustable and fixed output voltage settings via the factory fuse as well. Because the input source of the load switch in Channel 3 shares the FB2 pin, the load switch in Channel 3 is unusable when Channel 2 is configured in adjustable output mode via the factory fuse. UNDERVOLTAGE LOCKOUT (UVLO) The UVLO circuitry monitors the input voltage level of the ADP5310 in the PVIN2 pin. When the input voltage falls below 2.40 V (typical), all channels turn off. After the input voltage rises above 2.55 V (typical), the soft start period is initiated, and the corresponding channel is enabled when the ENx pin is high. ENABLE AND SHUTDOWN FEATURES The ADP5310 uses the enable pins (EN1 and EN3) at logic levels to enable and disable Channel 1 and Channel 3. The associated channel begins operation with soft start when the enable pin is toggled from logic low to logic high. Pulling an enable pin low forces the associated channel into a shutdown condition. The buck regulator in Channel 2 is always alive as long as the PVIN2 voltage is above the UVLO threshold. INTERNAL LINEAR REGULATOR (VREG) The internal linear VREG regulator in the ADP5310 provides a stable 3.9 V power supply for the bias voltage of the MOSFET drivers and internal control circuits. Connect a 1.0 F ceramic capacitor between VREG and ground. OSCILLATOR AND SYNCHRONIZATION The ADP5310 ensures that both buck regulators operate at the same switching frequency when both buck regulators are in PWM mode. The ADP5310 offers 600 kHz or 1.2 MHz switching frequency options in PWM operation mode via the factory fuse. The default switching frequency is 1.2 MHz. The switching frequency of the ADP5310 can be synchronized to an external clock with a frequency range from 400 kHz to 1.4 MHz. The ADP5310 automatically detects the presence of an external clock applied to the SYNC/MODE pin, and the switching frequency transitions to the frequency of the external clock. When the external clock signal stops, the device automatically switches back to the internal clock and continues to operate. CURRENT LIMIT The buck regulators in the ADP5310 have protection circuitry that limit the direction and the amount of current to a certain level that flows through the high-side MOSFET and the lowside MOSFET in cycle-by-cycle mode. The positive current limit on the high-side MOSFET limits the amount of current that can flow from the input to the output. The negative current limit on the low-side MOSFET prevents the inductor current from reversing direction and flowing out of the load. SHORT-CIRCUIT PROTECTION The buck regulators in the ADP5310 include frequency foldback to prevent current runaway on a hard short. When the output voltage at the feedback pin falls below 0.3 V, indicating the possibility of a hard short at the output, the switching frequency (in PWM mode) is reduced to 1/4 of the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. SOFT START The ADP5310 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the device. The default soft start time is 350 s for the regulators in Channel 1 and Channel 2. Different soft start times can be programmed for each channel by the factory fuse. STARTUP WITH PRECHARGED OUTPUT The buck regulators in the ADP5310 include a precharged start-up feature to protect the low-side FETs from damage during startup. If the output voltage is precharged before the regulator is turned on, the regulator prevents reverse inductor current, which discharges the output capacitor until the internal soft start reference voltage exceeds the precharged voltage on the feedback pin. 100% DUTY OPERATION With a drop in input voltage or with an increase in load current, the buck regulator in the ADP5310 may reach a limit where, even with the high-side MOSFET on 100% of the time, the ADP5310 works in 100% duty operation and the output is lower than the preset value. At this limit, the buck regulator transitions to a mode where the high-side MOSFET switch stays on 100% of the time. When the input conditions charge again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. Rev. A | Page 19 of 28 ADP5310 Data Sheet ACTIVE DISCHARGE LOAD SWITCH All channels in the ADP5310 integrate an optional, factory programmable, discharge switch from the switching node (or from the VOUT3 pin in the load switch) to ground. This switch turns on when its associated regulator is disabled, which helps discharge the output capacitor quickly. The typical value of the discharge switch is 282 to 287 for each channel. The ADP5310 integrates a high-side load switch that operates from 1.65 V to 5.5 V. The supply of the load switch is connected to the FB2 pin of Channel 2 internally, which provides the power domain isolation for the output of Channel 2 and helps extend battery operation time. The Channel 3 load switch has a low on resistance of 494 m (typical) at VOUT3 = 2.5 V. By default, the discharge function is not enabled. The option to enable this active discharge function can be programmed for each channel by the factory fuse. The inrush control circuitry (soft start) is included in the load switch as well. The default soft start time is 12 s. Different soft start times can be programmed by the factory fuse. POWER-GOOD FUNCTION Note that the load switch in Channel 3 is not usable when Channel 2 is configured as the adjustable output mode via the factory fuse. The ADP5310 includes an open-drain, power-good output (PWRGD pin) that becomes active high when the buck regulator in Channel 1 is operating normally. THERMAL SHUTDOWN A logic high on the PWRGD pin indicates that the regulated output voltage of the buck regulator in Channel 1 is above 92% (typical) of its nominal output for a delay time greater than approximately 16 switching cycles (typical). When the regulated output voltage of the buck regulator in Channel 1 falls below 87% (typical) of its nominal output, the PWRGD pin goes low. If the ADP5310 junction temperature exceeds 135C, the thermal shutdown circuit turns off the IC except for the internal linear regulator. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15C hysteresis is included so that the ADP5310 does not return to operation after thermal shutdown, until the on-chip temperature falls below 120C. When the device exits thermal shutdown, a soft start is initiated for each enabled channel. Rev. A | Page 20 of 28 Data Sheet ADP5310 APPLICATIONS INFORMATION This section describes the external components selection for the ADP5310. The typical application circuit is shown in Figure 56. L1 4.7H FROM MCU EN1 PVIN1 PVIN PVIN2 C1 10F MLCC SW1 VOUT1 C3 10F MLCC PGND1 R1 ADP5310 R2 R3 PWRGD PWRGD EN3 VOUT3 VOUT2 SW2 VOUT3 C5 220nF MLCC PGND2 VREG L2 4.7H C4 10F MLCC FB2 AGND 13008-056 C2 1F Figure 56. Typical Application Circuit EXTERNAL COMPONENT SELECTION Table 6, Table 7, and Table 8 list external component selections for the ADP5310 application circuit. The selection of components is dependent on the input voltage, output voltage, and load current requirements. Additionally, trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. SELECTING THE INDUCTOR The high frequency switching of the ADP5310 allows the use of small surface-mount power inductors. The inductor value affects the transition from PWM to PSM, efficiency, output ripple, and current limit values. Use the following equation to calculate the ideal inductance, which is derived from the inductor current slope compensation, for a given output voltage and switching frequency: L= I I PK = I LOAD( MAX ) + L 2 FB1 NC SYNC/MODE FROM MCU The dc resistance (DCR) value of the selected inductor affects efficiency. A minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple, as shown in the following equation: 1.2 x VOUT k x f SW OUTPUT CAPACITOR Output capacitance is required to minimize the voltage overshoot, voltage undershoot, and the ripple voltage present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple; Furthermore, use capacitors such as the X5R and X7R dielectric. Do not use Y5V and Z5U capacitors. Y5V and Z5U capacitors are unsuitable choices because of their large capacitance variation over temperature and their dc bias voltage changes. Because ESR is important, select the capacitor using the following equation: ESRCOUT where: ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. Use the following equation to determine the output capacitance: C OUT Increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. When choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. An input capacitor is required to reduce input voltage ripple and source impedance. Place the input capacitor as close as possible to the PVINx pin. A low ESR X7R or X5R type capacitor is highly recommended to minimize the input voltage ripple. Use the following equation to determine the rms input current: The ripple current is calculated as follows: V VOUT x 1 - OUT f SW x L VIN I L 8 x f SW x VRIPPLE INPUT CAPACITOR where: L is the inductor value in H. VOUT is the output voltage for Channel 1 and Channel 2 of the buck regulator. k is 1.06 (Channel 1) or 0.478 (Channel 2). fSW is the switching frequency in MHz (1.2 MHz typical). I L = VRIPPLE I L Rev. A | Page 21 of 28 I RMS I LOAD( MAX ) VOUT (VIN - VOUT ) VIN ADP5310 Data Sheet ADJUSTABLE OUTPUT VOLTAGE PROGRAMMING The ADP5310 features an adjustable output voltage range from 0.8 V to 5.0 V. The output voltage is set by the ratio of two external resistors. The device servos the output to maintain the voltage at the FBx pin at 0.8 V, referenced to ground; the current in R1 is then equal to 0.8 V/R2 plus the FB pin bias current. The bias current of the FBx pin, 15 nA at 25C, flows through R2 into the FBx pin. The output voltage is calculated using the equation VOUT = 0.8 V(1 + R1/R2) + (IFB_ADJ)(R1) To minimize errors in the output voltage caused by the bias current of the FBx pin, maintain a value of R2 that is less than 200 k. For example, when R1 and R2 each equal 200 k, the output voltage is 1.6 V. The output voltage error introduced by the FBx pin bias current is 3 mV, or 0.187%, assuming a typical FBx pin bias current of 15 nA at 25C. Note that in shutdown mode, the output is turned off and the divider current is zero. EFFICIENCY Efficiency is the ratio of output power to input power. The high efficiency of the ADP5310 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package, which in turn, reduces thermal constraints. Second, the high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (RDS(ON)) associated with them. The amount of power loss is approximated by PSW_COND = (RDS(ON)_P x D + RDS(ON)_N x (1 - D)) x IOUT ADP5310 has high switching frequency dc-to-dc regulators, shielded ferrite core material is recommended because of its low EMI. To estimate the total amount of power lost in the inductor (PL), use the following equation: PL = DCR x IOUT2 + Core Losses Driver Losses Driver losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Estimate driver losses using the following equation: PDRIVER = (CGATE_P + CGATE_N) x VIN2 x fSW where: CGATE_P is the gate capacitance of the internal high-side switch. CGATE_N is the gate capacitance of the internal low-side switch. fSW is the switching frequency. The typical value for both gate capacitances, CGATE_P and CGATE_N, is 150 pF. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of an SWx node transition, the power switch provides all of the inductor current. The source-to-drain voltage of the power switch is half of the input voltage, resulting in power loss. Transition losses increase with both load current and input voltage and occur twice for each switching cycle. Use the following equation to estimate transition losses: PTRAN = VIN/2 x IOUT x (tR + tF) x fSW where: tR is the rise time of the SWx node. tF is the fall time of the SWx node. 2 where: The typical value for the rise and fall times, tR and tF, is 2 ns. V D = OUT VIN RECOMMENDED BUCK EXTERNAL COMPONENTS The internal resistance of the power switches increases with temperature and increases when the input voltage is less than 5.5 V. The recommended external components for use with the ADP5310 are listed in Table 6, Table 7, and Table 8. Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal DCR associated with it. Larger size inductors have smaller DCR, which can decrease inductor conduction losses. Inductor core losses relate to the magnetic permeability of the core material. Because the Rev. A | Page 22 of 28 Data Sheet ADP5310 Table 6. Channel 1 Inductors Vendor Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft 1 Model XFL4020-102ME XFL4020-152ME XFL4020-222ME XFL4020-332ME XFL4020-472ME XFL4020-222ME XFL4020-332ME XFL4020-472ME XAL4030-682ME XAL4040-103ME Frequency 1.2 MHz 1.2 MHz 1.2 MHz 1.2 MHz 1.2 MHz 600 kHz 600 kHz 600 kHz 600 kHz 600 kHz Output Voltage (V) 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 Ideal Value (H) 1.1 1.7 2.4 3.1 4.7 2.3 3.4 4.7 6.2 9.4 Standard Value (H) 1 1.5 2.2 3.3 4.7 2.2 3.3 4.7 6.8 10 Dimensions (mm) 4x4x2 4x4x2 4x4x2 4x4x2 4x4x2 4x4x2 4x4x2 4x4x2 4x4x3 4x4x4 Standard Value (H) 2.2 3.3 4.7 6.8 6.8 10 4.7 6.8 10 10 15 22 Dimensions (mm) 4x4x2 4x4x2 4x4x2 4x4x3 4x4x3 4x4x4 4x4x2 4x4x3 4x4x4 4x4x4 4x4x4 6 x 6 x 3.5 ISAT 1 (A) 4.5 4.1 3.1 2.7 2.0 3.1 2.7 2.0 1.9 1.5 DCR (m) 12 16 24 38 57 24 38 57 74 92 ISAT 1 (A) 4.1 3.1 2.0 1.9 1.9 1.5 2.0 1.9 1.5 1.5 1.3 1.6 DCR (m) 24 38 57 74 74 92 57 74 92 92 120 145 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current. Table 7. Channel 2 Inductors Vendor Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft Coilcraft 1 Model XFL4020-222ME XFL4020-332ME XFL4020-472ME XAL4030-682ME XAL4030-682ME XAL4040-103ME XFL4020-472ME XAL4030-682ME XAL4040-103ME XAL4040-103ME XAL4040-153ME LPS6235-223ML Frequency 1.2 MHz 1.2 MHz 1.2 MHz 1.2 MHz 1.2 MHz 1.2 MHz 600 kHz 600 kHz 600 kHz 600 kHz 600 kHz 600 kHz Output Voltage (V) 1.2 1.8 2.5 3.0 3.3 5 1.2 1.8 2.5 3.0 3.3 5 Ideal Value (H) 2.5 3.8 5.2 6.3 6.9 10.5 5.0 7.5 10.5 12.6 13.8 20.9 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current. Table 8. 10 F Capacitors Vendor Murata Murata Murata Murata Murata Murata Murata Model GRM32ER7YA106KA12 GRM32DR61E106KA12 GRM31CR61C106KA88 GRM32ER7YA106KA12 GRM32DR61E106KA12 GRM31CR61C106KA88 GRM21BR61C106KE15 Case Size 1210 1210 1206 1210 1210 1206 0805 Voltage Rating (V) 35 25 16 35 25 16 16 Rev. A | Page 23 of 28 Location Input Input Input Output Output Output Output Input Voltage (V) 12 < VIN < 15 8 < VIN < 12 VIN < 8 Not applicable Not applicable Not applicable Not applicable Output Voltage (V) Not applicable Not applicable Not applicable 9 < VOUT < VIN 7 < VOUT < 9 2.5 < VOUT < 7 VOUT < 2.5 ADP5310 Data Sheet CAPACITOR SELECTION Output Capacitor The ADP5310 is designed for operation with small, space-saving ceramic capacitors, but functions with most common capacitors provided that the ESR value is carefully considered. The ESR of the output capacitor affects the stability of the control loop. A minimum output capacitance of 6.2 F with an ESR of 10 m or less is recommended to ensure the stability of the ADP5310. Input Bypass Capacitor recommended for best performance. Y5V and Z5U dielectrics are not recommended because of their poor temperature and dc bias characteristics. Use the following equation to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage: CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient (TC). TOL is the worst-case component tolerance. Connect a 10 F capacitor from PVINx to PGND to reduce the circuit sensitivity to the printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 10 F of output capacitance is required, increase the input capacitor to match the output capacitance to improve the transient response. In this example, the worst-case TC over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 8.53 F at 12 V for the 10 F, 35 V capacitor in a 1210 package. Input and Output Capacitor Properties Substituting these values in Equation 1 yields Use any good quality ceramic capacitors with the ADP5310; however they must meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectric capacitors with a voltage rating of 6.3 V to 25 V are CEFF = 8.53 F x (1 - 0.15) x (1 - 0.1) = 6.53 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ADP5310 over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5310, it is imperative that the effects of dc bias, temperature, and tolerances of the capacitors are evaluated for each application. CIRCUIT BOARD LAYOUT RECOMMENDATIONS 10F 25V/X5R 1206 VIN 4.7H 4mm x 4mm 16 SW1 PVIN2 2 15 PGND1 NC 3 ADP5310 PGND2 5 12 PWRGD VOUT3 FB2 6 1.0F 6.3V/X5R 0603 13 FB1 100k 0402 11 SYNC/MODE VOUT3 7 10 VREG EN3 8 9 AGND 15.75 Figure 57. Typical PCB Layout for the ADP5310 Rev. A | Page 24 of 28 13008-057 10F 25V/X5R 1206 10F 25V/X5R 1206 14 EN1 100k 0402 SW2 4 8.94 VOUT1 PVIN1 1 1.0F 6.3V/X5R 0402 VOUT2 4.7H 4mm x 4mm Data Sheet ADP5310 TYPICAL APPLICATION CIRCUITS Figure 58 and Figure 59 show how the ADP5310 can be applied in energy metering and medical applications controlled by a microcontroller or a processor. ADP5310 SW1 EN1 FROM MCU CHANNEL 1 PGND1 BUCK REGULATOR FB1 (800mA) PWRGD TO MCU PVIN1 - + - + 2 x LiMnO2 MAX = 15V MIN = 2.7V PVIN2 NC 10F SYNC/ MODE 3.6V~4.6V AT 400mA 4.7H CHANNEL 2 SW2 ULTRALOW POWER PGND2 BUCK REGULATOR FB2 (50mA/300mA) PA 10F R1 R2 VOUT CONTROL (BY DAC OR GPIO SWITCH) 2.2V~2.8V AT 2A 4.7H 10F MCU (ALWAYS ON) INPUT/ OUTPUT CHANNEL 3 LOAD SWITCH EN3 FROM MCU 1F ADF70xx (Rx/Tx) AGND 13008-058 VREG 2.2V~2.8V AT 15mA VOUT3 1F Figure 58. Typical Application of a Smart Meter ALWAYS ON HIBERNATE ADP5310 FROM DSP TO DSP - + - + MAX = 15V MIN = 2.7V SW1 CHANNEL 1 PWRGD PGND1 BUCK REGULATOR PVIN1 FB1 (800mA) EN1 PVIN2 NC 22F SYNC/ MODE CHANNEL 2 SW2 ULTRALOW POWER PGND2 BUCK REGULATOR FB2 (50mA/300mA) 1.0H 1.1V 10F R1 6.8H VOUT CONTROL (BY DAC OR R2 SWITCH) 3.3V 10F ADP160 VDD_INT ADI DSP VDD_EXT VDD_OTP VDD_HADC VDD_USB VDD_RTC VDD_DMC 1.8V LPDDR VREG MODE: HIGH = FORCED PWM LOW = FORCED HYSTERESIS VOUT3 3.3V CMOS SENSOR 3.3V PERIPHERAL (ALWAYS ON) 3.3V PERIPHERAL (OFF HIBERNATE) 1F AGND 1F Figure 59. Battery Powered Typical Application with a DSP from Analog Devices, Inc. Rev. A | Page 25 of 28 13008-059 FROM DSP CHANNEL 3 LOAD SWITCH EN3 ADP5310 Data Sheet FACTORY PROGRAMMABLE OPTIONS To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 9. Output Voltage Options for Channel 1 (Fixed Output Options: 1.2 V to 5.0 V) Option Option 0 Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Description 0.8 V adjustable output (default) 1.2 V fixed output 1.5 V fixed output 1.8 V fixed output 2.5 V fixed output 2.85 V fixed output 3.3 V fixed output 5.0 V fixed output Table 10. Output Voltage Options for Channel 2 (Fixed Output Options: 1.20 V to 3.60 V in 50 mV Increments, and 3.60 V to 5.00 V in 100 mV Increments) Option Option 0 Option 1 Option 2 ... Option 35 Option 36 Option 37 Option 38 ... Option 48 Option 49 Option 50 Option 51 ... Option 62 Option 63 Description 0.8 V adjustable output (note that the Channel 3 load switch is not usable in this configuration) 1.20 V fixed output 1.25 V fixed output ... 2.90 V fixed output 2.95 V fixed output 3.00 V fixed output (default) 3.05 V fixed output ... 3.55 V fixed output 3.60 V fixed output 3.70 V fixed output 3.80 V fixed output ... 4.90 V fixed output 5.00 V fixed output Table 11. Switching Frequency Option Option 0 Option 1 Description 1.2 MHz (default) 600 kHz Table 12. Operation Mode for Channel 1 Option Option 0 Option 1 Description Forced PWM mode Automatic PWM/PSM mode (default) Table 13. Output Discharge Functionality Options for Channel 1 Option Option 0 Option 1 Description Output discharge function disabled for the buck regulator in Channel 1 (default) Output discharge function enabled for the buck regulator in Channel 1 Rev. A | Page 26 of 28 Data Sheet ADP5310 Table 14. Output Discharge Functionality Options for Channel 2 Option Option 0 Option 1 Description Output discharge function disabled for the buck regulator in Channel 2 (default) Output discharge function enabled for the buck regulator in Channel 2 Table 15. Output Discharge Functionality Options for Channel 3 Option Option 0 Option 1 Description Output discharge function disabled for the load switch in Channel 3 (default) Output discharge function enabled for the load switch in Channel 3 Table 16. Soft Start Time for Channel 1 Option Option 0 Option 1 Description 350 s (default) 2800 s Table 17. Soft Start Time for Channel 2 Option Option 0 Option 1 Description 350 s (default) 2800 s Table 18. Turn-On Rise (Soft Start) Time for Channel 3 Option Option 0 Option 1 Option 2 Option 3 Description 3 s 12 s (default) 48 s 192 s Rev. A | Page 27 of 28 ADP5310 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 9 4.50 4.40 4.30 1 6.40 BSC 8 TOP VIEW BOTTOM VIEW 1.05 1.00 0.80 1.20 MAX 0.15 0.05 SEATING PLANE COPLANARITY 0.10 0.65 BSC 3.05 3.00 SQ 2.95 EXPOSED PAD 0.30 0.19 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 8 0 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-ABT 02-17-2012-A 16 Figure 60. 16-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] (RE-16-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5310AREZN-255R7 ADP5310AREZN-2.8R7 ADP5310AREZN-3.3R7 ADP5310AREZN-R7 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage Channel 1 = adjustable, Channel 2 = 2.55 V Channel 1 = adjustable, Channel 2 = 2.8 V Channel 1 = adjustable, Channel 2 = 3.3 V Channel 1 = adjustable with automatic PWM/PSM mode, Channel 2 = adjustable ADP5310READJ-EVALZ 1 Package Description 16-Lead TSSOP_EP 16-Lead TSSOP_EP 16-Lead TSSOP_EP 16-Lead TSSOP_EP Evaluation Board Z = RoHS Compliant Part. (c)2015-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13008-0-11/16(A) Rev. A | Page 28 of 28 Package Option RE-16-2 RE-16-2 RE-16-2 RE-16-2