55/75107A * 55/75108A 55/75107B - 55/75108B DUAL LINE RECEIVERS FAIRCHILD LINEAR INTEGRATED CIRCUITS GENERAL DESCRIPTION The 55/75107A/B and 55/75108A/B are high speed, two-channel Line Receivers with common voltage supply and ground terminals. They are designed to detect input signals of 25mV (or greater) amplitude and convert the polarity of the signal into appropriate TTL compatible output logic levels. They feature high input impedance and low input currents which induce very little foading on the transmission line making these devices ideal for use in party line systems. The receiver input common mode voltage range is 43V but can be increased to +15V by the use of input attenuators. Separate or common strobes are available. The 55/75107A/B circuit features an active pull-up (totem pole output). The 55/75108A/B circuit features an open collector output configuration that permits wired-QR connections. The receivers are designed to be used with the 55109/75109 and $5110/75110 line drivers. The 55/75107A/B and 55/75108A/B line receivers are useful in high speed balanced, unbalanced and party fine transmission systems and as data comparators. (See following description of A and B versions.) HIGH SPEED STANDARD SUPPLY VOLTAGES DUAL CHANNELS HIGH COMMON-MODE REJECTION RATIO HIGH INPUT IMPEDANCE HIGH INPUT SENSITIVITY INPUT COMMON-MODE VOLTAGE RANGE OF +3 V SEPARATE OR COMMON STROBES TTL OR DTL DRIVE CAPABILITY WIRED-OR OUTPUT CAPABILITY HIGH DC NOISE MARGINS STROBE INPUT CLAMP DIODES 55/75107B SERIES DEVICES ARE DIRECT REPLACEMENTS FOR 55/75107A SERIES DEVICES B VERSION AVAILABLE UPON REQUEST INPUT IS DIODE PROTECTED AGAINST POWER-OFF LOADING ON B VERSIONS DEVICES The essential difference between the 55/75107A and 55/75107B versions is shown in the following schematics of the input stage: Vec+ Vec+ > < 4 < < 3 3 3 ; | INPUT | | PROTECTION | ! DIODES I 1 1 I A I A | | 8 B A Version l "8" Version i The input protection diodes are useful! in certain party-line systems which may have multiple Vec+ power supplies and, in which case, may be operated with some of the Voc+ supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows: A Version = B Version = This would be a problem in specific systems which might possibly have the transmission lines biased to some potential greater than 1.4 V. Since this is not a widespread application problem, both the A and B versions will be available. The ratings and characteristic specifications of the B versions are the same as those of the A versions. The B versions wifl be supplied upon request. : CONNECTION DIAGRAM 14-LEAD DIP (TOP VIEW) PACKAGE OUTLINES 6A 9A 31 PACKAGE CODES D P F IN At IN A2 NC OUTA STROBE A STROBE ORDER INFORMATION TYPE PART NO. 55107A 55107AFM 5107A 55107ADM 7S107A 75107ADC 75107A 78107APC 55108A 55108AFM 55108A 55108ADM 75108A 75108ADC 75108A 75108APC 551078 55107BFM 55107B 5107BDM 78107B 75107BDC 75107B 75107BPC 55108B 55108BFM 55108B 55108BDM 75108B 75108BDC 75108B 75108BPC 11-102FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A * 55/75107B * 55/75108A 55/75108B EQUIVALENT CIRCUIT Ri 1209 Vec+ O We 4 grt <R2 SRS AB Ro -_ Sine S$ 1k $4000 aka taka 4 to10 t a4 RG J A2Kns &--fla1 03 4 ar fF, 08 ag $uh OUT A + 012 mo Ko a2 + z z2 RT $Aio | INPUTS 760 2 Sina ie GND A20 tos os STROBE A orig $39k2 $A3 $ R6 <ce ee et 4 4 Kos a3 Vec- L STROBE ais a17 3 ee Sai R17 S3kn 23kQ B20= Koz a2 STROBE B INPUTS. . R20: B10-J aw ais z3 za 7600 Ke Kon [ox R19 s 021 42 as gr $Ri5 srs R21 Sika S1Ka 2 4002 4ka NOTE: Components shown with dashed lines are applicable to the 55107A/8 and 75107A/B only. See preceding description for differences between A and B versions. ABSOLUTE MAXIMUM RATINGS Supply Voltage (Note 1) Internal Power Dissipation (Note 3) Differential Input Voltage (Note 2) Common Mode Input Voltage (Note 1) Strobe Input Voltage (Note 1) Operating Temperature Range 55107A/107B/108A/108B 75107A/107B/108A/108B Storage Temperature Range Lead Temperature Hermetic DIP, Flatpak (Soldering, 60 s) Molded DtP (Soldering, 10 s) Notes on following pages. 17V 670 mW 26V 15V 5.5V 85C to +125C 0C to +70C 65C to +150C 300C 260C 11-103FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A * 55/75107B * 55/75108A * 56/75108B ELECTRICAL CHARACTERISTICS (Ratings Apply Over Full Ambient Temperature Range With Vcc+= Max and Voc_. = Max, unless otherwise noted) (Notes 4 & 6) 55/75107A, 55/75107B SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS tH input HIGH Current Voirr = 0.5 V, Vom = -3 V tot+3 V 30 75 BA Ye Input LOW Current VoIFF = -2 V, Vom = 3 V to +3 V -10 uA v =2.4V NWHIG) Gate Input HIGH Current GATE 40 HA VGATE = Vt 1.0 mA NL(G} Gate Input LOW Current VGaATE =04V 1.6 mA Vv. =2.4 lH(s) Strobe Input HIGH Current STROBE * 2.4 V 80 HA VSTROBE = V+ 2.0 mA lies) Strobe Input LOW Current VsSTROBE = 0.4 V 3.2 mA Vv = Vou Output HIGH Voltage IL = 400 uA, Vom = -3 V to +3 V ccy=MIN| 34 v Vec = MIN Vv, = MIN VoL Output LOW Voltage ISINK = 16 MA, Voy =3V to +3 V ot 0.4 v Voec = MIN isc Short-Circuit Output Current | Vout = 0 (Note 5) 18 70 mA lec+ Positive Supply Current Vout = Vou. I. = 9, Ta = 25C 18 30 mA !cc | Negative Supply Current Vout = Vor. IL = 9, Ta = 25C ~8.4 15 mA AC CHARACTERISTICS (Vcc4 = +5 V, Vec 2 5 V, RL = 390 2, CL = 50 pF, Ta = 25C. See Test Circuit) tpLH (D) 17 25 ns tpHL (D) 17 25 PHL) Propagation Delay Time tpLH(S) 10 15 ns tpHL (S) 10 15 ns ELECTRICAL CHARACTERISTICS 55/75108A, 55/75108B (Ratings Apply Over Full Ambient Temperature Range With Vcc + = Max and Vcoc_ = Max, uniess otherwise noted) (Notes 4 & 6) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX | UNITS i) Input HIGH Current VbDIFF = 0.5 V, Vom =~3 V to +3 V 30 75 uA Ve Input LOW Current Vorrpe =2 V. Vom = 3 V to+3V -10 BA Vv =2.4V 40 A WHIG) Gate Input HIGH Current GATE p VGATE = V+ 1.0 mA NIL(G) Gate Input LOW Current VGATE =04V 1.6 mA HH (Ss) Strobe Input HIGH Current VsTROBE = 2,4V 80 uA VsTROBE = V+ 2.0 mA Ls) Strobe Input LOW Current VsTROBE = 0.4V 3.2 mA Vv = MIN VoL Output LOW Voltage ISINK = 16 MA, Vom = -3 V to +3 V [Cot 0.4 v Vec = MIN Vv Output HIGH Current Vv V+ Vec+ = MIN IH urre! = OuT Voc. = MIN 250 uA loc+ Positive Supply Current Vout = Vor. tL = 0, Ta = 25C 18 30 mA loc Negative Supply Current Vout = Vou. !L = 9, Ta = 28C 8.4 ~18 mA AC CHARACTERISTICS (Vccz = +5 V, Vec = 5 V. RL, = 390 2, CL = 15 pF, Ta = 25C. See Test Circuit) tpLH(D) 19 25 ns tpHi(D) p on D , 19 25 ns tPLn tS) ropagation Delay Time 13 20 ns teu (S) 13 20 ns 11-104FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A 55/75107B * 55/75108A * 55/75108B TRUTH TABLE RECOMMENDED COMBINATIONS INPUT A-TO-GROUND VOLTAGE - V 4 ~3 OF INPUT VOLTAGE FOR LINE RECEIVERS 2 -1 0 7 203 INPUT B.TO.GROUND VOLTAGE - V DIFFERENTIAL INPUTS STROBES OUTPUT AB G s Vip = 25 mv LorH | LorH H LorH L H 25 MV < Vip <25 mv L LorH H H H INDETERMINATE LorH L H Vip <25 mV L LorH H H H L TYPICAL PERFORMANCE CURVES OUTPUT VOLTAGE INPUT HIGH CURRENT AS A FUNCTION OF DIFFERENTIAL INPUT VOLTAGE > 7 4 8 3 x 33 $ fs BE: -8 1 Voc_ = ~8V. Neio Tanase a) -70 o 0 7 OO OIFFERENTIAL INPUT VOLTAGE - mV 55/75108A, 55/75108B PROPAGATION DELAY TIME LOW.-TO-HIGH LEVEL AS A FUNCTION OF AMBIENT TEMPERATURE Voos = BY Veet = sv + 150F PROPAGATION DELAY TIME ns 8 8 0 % 50 AMBIENT TEMPERATURE ~ C NOTES: 1. 2. 3. at 7.1 mMW/C uvove 60C. 4. PROPAGATION DELAY TIME ns. INPUT HIGH CURRENT pA INTO 1A OR 2A AS A FUNCTION OF AMBIENT TEMPERATURE 100 Vocs = 5 Vec- 7-8 V a0 SUPPLY CURRENT mA - -0 -% 6 8 BO 8 AMBIENT TEMPERATURE C 100125 55/75108A, 55/75108B PROPAGATION DELAY TIME HIGH-TO-LOW LEVEL AS A FUNCTION OF AMBIENT TEMPERATURE PROPAGATION DELAY TIME ne +B 0 Ey AMBIENT TEMPERATURE - C 125 These voitages are with respect to network ground terminal. These voitage values are at the noninverting (+) terminal with respect to the inverting () terminal. For Hermetic DIP rating applies to ambient temperatures up to 70C, above 70C: derate linearly at 8.3 mW/C. For Flatpak derate linearly HIGH LOGIC LEVEL SUPPLY CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE Voce 2 8 Veen" -5 a -16 50S AMBIENT TEMPERATURE C 5/75'107A, 55/75107B PROPAGATION DELAY TIME (STROBE INPUTS) AS A FUNCTION OF AMBIENT TEMPERATURE Voce 9 5 vec- = -8. + 390: CL > Voor a -7% -50 -% 0 2 OS AMBIENT TEMPERATURE ~ C 100128 PROPAGATION DELAY TIME ns PROPAGATION DELAY TIME ns. 55/75107A, 55/75107B PROPAGATION DELAY TIME (DIFFERENTIAL INPUTS) AS A FUNCTION OF AMBIENT TEMPERATURE 0 vi "SV vest os Slr, = 3000 CU + 500F 8 y a 0 75 80-25 AMBIENT TEMPERATURE ~ C 0 2 $0 7% 100 125 55/75108A, 55/75108B PROPAGATION DELAY TIME (STROBE INPUTS) AS A FUNCTION OF AMBIENT TEMPERATURE 64 --5 Ty vee & RL 3002 CL + SOnF 8 & 3 a a o 0 -75 -0 -2% 0 % SO 75 AMBIENT TEMPERATURE C 100128 For 55107A4/B and 55108A/B guaranteed supply voitage range is 4.5 V to 5.5 V. Operating temperature range is 55C < Tas +125C, For 75107A/B and 75108A/B guaranteed supply voltage range is 4.75 V to +5.25 V. Operating temperature range is OC < TaX< 70C. aoa . Note more than one (1) output should be shorted at a time. Voc Max implies Vec = 5.5 V or 5.25 V, depending on device type. 11-105FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A * 55/75107B * 55/75108A 55/75108B AC CHARACTERISTICS AC TEST CIRCUIT DIFFERENTIAL INPUT Vec~=-5.0V OUTPUT SS107A/B 75107 A/6 INPUT AT bh inpur az! QUTPUT A PULSE GENERATOR 502 I See Note 1 Vrer | | 100 mv 81) 82! l = L one a aes a STROBE A STROBE STROBE B OUTPUT put STROBE 502 INPUT See Note 2 PULSE - GENERATOR See Note 7 NOTES: KK oL 18 pF See Note 3 55108A/8 76108A/B / 1, The pulse generators have the following characteristics: Zou, = 50 8%, ty = tf = 10 + 5 ns, toy = 500 ns, PRR = 1 MHz, tp2 = 1 Ms, PRR = 500 kHz. . Strobe input pulse is applied to Strobe A when inputs A1-A2 are being tested: to common Strobe when inputs A1-A2 or B1-B2 are being 2 tested, and to Strobe 8 when inputs 81-B2 are being tested. 3. C_ includes probe and jig capacitance. 4. All diodes are 1N916. VOLTAGE WAVEFORMS INPUT A STROBE INPUT Aors PLD) QUTPUT A 11-106FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A 55/75107B * 55/75108A 55/75108B APPLICATION BASIC BALANCED.LINE TRANSMISSION SYSTEM Ry ra NAP = Wi Ww + Ry Ry = DATA 1 TWISTED-PAIR OR EQUIVALENT INPUT TRANSMISSION LINE 2 Z9=2Ry A STROBES INNIBIT ORIVER - kb -| RECEIVER The 55/75107A/B dual line circuits are designed specifically for use in high speed data transmission systems that utilize balanced, terminated transmission lines such as twisted-pair lines. The system operates in the balanced mode, so that noise induced on one line is also induced on the other. The noise appears common-mode at the receiver input terminals where it is rejected. The ground connection between the line driver and receiver is not part of the signal circuit so that system performance is not affected by circulating ground currents. The unique driver output circuit allows terminated transmission lines to be driven at normal line impedances. High speed system operation is ensured since line reflections are virtually eliminated when terminated lines are used. Cross-talk is minimized by low signal amplitudes and low line impedances. The typical data delay in a system is approximately (30+1.3L) ms, where L is the distance in feet separating the driver and receiver. This delay inctudes one gate delay in both the driver and receiver. Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current. The driven line is selected by appropriate driver-input logic levels. The voltage difference is approximately: VoIFF = 1/2 tout (on) * Rt High series line resistance will cause degradation of the signal. The receivers, however, will detect signals as low as 25 mV (or less), For normal line resistances, data may be recovered from lines of several thousand feet in length. Line-termination resistors (R-~) are required only at the extreme ends of the line. For short lines, termination resistors at the receiver only may Prove adequate. The signal amplitude will then be approximately: VDIFF ~ !ouT (on) * RT DATA-BUS OR PARTY-LINE SYSTEM RECEIVER ? RECEIVER 2 RECEIVER 4 STROBES STROBES TWISTED-PAIR LINE STROBES Rr P P e Ry AAA A WA rng cL TL RA ann = bw we ot LOCATION 2 DATA DRIVER 1 ORIVER 3 DRIVER 4 INPUT 1 1 1 2 2 t 2 INHIBIT A A A c c c LOCATION 1 LOCATION 3 LOCATION 4 The strobe feature of the receivers and the inhibit feature of the drivers allow the 55/75107A/B dual line circuits to be used in data-bus or party-line systems. In these applications, several drivers and receivers may share a common transmission line. An enabled driver transmits data to all enabled receivers on the line while other drivers and receivers are disabled. Data is thus time-multiplexed on the transmission line. The 55/75107A/B device specifications allow widely varying thermal and electrical environments at the various driver and receiver locations. The data-bus systern offers maximum performance at minimum cost. 11-107FAIRCHILD LINEAR INTEGRATED CIRCUITS 55/75107A * 55/75107B 55/75108A * 55/75108B APPLICATION (Contd) UNBALANCED OR SINGLE-LINE SYSTEMS 55/75107A/8 OR 55/75 108A/B INPUT OJ VREFOJ OUTPUT STROBES The 55/75107A/B dual line circuits may also be used in unbalanced or single-line systems. Although these systems do not offer the same performance as balanced systems for long lines, they are adequate for very short lines where environment noise is not severe. The receiver threshold fevel is established by applying a dc reference line is applied to the remaining input. The reference voltage should voltage to one receiver input terminal. The signal from the transmission be optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage should be in the range of 3.0 V to +3.0 V. It can be provided by a voltage supply or by a voltage divider from an avaitable supply voltage. PRECAUTIONS IN THE USE OF 55/75107A/B AND 55/751084/B DUAL LINE RECEIVERS The following precaution should be observed when using or testing 55/75107A/B line circuits: When only one receiver in a package is being used, at least one of the differentia! inputs of the unused receiver should be terminated at some voltage between 3.0 V and +3.0 V, preferably at ground. Failure to do so will cause improper operation of the unit being used because of common bias circuitry for the current sources of the two receivers. INCREASING COMMON-MODE INPUT VOLTAGE RANGE OF RECEIVER RI m 2 55/75107A/B or or 3 R2 $5/75108A/8 < J > fa STROBE! RI < S - FOR BALANCED, TERMINATED LINES, Zout 2 2R1 + 2R2 The 55/75107A/B and 55/75108A/B line receivers feature a common-mode input voltage range of +3.0 V. This satisfies the require- ments for all but the noisiest system applications. For these severe noise environments, the common-mode range can be extended by the use of external input attenuators. Common-mode input voltages can in this way be reduced to +3.0 V at the receiver input terminals. Differential data signats will be reduced proportionately. Input sensitivity, input impedance and delay times will be adversely affected. 55108A/75108A DOT-OR OUTPUT CONNECTIONS 55/75108A/B 55/75 108A/8 OUTPUT DOT-OR CONNECTION The 55/75108A/B line receivers feature an open-collector-output circuit that can be connected in the DOT-OR logic configuration with other 55/75108A/B outputs. This allows a level of logic to be_ implemented without additional logic delay. 11-108