Features S124 MCU (Ultra-Low-Power MCU) 32-bit ARM(R) Cortex(R)-M0+ microcontroller Ultra-low power 32-MHz ARM(R) Cortex(R)-M0+ microcontroller, up to 128-KB code flash memory, 16-KB SRAM, Capacitive Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features. Features ARM Cortex-M0+ Core ARMv6-M architecture Maximum operating frequency: 32 MHz Debug and Trace: DWT, BPU, CoreSightTM MTB-M0+ CoreSight Debug Port: SW-DP Memory Up to 128-KB code flash memory 4-KB data flash memory (up to 100,000 erase/write cycles) Up to 16-KB SRAM 128-bit unique ID Connectivity USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2 Serial Communications Interface (SCI) x 3 - UART - Simple IIC - Simple SPI Serial Peripheral Interface (SPI) x 2 I2C bus interface (IIC) x 2 CAN module (CAN) Analog 14-Bit A/D Converter (ADC14) 12-Bit D/A Converter (DAC12) Low-Power Analog Comparator (ACMPLP) x 2 Temperature Sensor (TSN) Timers General PWM Timer 32-Bit (GPT32) General PWM Timer 16-Bit (GPT16) x 6 Asynchronous General-Purpose Timer (AGT) x 2 Watchdog Timer (WDT) Safety SRAM Parity Error Check Flash Area Protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) Calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO Readback Level Detection Register Write Protection Main Oscillator Stop Detection R01DS0264EU0100 Rev.1.00 Feb 23, 2016 System and Power Management Low-power modes RealTime Clock (RTC) Event Link Controller (ELC) Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection with voltage settings Security and Encryption AES128/256 True Random Number Generator (TRNG) Human Machine Interface (HMI) Capacitive Touch Sensing Unit (CTSU) Multiple Clock Sources Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 5.5 V) (1 to 4 MHz when VCC = 1.6 to 5.5 V) Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) Independent watchdog timer OCO (15 kHz) Clock trim function for HOCO/MOCO/LOCO Clock out support General Purpose I/O Ports Up to 51 input/output pins - Up to 3 CMOS input - Up to 48 CMOS input/output - Up to 6 5-V tolerant input/output (when VCC = 3.6 V) - Up to 16 pins high current (20 mA) Operating Voltage VCC: 1.6 to 5.5 V Operating Temperature and Packages Ta = -40C to +85C - 36-pin LGA (4 mm x 4 mm, 0.5 mm pitch) Ta = -40C to +105C - 64-pin LQFP (10 mm x 10 mm, 0.5 mm pitch) - 48-pin LQFP (7 mm x 7 mm, 0.5 mm pitch) - 64-pin QFN (8 mm x 8 mm, 0.4 mm pitch) - 48-pin QFN (7 mm x 7 mm, 0.5 mm pitch) - 40-pin QFN (6 mm x 6 mm, 0.5 mm pitch) Page 1 of 95 S124 1. 1. Overview Overview The S124 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Based on the energy-efficient ARM(R) Cortex(R)-M0+ 32-bit core, this MCU is particularly well suited for cost-sensitive and low-power applications. The MCU in this series feature: Up to 128 KB code flash memory 16-KB SRAM Capacitive Touch Sensing Unit (CTSU) 14-bit ADC 12-bit DAC Security features. 1.1 Function Outline Table 1.1 ARM core Feature Functional description ARM Cortex-M0+ Maximum operating frequency: up to 32 MHz ARM Cortex-M0+: - Revision: r0p1-00rel0 - ARMv6-M architecture profile - Single-cycle integer multiplier. SysTick timer - Driven by LOCO clock. Table 1.2 Memory Feature Functional description Code flash memory Maximum 128 KB code flash memory. See section 37, Flash Memory in User's Manual. Data flash memory 4 KB data flash memory. See section 37, Flash Memory in User's Manual. Option-Setting Memory The option-setting memory determines the state of the MCU after a reset. See section 6, Option-Setting Memory and Information Memory in User's Manual. SRAM The MCU has an on-chip high-speed SRAM with even parity bit. See section 36, SRAM in User's Manual. Table 1.3 System (1/2) Feature Functional description Operating mode Two operating modes: Single-chip mode SCI boot mode. See section 3, Operating Modes in User's Manual. Reset The MCU has 9 types of resets: RES pin reset Power-on reset Independent watchdog timer reset Watchdog timer reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset SRAM parity error reset Software reset. See section 5, Resets in User's Manual. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 2 of 95 S124 Table 1.3 1. Overview System (2/2) Feature Functional description Low Voltage Detection (LVD) The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the detection level can be selected using a software program. See section 7, Low Voltage Detection (LVD) in User's Manual. Clock Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) Independent Watchdog Timer on-chip oscillator Clock out support. See section 8, Clock Generation Circuit in User's Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The clock frequency accuracy measurement circuit (CAC) is used to check the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual. Low Power Mode The MCU has several functions for reducing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 10, Low Power Modes in User's Manual. Register Write Protection The Register Write Protection function protects important registers from being overwritten due to software errors. See section 11, Register Write Protection in User's Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. See section 22, Watchdog Timer (WDT) in User's Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control. The watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 23, Independent Watchdog Timer (IWDT) in User's Manual. Table 1.4 Interrupt Control Feature Functional description Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in User's Manual. Table 1.5 Event Link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in User's Manual. Table 1.6 Direct memory access Feature Functional description Data Transfer Controller (DTC) The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User's Manual. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 3 of 95 S124 Table 1.7 1. Overview Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 1 channel and a 16-bit timer with 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors can be generated. The GPT can also be used as a general-purpose timer. See section 19, General PWM Timer (GPT) in User's Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 18, Port Output Enable for GPT (POEG) in User's Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 20, Asynchronous General Purpose Timer (AGT) in User's Manual. Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are used by switching register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 21, Realtime Clock (RTC) in User's Manual. Table 1.8 Communication interfaces (1/2) Feature Functional description Serial Communications Interface (SCI) The Serial Communication Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces: Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA)) 8-bit clock synchronous interface Simple IIC (master-only) Simple SPI Smart card interface The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 25, Serial Communications Interface (SCI) in User's Manual. I2C Bus interface (IIC) The MCU has a two-channel I2C bus interface (IIC). The IIC module conforms with and provides a subset of the NXP I2C bus (Inter-Integrated Circuit bus) interface functions. See section 26, I2C Bus Interface (IIC) in User's Manual. Serial Peripheral Interface (SPI) The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices. See section 28, Serial Peripheral Interface (SPI) in User's Manual. Controller Area Network (CAN) Module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 27, Controller Area Network (CAN) Module in User's Manual. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 4 of 95 S124 Table 1.8 1. Overview Communication interfaces (2/2) Feature Functional description USB 2.0 Full-Speed Module (USBFS) The MCU incorporates a USB 2.0 Full-Speed module (USBFS). The USBFS is a USB controller that is equipped to operate as a device controller. The module supports full-speed and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 5 pipes. PIPE0 and PIPE4 to PIPE7 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply 3.3 V. See section 24, USB 2.0 Full-Speed Module (USBFS) in User's Manual. Table 1.9 Analog Feature Functional description 14-bit A/D Converter (ADC14) The MCU incorporates up to one unit of a 14-bit successive approximation A/D converter. Up to 18 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 30, 14-Bit A/D Converter (ADC14) in User's Manual. 12-bit D/A Converter (DAC12) The MCU includes a 12-bit D/A converter with an output amplifier. See section 31, 12-Bit D/A Converter (DAC12) in User's Manual. Temperature Sensor (TSN) The on-chip Temperature Sensor can be used to determine and monitor the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC for conversion and can be further used by the end application. See section 32, Temperature Sensor (TSN) in User's Manual. Low-Power Analog Comparator (ACMPLP) Analog comparators can be used to compare a reference input voltage and analog input voltage. The comparison result can be read by software and also be output externally. The reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or from the internal reference voltage (Vref) generated internally in this MCU. The ACMPLP response speed can be set before starting an operation. Setting high-speed mode decreases the response delay time, but increases current consumption. Setting lowspeed mode increases the response delay time, but decreases current consumption. See section 33, Low-Power Analog Comparator (ACMPLP) in User's Manual. Table 1.10 Human machine interfaces Feature Functional description Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting a rising/falling edge to the key interrupt input pins. See section 17, Key Interrupt Function (KINT) in User's Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode. See section 34, Capacitive Touch Sensing Unit (CTSU) in User's Manual. Table 1.11 Data processing Feature Functional description Cyclic Redundancy Check (CRC) Calculator The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB first or MSB first communication. Additionally, various CRC generation polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 29, Cyclic Redundancy Check (CRC) Calculator in User's Manual. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 5 of 95 S124 Table 1.11 1. Overview Data processing Feature Functional description Data Operation Circuit (DOC) The Data Operation Circuit (DOC) is used to compare, add, and subtract 16-bit data. See section 35, Data Operation Circuit (DOC) in User's Manual. Table 1.12 Security Feature Functional description AES See the AES Engine chapter. True Random Number Generator (TRNG) See True Random Number Generator chapter. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 6 of 95 S124 1.2 1. Overview Block Diagram Figure 1.1 shows the block diagram of this MCU superset. Individual devices within the group may have a subset of the features. Memories Interrupt Control 128 KB Code Flash ICU ARM Cortex-M0+ System POR/LVD Clocks MOSC/SOSC 4 KB Data Flash Reset (H/M/L) OCO 16 KB SRAM NVIC Mode Control System Timer Power Control Test and DBG I/F Register Write Protection DMA DTC Timers Communication Interfaces Human Machine Interfaces GPT32 x 1 GPT16 x 6 SCI x 3 CTSU AGT x 2 IIC x 2 KINT RTC SPI x 2 CAN x 1 USBFS with BC1.2 WDT/IWDT Event Link CAC Data Processing Analogs ELC CRC ADC14 TSN Security DOC DAC12 ACMPLP x 2 AES + TRNG Figure 1.1 Block diagram R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 7 of 95 S124 1.3 1. Overview Part Numbering R 7 F S1 2 4 7 7 3 A 0 1 C F M Package type FM: LQFP 64 pins FL: LQFP 48 pins LM: LGA 36 pins NB: QFN 64 pins NE: QFN 48 pins NF: QFN 40 pins Quality ID Software ID Operating temperature 2: -40 C to 85 C 3: -40 C to 105 C Code flash memory size 6: 64 KB 7: 128 KB Feature set 7: Superset Group name 4: S124 Core 2: ARM Cortex-M0+ Series name 1: Ultra low power Renesas Synergy family Flash memory Renesas microcontroller Renesas Figure 1.2 Part numbering scheme R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 8 of 95 S124 1.4 1. Overview Function Comparison Table 1.13 Function comparison R7FS124773A01CFM/ R7FS124763A01CFM/ R7FS124773A01CNB/ R7FS124763A01CNB Parts number R7FS124773A01CFL/ R7FS124763A01CFL/ R7FS124773A01CNE/ R7FS124763A01CNE Pin count 64 48 Package LQFP/QFN LQFP/QFN R7FS124773A01CNF/ R7FS124763A01CNF Code flash memory 128/64 KB Data flash memory 4 KB SRAM System CPU clock Interrupt control ICU Event control ELC DMA DTC Timers GPT32 Analog 40 36 QFN LGA 7 6 4 4 2 2 12 11 17 13 5 4 16 KB Parity Communication R7FS124772A01CLM/ R7FS124762A01CLM 4 KB 32 MHz Yes 8 8 Yes 1 GPT16 6 6 AGT 2 2 RTC Yes WDT/IWDT Yes SCI 3 IIC 2 SPI 2 CAN Yes USBFS Yes ADC14 18 14 DAC12 1 ACMPLP 2 TSN Yes HMI CTSU 31 23 KINT 8 5 Data processing CRC Yes DOC Yes Security R01DS0264EU0100 Rev.1.00 Feb 23, 2016 AES and TRNG Page 9 of 95 S124 1.5 1. Overview Pin Functions Table 1.14 Pin functions (1/3) Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-F capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. Clock VSS Input Ground pin. Connect it to the system power supply (0 V). XTAL Output EXTAL Input Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. XCIN Input XCOUT Output Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. CLKOUT Output Clock output pin. Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins must not be changed during operation mode transition at the time of release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin. On-chip debug SWDIO I/O Serial Wire debug Data Input/Output pin. SWCLK Input Serial Wire Clock pin. NMI Input Non-maskable interrupt request pin. IRQ0 to IRQ7 Input Maskable interrupt request pins. GTETRGA, GTETRGB Input External trigger input pin. GTIOC0A to GTIOC6A, GTIOC0B to GTIOC6B I/O Input capture, Output Compare, or PWM output pin. GTIU Input Hall sensor input pin U. GTIV Input Hall sensor input pin V. GTIW Input Hall sensor input pin W. GTOUUP Output Three-phase PWM output for BLDC motor control (positive U phase). Interrupt GPT AGT GTOULO Output Three-phase PWM output for BLDC motor control (negative U phase). GTOVUP Output Three-phase PWM output for BLDC motor control (positive V phase). GTOVLO Output Three-phase PWM output for BLDC motor control (negative V phase). GTOWUP Output Three-phase PWM output for BLDC motor control (positive W phase). GTOWLO Output Three-phase PWM output for BLDC motor control (negative W phase). AGTEE0, AGTEE1 Input External event input enable. AGTIO0, AGTIO1 I/O RTC External event input and pulse output. AGTO0, AGTO1 Output Pulse output. AGTOA0, AGTOA1 Output Output compare match A output. AGTOB0, AGTOB1 Output Output compare match B output. RTCOUT Output Output pin for 1-Hz/64-Hz clock. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 10 of 95 S124 Table 1.14 1. Overview Pin functions (2/3) Function Signal I/O Description SCI SCK0, SCK1, SCK9 I/O Input/output pins for the clock (clock synchronous mode). RXD0, RXD1, RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode). TXD0, TXD1, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode). CTS0_RTS0, CTS1_RTS1, CTS9_RTS9 I/O Input/Output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active LOW. SCL0, SCL1, SCL9 I/O Input/output pins for the IIC clock (simple IIC). SDA0, SDA1, SDA9 I/O Input/output pins for the IIC data (simple IIC). SCK0, SCK1, SCK9 I/O Input/output pins for the clock (simple SPI). MISO0, MISO1, MISO9 I/O Input/output pins for slave transmission of data (simple SPI). MOSI0, MOSI1, MOSI9 I/O Input/output pins for master transmission of data (simple SPI). SS0, SS1, SS9 Input Slave-select input pins (simple SPI), active LOW. IIC SPI CAN USBFS Analog power supply SCL0, SCL1 I/O Input/output pins for clock. SDA0, SDA1 I/O Input/output pins for data. RSPCKA, RSPCKB I/O Clock input/output pin. MOSIA, MOSIB I/O Inputs or outputs data output from the master. MISOA, MISOB I/O Inputs or outputs data output from the slave. SSLA0, SSLB0 I/O Input or output pin for slave selection. SSLA1 to SSLA3, SSLB1 to SSLB3 Output Output pin for slave selection. CRX0 Input Receive data. CTX0 Output Transmit data. VSS_USB Input Ground pins. VCC_USB_LDO Input Power supply pin for USB LDO regulator. VCC_USB I/O Input: Power supply pin for USB transceiver. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. USB_DP I/O D+ I/O pin of the USB on-chip transceiver. This pin should be connected to the D+ pin of the USB bus. USB_DM I/O D- I/O pin of the USB on-chip transceiver. This pin should be connected to the D- pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a function controller. AVCC0 Input Analog voltage supply pin for the analog. Connect this pin to VCC. AVSS0 Input Analog ground pin. Connect this pin to VSS. VREFH0 Input Analog reference voltage supply pin for the A/D converter. Connect this pin to VCC when not using the A/D converter. VREFL0 Input Analog reference ground pin for the A/D converter. Connect this pin to VSS when not using the A/D converter. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 11 of 95 S124 Table 1.14 1. Overview Pin functions (3/3) Function Signal I/O Description ADC14 AN000 to AN010, AN016 to AN022 Input Input pins for the analog signals to be processed by the A/D converter. ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion, active LOW. DAC12 DA0 Output Output pins for the analog signals to be processed by the D/A converter. ACMPLP VCOUT Output Comparator output pin. CMPREF0, CMPREF1 Input Reference voltage input pins. CMPIN0, CMPIN1 Input Analog voltage input pins. TS00 to TS28, TS30, TS31 Input Capacitive touch detection pins (touch pins). TSCAP - Secondary power supply pin for the touch driver. KINT KR00 to KR07 Input Key interrupt input pins. I/O ports P000 to P004, P010 to P015 I/O General-purpose input/output pins. CTSU P100 to P113 I/O General-purpose input/output pins. P200 Input General-purpose input pin. P201, P204 to P206, P212, P213 I/O General-purpose input/output pins. P214, P215 Input General-purpose input pins. P300 to P304 I/O General-purpose input/output pins. P400 to P403, P407 to P411 I/O General-purpose input/output pins. P500 to P502 I/O General-purpose input/output pins. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 12 of 95 S124 1.6 1. Overview Pin Assignments Figure 1.3 P100 P101 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110 P109 P108/SWDIO 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 1.3 to Figure 1.8 show the pin assignments. P500 49 32 P300/SWCLK P501 50 31 P301 P502 51 30 P302 P015 52 29 P303 P014 53 28 P304 P013 54 27 P200 P012 55 26 P201/MD AVCC0 56 25 RES AVSS0 57 24 P204 P011/VREFL0 58 23 P205 P010/VREFH0 59 22 P206 P004 60 21 VCC_USB_LDO P003 61 20 VCC_USB P002 62 19 USB_DP P001 63 18 USB_DM P000 64 17 VSS_USB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P400 P401 P402 P403 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 R7FS1247x3A01CFM Pin assignment for LQFP 64-pin (Top view) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 13 of 95 33 34 35 36 37 38 39 40 41 42 43 44 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110 P109 P108/SWDIO 45 46 47 P100 P101 1. Overview 48 S124 P500 P501 P502 P015 P014 P013 P012 AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 49 32 50 31 58 23 59 22 60 21 61 20 62 19 63 18 P300/SWCLK P301 P302 P303 P304 P200 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB USB_DP USB_DM 51 30 52 29 53 28 54 27 55 26 P000 64 17 VSS_USB 24 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 P400 P401 P402 P403 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 1 57 2 R7FS1247x3A01CNB 56 Figure 1.4 Pin assignment for QFN 64-pin (Top view) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 14 of 95 P100 P101 P102 P103 P104 VSS VCC P112 P111 P110 P109 P108/SWDIO 35 34 33 32 31 30 29 28 27 26 25 1. Overview 36 S124 P500 37 24 P300/SWCLK P015 38 23 P301 P014 39 22 P302 P013 40 21 P200 P012 41 20 P201/MD AVCC0 42 19 RES AVSS0 43 18 P206 P011/VREFL0 44 17 VCC_USB_LDO P010/VREFH0 45 16 VCC_USB P002 46 15 USB_DP P001 47 14 USB_DM P000 48 13 VSS_USB 12 P408 P407 10 11 VCC P409 7 P213/XTAL 9 6 VSS 8 5 P214/XCOUT P212/EXTAL 4 P215/XCIN 3 VCL P400 2 25 26 27 28 29 30 31 32 33 P102 P103 P104 VSS VCC P112 P111 P110 P109 P108/SWDIO 34 35 P100 P101 36 Pin assignment for LQFP 48-pin (Top view) P500 P015 P014 P013 P012 AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P002 P001 37 24 38 23 44 17 45 16 46 15 47 14 P300/SWCLK P301 P302 P200 P201/MD RES P206 VCC_USB_LDO VCC_USB USB_DP USB_DM 39 22 40 21 41 20 P000 48 13 VSS_USB 18 12 11 10 9 8 7 6 5 19 P400 P401 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P409 P408 P407 4 R7FS1247x3A01CNE 3 43 2 42 1 Figure 1.5 P401 1 R7FS1247x3A01CFL Figure 1.6 Pin assignment for QFN 48-pin (Top view) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 15 of 95 21 22 23 24 25 26 P102 P103 P104 P112 P111 P110 P109 P108/SWDIO 27 28 29 P100 P101 1. Overview 30 S124 P015 P014 P013 P012 AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P001 31 20 32 19 37 14 38 13 39 12 P300/SWCLK P301 P200 P201/MD RES VCC_USB_LDO VCC_USB USB_DP USB_DM 33 18 34 17 P000 40 11 VSS_USB 35 16 10 9 8 7 6 5 4 3 1 15 P400 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P408 P407 2 R7FS1247x3A01CNF 36 Figure 1.7 Pin assignment for QFN 40-pin (Top view) R7FS1247x2A01CLM Figure 1.8 A B 6 P015 P100 5 P014 4 C D E F P112 P111 P108 /SWDIO P300 /SWCLK 6 P013 P101 P110 P200 VCC_USB _LDO 5 AVCC0 P012 P102 P109 P201/MD VCC_USB 4 3 AVSS0 P011 /VREFL0 P103 P213 /XTAL RES USB_DP 3 2 P010 /VREFH0 P000 P400 P212 /EXTAL P407 USB_DM 2 1 VCL P215 /XCIN P214 /XCOUT VSS VCC VSS_USB 1 A B D E F C Pin assignment for LGA 36-pin (Top view, pad side down) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 16 of 95 S124 1. Overview Pin Lists - - P402 4 - - - - P403 5 3 3 2 A1 6 4 4 3 B1 XCIN P215 7 5 5 4 C1 XCOUT P214 8 6 6 5 D1 VSS 9 7 7 6 D3 XTAL P213 10 8 8 7 D2 EXTAL P212 AGTEE1 VCC Interrupt - SCK0_B/ SCK1_B SCL0_A TS20 IRQ0 CTX0_B CTS0_RT SDA0_A S0_B/ SS0_B/ TXD1_B/ MOSI1_B/ SDA1_B TS19 IRQ5 CRX0_B RXD1_B/ MISO1_B/ SCL1_B TS18 IRQ4 CTS1_RT S1_B/ SS1_B TS17 GTIOC6A _A GTETRG GTIOC6B A_B _A CTSU - AGTIO1_ D DAC12, ACMPLP 3 P400 ADC14 P401 CACREF_ C GTIOC3A _B SPI - HMI IIC C2 - Analogs SCI 1 USBFS,CAN 1 2 Communication Interfaces RTC 1 2 GPT_OPS, POEG 1 2 AGT LGA36 I/O ports QFN40 Power, System, Clock, Debug, CAC Timers QFN48 LQFP48 LQFP64 Pin number GPT 1.7 VCL GTETRG A_D TXD1_A/ MOSI1_A/ SDA1_A IRQ2 GTETRG B_D RXD1_A/ MISO1_A/ SCL1_A IRQ3 11 9 9 8 E1 12 - - - - P411 AGTOA1 GTOVUP GTIOC6A _B _B TXD0_B/ MOSI0_B/ SDA0_B MOSIA_B TS07 IRQ4 13 - - - - P410 AGTOB1 GTOVLO GTIOC6B _B _B RXD0_B/ MISO0_B/ SCL0_B MISOA_B TS06 IRQ5 14 10 10 - - P409 GTOWUP GTIOC5A _B _B TXD9_A/ MOSI9_A/ SDA9_A TS05 IRQ6 15 11 11 9 - P408 GTOWLO GTIOC5B _B _B RXD9_A/ MISO9_A/ SCL9_A TS04 IRQ7 16 12 12 10 E2 P407 17 13 13 11 F1 18 14 14 12 F2 19 15 15 13 F3 20 16 16 14 F4 VCC_US B VCC_US B_LDO RTCOUT USB_VBU CTS0_RT SDA0_B S S0_D/ SS0_D SSLB3_A ADTRG0_ B TS03 RXD0_D/ SDA1_A MISO0_D/ SCL0_D SSLB1_A TS01 IRQ0 TXD0_D/ SCL1_A MOSI0_D/ SDA0_D/ CTS9_RT S9_A/ SS9_A SSLB0_A TSCAP_A IRQ1 VSS_USB USB_DM USB_DP 21 17 17 15 F5 22 18 18 - - 23 - - - - CLKOUT_ A P205 AGTO1 24 - - - - CACREF_ A P204 AGTIO1_ A 25 19 19 16 E3 RES 26 20 20 17 E4 MD 27 21 21 18 E5 P200 28 - - - - P304 GTIOC1A _B 29 - - - - P303 GTIOC1B _B P206 GTIU_A GTIV_A GTIOC4A _B GTIW_A GTIOC4B _B SCK0_D/ SCK9_A SCL0_B RSPCKB_ A TS00 P201 NMI TS02 30 22 22 - - P302 GTOUUP GTIOC4A _A _A SSLB3_B TS08 IRQ5 31 23 23 19 - P301 GTOULO GTIOC4B _A _A SSLB2_B TS09 IRQ6 32 24 24 20 F6 SWCLK P300 GTOUUP GTIOC0A _C _A SSLB1_B 33 25 25 21 E6 SWDIO P108 GTOULO GTIOC0B _C _A 34 26 26 22 D4 CLKOUT_ B P109 GTOVUP GTIOC1A _A _A R01DS0264EU0100 Rev.1.00 Feb 23, 2016 CTX0_A CTS9_RT S9_B/ SS9_B SSLB0_B TXD9_B/ MOSI9_B/ SDA9_B MOSIB_B TS10 Page 17 of 95 S124 1. Overview MISOB_B RSPCKB_ B 36 28 28 24 D6 P111 GTIOC3A _A SCK0_C/ SCK9_B 37 29 29 25 C6 P112 GTIOC3B _A TXD0_C/ MOSI0_C/ SDA0_C 38 - - - - P113 39 30 30 - - VCC 40 31 31 - - VSS 41 - - - - P107 Interrupt CRX0_A CTS0_RT S0_C/ SS0_C/ RXD9_B/ MISO9_B/ SCL9_B HMI CTSU GTOVLO GTIOC1B _A _A ADC14 SPI IIC USBFS,CAN Analogs DAC12, ACMPLP P110 RTC D5 Communication Interfaces GPT LGA36 23 GPT_OPS, POEG QFN40 27 AGT QFN48 27 I/O ports LQFP48 35 Power, System, Clock, Debug, CAC LQFP64 Timers SCI Pin number VCOUT TS11 IRQ3 TS12 IRQ4 TSCAP_C GTIOC0A _B 42 - - - - P106 43 - - - - P105 GTETRG A_C 44 32 32 26 - P104 GTETRG B_B 45 33 33 27 C3 P103 46 34 34 28 C4 P102 47 35 35 29 C5 48 36 36 30 49 37 37 50 - - KR07 GTIOC0B _B SSLA3_A KR06 SSLA2_A KR05/ IRQ0 RXD0_C/ MISO0_C/ SCL0_C SSLA1_A GTOWUP GTIOC2A _A _A CTX0_C CTS0_RT S0_A/ SS0_A SSLA0_A AGTO0 GTOWLO GTIOC2B _A _A CRX0_C P101 AGTEE0 GTETRG GTIOC5A B_A _A TXD0_A/ SDA1_B MOSIA_A MOSI0_A/ SDA0_A/ CTS1_RT S1_A/ SS1_A AN021 B6 P100 AGTIO0_ GTETRG GTIOC5B A A_A _A RXD0_A/ SCL1_B MISOA_A MISO0_A/ SCL0_A/ SCK1_A AN022 - - P500 AGTOA0 GTIU_B GTIOC2A _B AN016 - - P501 AGTOB0 GTIV_B GTIOC2B _B AN017 GTIW_B GTIOC3B _B AN018 SCK0_A TS13 KR04/ IRQ1 CMPREF 1 TS14 KR03 RSPCKA_ AN020/ CMPIN1 A ADTRG0_ A TS15 KR02 CMPREF 0 TS16 KR01/ IRQ1 CMPIN0 TS26 KR00/ IRQ2 AN019 51 - - - - P502 52 38 38 31 A6 P015 AN010 53 39 39 32 A5 P014 AN009 54 40 40 33 B5 P013 AN008 55 41 41 34 B4 P012 AN007 56 42 42 35 A4 TS27 TS28 IRQ7 DA0 AVCC0 57 43 43 36 A3 AVSS0 58 44 44 37 B3 VREFL0 P011 AN006 TS31 59 45 45 38 A2 VREFH0 P010 AN005 TS30 60 - - - - P004 AN004 TS25 61 - - - - P003 AN003 TS24 62 46 46 - - P002 AN002 TS23 IRQ2 63 47 47 39 - P001 AN001 TS22 IRQ7 64 48 48 40 B2 P000 AN000 TS21 IRQ6 Note: IRQ3 Several pin names have the added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning functionality. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 18 of 95 S124 2. 2. Electrical Characteristics Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions: VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH0 = 1.6 to AVCC0, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = Topr Note 1. The typical condition is set to VCC = 3.3V. Note 2. When USBFS is not used. Figure 2.1 shows the timing conditions. For example P100 C VOH = VCC x 0.7, VOL = VCC x 0.3 VIH = VCC x 0.7, VIL = VCC x 0.3 Load capacitance C = 30pF Figure 2.1 Input or output timing measurement conditions The measurement conditions of timing specification in each peripherals are recommended for the best peripheral operation. However, make sure to adjust driving abilities of each pins to meet your conditions. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 19 of 95 S124 2.1 2. Electrical Characteristics Absolute Maximum Ratings Table 2.1 Absolute maximum ratings Item Power supply voltage Input voltage 5V-tolerant ports*1 Symbol Value Unit VCC -0.5 to +6.5 V Vin -0.3 to +6.5 V P000 to P004 P010 to P015 Vin -0.3 to AVCC0 + 0.3 V Others Vin -0.3 to VCC + 0.3 V Reference power supply voltage VREFH0 -0.3 to +6.5 V Analog power supply voltage AVCC0 -0.5 to +6.5 V USB power supply voltage VCC_USB -0.5 to +6.5 V VCC_USB_LDO -0.5 to +6.5 V VAN -0.3 to AVCC0 + 0.3 V -0.3 to VCC + 0.3 V Analog input voltage When AN000 to AN010 are used When AN016 to AN022 are used Operating temperature*2 *3 Topr -40 to +105 C Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about 0.1 F as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7-F capacitor. The capacitor must be placed close to the pin. Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. Note 2. See section 2.2.1, Tj/Ta Definition. Note 3. Contact Renesas Electronics sales office for information on derating operation under Ta = +85C to +105C. Derating is the systematic reduction of load for improved reliability. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 20 of 95 S124 Table 2.2 2. Electrical Characteristics Recommended operating conditions Item Symbol Value Min Typ Max Unit Power supply voltages VCC*1, *2 When USBFS is not used 1.6 - 5.5 V When USBFS is used VCC_USB USB Regulator Disable - 3.6 V When USBFS is used VCC_USB _LDO USB Regulator Enable - 5.5 V - 0 - V - VCC - V When USBFS is used 3.0 USB Regulator Disable (Input) 3.3 3.6 V When USBFS is not used VCC - V - 5.5 V VSS USB power supply voltages VCC_USB VCC_USB_LDO When USBFS is not used - When USBFS is used 3.8 USB Regulator Enable Analog power supply voltages VSS_USB - 0 - V AVCC0*1, *2 1.6 - 5.5 V AVSS0 VREFH0 VREFL0 When used as ADC14 Reference - 0 - V 1.6 - AVCC0 V - 0 - V Note 1. Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC 2.0 V AVCC0 = VCC when VCC < 2.0 V. Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 21 of 95 S124 2. Electrical Characteristics 2.2 DC Characteristics 2.2.1 Tj/Ta Definition Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) -40 to +105C Item Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 125 C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode SubOSC-speed mode Note: Make sure that Tj = Ta + ja x total power consumption (W), where total power consumption = (VCC - VOH) x IOH + VOL x IOL + ICCmax x VCC. 2.2.2 Table 2.4 I/O VIH, VIL I/O VIH, VIL (1) Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Schmitt trigger input voltage Input voltage (except for Schmitt trigger input pin) IIC (except for SMBus)*1 Symbol Min VIH VCC x 0.7 VIL -0.3 Max Unit Test Conditions - 5.8 V - - VCC x 0.3 Typ VT VCC x 0.05 - - RES, NMI Other peripheral input pins excluding IIC VIH VCC x 0.8 - VCC + 0.3 VIL -0.3 - VCC x 0.2 VT VCC x 0.1 - - IIC (SMBus)*2 VIH 2.2 - VCC + 0.3 VCC = 3.6 to 5.5 V VIH 2.0 - VCC + 0.3 VCC =2.7 to 3.6 V VIL -0.3 - 0.8 - VIH VCC x 0.8 - 5.8 VIL -0.3 - VCC x 0.2 P000 to P004 P010 to P015 VIH AVCC0 x 0.8 - AVCC0 + 0.3 VIL -0.3 - AVCC0 x 0.2 EXTAL Input ports pins except for P000 to P004, P010 to P015 VIH VCC x 0.8 - VCC + 0.3 VIL -0.3 - VCC x 0.2 5V-tolerant ports*3 Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins) Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins) Note 3. P205, P206, P400, P401, P407 (total 5pins) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 22 of 95 S124 Table 2.5 2. Electrical Characteristics I/O VIH, VIL (2) Conditions: VCC = AVCC0 = 1.6 to 2.7 V Item Symbol Min Typ Max Unit Test Conditions V - Schmitt trigger input voltage RES, NMI Peripheral input pins VIH VCC x 0.8 - VCC + 0.3 VIL -0.3 - VCC x 0.2 VT VCC x 0.01 - - Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports*1 VIH VCC x 0.8 - 5.8 VIL -0.3 - VCC x 0.2 P000 to P004 P010 to P015 VIH AVCC0 x 0.8 - AVCC0 + 0.3 VIL -0.3 - AVCC0 x 0.2 EXTAL Input ports pins except for P000 to P004, P010 to P015 VIH VCC x 0.8 - VCC + 0.3 VIL -0.3 - VCC x 0.2 Note 1. P205, P206, P400, P401, P407 (total 5pins) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 23 of 95 S124 2.2.3 Table 2.6 2. Electrical Characteristics I/O IOH, IOL I/O IOH, IOL Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Permissible output current (average value per pin) Ports P000 to P004, P010 to P015, P212, P213 Ports P408, P409 - Low drive*1 drive*2 Middle VCC = 2.7 to 3.0 V drive*2 Middle VCC = 3.0 to 5.5 V Other output Permissible output current (max value per pin) pins*3 Min Typ Max Unit IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -8.0 mA IOL - - 8.0 mA IOH - - -20.0 mA IOL - - 20.0 mA IOH - - -4.0 mA IOL - - 4.0 mA Middle drive*2 IOH - - -8.0 mA IOL - - 8.0 mA Ports P000 to P004, P010 to P015, P212, P213 - IOH - - -4.0 mA IOL - - 4.0 mA Ports P408, P409 Low drive*1 IOH - - -4.0 mA IOL - - 4.0 mA Middle drive*2 VCC = 2.7 to 3.0 V IOH - - -8.0 mA IOL - - 8.0 mA Middle drive*2 VCC = 3.0 to 5.5 V IOH - - -20.0 mA IOL - - 20.0 mA Low drive*1 IOH - - -4.0 mA IOL - - 4.0 mA Middle drive*2 IOH - - -8.0 mA Other output pins*3 Permissible output current (max value total pins) Low drive*1 Symbol Total of ports P000 to P004, P010 to P015 Total of all output pin IOL - - 8.0 mA IOH (max) - - -30 mA IOL (max) - - 30 mA IOH (max) - - -60 mA IOL (max) - - 60 mA Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 s. Note 1. This is the value when low driving ability is selected with the port drive capability bit in the PmnPFS register. Note 2. This is the value when middle driving ability is selected with the port drive capability bit in the PmnPFS register. Note 3. Except for Ports P200, P214, P215, which are input ports. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 24 of 95 S124 2. Electrical Characteristics 2.2.4 I/O VOH, VOL, and Other Characteristics Table 2.7 I/O VOH, VOL (1) Conditions: VCC = AVCC0 = 4.0 to 5.5 V Item Output voltage IIC*1, *2 Ports P408, P409*2, *3 Ports P000 to P004 P010 to P015 Low drive Middle drive Other output pins*4 Low drive Middle drive Note 1. Note 2. Note 3. Note 4. Symbol Min Typ Max Unit Test conditions VOL - - 0.4 V IOL = 3.0 mA VOL - - 0.6 IOL = 6.0 mA VOH VCC - 1.0 - - IOH = -20 mA VOL - - 1.0 IOL = 20 mA VOH AVCC0 - 0.8 - VOL - - VOH AVCC0 - 0.8 - VOL - - 0.8 IOL = 4.0 mA VOH VCC - 0.8 - - IOH = -2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH VCC - 0.8 - - IOH = -4.0 mA VOL - - 0.8 IOL = 4.0 mA IOH = -2.0 mA 0.8 IOL = 2.0 mA IOH = -4.0 mA SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins). This is the value when middle driving ability is selected with the port drive capability bit in the PmnPFS register. Based on characterization data, not tested in production. Except for Ports P200, P214, P215, which are input ports. Table 2.8 I/O VOH, VOL (2) Conditions: VCC = AVCC0 = 2.7 to 4.0 V Item Output voltage Symbol Min Typ Max Unit Test conditions IIC*1, *2 VOL - - 0.4 V IOL = 3.0 mA VOL - - 0.6 IOL = 6.0 mA Ports P408, P409*2, *3 VOH VCC - 1.0 - - IOH = -20 mA VCC = 3.3 V VOL - - 1.0 IOL = 20 mA VCC = 3.3 V VOH AVCC0 - 0.5 - - IOH = -1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH AVCC0 - 0.5 - - IOH = -2.0 mA VOL - - 0.5 IOL = 2.0 mA Ports P000 to P004 P010 to P015 Low drive Middle drive Other output pins*4 Low drive Middle drive Note 1. Note 2. Note 3. Note 4. VOH VCC - 0.5 - - IOH = -1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH VCC - 0.5 - - IOH = -2.0 mA VOL - - 0.5 IOL = 2.0 mA SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins). This is the value when middle driving ability is selected with the port drive capability bit in the PmnPFS register. Based on characterization data, not tested in production. Except for Ports P200, P214, P215, which are input ports. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 25 of 95 S124 Table 2.9 2. Electrical Characteristics I/O VOH, VOL (3) Conditions: VCC = AVCC0 = 1.6 to 2.7 V Item Output voltage Ports P000 to P004 P010 to P015 Low drive Middle drive Other output pins*1 Low drive Middle drive Symbol Min Typ Max VOH AVCC0 - 0.3 - - Unit Test conditions IOH = -0.5 mA VOL - - 0.3 IOL = 0.5 mA VOH AVCC0 - 0.3 - - IOH = -1.0 mA VOL - - 0.3 VOH VCC - 0.3 - - VOL - - 0.3 IOL = 0.5 mA VOH VCC - 0.3 - - IOH = -1.0 mA VOL - - 0.3 IOL = 1.0 mA IOL = 1.0 mA V IOH = -0.5 mA Note 1. Except for Ports P200, P214, P215, which are input ports. Table 2.10 I/O other characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Input leakage current RES, Ports P200, P214, P215 | Iin | - - 1.0 A Vin = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | ITSI | - - 1.0 A Vin = 0 V Vin = 5.8 V - - 1.0 Other ports Input pull-up resistor Input capacitance Vin = 0 V Vin = VCC All ports (except for P200, P214, P215) RU 10 20 50 k Vin = 0 V USB_DP, USB_DM, P200 Cin - - 30 pF - - 15 Vin = 0 V f = 1 MHz Ta = 25C Other input pins R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 26 of 95 S124 2.2.5 2. Electrical Characteristics I/O Pin Output Characteristics of Low Drive Capacity IOH/IOL vs VOH/VOL 60 50 VCC = 5.5 V 40 30 VCC = 3.3 V IOH/IOL [mA] 20 VCC = 2.7 V 10 VCC = 1.6 V 0 VCC = 1.6 V -10 VCC = 2.7 V -20 VCC = 3.3 V -30 -40 -50 VCC = 5.5 V -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.2 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25C When Low drive output is Selected (Reference Data) IOH/IOL vs VOH/VOL 3 Ta = -40C Ta = 25C Ta = 105C 2 IOH/IOL [mA] 1 0 -1 Ta = 105C Ta = 25C -2 Ta = -40C -3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.3 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.6 V When Low drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 27 of 95 S124 2. Electrical Characteristics IOH/IOL vs VOH/VOL 20 15 Ta = -40C Ta = 25C Ta = 105C IOH/IOL [mA] 10 5 0 -5 Ta = 105C Ta = 25C -10 Ta = -40C -15 -20 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.4 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V When Low drive output is Selected (Reference Data) IOH/IOL vs VOH/VOL 30 Ta = -40C Ta = 25C Ta = 105C 20 ] A [m L O /IH IO 10 0 -10 Ta = 105C Ta = 25C -20 Ta = -40C -30 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.5 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V When Low drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 28 of 95 S124 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C Ta = 105C 40 IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.6 2.2.6 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V When Low drive output is Selected (Reference Data) I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V 0 -20 -40 -60 -80 -100 -120 -140 VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.7 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25C When Middle drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 29 of 95 S124 2. Electrical Characteristics IOH/IOL vs VOH/VOL 6 Ta = -40C Ta = 25C Ta = 105C 4 IOH/IOL [mA] 2 0 -2 Ta = 105C -4 Ta = 25C Ta = -40C -6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.8 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.6 V When Middle drive output is Selected (Reference Data) IOH/IOL vs VOH/VOL 40 Ta = -40C Ta = 25C Ta = 105C 30 IOH/IOL [mA] 20 10 0 -10 -20 Ta = 105C Ta = 25C -30 Ta = -40C -40 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.9 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V When Middle drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 30 of 95 S124 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C 40 Ta = 105C IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.10 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V When Middle drive output is Selected (Reference Data) IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 Ta = -40C Ta = 25C Ta = 105C Ta = 105C Ta = 25C Ta = -40C 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.11 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V When Middle drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 31 of 95 S124 2.2.7 2. Electrical Characteristics P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.12 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25C When Middle drive output is Selected (Reference Data) IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C Ta = 105C 40 IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.13 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V When Low drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 32 of 95 S124 2. Electrical Characteristics IOH/IOL vs VOH/VOL 100 Ta = -40C Ta = 25C Ta = 105C 80 60 40 IOH/IOL [mA] 20 0 -20 -40 Ta = 105C -60 Ta = 25C -80 Ta = -40C -100 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.14 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V When Middle drive output is Selected (Reference Data) IOH/IOL vs VOH/VOL 220 Ta = -40C Ta = 25C Ta = 105C 180 140 IOH/IOL [mA] 100 60 20 -20 -60 -100 -140 Ta = 105C Ta = 25C -180 Ta = -40C -220 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.15 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V When Low drive output is Selected (Reference Data) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 33 of 95 S124 2.2.8 2. Electrical Characteristics IIC I/O Pin Output Characteristics IOL vs VOL 120 110 VCC = 5.5 V (Middle drive) 100 90 IOL [mA] 80 70 60 50 VCC = 3.3V (Middle drive) VCC = 5.5V (Low drive) 40 VCC = 2.7V (Middle drive) 30 VCC = 3.3V (Low drive) 20 10 VCC = 2.7V (Low drive) 0 0 1 2 3 4 5 6 VOL [V] Figure 2.16 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25C R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 34 of 95 S124 2.2.9 Table 2.11 2. Electrical Characteristics Operating and Standby Current Operating and standby current (1) (1/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Supply current*1 High-speed mode*2 Normal mode All peripheral clock disabled, code executing from flash*5 All peripheral clock disabled, CoreMark code executing from flash*5 All peripheral clock enabled, code executing from flash*5 Sleep mode ICLK = 32 MHz Symbol Typ*9 Max Unit Test Conditions ICC 3.6 - mA *7 ICLK = 16 MHz 2.4 - ICLK = 8 MHz 1.7 - ICLK = 32 MHz 5.6 - ICLK = 16 MHz 3.5 - ICLK = 8 MHz 2.4 - ICLK = 32 MHz 9.5 - ICLK = 16 MHz 5.4 - ICLK = 8 MHz 3.3 - All peripheral clock enabled, code executing from flash*5 ICLK = 32 MHz - 21.0 All peripheral clock disabled*5 ICLK = 32 MHz 1.5 - All peripheral clock enabled*5 ICLK = 16 MHz 1.1 - ICLK = 8 MHz 0.9 - ICLK = 32 MHz 7.2 - ICLK = 16 MHz 4.0 - ICLK = 8 MHz 2.4 - 2.5 - 1.7 - 1.5 - Increase during BGO operation*6 Middle-speed mode*2 Normal mode Sleep mode All peripheral clock disabled, code executing from flash*5 ICLK = 12 MHz ICC All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 12 MHz 2.7 - ICLK = 8 MHz 1.9 - All peripheral clock enabled, code executing from flash*5 ICLK = 12 MHz 3.9 - ICLK = 8 MHz 3.0 - All peripheral clock enabled, code executing from flash*5 ICLK = 12 MHz - 8.0 All peripheral clock disabled*5 ICLK = 12 MHz 0.8 - ICLK = 8 MHz 0.8 - All peripheral clock enabled*5 ICLK = 12 MHz 2.9 - ICLK = 8 MHz 2.2 - 2.5 - 0.2 - ICLK = 8 MHz Increase during BGO operation*6 Low-speed mode*3 Normal mode Sleep mode R01DS0264EU0100 Rev.1.00 Feb 23, 2016 ICC *8 *7 *8 mA *7 *8 *7 *8 mA *7 All peripheral clock disabled, code executing from flash*5 ICLK = 1 MHz All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.3 - All peripheral clock enabled, code executing from flash*5 ICLK = 1 MHz 0.4 - All peripheral clock enabled, code executing from flash*5 ICLK = 1 MHz - 2.0 All peripheral clock disabled*5 ICLK = 1 MHz 0.2 - *7 All peripheral clock enabled*5 ICLK = 1 MHz 0.3 - *8 *8 Page 35 of 95 S124 Table 2.11 2. Electrical Characteristics Operating and standby current (1) (2/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Supply current*1 Low-voltage mode*3 Normal mode Sleep mode Suboscspeed mode*4 Normal mode Sleep mode Symbol Typ*9 Max Unit Test Conditions ICC 1.4 - mA *7 All peripheral clock disabled, code executing from flash*5 ICLK = 4 MHz All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 4 MHz 1.4 - All peripheral clock enabled, code executing from flash*5 ICLK = 4 MHz 2.1 - All peripheral clock enabled, code executing from flash*5 ICLK = 4 MHz - 4.0 All peripheral clock disabled*5 ICLK = 4 MHz 0.9 - *7 All peripheral clock enabled*5 ICLK = 4 MHz 1.6 - *8 All peripheral clock disabled, code executing from flash*5 ICLK = 32.768 kHz 5.9 - All peripheral clock enabled, code executing from flash*5 ICLK = 32.768 kHz 13.0 - All peripheral clock enabled, code executing from flash*5 ICLK = 32.768 kHz - 55.0 All peripheral clock disabled*5 ICLK = 32.768 kHz 3.2 - *7 All peripheral clock enabled*5 ICLK = 32.768 kHz 10.0 - *8 ICC *8 A *7 *8 Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution. Note 7. PCLKB and PCLKD are set to divided by 64. Note 8. PCLKB and PCLKD are the same frequency as that of ICLK. Note 9. VCC = 3.3 V. Table 2.12 Operating and standby current (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Supply current*1 Software Standby mode*2 Ta = 25C Ta = 55C Symbol Typ*3 Max Unit Test conditions ICC 0.4 1.5 A - 0.6 5.5 Ta = 85C 1.2 10.0 Ta = 105C 2.6 40.0 Increment for RTC operation with low-speed on-chip oscillator*4 0.4 - - Increment for RTC operation with sub-clock oscillator*4 0.5 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.3 - SOMCR.SODRV[1:0] are 00b (Normal mode) Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOS transistors are in the off state. Note 2. The IWDT and LVD are not operating. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 36 of 95 S124 2. Electrical Characteristics Note 3. VCC = 3.3 V. Note 4. Includes the current of low-speed on-chip oscillator or sub-oscillation circuit. Table 2.13 Operating and standby current (3) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Analog power supply current Reference power supply current Symbol During A/D conversion (at high-speed conversion) IAVCC During A/D conversion (at low-power conversion) Min Typ Max Unit Test conditions - - 3.0 mA - - - 1.0 mA - During D/A conversion*1 - 0.4 0.8 mA - Waiting for A/D and D/A conversion (all units) - - 1.0 A - - - 150 A - - - 60 nA - During A/D conversion (at high-speed conversion) IREFH0 Waiting for A/D conversion (all units) Temperature sensor ITNS - 75 - A - Low-power analog comparator (ACMPLP) operating current ICMPLP - 15 - A - USB operating current Window mode Comparator high-speed mode - 10 - A - Comparator low-speed mode - 2 - A - During USB communication under the following settings and conditions: Function controller is in Full-Speed mode and - Bulk OUT transfer is (64 bytes) x 1 - Bulk IN transfer is (64 bytes) x 1 Host device is connected by a 1-meter USB cable from the USB port. IUSBF*2 - 3.6 (VCC) 1.1 (VCC_USB)*4 - mA - During suspended state under the following setting and conditions: Function controller is in Full-Speed mode (the USB_DP pin is pulled up) Software Standby mode Host device is connected by a 1-meter USB cable from the USB port. ISUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - A - Note 1. The reference power supply current is included in the power supply current value for D/A conversion. Note 2. Current is consumed only by the USBFS. Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU in the suspended state. Note 4. When VCC = VCC_USB = 3.3 V. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 37 of 95 S124 2. Electrical Characteristics 2.2.10 VCC Rise and Fall Gradient and Ripple Frequency Table 2.14 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 5.5 V Item Power-on VCC rising gradient Voltage monitor 0 reset disabled at startup Symbol Min Typ Max Unit Test conditions SrVCC 0.02 - 2 ms/V - 0.02 - - Voltage monitor 0 reset enabled at startup*1, *2 Note 1. When OFS1.LVDAS = 0. Note 2. Turn the power supply voltage on according to the normal startup rising gradient because the register settings set by OFS1 are not read in boot mode. Table 2.15 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6 V). When the VCC change exceeds VCC 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met. Item Symbol Min Typ Max Allowable ripple frequency fr (VCC) - - 10 kHz Figure 2.17 Vr (VCC) VCC x 0.2 - - 1 MHz Figure 2.17 Vr (VCC) VCC x 0.08 - - 10 MHz Figure 2.17 Vr (VCC) VCC x 0.06 1.0 - - ms/V When VCC change exceeds VCC 10% Allowable voltage change rising and falling gradient dt/dVCC Unit Test conditions 1/fr(VCC) VCC Figure 2.17 Vr(VCC) Ripple waveform R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 38 of 95 S124 2.3 2. Electrical Characteristics AC Characteristics 2.3.1 Table 2.16 Frequency Operation frequency in high-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 5.5 V Item Operation frequency System clock (ICLK)*1, *2, *4 Peripheral module clock Peripheral module clock *4 (PCLKB)*4 (PCLKD)*3, Symbol Min Typ Max Unit f 0.032768 - 32 MHz 2.4 to 2.7 V 0.032768 - 16 2.7 to 5.5 V - - 32 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 2.7 to 5.5 V Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Table 2.17 Operation frequency in middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Operation frequency Symbol System clock (ICLK)*1, *2, *4 Peripheral module clock (PCLKB)*4 Peripheral module clock (PCLKD)*3, *4 2.7 to 5.5 V f Min Typ Max Unit MHz 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 39 of 95 S124 Table 2.18 2. Electrical Characteristics Operation frequency in low-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Operation frequency Symbol Min Typ Max Unit f 0.032768 - 1 MHz 1.8 to 5.5 V - - 1 1.8 to 5.5 V - - 1 System clock (ICLK)*1, *2, *4 1.8 to 5.5 V Peripheral module clock (PCLKB)*4 Peripheral module clock (PCLKD)*3, *4 Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. Note 2. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Table 2.19 Operation frequency in low-voltage mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Operation frequency Symbol Min Typ Max Unit f 0.032768 - 4 MHz 1.6 to 5.5 V - - 4 1.6 to 5.5 V - - 4 System clock (ICLK)*1, *2, *4 1.6 to 5.5 V Peripheral module clock (PCLKB)*4 Peripheral module clock (PCLKD)*3, *4 Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Table 2.20 Operation frequency in Subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Operation frequency Symbol System clock (ICLK)*1, *3 1.8 to 5.5 V f Min Typ Max Unit kHz 27.8528 32.768 37.6832 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKD)*2, *3 1.8 to 5.5 V - - 37.6832 Note 1. Programming and erasing the flash memory is not possible. Note 2. The 14-bit A/D converter cannot be used. Note 3. See section 8, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 40 of 95 S124 2.3.2 Table 2.21 2. Electrical Characteristics Clock Timing Clock timing (1/2) Item Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time tXcyc 50 - - ns Figure 2.18 EXTAL external clock input high pulse width tXH 20 - - ns EXTAL external clock input low pulse width tXL 20 - - ns EXTAL external clock rising time tXr - - 5 ns EXTAL external clock falling time tXf - - 5 ns tEXWT 0.3 - - s - fEXTAL - - 20 MHz 2.4 VCC 5.5 EXTAL external clock input wait time*1 EXTAL external clock input frequency Main clock oscillator oscillation frequency fMAIN - - 8 1.8 VCC < 2.4 - - 1 1.6 VCC < 1.8 1 - 20 1 - 8 1 - 4 LOCO clock oscillation frequency fLOCO 27.8528 32.768 37.6832 LOCO clock oscillation stabilization time tLOCO - - IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 MOCO clock oscillation frequency fMOCO 6.8 8 MOCO clock oscillation stabilization time tMOCO - - HOCO clock oscillation frequency fHOCO24 23.64 Sub-clock oscillator oscillation frequency R01DS0264EU0100 Rev.1.00 Feb 23, 2016 1.6 VCC < 1.8 100 s Figure 2.19 17.25 kHz - 9.2 MHz - 1 s - 24 24.36 MHz Ta = -40 to -20C 1.8 VCC 5.5 22.68 24 25.32 Ta = -40 to 85C 1.6 VCC < 1.8 23.76 24 24.24 Ta = -20 to 85C 1.8 VCC 5.5 23.52 24 24.48 Ta = 85 to 105C 2.4 VCC 5.5 31.52 32 32.48 Ta = -40 to -20C 1.8 VCC 5.5 30.24 32 33.76 Ta = -40 to 85C 1.6 VCC < 1.8 31.68 32 32.32 Ta = -20 to 85C 1.8 VCC 5.5 31.36 32 32.64 Ta = 85 to 105C 2.4 VCC 5.5 47.28 48 48.72 Ta = -40 to -20C 1.8 VCC 5.5 47.52 48 48.48 Ta = -20 to 85C 1.8 VCC 5.5 47.04 48 48.96 Ta = -40 to 105C 2.4 VCC 5.5 63.04 64 64.96 Ta = -40 to -20C 2.4 VCC 5.5 63.36 64 64.64 Ta = -20 to 85C 2.4 VCC 5.5 62.72 64 65.28 Ta = 85 to 105C 2.4 VCC 5.5 tHOCO24 tHOCO32 - - 37.1 tHOCO48 - - 43.3 tHOCO64 - - 80.6 tHOCO24 tHOCO32 tHOCO48 tHOCO64 - - 100.9 fSUB - 32.768 - fHOCO64*4 Low-voltage mode 1.8 VCC < 2.4 - fHOCO48*3 Except lowvoltage mode 2.4 VCC 5.5 kHz fHOCO32 HOCO clock oscillation stabilization time*5, *6 MHz s Figure 2.20 kHz - Page 41 of 95 S124 2. Electrical Characteristics Table 2.21 Clock timing (2/2) Item Symbol Min Typ Max Unit Test conditions Sub-clock oscillation stabilization time*2 tSUBOSC - 0.5 - s Figure 2.21 Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external clock is stable. Note 2. After changing the setting of the SOSCCR.SOSTP bit so that the sub-clock oscillator operates, only start using the sub-clock after the sub-clock oscillation stabilization wait time that is equal to or greater than the oscillator manufacturer's recommended value has elapsed. Note 3. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V. Note 4. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V. Note 5. This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state. When the HOCOCR.HCSTP bit is cleared to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 s. Note 6. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed. tXcyc tXL tXH XTAL external clock input VCC x 0.5 tXr Figure 2.18 tXf XTAL external clock input timing LOCOCR.LCSTP tLOCO LOCO clock oscillator output Figure 2.19 LOCO clock oscillation start timing HOCOCR.HCSTP tHOCOx*1 HOCO clock Note 1. Figure 2.20 x = 24, 32, 48, 64 HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit) SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output Figure 2.21 Sub-clock oscillation start timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 42 of 95 S124 2.3.3 Table 2.22 2. Electrical Characteristics Reset Timing Reset timing Symbol Min Typ Max Unit Test conditions At power-on tRESWP 3 - - ms Figure 2.22 Not at power-on tRESW 30 - - s Figure 2.23 tRESWT - 0.7 - ms Figure 2.22 - 0.3 - - 0.5 - s Figure 2.23 Figure 2.24 Item RES pulse width Wait time after RES cancellation (at power-on) LVD0 enabled*1 LVD0 disabled*2 LVD0 enabled*1 Wait time after RES cancellation (during powered-on state) LVD0 Reset period Wait time after internal reset cancellation tRESWT2 disabled*2 - 0.05 - IWDT*3 tRESWIW - 1 - IWDT clock cycle Internal reset (except IWDT) tRESWIR - 1 - ICLK cycle LVD0 enabled*1 tRESWT3 - 0.5 - s - 0.05 - LVD0 disabled*2 Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Note 3. When IWDTCR.CKS[3:0] = 0000b. VCC RES tRESWP Internal reset tRESWT Figure 2.22 Reset input timing at power-on tRESW RES Internal reset tRESWT2 Figure 2.23 Reset input timing (1) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 43 of 95 S124 2. Electrical Characteristics tRESWIW, tRESWIR Independent watchdog timer reset Software reset Internal reset tRESWT3 Figure 2.24 Reset input timing (2) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 44 of 95 S124 2. Electrical Characteristics 2.3.4 Wakeup Time Table 2.23 Timing of recovery from low power modes (1) Item Recovery time from Software Standby mode*1 Note 1. Note 2. Note 3. Note 4. Note 5. High-speed mode Min Typ Max Unit Test conditions Figure 2.25 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz)*2 tSBYMC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz)*3 tSBYEX - 14 25 s System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO - 43 52 s System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO - 44 52 s System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO - 82 110 s System clock source is MOCO tSBYMO - 16 25 s The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. The HOCO clock wait control register (HOCOWTCR) is set to 05h. The HOCO clock wait control register (HOCOWTCR) is set to 06h. Table 2.24 Timing of recovery from low power modes (2) Item Recovery time from Software Standby mode*1 Note 1. Note 2. Note 3. Note 4. Symbol Middle-speed mode Symbol Min Typ Max Unit Test conditions Figure 2.25 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz)*2 tSBYMC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz)*3 tSBYEX - 2.9 10 s System clock source is HOCO*4 tSBYHO - 38 50 s System clock source is MOCO (8 MHz) tSBYMO - 3.5 5.5 s The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. The system clock is 12 MHz. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 45 of 95 S124 Table 2.25 2. Electrical Characteristics Timing of recovery from low power modes (3) Item Recovery time from Software Standby mode*1 Low-speed mode Symbol Min Typ Max Unit Test conditions Figure 2.25 Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (1 MHz)*2 tSBYMC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX - 28 50 s tSBYMO - 25 35 s System clock source is MOCO (1 MHz) Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.26 Timing of recovery from low power modes (4) Item Recovery time from Software Standby mode*1 Low-voltage mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator External clock input to main clock oscillator System clock source is main clock oscillator Symbol Min Typ Max Unit Test conditions tSBYMC - 2 3 ms Figure 2.25 tSBYEX - 108 130 s tSBYHO - 108 130 s (4 MHz)*2 (4 MHz)*3 System clock source is HOCO (4 MHz) Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.27 Timing of recovery from low power modes (5) Symbol Min Typ Max Unit Test conditions System clock source is sub-clock oscillator (32.768 kHz) tSBYSC - 0.85 1 ms Figure 2.25 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms Item Recovery time from Software Standby mode*1 SubOSC-speed mode Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 46 of 95 S124 2. Electrical Characteristics Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYEX, tSBYMO, tSBYHO Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Figure 2.25 Software Standby mode cancellation timing Table 2.28 Timing of recovery from low power modes (6) Item Recovery time from Software Standby mode to Snooze Symbol Min Typ Max Unit Test conditions High-speed mode System clock source is HOCO tSNZ - 36 45 s - Middle-speed mode System clock source is MOCO (8 MHz) tSNZ - 1.3 3.6 s Low-speed mode System clock source is MOCO (1 MHz) tSNZ - 10 13 s Low-voltage mode System clock source is HOCO (4 MHz) tSNZ - 87 110 s R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 47 of 95 S124 2.3.5 2. Electrical Characteristics NMI and IRQ Noise Filter Table 2.29 NMI and IRQ noise filter Item Symbol Min Typ Max Unit Test conditions NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc x 2 200 ns - - 200 - - NMI digital filter enabled tNMICK x 3 200 ns tNMICK x 3.5*2 - - 200 - - tPcyc x 2*1 - - 200 - - - - tPcyc x IRQ pulse width tIRQW 2*1 tIRQCK x 3.5*3 tPcyc x 2 > 200 ns tNMICK x 3 > 200 ns ns IRQ digital filter disabled tPcyc x 2 200 ns tPcyc x 2 > 200 ns IRQ digital filter enabled tIRQCK x 3 200 ns tIRQCK x 3 > 200 ns Note: 200 ns minimum in Software Standby mode. Note 1. tPcyc indicates the PCLKB cycle. Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7). NMI tNMIW Figure 2.26 NMI interrupt input timing IRQ tIRQW Figure 2.27 IRQ interrupt input timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 48 of 95 S124 2.3.6 Table 2.30 2. Electrical Characteristics I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing Item Symbol Min Max Unit Test conditions I/O Ports Input data pulse width tPRW 1.5 - tPcyc Figure 2.28 POEG POEG input trigger pulse width tPOEW 3 - tPcyc Figure 2.29 GPT Input capture pulse width tGTICW 1.5 - tPDcyc Figure 2.30 2.5 - 250 - ns Figure 2.31 2.4 V VCC < 2.7 V 500 - ns 1.8 V VCC < 2.4 V 1000 - ns 1.6 V VCC < 1.8 V 2000 - ns Single edge Dual edge AGT AGTIO, AGTEE input cycle AGTIO, AGTEE input high level width, low-level width 2.7 V VCC 5.5 V 2.7 V VCC 5.5 V tACYC*1 tACKWH, tACKWL 100 - ns 200 - ns 400 - ns 800 - ns 62.5 - ns 2.4 V VCC < 2.7 V 125 - ns 1.8 V VCC < 2.4 V 250 - ns 1.6 V VCC < 1.8 V 500 - ns 2.4 V VCC < 2.7 V 1.8 V VCC < 2.4 V 1.6 V VCC < 1.8 V AGTIO, AGTO, AGTOA, AGTOB output frequency 2.7 V VCC 5.5 V tACYC2 Figure 2.31 ADC14 14-bit A/D converter trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.32 KINT Key interrupt input low-level width tKR 250 - ns Figure 2.33 Note 1. Constraints on AGTIO input: tPcyc x 2 (tPcyc: PCLKB cycle) < tACYC. Port tPRW Figure 2.28 I/O ports input timing POEG input trigger tPOEW Figure 2.29 POEG input trigger timing Input capture tGTICW Figure 2.30 GPT input capture timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 49 of 95 S124 2. Electrical Characteristics tACYC tACKWL tACKWH AGTIO, AGTEE (input) tACYC2 AGTIO, AGTO, AGTOA, AGTOB (output) Figure 2.31 AGT I/O timing ADTRG0 tTRGW Figure 2.32 ADC14 trigger input timing KR00 to KR07 tKR Figure 2.33 2.3.7 Table 2.31 Key interrupt input timing CAC Timing CAC timing Item CAC CACREF input pulse width tPBcyc tcac*2 tPBcyc > tcac*2 Symbol Min Typ Max Unit Test conditions tCACREF 4.5 x tcac + 3 x tPBcyc - - ns - 5 x tcac + 6.5 x tPBcyc - - ns Note 1. tPBcyc: PCLKB cycle. Note 2. tcac: CAC count clock source cycle. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 50 of 95 S124 2. Electrical Characteristics 2.3.8 SCI Timing Table 2.32 SCI timing (1) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item SCI Input clock cycle Asynchronous Symbol Min Max Unit*1 Test conditions tScyc 4 - tPcyc Figure 2.34 6 - Input clock pulse width Clock synchronous tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr - 20 ns Input clock fall time tSCKf - 20 ns 6 - tPcyc 4 - Output clock cycle Asynchronous tScyc Clock synchronous Output clock pulse width Output clock rise time 1.8V or above tSCKW 0.4 0.6 tScyc tSCKr - 20 ns - 30 - 20 - 30 1.6V or above Output clock fall time 1.8V or above tSCKf 1.6V or above Transmit data delay (master) Clock synchro nous Transmit data delay (slave) Clock synchro nous - 40 1.6V or above - 45 2.7V or above - 55 2.4V or above - 60 1.8V or above - 100 1.8V or above tTXD 1.6V or above Receive data setup time (master) Clock synchro nous - 125 45 - 2.4V or above 55 - 1.8V or above 90 - 1.6V or above 110 - 2.7V or above 40 - 1.6V or above 45 - 2.7V or above tRXS ns ns Figure 2.35 ns ns Receive data setup time (slave) Clock synchro nous ns Receive data hold time (master) Clock synchronous tRXH 5 - ns Receive data hold time (slave) Clock synchronous tRXH 40 - ns Note 1. tPcyc: PCLKB cycle. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 51 of 95 S124 2. Electrical Characteristics tSCKW tSCKr tSCKf SCKn (n = 0, 1, 9) tScyc Figure 2.34 SCK clock input timing SCKn tTXD TXDn tRXS tRXH RXDn n = 0, 1, 9 Figure 2.35 SCI input/output timing in clock synchronous mode R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 52 of 95 S124 2. Electrical Characteristics Table 2.33 SCI timing (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Simple SPI SCK clock cycle output (master) Symbol Min Max Unit*1 Test conditions tSPcyc 4 65536 tPcyc Figure 2.36 6 65536 SCK clock cycle input (slave) SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc tSPCKr, tSPCKf - 20 ns - 30 tSU 45 - 2.4V or above 55 - 1.8V or above 80 - 1.6V or above 110 - 2.7V or above 40 - 1.6V or above 45 - 33.3 - 40 - SCK clock rise and fall time 1.8V or above 1.6V or above Data input setup time Master Slave Data input hold time 2.7V or above Master tH Slave tLEAD 1 - tSPcyc SS input hold time tLAG 1 - tSPcyc tOD - 40 ns Data output hold time Master 1.8V or above 1.6V or above - 50 Slave 2.4V or above - 65 1.8V or above - 100 1.6V or above - 125 -10 - 2.4V or above -20 - 1.8V or above -30 - 1.6V or above -40 - -10 - - 20 1.8V or above - 20 1.6V or above - 30 Master 2.7V or above tOH Slave Data rise and fall time tDr, tDf Master Slave Figure 2.37 to Figure 2.40 ns SS input setup time Data output delay Simple SPI ns ns ns Slave access time tSA - 6 tPcyc Slave output release time tREL - 6 tPcyc Figure 2.40 Note 1. tPcyc: PCLKB cycle R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 53 of 95 S124 2. Electrical Characteristics tSPCKr tSPCKWH VOH SCKn master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH SCKn slave select input VIL (n = 0, 1, 9) tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 x VCC, VOL = 0.3 x VCC, VIH = 0.7 x VCC, VIL = 0.3 x VCC Figure 2.36 SCI simple SPI mode clock timing SCKn CKPOL = 0 output SCKn CKPOL = 1 output tSU MISOn input tH MSB IN tDr, tDf MOSIn output DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 0, 1, 9) Figure 2.37 SCI simple SPI mode timing (master, CKPH = 1) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 54 of 95 S124 2. Electrical Characteristics SCKn CKPOL = 1 output SCKn CKPOL = 0 output tSU MISOn input tH MSB IN tOH DATA LSB IN tOD MOSIn output MSB IN tDr, tDf MSB OUT DATA LSB OUT IDLE MSB OUT (n = 0, 1, 9) Figure 2.38 SCI simple SPI mode timing (master, CKPH = 0) tTD SSn input tLEAD tLAG SCKn CKPOL = 0 input SCKn CKPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 0, 1, 9) Figure 2.39 SCI simple SPI mode timing (slave, CKPH = 1) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 55 of 95 S124 2. Electrical Characteristics tTD SSn input tLEAD tLAG SCKn CKPOL = 1 input SCKn CKPOL = 0 input tSA tOH tOD LSB OUT (Last data) MISOn output tREL MSB OUT tSU MOSIn input LSB OUT DATA tH MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 0, 1, 9) Figure 2.40 Table 2.34 SCI simple SPI mode timing (slave, CKPH = 0) SCI timing (3) Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Simple IIC (Standard mode) Simple IIC (Fast mode) Symbol Min Max Unit Test conditions SDA input rise time tSr - 1000 ns Figure 2.41 SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 x tIICcyc ns Data input setup time tSDAS 250 - ns Data input hold time tSDAH 0 - ns - 400 pF SCL, SDA capacitive load Cb SCL, SDA input rise time tSr - 300 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 4 x tIICcyc ns Data input setup time tSDAS 100 - ns Data input hold time tSDAH 0 - ns - 400 pF SCL, SDA capacitive load Note: *1 Cb *1 Figure 2.41 tIICcyc: IIC internal reference clock (IIC) cycle. Note 1. Cb indicates the total capacity of the bus line. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 56 of 95 S124 2. Electrical Characteristics VIH SDAn VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCLn P*1 (n = 0, 1, 9) P*1 Sr*1 S*1 tSf tSCLL tSr tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Restart condition Figure 2.41 SCI simple IIC mode timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 57 of 95 S124 2. Electrical Characteristics 2.3.9 SPI Timing Table 2.35 SPI timing (1/2) Conditions: Middle drive output is selected in the Drive Strength Control bit in the PmnPFS register. Symbol Min Max Unit*1 Test conditions tSPcyc 2 4096 tPcyc 6 4096 Figure 2.42 C = 30PF (tSPcyc - tSPCKR - tSPCKF) / 2 -3 - 3 x tPcyc - (tSPcyc - tSPCKR - tSPCKF) / 2 -3 - 3 x tPcyc - - 10 - 15 1.8V or above - 20 1.6V or above - 30 - 1 s 10 - ns 2.4V or above 10 - 1.8V or above 15 - Item SPI RSPCK clock cycle Master Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master tSPCKWL Slave RSPCK clock rise and fall time Output 2.7V or above 2.4V or above tSPCKr, tSPCKf Input Data input setup time Master Slave tSU 1.6V or above ns ns ns 20 - Master (RSPCK is PCLKB/2) tHF 0 - Master (RSPCK is not PCLKB/2) tH tPcyc - Slave tH 20 - SSL setup time Master tLEAD - 30 + N x tSpcyc*2 - ns 6 x tPcyc - ns SSL hold time Master - 30 + N x tSpcyc*3 - ns 6 x tPcyc - ns Data input hold time Slave Slave R01DS0264EU0100 Rev.1.00 Feb 23, 2016 tLAG Figure 2.43 to Figure 2.48 C = 30PF ns Page 58 of 95 S124 2. Electrical Characteristics Table 2.35 SPI timing (2/2) Conditions: Middle drive output is selected in the Drive Strength Control bit in the PmnPFS register. Item SPI Data output delay Master Slave 2.7V or above Symbol Min Max Unit*1 Test conditions tOD - 14 ns Figure 2.43 to Figure 2.48 C = 30PF 2.4V or above - 20 1.8V or above - 25 1.6V or above - 30 2.7V or above - 50 2.4V or above - 60 1.8V or above - 85 - 110 0 - 0 - tSPcyc + 2 x tPcyc 8 x tSPcyc + 2 x tPcyc 6 x tPcyc - - 10 2.4V or above - 15 1.8V or above - 20 1.6V or above - 30 - 1 s ns 1.6V or above Data output hold time Master Successive transmission delay Master MOSI and MISO rise and fall time Output tOH Slave tTD Slave 2.7V or above tDr, tDf Input SSL rise and fall time Output 10 - 15 1.8V or above - 20 1.6V or above - 30 - 1 s - 2 x tPcyc +50 ns 2.4V or above - 2 x tPcyc +60 1.8V or above - 2 x tPcyc +85 - 2 x tPcyc +110 - 2 x tPcyc +50 2.4V or above - 2 x tPcyc +60 1.8V or above - 2 x tPcyc +85 1.6V or above - 2 x tPcyc +110 2.7V or above tSA 1.6V or above Slave output release time ns - Input Slave access time ns 2.4V or above 2.7V or above tSSLr, tSSLf ns 2.7V or above tREL Figure 2.47 and Figure 2.48 C = 30PF ns Note 1. tPcyc: PCLKB cycle. Note 2. N is set as an integer from 1 to 8 by the SPCKD register. Note 3. N is set as an integer from 1 to 8 by the SSLND register. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 59 of 95 S124 2. Electrical Characteristics tSPCKr tSPCKWH VOH RSPCKA master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH RSPCKA slave select input VIL tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 x VCC, VOL = 0.3 x VCC, VIH = 0.7 x VCC, VIL = 0.3 x VCC Figure 2.42 SPI clock timing tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tH MSB IN tDr, tDf MOSIA output Figure 2.43 DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 60 of 95 S124 2. Electrical Characteristics tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN MOSIA output LSB IN DATA tDr, tDf Figure 2.44 tHF tOH MSB OUT MSB IN tOD DATA LSB OUT IDLE MSB OUT SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2) tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tH MSB IN tOH MOSIA output Figure 2.45 DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 61 of 95 S124 2. Electrical Characteristics tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN tOH DATA LSB IN tOD MOSIA output Figure 2.46 tH MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2) tTD SSLA0 input tLEAD tLAG RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input tSA tOH MISOA output MSB OUT tSU MOSIA input Figure 2.47 tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN SPI timing (slave, CPHA = 0) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 62 of 95 S124 2. Electrical Characteristics tTD SSLA0 input tLEAD tLAG RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input tSA MISOA output tOH tOD LSB OUT (Last data) MSB OUT tSU MOSIA input Figure 2.48 tREL tH MSB IN LSB OUT DATA MSB OUT tDr, tDf DATA LSB IN MSB IN SPI timing (slave, CPHA = 1) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 63 of 95 S124 2. Electrical Characteristics 2.3.10 IIC Timing Table 2.36 IIC timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V Symbol Min*1, *2 Max Unit Test conditions SCL input cycle time tSCL 6 (12) x tIICcyc + 1300 - ns Figure 2.49 SCL input high pulse width tSCLH 3 (6) x tIICcyc + 300 - ns Item IIC (standard mode, SMBus) IIC (Fast mode) Note: SCL input low pulse width tSCLL 3 (6) x tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) x tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) x tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) x tIICcyc + 4 x tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) x tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF SCL input cycle time tSCL 6 (12) x tIICcyc + 600 - ns SCL input high pulse width tSCLH 3 (6) x tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) x tIICcyc + 300 - ns SCL, SDA input rise time tSr 20 x (external pullup voltage/5.5V)*2 300 ns SCL, SDA input fall time tSf 20 x (external pullup voltage/5.5V)*2 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) x tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) x tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) x tIICcyc + 4 x tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) x tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF Figure 2.49 tIICcyc: IIC internal reference clock (IIC) cycle, tPcyc: PCLKB cycle Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 64 of 95 S124 2. Electrical Characteristics set to 1. Note 2. Only supported for SCL0_A and SDA0_A. VIH SDA0 and SDA1 VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCL0 and SCL1 P*1 tSf P*1 Sr*1 S*1 tSCLL tSr tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 2.49 I2C bus interface input/output timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 65 of 95 S124 2. Electrical Characteristics 2.3.11 CLKOUT Timing Table 2.37 CLKOUT timing Symbol Min Max Unit*1 Test conditions tCcyc 62.5 - ns Figure 2.50 VCC = 1.8 V or above 125 - VCC = 1.6 V or above 250 - 15 - 30 - Item CLKOUT CLKOUT pin output cycle*1 CLKOUT pin high pulse width*2 VCC = 2.7 V or above VCC = 2.7 V or above tCH VCC = 1.8 V or above VCC = 1.6 V or above CLKOUT pin low pulse width*2 CLKOUT pin output rise time CLKOUT pin output fall time Note 1. Note 2. 150 - 15 - VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - VCC = 2.7 V or above tCL - 12 VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 VCC = 2.7 V or above tCr - 12 VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 VCC = 2.7 V or above tCf ns ns ns ns When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). tCcyc tCH tCf CLKOUT pin output tCL tCr Test conditions: VOH = VCC x 0.7, VOL = VCC x 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 2.50 CLKOUT output timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 66 of 95 S124 2.4 2. Electrical Characteristics USB Characteristics 2.4.1 Table 2.38 USBFS Timing USB characteristics Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 5.5, Ta = -20 to +85C Item Input characteristics Output characteristics Symbol Min Max Unit Test conditions Input high level voltage VIH 2.0 - V - Input low level voltage VIL - 0.8 V - Differential input sensitivity VDI 0.2 - V | USB_DP - USB_DM | Differential common mode range VCM 0.8 2.5 V - Output high level voltage VOH 2.8 VCC_USB V IOH = -200 A Output low level voltage VOL 0.0 0.3 V IOL= 2 mA Cross-over voltage VCRS 1.3 2.0 V ns Figure 2.51, Figure 2.52, Figure 2.53 Rise time FS tr LS Fall time FS tf LS Rise/fall time ratio FS tr/tf LS VBUS characteristics Pull-up, pull-down Battery Charging Specification Ver 1.2 4 20 75 300 4 20 75 300 90 111.11 80 125 % Output resistance ZDRV 28 44 (Adjusting the resistance of external elements is not necessary.) VBUS input voltage VIH VCC x 0.8 - V - VIL - VCC x 0.2 V - Pull-down resistor RPD 14.25 24.80 k - Pull-up resistor RPUI 0.9 1.575 k During idle state RPUA 1.425 3.09 k During reception D + sink current IDP_SINK 25 175 A - D - sink current IDM_SINK 25 175 A - DCD source current IDP_SRC 7 13 A - Data detection voltage VDAT_REF 0.25 0.4 V - D + source voltage VDP_SRC 0.5 0.7 V Output current = 250 A D - source voltage VDM_SRC 0.5 0.7 V Output current = 250 A USB_DP, USB_DM VCRS 90% 90% 10% 10% tr Figure 2.51 ns tf USB_DP and USB_DM output timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 67 of 95 S124 2. Electrical Characteristics Observation point USB_DP 50 pF USB_DM 50 pF Figure 2.52 Test circuit for Full-Speed (FS) connection Observation point USB_DP 200 pF to 600 pF 3.6 V 1.5 K USB_DM 200 pF to 600 pF Observation point Figure 2.53 2.4.2 Table 2.39 Test circuit for Low-Speed (LS) connection USB External Supply USB regulator Item VCC_USB supply current Min Typ Max Unit Test conditions VCC_USB_LDO 3.8V - - 50 mA - VCC_USB_LDO 4.5V - - 100 mA - - 3.6 V - VCC_USB supply voltage R01DS0264EU0100 Rev.1.00 Feb 23, 2016 3.0 Page 68 of 95 S124 2. Electrical Characteristics 2.5 ADC14 Characteristics VREFH0 VREFH0 5.5 5.5 A/D Conversion Characteristics (1) 5.0 A/D Conversion Characteristics (2) 4.0 3.0 2.7 2.4 A/D Conversion Characteristics (3) 5.0 3.0 2.7 2.4 2.0 2.0 1.8 1.0 1.0 2.4 2.7 1.0 2.0 3.0 5.5 4.0 A/D Conversion Characteristics (4) 4.0 A/D Conversion Characteristics (5) A/D Conversion Characteristics (6) AVCC0 1.8 5.0 1.0 ADCSR.ADHSC = 0 Figure 2.54 Table 2.40 2.4 2.7 2.0 3.0 5.5 4.0 AVCC0 5.0 ADCSR.ADHSC = 1 AVCC0 to VREFH0 voltage range A/D conversion characteristics (1) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 64 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - - - 12 Bit - 0.70 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.13 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 0.5 12-bit mode Resolution time*1 Conversion (Operation at PCLKD = 64 MHz) Permissible signal source impedance Max. = 0.3 k Offset error Full-scale error - 0.75 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 64 MHz) Permissible signal source impedance Max. = 0.3 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 0.80 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.22 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Page 69 of 95 S124 Table 2.40 2. Electrical Characteristics A/D conversion characteristics (1) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 2.0 Full-scale error - 3.0 Max Unit Test Conditions 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.41 A/D conversion characteristics (2) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 48 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKD = 48 MHz) Permissible signal source impedance Max. = 0.3 k Offset error Full-scale error - - 12 Bit - 0.94 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above - 0.75 Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 48 MHz) Permissible signal source impedance Max. = 0.3 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 1.06 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Page 70 of 95 S124 Table 2.41 2. Electrical Characteristics A/D conversion characteristics (2) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 2.0 Full-scale error - 3.0 Max Unit Test Conditions 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.42 A/D conversion characteristics (3) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 32 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKD = 32 MHz) Permissible signal source impedance Max. = 1.3 k Offset error Full-scale error - - 12 Bit - 1.41 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above - 0.75 Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 32 MHz) Permissible signal source impedance Max. = 1.3 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 1.59 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Page 71 of 95 S124 Table 2.42 2. Electrical Characteristics A/D conversion characteristics (3) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 2.0 Full-scale error - 3.0 Max Unit Test Conditions 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.43 A/D conversion characteristics (4) in low power mode (1/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 24 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKD = 24 MHz) Permissible signal source impedance Max. = 1.1 k Offset error Full-scale error - - 12 Bit - 2.25 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above - 0.75 Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 24 MHz) Permissible signal source impedance Max. = 1.1 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 2.50 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Page 72 of 95 S124 Table 2.43 2. Electrical Characteristics A/D conversion characteristics (4) in low power mode (2/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 2.0 Full-scale error - 3.0 Max Unit Test Conditions 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.44 A/D conversion characteristics (5) in low power mode (1/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 16 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKD = 16 MHz) Permissible signal source impedance Max. = 2.2 k Offset error Full-scale error - - 12 Bit - 3.38 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above - 0.75 Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 16 MHz) Permissible signal source impedance Max. = 2.2 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 3.75 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Page 73 of 95 S124 Table 2.44 2. Electrical Characteristics A/D conversion characteristics (5) in low power mode (2/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 2.0 Full-scale error - 3.0 Max Unit Test Conditions 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.45 A/D conversion characteristics (6) in low power mode (1/2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Frequency Typ Max Unit Test Conditions 1 - 8 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKD = 8 MHz) Permissible signal source impedance Max. = 5 k Offset error Full-scale error - - 12 Bit - 6.75 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 1.0 7.5 LSB High-precision channel 10.0 LSB Other than above 7.5 LSB High-precision channel 10.0 LSB Other than above - 1.5 Quantization error - 0.5 - LSB - Absolute accuracy - 3.0 8.0 LSB High-precision channel 12.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKD = 8 MHz) Permissible signal source impedance Max. = 5 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 - - 14 Bit - 7.50 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Page 74 of 95 S124 2. Electrical Characteristics Table 2.45 A/D conversion characteristics (6) in low power mode (2/2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 4.0 Full-scale error - 6.0 Max Unit Test Conditions 30.0 LSB High-precision channel 40.0 LSB Other than above 30.0 LSB High-precision channel 40.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 12.0 32.0 LSB High-precision channel 48.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.46 A/D conversion characteristics (7) in low power mode (1/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 4 MHz - - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input capacitance Cs Analog input resistance Rs - - 2.5 k - Analog input voltage range Ain 0 - VREFH0 V - - - 12 Bit - 13.5 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 20.25 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 1.0 12-bit mode Resolution time*1 Conversion (Operation at PCLKD = 4 MHz) Permissible signal source impedance Max. = 9.9 k Offset error Full-scale error - 1.5 7.5 LSB High-precision channel 10.0 LSB Other than above 7.5 LSB High-precision channel 10.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 3.0 8.0 LSB High-precision channel 12.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - - - 14 Bit - 15.0 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 21.75 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h 14-bit mode Resolution time*1 Conversion (Operation at PCLKD = 4 MHz) Permissible signal source impedance Max. = 9.9 k R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 75 of 95 S124 Table 2.46 2. Electrical Characteristics A/D conversion characteristics (7) in low power mode (2/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Offset error - 4.0 Full-scale error - 6.0 Max Unit Test Conditions 30.0 LSB High-precision channel 40.0 LSB Other than above 30.0 LSB High-precision channel 40.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 12.0 32.0 LSB High-precision channel 48.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Table 2.47 14-bit A/D converter channel classification Classification Channel Conditions Remarks High-precision channel AN000 to AN010 AVCC0 = 1.6 to 5.5 V Normal-precision channel AN016 to AN022 Pins AN000 to AN010 cannot be used as general I/O, TS transmission, when the A/D converter is in use. Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 5.5 V - Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 5.5 V - Table 2.48 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1 Item Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D converter. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 76 of 95 S124 2. Electrical Characteristics FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Absolute accuracy 000h Offset error 0 Figure 2.55 Analog input voltage VREFH0 (full-scale) Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV, an absolute accuracy of 5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 77 of 95 S124 2.6 2. Electrical Characteristics DAC12 Characteristics Table 2.49 D/A conversion characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = AVCC0 or AVSS0 selected Item Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 - 0.47 V - DNL differential nonlinearity error - 0.5 2.0 LSB - INL integral nonlinearity error - 2.0 8.0 LSB - Offset error - - 30 mV - Full-scale error - - 30 mV - Output impedance - 5 - - Conversion time - - 30 s - Gain error Full-scale error Upper output limit Integral nonlinearity error (INL) Offset error Output analog voltage 1-LSB width for ideal D/A conversion characteristic Ideal output voltage Differential nonlinearity error (DNL) *1 Lower output limit Actual D/A conversion characteristic Offset error Ideal output voltage 000h D/A converter input code FFFh Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed. Figure 2.56 Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 78 of 95 S124 2. Electrical Characteristics Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code. 2.7 TSN Characteristics Table 2.50 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Relative accuracy - - 1.5 - C 2.4 V or above - 2.0 - C Below 2.4 V - -3.65 - mV/C - Temperature slope - Output voltage (at 25C) - - 1.05 - V VCC = 3.3 V Temperature sensor start time tSTART - - 5 s - Sampling time - 5 - - s 2.8 OSC Stop Detect Characteristics Table 2.51 Oscillation stop detection circuit characteristics Item Symbol Min Typ Max Unit Test conditions Detection time tdr - - 1 ms Figure 2.57 Main clock tdr OSTDSR.OSTDF MOCO clock ICLK Figure 2.57 Oscillation stop detection timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 79 of 95 S124 2.9 2. Electrical Characteristics POR and LVD Characteristics Table 2.52 Power-on reset circuit and voltage detection circuit characteristics (1) Conditions: VCC = AVCC0 Item Voltage detection level*1 Symbol Min Typ Max Unit Test Conditions Power-on reset (POR) VPOR 1.27 1.42 1.57 V Figure 2.58, Figure 2.59 Voltage detection circuit (LVD0)*2 Vdet0_0 3.68 3.85 4.00 V Vdet0_1 2.68 2.85 2.96 Figure 2.60 At falling edge VCC Vdet0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 Vdet0_4 1.60 1.69 1.82 Vdet1_0 4.13 4.29 4.45 V Vdet1_1 3.98 4.16 4.30 Figure 2.61 At falling edge VCC Vdet1_2 3.86 4.03 4.18 Vdet1_3 3.68 3.86 4.00 Vdet1_4 2.98 3.10 3.22 Vdet1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 V Figure 2.62 At falling edge VCC Voltage detection circuit (LVD1)*3 Voltage detection circuit (LVD2)*4 Vdet1_F 1.60 1.65 1.73 Vdet2_0 4.11 4.31 4.48 Vdet2_1 3.97 4.17 4.34 Vdet2_2 3.83 4.03 4.20 Vdet2_3 3.64 3.84 4.01 Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection level to overlap with that of the voltage detection circuit (LVD2), it cannot be specified whether LVD1 or LVD2 is used for voltage detection. Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits. Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits. Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (2) (1/2) Conditions: VCC = AVCC0 Item Symbol Min Typ Max Unit Test Conditions LVD0:enable*1 tLVD0,1,2 - 0.6 - s - LVD0:disable*2 tLVD1,2 - 0.2 - s - Response delay*3 tdet - - 350 s Figure 2.58, Figure 2.59 Minimum VCC down time tVOFF 450 - - s Figure 2.58, VCC = 1.0 V or above Power-on reset enable time tW (POR) 1 - - ms Figure 2.59, VCC = below 1.0 V Wait time after voltage monitoring 0,1,2 reset cancellation R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 80 of 95 S124 2. Electrical Characteristics Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (2) (2/2) Conditions: VCC = AVCC0 Item Symbol Min Typ Max Unit Test Conditions LVD operation stabilization time (after LVD is enabled) Td (E-A) - - 300 s Figure 2.61, Figure 2.62 Hysteresis width (POR) VPORH - 110 - mV - Hysteresis width (LVD1 and LVD2) VLVH - 70 - mV Vdet1_0 to Vdet1_4 selected. - 60 - Vdet1_5 to Vdet1_9 selected. - 50 - Vdet1_A to Vdet1_B selected. - 40 - Vdet1_C to Vdet1_D selected. - 60 - LVD2 selected Note 1. When OFS1.LVDAS = 0 Note 2. When OFS1.LVDAS = 1 Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD. tVOFF VCC VPOR 1.0 V Internal reset signal (active-low) tdet Figure 2.58 tdet tPOR Voltage detection reset timing VPOR VCC 1.0 V tw(POR) Internal reset signal (active-low) *1 tdet Note: tPOR tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held below the valid voltage (1.0 V). When VCC turns on, maintain tw(por) for 1.0 ms or more. Figure 2.59 Power-on reset timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 81 of 95 S124 2. Electrical Characteristics tVOFF VCC VLVH Vdet0 Internal reset signal (active-low) tdet Figure 2.60 tdet tLVD0 Voltage detection circuit timing (Vdet0) tVOFF VCC VLVH Vdet1 LVCMPCR.LVD1E Td(E-A) LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 tdet tdet tLVD1 When LVD1CR0.RN = 1 tLVD1 Figure 2.61 Voltage detection circuit timing (Vdet1) R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 82 of 95 S124 2. Electrical Characteristics tVOFF VCC VLVH Vdet2 LVCMPCR.LVD2E LVD2 Comparator output Td(E-A) LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 tdet tdet tLVD2 When LVD2CR0.RN = 1 tLVD2 Figure 2.62 2.10 Voltage detection circuit timing (Vdet2) CTSU Characteristics Table 2.54 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin Ctscap 9 10 11 nF - TS pin capacitive load Cbase - - 50 pF - Permissible output high current IoH - - -24 mA When the mutual capacitance method is applied R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 83 of 95 S124 2.11 2. Electrical Characteristics Comparator Characteristics Table 2.55 ACMPLP characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V Item Symbol Min Typ Max Unit Test conditions Reference voltage range VREF 0 - VCC -1.4 V - Input voltage range VI 0 - VCC V - Td VCC = 3.0 Slew rate of input signal > 50 mV/s Output delay Offset voltage - - 1.2 s Low-speed mode - - 5 s Window mode - - 2 s High-speed mode High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode - - - 60 mV - VRFH - 0.76 x VCC - V - VRFL - 0.24 x VCC - V - Tcmp 100 - - s - Internal reference voltage for window mode Operation stabilization wait time R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 84 of 95 S124 2.12 2. Electrical Characteristics Flash Memory Characteristics 2.12.1 Table 2.56 Code Flash Memory Characteristics Code flash characteristics (1) Item Symbol Min Typ Max Unit Conditions Reprogramming/erasure cycle*1 NPEC 1000 - - Times - tDRP 20*2, *3 - - Year Ta = +85C Data hold time After 1000 times NPEC Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000), erasing can be performed n times for each block. For instance, when 4-byte programming is performed 256 times for different addresses in 1-KB blocks, and then the entire block is erased, the reprogram/ erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.) Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics. Note 3. This result is obtained from reliability testing. Table 2.57 Code flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V ICLK = 1 MHz Item Programming time 4-byte ICLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit tP4 - 116 998 - 54 506 s Erasure time 1-KB tE1K - 9.03 287 - 5.67 222 ms Blank check time 4-byte tBC4 - - 56.8 - - 16.6 s 1-KB tBC1K - - 1899 - - 140 s Erase suspended time tSED - - 22.5 - - 10.7 s Startup area switching setting time tSAS - 21.9 585 - 12.1 447 ms Access window time tAWS - 21.9 585 - 12.1 447 ms OCD/serial programmer ID setting time tOSIS - 21.9 585 - 12.1 447 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - s Flash memory mode transition wait time 2 tMS 5 - - 5 - - s Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 85 of 95 S124 Table 2.58 2. Electrical Characteristics Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85C ICLK = 1 MHz Item ICLK = 8 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 4-byte tP4 - 157 1411 - 101 966 s Erasure time 1-KB tE1K - 9.10 289 - 6.10 228 ms Blank check time 2-byte tBC4 - - 87.7 - - 52.5 s 1-KB - - tBC1K - 1930 - 414 s Erase suspended time tSED - - 32.7 - - 21.6 s Startup area switching setting time tSAS - 22.8 592 - 14.2 465 ms Access window time tAWS - 22.8 592 - 14.2 465 ms OCD/serial programmer ID setting time tOSIS - 22.8 592 - 14.2 465 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - s Flash memory mode transition wait time 2 tMS 720 - - 720 - - ns Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. 2.12.2 Table 2.59 Data Flash Memory Characteristics Data flash characteristics (1) Item Reprogramming/erasure Data hold time cycle*1 After 10000 times of NDPEC After 100000 times of NDPEC After 1000000 times of NDPEC Symbol Min Typ Max Unit NDPEC 100000 1000000 - Conditions Times - tDDRP 20*2, *3 - - Year Ta = +85C 5*2, *3 - - Year - 1*2, *3 - Year Ta = +25C Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.) Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics. Note 3. These results are obtained from reliability testing. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 86 of 95 S124 Table 2.60 2. Electrical Characteristics Data flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V ICLK = 4 MHz Item ICLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 1-byte tDP1 - 52.4 463 - 42.1 387 s Erasure time 1-KB tDE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte tDBC1 - - 24.3 - - 16.6 s 1-KB - - tDBC1K - 1872 - 512 s Suspended time during erasing tDSED - - 13.0 - - 10.7 s Data flash STOP recovery time tDSTOP 5 - - 5 - - s Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Table 2.61 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85C ICLK = 4 MHz Item Programming time 1-byte ICLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit tDP1 - 94.7 886 - 87.0 837 s Erasure time 1-KB tDE1K - 9.59 299 - 7.82 266 ms Blank check time 1-byte tDBC1 - - 56.2 - - 50.9 s 1-KB tDBC1K - - 2.17 - - 1.21 ms Suspended time during erasing tDSED - - 23.0 - - 21.0 s Data flash STOP recovery time tDSTOP 720 - - 720 - - ns Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 87 of 95 S124 2.12.3 Table 2.62 2. Electrical Characteristics Serial Wire Debug (SWD) SWD characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Item Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.63 SWCLK clock high pulse width tSWCKH 35 - - ns SWCLK clock low pulse width tSWCKL 35 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 16 - - ns SWDIO hold time tSWDH 16 - - ns SWDIO data delay time tSWDD 2 - 70 ns Table 2.63 Figure 2.64 SWD characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Item Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.63 SWCLK clock high pulse width tSWCKH 120 - - ns SWCLK clock low pulse width tSWCKL 120 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 50 - - ns SWDIO hold time tSWDH 50 - - ns SWDIO data delay time tSWDD 2 - 150 ns Figure 2.64 tSWCKcyc tSWCKH SWCLK tSWCKf tSWCKL Figure 2.63 tSWCKr SWD SWCLK timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 88 of 95 S124 2. Electrical Characteristics SWCLK tSWDS tSWDH SWDIO (Input) tSWDD SWDIO (Output) tSWDD SWDIO (Output) tSWDD SWDIO (Output) Figure 2.64 SWD input output timing R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 89 of 95 S124 Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in "Packages" on the Renesas Electronics Corporation website. JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP64-10x10-0.50 PLQP0064KB-C -- 0.3 Unit: mm HD *1 D 48 33 64 HE 32 *2 E 49 17 1 16 NOTE 4 Index area NOTE 3 F S y S *3 bp 0.25 c A1 T A2 A e Lp L1 Detail F M NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol Min Nom Max D 9.9 10.0 10.1 10.1 E 9.9 10.0 A2 1.4 HD 11.8 12.0 12.2 HE 11.8 12.0 12.2 A 1.7 A1 0.05 0.15 bp 0.15 0.20 0.27 c 0.09 0.20 T 0q 3.5q 8q e 0.5 x 0.08 y 0.08 Lp 0.45 0.6 0.75 L1 1.0 (c) 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.1 LQFP 64-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 90 of 95 S124 Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP48-7x7-0.50 PLQP0048KB-B -- 0.2 HD Unit: mm *1 D 36 25 *2 48 HE 24 E 37 13 1 12 NOTE 4 Index area NOTE 3 F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. S Reference Dimensions in millimeters Symbol y S *3 bp 0.25 M A1 T c A2 A e Lp L1 Detail F Min Nom Max D 6.9 7.0 7.1 E 6.9 7.0 7.1 A2 1.4 HD 8.8 9.0 9.2 HE 8.8 9.0 9.2 A 1.7 A1 0.05 0.15 bp 0.17 0.20 0.27 c 0.09 0.20 T 0q 3.5q 8q e 0.5 x 0.08 y 0.08 Lp 0.45 0.6 0.75 L1 1.0 (c) 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.2 LQFP 48-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 91 of 95 S124 Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 32x b S AB e ZE w S A M A ZD D x 6 5 B 4 E 3 2.90 2 C INDEX MARK y1 D w S B S 1 F E D C B A E 2.90 A S y S DETAIL C DETAIL E DETAIL D R0.17 0.05 0.70 0.05 0.55 0.05 R0.12 0.05 0.75 0.55 (UNIT:mm) R0.17 0.05 0.70 0.05 R0.12 0.05 0.55 0.05 0.75 0.55 b (LAND PAD) 0.340.05 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.550.05 0.70 0.05 0.55 0.75 0.550.05 R0.2750.05 R0.350.05 ITEM D DIMENSIONS E 4.000.10 w 0.20 4.000.10 e 0.50 A 0.690.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 0.700.05 2012 Renesas Electronics Corporation. All rights reserved. Figure 1.3 LGA 36-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 92 of 95 S124 Appendix 1. Package Dimensions JEITA Package code P-HWQFN64-8x8-0.40 RENESAS code Previous code MASS(TYP.)[g] PWQN0064LA-A P64K8-40-9B5-3 0.16 D 33 48 DETAIL OF A PART 32 49 E A A1 17 64 c2 16 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 16 1 64 17 Dimension in Millimeters Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A 0.80 A1 0.00 b 0.17 e Lp B E2 ZE 32 49 33 ZD e b x M 0.23 0.40 0.30 0.40 0.50 x 0.05 y 0.05 ZD 1.00 ZE 1.00 c2 48 0.20 0.15 0.20 D2 6.50 E2 6.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. Figure 1.4 QFN 64-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 93 of 95 S124 Appendix 1. Package Dimensions JEITA Package code P-HWQFN48-7x7-0.50 RENESAS code Previous code MASS(TYP.)[g] PWQN0048KB-A 48PJN-A P48K8-50-5B4-6 0.13 D 25 36 DETAIL OF A PART 24 37 E A A1 13 48 c2 12 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 12 1 13 48 Dimension in Millimeters Min Nom Max D 6.95 7.00 7.05 E 6.95 7.00 7.05 A 0.80 A1 0.00 b 0.18 e Lp B E2 0.30 24 36 25 ZD e b x M 0.40 0.50 x 0.05 y 0.05 0.75 ZE 37 0.30 0.50 ZD ZE 0.25 c2 0.75 0.15 0.20 D2 5.50 E2 5.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. Figure 1.5 QFN 48-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 94 of 95 S124 Appendix 1. Package Dimensions JEITA Package code P-HWQFN40-6x6-0.50 RENESAS code Previous code MASS(TYP.)[g] PWQN0040KC-A P40K8-50-4B4-5 0.09 D 21 30 DETAIL OF A PART 20 31 E 40 A A1 11 c2 10 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 1 10 11 40 Dimension in Millimeters Min Nom Max D 5.95 6.00 6.05 E 5.95 6.00 6.05 A 0.80 A1 0.00 b 0.18 e Lp B E2 ZE 20 31 30 21 ZD e b Figure 1.6 x M 0.25 0.30 0.50 0.30 0.40 0.50 x 0.05 y 0.05 ZD 0.75 ZE 0.75 c2 0.15 0.20 D2 4.50 E2 4.50 0.25 S AB QFN 40-pin R01DS0264EU0100 Rev.1.00 Feb 23, 2016 Page 95 of 95 Revision History S124 Datasheet Rev. Date Chapter 1.00 Feb. 23, 2016 -- Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners. Revision History - 1 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2016 Renesas Electronics Corporation. All rights reserved. Colophon 5.0