VSP5010
PRODUCTPREVIEW
1
FEATURES APPLICATIONS
DESCRIPTION
VSP5010
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12-Bit, 31-MSPS, Dual-ChannelCCD ANALOG FRONT-END FOR DIGITAL COPIERS
•Copiers2
•Dual-Channel CCD Processing:
•Scanners– Correlated Double Sampler (CDS)
•Facsimiles– Sample-and-Hold Mode (S/H)– Digital Programmable Amplifier– CCD Offset Correction (OB Loop)
The VSP5010 is a complete application-specific•High-Performance ADC:
standard product (ASP) for charge-coupled device– 12-Bit Resolution
(CCD) line sensor applications such as copiers,scanners, and facsimiles. The VSP5010 provides two– INL: ± 2 LSB
independent line-processing channels, and performs– DNL: ± 0.5 LSB
analog front-end (AFE) data processing and– No Missing Codes Ensured
analog-to-digital conversion. Each channel featurescorrelated double sampling (CDS) and•High-Speed Operation:
sample-and-hold (S/H) processing stages, 14– Sample Rate: 31 MHz (max, Design
analog-to-digital converter (ADC) blocks, a digitalEnsured)
programmable gain amplifier (DPGA), and an optical– 78-dB SNR (at 0-dB Gain)
black (OB) correction loop. Data are output in a 12-bitword; two-channel ADC data are multiplexed and•Low-Power Consumption:
then output.– Low Voltage: 3.0 V to 3.6 V
The VSP5010 operates from a single 3.3-V supply.– Low Power: 290 mW (typ at 3.3 V)
The device is available in an LQFP-64 package.– Standby Mode: 20 mW (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
Copyright © 2008, Texas Instruments Incorporatedformative or design phase of development. Characteristic data andother specifications are design goals. Texas Instruments reservesthe right to change or discontinue these products without notice.
PRODUCTPREVIEW
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
VSP5010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
VSP5010PM Tray, 160 PiecesVSP5010PM LQFP-64 PM – 25 ° C to +85 ° C VSP5010PM
VSP5010PMR Tape and Reel, 1000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
VSP5010 UNIT
Supply voltage VCC, VDD +4.0 VSupply voltage differences VCC, VDD ± 0.1 VGround voltage differences AGND, DGND ± 0.1 VDigital input voltage – 0.3 to (VDD + 0.3) VAnalog input voltage – 0.3 to (VCC + 0.3) VInput current (all pins except supplies) ± 10 mAAmbient temperature under bias – 40 to +125 ° CStorage temperature – 55 to +150 ° CJunction temperature +150 ° CLead temperature (soldering, 5s) +260 ° CPackage temperature (I
R
reflow, peak, 10s) +235 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functionaloperation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Over operating free-air temperature range, unless otherwise noted.
MIN NOM MAX UNIT
Analog supply voltage VCC 3 3.3 3.6 VDigital supply voltage VDD 3 3.3 3.6 VAnalog input voltage, full-scale (0 dB) 1Digital input logic family CMOSDigital input clock frequency System clock 10 30 MHzDigital output load capacitance 30 pFOperating free-air temperature, T
A
– 25 +85 ° C
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ELECTRICAL CHARACTERISTICS
VSP5010
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Over operating free-air temperature range, unless otherwise noted.
VSP5010PM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 12 Bits
SIGNAL PASS
Signal pass 2 Channels
MAXIMUM CONVERSION RATE
Maximum conversion rate 30 MHz
DIGITAL INPUT
V
T+
Positive-going threshold 1.8 VInput voltage
V
T –
Negative-going threshold 1.1 VI
IH
Logic high, V
IN
= +3 V ± 20 µAInput current
I
IL
Logic low, V
IN
= 0 V ± 20 µAVCC +Input limit – 0.3 V0.3SYSCLK clock duty cycle 50 %Input capacitance 5 pF
DIGITAL OUTPUT (Even Channel and Odd Channel)
Logic family CMOSLogic coding Straight BinaryMultiplexing frequency 60 MHzV
OH
Logic high, I
OH
= – 2 mA 2.5 VOutput voltage
V
OL
Logic low, I
OL
= 2 mA 0.4 V
ANALOG INPUT (CCDIN)
Input level for full-scale output DPGA gain = 0 dB 1400 mVAllowable feed-through level 1.0 VInput capacitance 15 pFInput limit – 0.3 3.6 V
TRANSFER CHARACTERISTICS
CDS mode = 0 dB, DPGA gain = 0 dB ± 0.5 ± 1 LSBDifferential nonlinearity (DNL)
SH mode, DPGA gain = 0 dB ± 0.5 ± 1 LSBCDS mode = 0 dB, DPGA gain = 0 dB ± 2 ± 4 LSBIntegral nonlinearity (INL)
SH mode, DPGA gain = 0 dB ± 4 LSBNo missing codes DPGA gain = 0 dB EnsuredStep input settling time Full-scale step input 1 PixelOverload recovery time Step input from 2.0 V to 0 V 2 Pixels9Data latency Clocks(fixed)DPGA gain = 0 dB 78 dBSignal-to-noise ratio
(1)
DPGA gain = +24 dB 54 dBChannel mismatch ± 3 %
CORRELATED DOUBLE SAMPLER (CDS)
Reference level sample settling time Within 1 LSB, driver impedance = 50 Ω8.3 nsData level sample settling time Within 1 LSB, driver impedance = 50 Ω83 ns
(1) SNR = 20 log (16384/output rms noise in LSB), input connected to ground through capacitor.
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ELECTRICAL CHARACTERISTICS (continued)Over operating free-air temperature range, unless otherwise noted.
VSP5010PM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CLAMP
Clamp-on resistance 400 Ω
Clamp level 1.5 V
OB CLAMP LOOP
CCD offset correction range – 300 300 mVDAC resolution 10 BitsMinimum DAC output current COB pin ± 0.15 µAMaximum DAC output current COB pin ± 153 µALoop time constant C
COB
= 0.1 µF 40.7 µsSlew rate C
COB
= 0.1 µF, at current DAC full-scale output 1530 V/sProgram range 0 510 LSBOptical black clamp level
OB clamp code = 0101 0000b 160 LSB
REFERENCE
Positive reference voltage 1.85 VNegative reference voltage 1.1 V
DIGITAL PROGRAMMABLE AMPLIFIER (DPGA)
Gain program resolution 10 BitsGain code = 11 1111 1111b 24 dB 16 V/VGain code = 10 0000 0000b 18 dB 8 V/VGain
Gain code = 00 0100 0000b 0 dB 1 V/VGain code = 00 0000 0000b — 0 V/VGain error ± 0.5 dB
SERIAL INTERFACE
Chip address = 2 bits, register address = 4 bits,Data length 2 Bytesand data = 10 bitsSerial clock frequency 10 MHz
POWER SUPPLY
Supply voltage VCC, VDD 3.0 3.3 3.6 VVCC = VDD = 3.3 V, f
SYSCLK
= 30 MHz,
290 mWload = 10 pFPower dissipation
Standby mode 20 mW
TEMPERATURE RANGE
Operation temperature – 25 +85 ° CStorage temperature – 55 +125 ° CThermal resistance θ
JA
LQFP-64 package 83 ° C/W
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PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
BYP_EV
CCDIN_EV
AGND
VCC
REFN_EV
CM_EV
REFP_EV
AGND
VCC
REFP_OD
CM_OD
REFN_OD
VCC
AGND
CCDIN_OD
BYP_OD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
B0(LSB)
B1
B2
B3
B4
B5
CLPOB
SYSCLK
SHD
SHP
B6
B7
B8
B9
B10
B11(MSB)
DGND
VCC
OUTENB
DGND
VDD
AGND
VCC
AGND
SDI
SCLK
WRT
RDO
AGND
VCC
COB_OD
BYPR_OD
BYPP_OD
BYPM_OD
64 63 62 61 60 59 58 57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
AGND
INPUTCLP
RESET
CA0
CDS/SH_SEL
CA1
AGND
VCC
AGND
COB_EV
BYPP_EV
BYPR_EV
BYPM_EV
AGND
VSP5010
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VSP5010PM
LQFP-64
(TOP VIEW)
Table 1. TERMINAL FUNCTIONSTERMINAL
NAME NO. TYPE
(1)
DESCRIPTION
B0 (LSB) 1 DO ADC output, bit 0 (least significant bit)
B1 2 DO ADC output, bit 1
B2 3 DO ADC output, bit 2
B3 4 DO ADC output, bit 3
B4 5 DO ADC output, bit 4
B5 6 DO ADC output, bit 5
CLPOB 7 DI Optical black clamp pulse
SYSCLK 8 DI System clock input
SHD 9 DI CCD data sampling pulse
SHP 10 DI CCD reference sampling pulse
B6 11 DO ADC output, bit 6
B7 12 DO ADC output, bit 7
B8 13 DO ADC output, bit 8
B9 14 DO ADC output, bit 9
B10 15 DO ADC output, bit 10
B11 (MSB) 16 DO ADC output, bit 11 (most significant bit)
DGND 17 P Digital ground for digital outputs (B0 – B11)
(1) Designators in TYPE: P = power supply and ground; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
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Table 1. TERMINAL FUNCTIONS (continued)TERMINAL
NAME NO. TYPE
(1)
DESCRIPTION
VDD 18 P Digital supply for digital outputs (B0 – B11)
AGND 19 P Analog ground
VCC 20 DI Analog power supply
AGND 21 DI Analog ground
SDI 22 DI Serial interface data input
SCLK 23 DI Serial interface data shift clock (rising edge trigger)
WRT 24 DI Serial interface data write pulse (rising edge trigger)
RDO 25 DO Serial interface register read output
AGND 26 P Analog ground
AGND 27 P Analog ground
VCC 28 P Analog power supply
COB_OD 29 AO OB loop output voltage (odd); connect 0.1- µF capacitor between ground
BYPR_OD 30 AO Input buffer reference bypass (odd)
BYPP_OD 31 AO CDS positive reference bypass (odd); open or bypass to ground by a 0.1- µF capacitor
BYPM_OD 32 AO CDS negative reference bypass (odd); open or bypass to ground by a 0.1- µF capacitor
BYP_OD 33 AO CDS common reference bypass (odd); bypass to ground by a 0.1- µF capacitor
CCDIN_OD 34 AI CCD signal input (odd)
AGND 35 P Analog ground
VCC 36 P Analog supply
REFN_OD 37 AO ADC negative reference bypass (odd); bypass to ground by a 0.1- µF capacitor
CM_OD 38 AO ADC common reference (odd); bypass to ground by a 0.1- µF capacitor
REFP_OD 39 AO ADC positive reference (odd); bypass to ground by a 0.1- µF capacitor
VCC 40 P Analog power supply
AGND 41 P Analog ground
REFP_EV 42 AO ADC positive reference bypass (even); bypass to ground by a 0.1- µF capacitor
CM_EV 43 AO ADC common reference bypass (even); bypass to ground by a 0.1- µF capacitor
REFN_EV 44 AO ADC negative reference bypass (even); bypass to ground by a 0.1- µF capacitor
VCC 45 P Analog power supply
AGND 46 P Analog ground
CCDIN_EV 47 AI CCD signal input (even)
BYP_EV 48 AO CDS common reference bypass (even); bypass to ground by a 0.1- µF capacitor
BYPM_EV 49 AO CDS negative reference bypass (even); bypass to ground by a 0.1- µF capacitor
BYPP_EV 50 AO CDS positive reference bypass (even); bypass to ground by a 0.1- µF capacitor
BYPR_EV 51 AO Input buffer reference bypass (even); bypass to ground by a 0.1- µF capacitor
COB_EV 52 AO OB loop output voltage (even); connect 0.1- µF capacitor between ground
VCC 53 P Analog power supply
AGND 54 P Analog ground
AGND 55 P Analog ground
CDS/SH_SEL 56 DI CDS/SH mode select; high = CDS mode, low = SH mode
CA1 57 DI Chip address 1
CA0 58 DI Chip address 0
INPUTCLP 59 DI Input clamp control (active low)
RESET 60 DI Asynchronous register reset (active low)
OUTENB 61 DI Output enable/disable; high = high impedance, low = output enable
AGND 62 P Analog ground
VCC 63 P Analog power supply
DGND 64 P Digital ground for digital outputs (B0 – B11)
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FUNCTIONAL BLOCK DIAGRAM
SCLK SDI WRTRDO
INPUTCLP
SYSCLK
SHP
CCDIN_OD
CCDOut
Signal
CCDIN_EV
CCDOut
Signal
SHD
RESET
CDS/SHSEL
CA1
CA0
CLPOB
REFN_ODCM_ODREFP_ODBYP_ODBYPM_ODBYPP_OD COB_OD
12-Bit
DigitalOutput
OUTENB
REFN_E
CM_E
REFP_EBYP_EBYPM_EBYPP_E COB_E
ODDChannel
InternalReference
Current
DAC
14-Bit
ADC
Decoder
Output
Register
EVEN Channel
InternalReference
Digital
PGA
Output
Control
Digital
PGA
Output
Register
Current
DAC Decoder
Clamp
CDS/SH
Timing/Control
CDS/SH
Serial
Interface
Buffer
Buffer
Clamp
14-Bit
ADC
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CCD
Signal
SHP
(External)
SHD
(External)
ADC_Clock
(Internal)
ECHData
(Internal)
OCHData
(Internal)
SYSCLK
(External)
MUXData
(Internal)
MUXClock
(Internal)
B[11:0]
(External)
tOD
tD1
tINHIBIT
tD2
N+2N+1N
tS
tWD
N-9(EV)
N-8
N-9(OD) N-8(EV) N-8(OD) N-7(EV)
N-9(EV) N-9(OD) N-8(EV) N-8(OD)
N-7 N-6
N-8 N-7 N-6
tWP
tS
tADC tADC tCKP
tCKP
tPD tDP
tCKP
TIMING CHARACTERISTICS
VSP5010
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Figure 1. VSP5010 CDS Mode Timing Specifications (Even and Odd Channels) 1
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period
(1)
32 nst
ADC
SYSCLK pulse width
(2)
16 nst
WP
SHD pulse width 6 8.3 nst
WD
SHD pulse width 6 8.3 nst
PD
SHP trailing edge to SHD leading edge 8 nst
DP
SHD trailing edge to SHP leading edge 8 nst
S
Sampling delay 3.5 nst
INHIBIT
Inhibited clock period 10 nst
D1
Internal MUX clock delay 1
(3)
4 nst
D2
Internal MUX clock delay 2
(3)
4 nsOutput delay at data output delay = 0 ns
(4)
13 nst
OD
Output delay at data output delay = 2 ns
(4)
DL Data latency
(5)
13 ns
(1) Design ensured. A shipment final test is 33 ns.(2) Design ensured. A shipment final test is 16.7 ns.(3) See the Serial Interface section.(4) Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface. See theMPX Clock Edge Phase configuration.(5) Depending on an Internal MUX clock delay and output delay, latency can carry out the decrease of an increase.
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CCD
Signal
SHP
(External)
SYSCLK
(External)
ECHData
(Internal)
OCHData
(Internal)
MUXData
(Internal)
MUXClock
(Internal)
B[11:0]
(External)
N+2N+1N
N-8 N-7 N-6
N-8 N-7 N-6
N-9(OD) N-9(EV) N-8(OD) N-8(EV) N-7(OD)
N-9(OD) N-9(EV) N-8(OD) N-8(EV)
tWD tS
tDS
tOD
tD1 tD2
tCKP
tCKP
tADC
tADC
TIMING CHARACTERISTICS
VSP5010
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Figure 2. VSP5010 SH Mode Timing Specifications (Even and Odd Channels) 1
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period
(1)
32 nst
ADC
SYSCLK pulse width
(2)
16 nst
WD
SHD pulse width 6 8.3 nst
S
Sampling delay 3.5 nst
DS
SHD trailing edge to SYSCLK leading edge – 8 +6 nst
D1
Internal MUX clock delay 1
(3)
4.5 nst
D2
Internal MUX clock delay 2
(3)
12.5 nsOutput delay at data output delay = 0 ns
(4)
13 nst
OD
Output delay at data output delay = 2 ns
(5)
17 nsDL Data latency 9 Clocks
(1) Design ensured. A shipment final test is 33 ns.(2) Design ensured. A shipment final test is 16.7 ns.(3) See the Serial Interface section.(4) Load = 25 pF, data output delay = 0 ns indicates that the delay time is set by the Configuration Register of the serial interface.(5) Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface.
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WRT
SCLK
SD MSB
(CA1)
LSB
(D0)
tXW
tDS
tCKH
tDH
tCKL
tXH
tCKP
TwoBytes
tXS
TIMING CHARACTERISTICS (31-MHz Operation)
VSP5010
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Figure 3. Serial Interface Timing Specification 1
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period 100 nst
CKH
Clock high pulse width 40 nst
CKL
Clock low pulse width 40 nst
DS
Data setup time 30 nst
DH
Data hold time 30 nst
XS
WRTL to SCLK setup time 15 nst
XH
SCLK to WRT hold time 15 nst
XW
WRT setup time 15 ns
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WRT
tXS
tX
tCKH
tCKL
tCKP tDA tDH tCKP
tRS tCKH
tCKH tXH
tXS
SCLK 1 2 15 16 1 2 9 10
SD MSB
(CA1)
LSB
(D0)
MSB
(D9)
LSB
(D0)
RD
tXR
TwoBytes
10Bits
TIMING CHARACTERISTICS
VSP5010
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Figure 4. Serial Interface Timing Specification 2 (Read)
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CKP
Clock period 100 nst
CKH
Clock high pulse width 40 nst
CKL
Clock low pulse width 40 nst
DS
Data setup time (write) 30 nst
DH
Data hold time (write) 30 nst
XS
WRTL to SCLK setup time 15 nst
XH
SCLK to WRT hold time 15 nst
XW
WRT setup time 15 nst
WRW
Minimum WRT width 10 nst
RS
Data setup time (reading) 30 ns
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APPLICATION INFORMATION
OVERVIEW
CORRELATED DOUBLE SAMPLER (CDS) AND SAMPLE/HOLD (S/H) CIRCUIT
VSP5010
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The VSP5010 was developed as an analog front-end for charge-coupled device (CCD) line imaging sensorapplications such as copiers, facsimiles, and so forth. The VSP5010 provides two independent EVEN/ODDchannels for processing, with each channel operating at 31 MHz.
Output signals from each EVEN/ODD channel of the CCD image sensor are sampled at the correlated doublesampling (CDS) circuit and then transmitted to a 14-bit, high-precision analog-to-digital converter (ADC). TheADC output is then amplified by the required gain at a digital programmable gain amplifier (DPGA) and thenrounded to 12-bit data, and output sequentially as EVEN/ODD data that are synchronized with SYSCLK. TheCDS stage can be also used as a sample-and-hold (S/H) step.
Each channel has an optical black level clamp circuit (OB loop) and automatically compensates offsets of theCCD and CDS/SH during the OB pixel period (CLPOB). The OB level output value can be set at a required valuethrough the serial interface. DC bias lost in ac coupling is reproduced as an input clamp voltage, which is thenecessary level for internal operation. Input clamp voltage is charged to a capacitor that is connected to CCDINduring a dummy pixel period ( INPUTCLP) by SHP.
Gain setting, operation polarity of each clock, operating mode selection, and so forth are done through the serialinterface by accessing internal registers. Each setting of register values can be reset to its respective defaultvalue by setting RESET to active low.
The CDS circuit removes low-frequency and/or common-mode noise, such as fluctuations per pixel, from theCCD image sensor output. Noises longer than one pixel period among the input signals are rejected by asubtraction operation at the CDS circuit. Figure 5 shows a simplified CDS block diagram.
Figure 5. Simplified Block Diagram
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C =10pF
1
C =10pF
2
OPA
VSP5010
VCLAMP
CIN CCDIN
SHD
VCLAMP
SHP
CCD
Output
SHP
INPUTCLP
INPUT CLAMP (DUMMY PIXEL CLAMP)
HIGH PRECISION A/D CAPACITOR
VSP5010
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The CDS circuit can be configured as a sample-and-hold (S/H) circuit by the CDS/SH SEL pin. A simplified S/Hcircuit block diagram is shown in Figure 6 .
In the S/H mode, the input clamp voltage (V
CLAMP
) is charged by INPUTCLP and the sampling signal (SHD) tothe C
IN
capacitor. INPUTCLP is activated at the dummy pixel (or OB pixel) of CCD. By these operations, thedummy pixel (or OB pixel) level voltage is fixed to V
CLAMP
at the CCDIN terminal.
When sampling for the OB pixel and an effective pixel, the V
CLAMP
voltage is charged to capacitor C
1
, and C
2charges the voltage lower than V
CLAMP
according to the signal voltage from the CCD. As the voltage difference inC
1
and C
2
is acquired during the hold period, signals from the CCD are acquired as voltage based on V
CLAMP
.
In CDS mode, the signal voltage is received as the voltage difference between the sampled voltage of SHP(reference level) and SHD (data level); the signal level is not affected even when V
CLAMP
charges or fluctuatesbecause of leakage, etc. However, when operated as S/H, the V
CLAMP
fluctuation is read as an offset errorbecause the signal is acquired based on V
CLAMP
. In order to prevent V
CLAMP
leakage, a buffer is inserted at theinput in S/H mode.
Figure 6. Simplified Sample-and-Hold (S/H) Circuit
Output from the CCD image sensor is ac-coupled with the VSP5010 through a capacitor. The purpose of theinput clamp is to reproduce the dc bias lost by ac coupling, and to supply an optimum dc bias for proper deviceoperation at the CDS/SH circuit. Refer to Figure 5 and Figure 6 for simplified block diagrams of the input clampcircuit.
The input signal level is clamped to the internal reference voltage by activating both SHP (during CDS mode;activate SHD during SH mode) and INPUTCLP during the CCD dummy pixel output period.
The ADC block of the VSP5010 consists of a pipeline architecture. This converter has a complete differentialcircuit configuration and error correction circuit, and ensures 14-bit resolution.
Circuits that generate the necessary reference voltage at the ADC are built inside the device, and are shown asREFP (high-potential reference), REFN (low-potential reference), and CM (common-mode voltage) pins outsidethe device. In order to assure ADC accuracy, these reference voltage pins must be sufficiently decoupled by acapacitor (0.1 µF recommended).
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DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)
128 256 10240
InputGainControl
18
16
14
12
10
8
6
4
2
0
Gain(V/V)
384 512 640 768 896
OPTICAL BLACK LEVEL (OB) LOOP AND OB CLAMP LEVEL
Current
DAC
CPLOB
COB
DPGA
OBClamp
Level
DATA
OUT
ADC
CDS/SH
CCDIN
BYPP2
Decoder
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The DPGA circuit can control gain values in the range of 0 V/V to 16 V/V by inputting a digital code through theserial interface. Gain changes linearly in proportion to the code setting, as shown in Figure 7 .
Figure 7. Block Diagram of CDS and Input Clamp
The VSP5010 has a built-in self-calibration circuit (OB loop) that compensates the OB level by using optical black(OB) pixels output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown inFigure 8 .
Figure 8. OB Loop and OB Level Clamp
The CCD offset is compensated by converging this calibration circuit while activating CLPOB during a periodwhen OB pixels are output from the CCD.
In CDS mode, CCD offset is compensated as a difference between the reference level and the data level of theOB pixel. In SH mode, V
CLAMP
is compensated by INPUTCLP as the difference between fixed dummy pixels andthe OB pixels.
These compensated signal levels are recognized as actual OB levels, and outputs are clamped to OB levels setby the serial interface. These OB levels are the base of black for the effective pixel period thereafter.
The DPGA is a gain stage outside the OB loop; therefore, OB levels are not affected even when the gainchanges.
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PRODUCTPREVIEW
T=C/(16384 IMIN)´
(1)
SR=I /C
MAX
(2)
SETTLING OF OB LOOP AND INPUT CLAMP
STANDBY MODE
VSP5010
www.ti.com
................................................................................................................................................................................................ SBES014 – AUGUST 2008
The converging time of the OB loop is determined based on the capacitor value connected to the COB terminaland the output from the current output digital-to-analog converter (DAC) of the loop. The time constant (T) can beobtained from Equation 1 :
Where:
•C is the capacitor value connected to COB,•I
MIN
is the minimum current (0.15 µA) of the current DAC, which has a current equivalent to 1 LSB of theDAC converter output.
When C = 0.1 µF, T is 40.7 µs.
The slew rate (SR) can be obtained from Equation 2 :
Where:
•C is the capacitor value connected to COB,•I
MAX
is the maximum current (153 µA) of the current DAC, which is the equivalent current to 1023 LSB ofthe DAC converter output.
The OB clamp level (digital output value) can be set externally through the serial interface by inputting a digitalcode to the OB clamp level register. The digital code to be input and the corresponding OB clamp level areshown in Table 2 .
Table 2. Input Code and OB Clamp Level to be Set
CLAMP LEVEL (LSB)
CODE VSP5010 (12-BIT)
0000 0000b 00000 0001b 2— —0100 1111b 1580101 0000 (default) 1600101 0001b 162— —1011 1111b 5081111 1111b 510
Because these capacitors are discharged at start-up and after a long standby state, these two capacitors mustbe charged to the proper operational voltage.
The charging time for the input clamp voltage is the logical AND of SHP (SHD in S/H mode) and INPUTCLP. Theactual charging time per line is the duration of the SHP pulse times the number of dummy pixels in the line.Equally, COB is only charged during the OB pixel period. Therefore, some time is necessary to bring theVSP5010 into a normal operating state at device start-up.
Though start-up time depends on the number of dummy and pixels per line, at least 500 ms to 1 s should beallowed.
Normal operation mode and standby mode can be switched by the serial interface.
In standby mode, power consumption can be saved; all operation is suspended other than the interface circuitand reference voltage supply. During standby mode, additional power consumption may be obtained bysuspending SYSCLK. When restoring a SYSCLK that was suspended during standby mode, more than twoclocks of SYSCLK must be acquired before inputting commands.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
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PRODUCTPREVIEW
OUTPUT DATA DELAY
TEST MODE AND TEST PATTERN
CHIP ADDRESS
REGISTER READING
VSP5010
SBES014 – AUGUST 2008 ................................................................................................................................................................................................
www.ti.com
Large transient noise occurs when the output data change because several logic lines change simultaneously.When this transient noise timing overlaps the analog signal sampling timing, it may affect the ADC convertingvalue. To avoid this effect, changing the timing of the VSP5010 output data can be delayed in approximately 3-nssteps by serial control.
The delay value set refers to the increase in default time between SYSCLKL and the data output set in the timingspecification.
The VSP5010 can be set to test mode by setting the configuration register. During test mode, the test patterngenerated inside will be output with or without a CCD input signal.
There are two test patterns. One is a pattern which outputs the code that is the OB level +128 LSB for aspecified number of pixels (stripe pattern); the other is a pattern which increments the output code from 1 to 4095by a specified number of LSBs per pixel (gradation pattern). These patterns can be selected by setting theconfiguration register through the serial interface.
The VSP5010 has two chip address pins, CA0 and CA1. Setting these pins gives a particular address for thedevice, and the data-writing device can be selected by the address in serial interface data. By this function, theserial interface can be used as a common line for up to four devices.
Each register data can be read from the RDO pin by setting bit A3 of the serial interface data to '1', and settingthe reading register address to A[2:0].
After writing the address to specify which register is to be read, assert WRT and apply SCLK. The value of theregister is output sequentially on the RD pin. Refer to the Serial Interface Timing Specification 2 (Read) fordetails.
While reading registers, the writing function is disabled.
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PRODUCTPREVIEW
SERIAL INTERFACE REGISTER DESCRIPTION
Configuration Register Description (Address = 000h)
VSP5010
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................................................................................................................................................................................................ SBES014 – AUGUST 2008
The serial interface of the VSP5010 is composed of three signals; SDI, SCLK, and WRT. SDI data aresequentially stored to the shift register at the rising edge of SCLK, and shift register data are stored to theparallel latch at the rising edge of WRT.
Serial data are two bytes of fixed length and are composed of a two-bit chip address, a four-bit register address,and 10-bit data. The chip address can only write register to a device that matches its value to the address set byCA0 and CA1. By using this two-bit chip address, the serial interface can be shared by other devices.
Both the address (A[3:0]) and the serial data (D[9:0]) start with the MSB (A3, D9) and end with the LSB (A0, D0).When data with more than two bytes are applied, the final two bytes immediately before the rising edge of WRTare effective, and any data writtenbefore that are lost.
Register configuration and serial data format are shown in Table 3 .
Each register value is defined at the time of device power-on (VCC = 2.1 V (typ)).
Table 3. Serial Interface Command Data Format
MSB LSB
REGISTERS CA1 CA0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Configuration X
(1)
X 0 0 0 0 0 0 C7 C6 0 C4 0 C2 C1 C0Standby mode and
X X 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 0 S0Clk DlyDPGA gain EVEN X X 0 0 1 0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0DPGA gain ODD X X 0 0 1 1 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0OB clamp level
X X 0 1 0 0 0 0 O7 O6 O5 O4 O3 O2 O1 O0EVEN
OB clamp level
X X 0 1 0 1 0 0 O7 O6 O5 O4 O3 O2 O1 O0ODD
Test mode X X 0 1 1 0 0 0 0 0 T5 T4 0 T2 0 T0Internal ADCK
XX011100000000PT1 0monitor
Read out X X 1 R2 R1 R0 X X X X X X X X X X
Bits C[2:0] Clock Polarity
Bit C0 ( INPUTCLP Polarity) Bit C1 (CLPOB Polarity) Bit C2 (SHP/SHD Polarity)
0 = Active low (default) 0 = Active low (default) 0 = Active low (default)1 = Active high 1 = Active high 1 = Active high
Bit C4 Data Output Order
0 = EVEN/ODD (default)1 = ODD/EVEN
Bits C[7:6] Data Output Delay
Bit C7 Bit C6
0 = Time (0 ns, typ) (default) 0 Delay = time (0 ns, typ) (default)0 = Delay time (2 ns, typ) 1 = Delay time (2 ns, typ)1 = Delay time (4 ns, typ) 0 = Delay time (4 ns, typ)1 = Delay time (6 ns, typ) 1 = Delay time (6 ns, typ)
(1) X = Don ' t care.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
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PRODUCTPREVIEW
Standby Mode and MPX Clock Edge Phase Description (Address = 01h)
DlyEdge1
tD
DlyEdge2
SysClock(30MHz)
OutClock(60MHz)
Internal ADCK Monitor Description (Address = 07h)
EVEN Channel Gain Register Description (Address = 02h)
ODD Channel Gain Register Description (Address = 03h)
EVEN Channel OB Clamp Register Description (Address = 04h)
ODD Channel OB Clamp Register Description (Address = 05h)
VSP5010
SBES014 – AUGUST 2008 ................................................................................................................................................................................................
www.ti.com
Bit S0 Standby/Normal Operation Select
0 = Normal operation mode (default)1 = Standby mode
Bits D[8:1] MPX Clock Edge Phase
Figure 9 illustrates the MPX clock edge phase.
Bits D[5:2] Dlyedge 2 Timing (except constant delay t
D1
)
0000b = Delay time (1.6 ns)1000b = Delay time (8.0 ns) (default, 0.8 ns/step)1111b = Delay time (13.6 ns)
Bits D[9:6] Dlyedge 1 Timing (except constant delay t
D1
)
0000b = Delay time ( – 2.4 ns)1000b = Delay time (0 ns) (default, 0.3 ns/step)1111b = Delay time (2.1 ns)
Figure 9. MPX Clock Edge Phase
CAUTION:
Please do not use at Delayedge 1 > Delayedge 2
(example: D[5:2] = 0000b and D[9:6] = 1111b)
Delayedge2 should maintain sufficient width to allow proper data output timing.
Bit D1 PT1
0 = Normal
1 = Internal ADC clock to B0 (ADC output, bit 0, least significant bit)
Bits G[9:0] Gain Value
GAIN[9:0] /64 (default = 00 0100 0000b)
Bits G[9:0] Gain Value
GAIN[9:0] /64 (default = 00 0100 0000b)
Bits O[7:0] OB Clamp Level
2 LSB × O[7:0] (default = 0101 0000b)
Bits O[7:0] OB Clamp Level
2 LSB × O[7:0] (default = 0101 0000b)
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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PRODUCTPREVIEW
Test Mode Register Description (Address = 06h)
Register Read Out Description
POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS
VSP5010
www.ti.com
................................................................................................................................................................................................ SBES014 – AUGUST 2008
Bit T0 Test Mode Enable/Disable
0 = Disable (default)1 = Enable
Bit T2 Test Pattern Select
0 = Gradation pattern (default)1 = Stripe pattern
Bits T[5:4] Test Pattern Data Interval
Bit T5 Bit T4
0 = Stripe pattern (8 pixels), gradation
0 = Stripe pattern (8 pixels), gradation pattern (2 pixels) (default)pattern (2 pixels) (default)0 = Stripe pattern (16 pixels),
1 = Stripe pattern (16 pixels), gradation pattern (4 pixels)gradation pattern (4 pixels)1 = Stripe pattern (32 pixels),
0 = Stripe pattern (32 pixels), gradation pattern (8 pixels)gradation pattern (8 pixels)1 = Stripe pattern (64 pixels),
1 = Stripe pattern (64 pixels), gradation pattern (16 pixels)gradation pattern (16 pixels)
Bit A[2:0] R[2:0]
2:0 = Set reading register address
The VSP5010 incorporates a very high-precision and high-speed ADC and analog circuitry which are vulnerableto any extraneous noise from the rails or elsewhere. For this reason, although the VSP5010 has analog anddigital supply pins, it should be treated as an analog component; all supply pins except for VDD should bepowered by the analog supply only. This configuration ensures the most consistent results, because digital powerlines often carry high levels of wideband noise that would otherwise be coupled into the device and degrade theachievable performance.
Proper grounding, short lead length, and the use of ground planes are also very important for high-frequencydesigns. Multilayer printed circuit boards (PCBs) are recommended for the best performance; these types ofboards offer distinct advantages such as minimizing ground impedance, separation of signal layers by groundlayers, and so forth. It is highly recommended that analog and digital ground pins of the VSP5010 be joinedtogether at the IC and be connected only to the analog ground of the system.
The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply VDD (pin 18) and it shouldbe separated from the other supply pins completely or at least with a ferrite bead.
Because of the high operation speed, the converter also generates high-frequency current transients and noisethat are fed back into the supply and reference lines. This additional interference requires the supply andreference pins be sufficiently bypassed. In most cases, 0.1- µF ceramic chip capacitors are adequate to decouplethe reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum(1- µF to 22- µF) and ceramic (0.1- µF) capacitors. The effectiveness of the decoupling depends largely on theproximity to the individual pin. VDD should be decoupled to the proximity of DGND (pin 17 and pin 64).
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
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PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
VSP5010PM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) A42 SNBI Level-1-260C-UNLIM
VSP5010PMG6 ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) A42 SNBI Level-1-260C-UNLIM
VSP5010PMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) A42 SNBI Level-1-260C-UNLIM
VSP5010PMRG6 ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) A42 SNBI Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
VSP5010PMR LQFP PM 64 1000 330.0 25.4 12.8 12.8 1.9 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
VSP5010PMR LQFP PM 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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