Sample & Buy Product Folder Technical Documents Support & Community Tools & Software Reference Design LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 LM4140 High Precision Low Noise Low Dropout Voltage Reference 1 Features 3 Description * * * * * * The LM4140 series of precision references are designed to combine high accuracy, low drift, and noise with low power dissipation in a small package. 1 * * * * High Initial Accuracy: 0.1% Ultra-Low Noise Low Temperature Coefficient: 3 ppm/C (A Grade) Low Voltage Operation: 1.8V Low Dropout Voltage: 20 mV (Typical) at 1mA Supply Current: 230 A (Typical), 1 A Disable Mode Enable Pin Output Voltage Options: 1.024 V, 1.25 V, 2.048 V, 2.5 V, and 4.096 V Custom Voltages From 0.5 V to 4.5 V Temperature Range: 0C to 70C The LM4140 is the industry's first reference with output voltage options lower than the bandgap voltage. The key to the advance performance of the LM4140 is the use of EEPROM registers and CMOS DACs for temperature coefficient curvature correction and trimming of the output voltage accuracy of the device during the final production testing. The major advantage of this method is the much higher resolution available with DACs than is available economically with most methods used by other bandgap references. 2 Applications * * * * * * * * * The low input and dropout voltage, low supply current, and output drive capability of the LM4140 makes this product an ideal choice for battery powered and portable applications. Portable, Battery-Powered Equipment Instrumentation and Test Equipment Automotive Industrial Process Control Data Acquisition Systems Medical Equipment Precision Scales Servo Systems Battery Charging The LM4140 is available in three grades (A, B, C) with 0.1% initial accuracy and 3, 6, and 10 ppm/C temperature coefficients. For even lower temperature coefficients, contact Texas Instruments. The device performance is specified over the temperature range 0C to 70C, and is available in compact 8-pin package. For other output voltage options from 0.5 V to 4.5 V, contact Texas Instruments. Device Information(1) PART NUMBER PACKAGE LM4140 SOIC (8) BODY SIZE (NOM) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Input 2 6 VIN 5 NC 3 Output VREF COUT 1 ...F Enable GND 1, 4 7, 8 Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Applications ................................................ 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2013) to Revision F Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Added Thermal Information table ........................................................................................................................................... 4 Changes from Revision D (April 2005) to Revision E * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View Ground 1 8 Ground VIN 2 7 Ground Enable 3 6 VREF Ground 4 5 NC Not to scale Pin Functions PIN NAME NO. TYPE (1) DESCRIPTION Enable 3 I Pulled to input for normal operation. Forcing this pin to ground turns off the output. Ground 1, 4, 7, 8 G Negative supply or ground connection. These pins must be connected to ground. NC 5 -- This pin must be left open. VIN 2 I Positive supply. VREF 6 O Reference output. Capable of sourcing up to 8 mA. (1) G = Ground, I = Input, O = Output Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 3 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Maximum voltage on any input pin MIN MAX UNIT -0.3 5.6 V 345 mW 150 C Output short-circuit duration Indefinite Power dissipation (TA = 25C) (2) Storage temperature, Tstg (1) (2) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Without PCB copper enhancements. The maximum power dissipation must be derated at elevated temperatures and is limited by TJMAX (maximum junction temperature), RJA (junction to ambient thermal resistance) and TA (ambient temperature). The maximum power dissipation at any temperature is: PDissMAX = (TJMAX - TA)/RJA up to the value listed in the Absolute Maximum Ratings. The RJA for the 8-pin SOIC package is 160C/W. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Ambient temperature 0 70 C Junction temperature 0 80 C 6.4 Thermal Information LM4140 THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 119.3 C/W RJC(top) Junction-to-case (top) thermal resistance 52.3 C/W RJB Junction-to-board thermal resistance 60.3 C/W JT Junction-to-top characterization parameter 14.5 C/W JB Junction-to-board characterization parameter 59.7 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 6.5 Electrical Characteristics VIN = 3 V for the 1.024-V and 1.25-V, VIN = 5 V for all other voltage options, VEN = VIN, COUT = 1 F (1), ILOAD = 1 mA, and TA = TJ = 25C (unless otherwise noted) PARAMETER MIN (2) TEST CONDITIONS VREF Output voltage initial accuracy (4) All versions TCVREF/C Temperature coefficient 0C TA 70C TYP (3) 1.024-V and 1.25-V options, 1.8 V VIN 5.5 V Line regulation 6 C grade 10 TA = 25C 50 0C TA 70C 1 mA ILOAD 8 mA 4.096-V option 1 0C TA 70C TA = 25C 5 0C TA 70C 60 VREF Thermal hysteresis (5) 0C TA + 70C 20 Operating voltage 1.024-V and 1.25-V options, IL = 1 mA to 8 mA, 0C TA 70C IL = 8 mA Dropout voltage (6) IL = 1 mA 4.096-V option IL = 8 mA Output noise voltage (7) VN Supply current ILOAD = 0 mA IS(OFF) Supply current VEnable < 0.4 V VH Logic high input voltage 0C TA 70C IH Logic high input current VL Logic low input voltage IL Logic low input current ISC Short-circuit current (3) (4) (5) (6) (7) 35 ppm/mA TA = 25C ppm ppm 5.5 20 40 160 235 0C TA 70C 0C TA 70C 400 TA = 25C 20 40 195 270 0C TA 70C 0C TA 70C 490 TA = 25C 230 0C TA 70C VPP 320 375 TA = 25C 265 0C TA 70C 350 A 400 TA = 25C 0.01 0C TA 70C 1 0.8 x VIN 0C TA 70C nA 0.4 1 8.5 A V 2 0C TA 70C mV 45 TA = 25C TA = 25C V 45 TA = 25C 2.2 4.096-V option (1) (2) 1.8 0.1 Hz to 10 Hz All other voltage options IS(ON) 20 150 1000 hours VIN-VREF ppm/V 200 150 Long-term stability IL = 1 mA 300 250 TA = 25C VREF 2.048-V and 2.5-V options ppm/C 350 20 0C TA 70C All other voltage options Load regulation 3 B grade TA = 25C All other voltage options, Vref + 200 mV VIN 5.5 V VREF/ILOAD UNIT 0.1% A grade VREF/VIN MAX (2) 20 V nA 35 40 mA For proper operation, a 1-F capacitor is required between the output pin and the GND pin of the device. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely parametric norm. High temperature and mechanical stress associated with PCB assembly can have significant impact on the initial accuracy of the LM4140 and may create significant shifts in VREF. Thermal hysteresis is defined as the changes in 25C output voltage before and after the cycling of the device from 0C to 70C. Dropout voltage is defined as the minimum input to output differential voltage at which the output voltage drops by 0.5% below the value measured with VIN = 3 V for the 1.024-V and 1.25-V, VIN = 5 V for all other voltage options. The output noise is based on 1.024 V option. Output noise is linearly proportional to VREF. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 5 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com 6.6 Typical Characteristics TA = 25C, no load, COUT = 1 F, VIN = 3 V for 1.024-V and 1.25-V, and 5 V for all other voltage options, and VIN = VEN (unless otherwise noted). The 1-F output capacitor is actively discharged to ground (see ON/OFF Operation for more details). 6 Figure 1. Power Up and Down Ground Current Figure 2. Enable Response Figure 3. Line Transient Response Figure 4. Load Transient Response Figure 5. Output Impedance Figure 6. Power Supply Rejection Ratio Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 Typical Characteristics (continued) TA = 25C, no load, COUT = 1 F, VIN = 3 V for 1.024-V and 1.25-V, and 5 V for all other voltage options, and VIN = VEN (unless otherwise noted). The 1-F output capacitor is actively discharged to ground (see ON/OFF Operation for more details). 1.024-V and 1.25-V options require 1.8-V supply Figure 7. Dropout Voltage vs Load Current Figure 8. Output Voltage Change vs Sink Current (ISINK) Figure 9. Total Current (IS(OFF)) vs Supply Voltage Figure 10. Total Current (IS(ON)) vs Supply Voltage Figure 11. Spectral Noise Density (0.1 Hz to 10 Hz) Figure 12. Spectral Noise Density (10 Hz to 100 kHz) Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 7 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) TA = 25C, no load, COUT = 1 F, VIN = 3 V for 1.024-V and 1.25-V, and 5 V for all other voltage options, and VIN = VEN (unless otherwise noted). The 1-F output capacitor is actively discharged to ground (see ON/OFF Operation for more details). 8 Figure 13. Ground Current vs Load Current Figure 14. Long-Term Drift Figure 15. Load Regulation vs Temperature Figure 16. Output Voltage vs Load Current Figure 17. Line Regulation vs Temperature Figure 18. IQ vs Temperature Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 Typical Characteristics (continued) TA = 25C, no load, COUT = 1 F, VIN = 3 V for 1.024-V and 1.25-V, and 5 V for all other voltage options, and VIN = VEN (unless otherwise noted). The 1-F output capacitor is actively discharged to ground (see ON/OFF Operation for more details). Figure 19. Short-Circuit Current vs Temperature Figure 20. Dropout Voltage vs Load Current (VOUT) = 2 V Figure 21. Typical Temperature Coefficient (Sample of 5 Parts) Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 9 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The LM4140 device is a high-precision series voltage reference available in 5 difference output voltage options, including the 1.024-V option below the bandgap voltage. The series reference can operate with input voltage as low as VREF + 400 mV over temperature, consuming 400 A or less over temperature depending on voltage option. While in shutdown, the device consumes 10 nA (typical). 7.2 Functional Block Diagram VIN EN Bandgap Cell + VOUT Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 ON/OFF Operation The LM4140 is designed to quickly reduce both VREF and IQ to zero when turned off. VREF is restored in less than 200 s when turned on. During the turnoff, the charge across the output capacitor is discharged to ground through internal circuitry. The LM4140 is turned off by pulling the enable input low, and turned on by driving the input high. If this feature is not to be used, the enable pin must be tied to the VIN to keep the reference on at all times (the enable pin must not be left floating). To ensure proper operation, the signal source used to drive the enable pin must be able to swing above and below the specified high and low voltage thresholds which ensure an ON or OFF state (see Electrical Characteristics). The ON/OFF signal may come from either a totem-pole output, or an open-collector output with pullup resistor to the LM4140 input voltage. This high-level voltage may exceed the LM4140 input voltage, but must remain within the absolute maximum rating for the enable pin. 7.4 Device Functional Modes Table 1 lists the operational modes of the LM4140. Table 1. Operational Modes 10 ENABLE PIN LOGIC STATE DESCRIPTION EN = VIN 1 Normal operation, device powered up EN = Ground 0 Device in shutdown Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Input Capacitors Although not always required, TI recommends an input capacitor. A supply bypass capacitor on the input assures that the reference is working from a source with low impedance, which improves stability. A bypass capacitor can also improve transient response by providing a reservoir of stored energy that the reference can use in case where the load current demand suddenly increases. The value used for CIN may be used without limit. 8.1.2 Output Capacitors The LM4140 requires a 1-F (nominally) output capacitor for loop stability (compensation) as well as transient response. During the sudden changes in load current demand, the output capacitor must source or sink current during the time it takes the control loop of the LM4140 to respond. This capacitor must be selected to meet the requirements of minimum capacitance and equivalent series resistance (ESR) range. In general, the capacitor value must be at least 0.2 F (over the actual ambient operating temperature), and the ESR must be within the range indicated in Figure 22, Figure 23, and Figure 24. Figure 22. 0.22-F ESR Range Figure 23. 1-F ESR Range Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 11 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Application Information (continued) Figure 24. 10-F ESR Range 8.1.3 Tantalum Capacitors Surface-mountable solid tantalum capacitors offer a good combination of small physical size for the capacitance value, and ESR in the range required by the LM4140. The results of testing the LM4140 stability with surface mount solid tantalum capacitors show good stability with values in the range of 0.1 F. However, optimum performance is achieved with a 1-F capacitor. Table 2 shows tantalum capacitors that have been verified as suitable for use with the LM4140. Table 2. 1-F Surface-Mount Tantalum Capacitor Selection Guide MANUFACTURER PART NUMBER Kemet T491A105M010AS NEC NRU105N10 Siemens B45196-E3105-K Nichicon F931C105MA Sprague 293D105X0016A2T Table 3. 2.2-F Surface-Mount Tantalum Capacitor Selection Guide MANUFACTURER PART NUMBER Kemet T491A225M010AS NEC NRU225M06 Siemens B45196/2.2/10/10 Nichicon F930J225MA Sprague 293D225X0010A2T 8.1.4 Aluminum Electrolytic Capacitors Although probably not a good choice for a production design, because of relatively large physical size, an aluminium electrolytic capacitor can be used in the design prototype for an LM4140 reference. A 1-F capacitor meeting the ESR conditions can be used. If the operating temperature drops below 0C, the reference may not remain stable, as the ESR of the aluminium electrolytic capacitor increases, and may exceed the limits indicated in the figures. 12 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 8.1.5 Multilayer Ceramic Capacitors Surface-mountable multilayer ceramic capacitors may be an attractive choice because of their relatively small physical size and excellent RF characteristics. However, they sometimes have an ESR values lower than the minimum required by the LM4140, and relatively large capacitance change with temperature. The manufacturer's datasheet for the capacitor must be consulted before selecting a value. Test results of LM4140 stability using multilayer ceramic capacitors show that a minimum of 0.2 F is usually required. Table 4 shows the multilayer ceramic capacitors that have been verified as suitable for use with the LM4140. Table 4. Surface-Mount Ceramic Capacitors Selection Guide CAPACITOR (F) MANUFACTURER PART NUMBER 2.2 Tokin 1E225ZY5U-C203 2.2 Murata GRM42-6Y5V225Z16 4.7 Tokin 1E475ZY5U-C304 8.1.6 Reverse Current Path The P-channel Pass transistor used in the LM4140 has an inherent diode connected between the VIN and VREF pins (see Figure 25). Figure 25. Internal P-Channel Pass Transistor Forcing the output to voltages higher than the input, or pulling VIN below voltage stored on the output capacitor by more than a Vbe, forward biases this diode and current flows from the VREF terminal to VIN. No damage to the LM4140 occurs under these conditions as long as the current flowing into the output pin does not exceed 50 mA. 8.1.7 Output Accuracy Like all references, either series or shunt, the after assembly accuracy is made up of primarily three components: initial accuracy itself, thermal hysteresis, and effects of the PCB assembly stress. LM4140 provides an excellent output initial accuracy of 0.1% and temperature coefficient of 6ppm/C (B Grade). For best accuracy and precision, the LM4140 junction temperature must not exceed 70C. The thermal hysteresis curve on this datasheet are performance characteristics of three typical parts selected at random from a sample of 40 parts. Parts are mounted in a socket to minimize the effect of PCB's mechnical expansion and contraction. Readings are taken at 25C following multiple temperature cycles to 0C and 70C. The labels on the X axis of Figure 26 indicate the device temperature cycle prior to measurement at 25C. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 13 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Figure 26. Typical Thermal Hysteresis The mechanical stress due to the PCB's mechanical and thermal stress can cause an output voltage shift more than the true thermal coefficient of the device. References in surface mount packages are more susceptible to these stresses because of the small amount of plastic molding which support the leads. Following the recommendations on Layout can minimize the mechanical stress on the device. 8.2 Typical Applications 8.2.1 Precision DAC Reference 4.1 k VIN VIN VREF LM4140 4.7 F 50 k 10T -4.096 100 k EN 1 mA GND DAC Copyright (c) 2016, Texas Instruments Incorporated Figure 27. Precision DAC Reference Schematic 8.2.1.1 Design Requirements Generate a precision, temperature-stable voltage reference for use in digital-to-analog converter applications. 8.2.1.2 Detailed Design Procedure Use LM4140-4.096 to generate a 4.096-V reference voltage. Use an adjustable resistor network to fine tune the reference. 14 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 Typical Applications (continued) 8.2.1.3 Application Curves Figure 29. Typical Temperature Coefficient (Sample of 5 Parts) Figure 28. Output Voltage vs Load Current 8.2.2 Boosted Output Current VIN = 5.0 V + 10 F 500 2N2907 VIN 100 k VOUT= 2.5 V at 50 mA VREF VIN 0V On Off LM4140 2.5 + 10 F EN GND Copyright (c) 2016, Texas Instruments Incorporated Figure 30. Boosted Output Current Schematic 8.2.2.1 Design Requirements Generate a reference voltage that can support 50 mA. 8.2.2.2 Detailed Design Procedure The LM4140-2.5 sets the reference level at 2.5 V. A 2N2907 PNP transistor is added, where the base is tied to VIN through a 500- resistor. The input current into the LM4140 increases with load current, which increases the voltage drop across the 500- resistor until the PNP transistor turns on and supplements the load current. See Figure 30 for the circuit diagram. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 15 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Typical Applications (continued) 8.2.3 Boosted Output Current With Current Limiter 12 k VIN = 4.5 V to 5.5 V + 1k 10 F 2 X 2N2907 IN OUT VIN 0V On Off + LM4140 2.5 VOUT= 2.5 V at 50 mA 10 F EN GND Copyright (c) 2016, Texas Instruments Incorporated Figure 31. Boosted Output Current With Current Limiter Schematic 8.2.3.1 Design Requirements Generate a reference voltage that can support 50 mA with current limiter. 8.2.3.2 Detailed Design Procedure The LM4140-2.5 sets the reference level at 2.5 V. Similar to Boosted Output Current, a PNP transistor is added between VIN and the output. Another PNP transistor is added to sense the current between VIN and the load. This additional transistor turns on above 50 mA, which turns off the pass transistor to the load. 8.2.4 Complimentary Outputs VREF VREF VIN R LM4140 1 F EN + VREF GND R/2 Copyright (c) 2016, Texas Instruments Incorporated * Low Noise Op Amp such as OP-27 Figure 32. Complimentary Outputs Schematic 8.2.4.1 Design Requirements Generate a positive and negative voltage reference. 8.2.4.2 Detailed Design Procedure Use the LM4140 to generate the positive reference. Pass the reference into a unity gain inverting amplifier for a negative reference output. 16 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 Typical Applications (continued) 8.2.5 Voltage Reference With Force and Sense Output VIN VREF + LM4140 100 k 1 F EN VREF Force VREF Sense GND Copyright (c) 2016, Texas Instruments Incorporated Figure 33. Voltage Reference With Force and Sense Output Schematic 8.2.5.1 Design Requirements Design a voltage reference source that has a force and sense output. 8.2.5.2 Detailed Design Procedure Use the LM4140 to generate a reference voltage. Pass this into the positive input terminal of an operation amplifier, and use the negative input as the sense input from the load. 8.2.6 Precision Programmable Current Source VIN IN OUT R1 2.45 k LM4140 EN 1 F RSET 1k GND IREF RL VIN ! IOUT u RL IOUT VREF 1k VREF ( ) IREF (R1 RSET ) R1 2.45 k: for IL 1 mA using LM4120 2.5 Copyright (c) 2016, Texas Instruments Incorporated Figure 34. Precision Programmable Current Source Schematic 8.2.6.1 Design Requirements Create a precision, adjustable current source. 8.2.6.2 Detailed Design Procedure Use LM4140 to create reference voltage across an adjustable resistor, R1 + RSET. The voltage reference creates a constant voltage source, and the adjustable resistor generates a proportional current. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 17 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com Typical Applications (continued) 8.2.7 Strain Gauge Conditioner for 350- Bridge Figure 35. Strain Gauge Conditioner for 350- Bridge Schematic 8.2.7.1 Design Requirements Supply a strain gage with a precision reference voltage. 8.2.7.2 Detailed Design Procedure Use LM4140 to generate 4.096-V reference voltage. Use the reference to drive the strain gage bridge. 8.2.8 Bipolar Voltage References for Low Power ADC Figure 36. Bipolar Voltage References for Low Power ADC Schematic 18 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 Typical Applications (continued) 8.2.8.1 Design Requirements Provide positive and negative reference voltages for the ADC1175 low power ADC. 8.2.8.2 Detailed Design Procedure Use LM4140 to generate a 2.5-V positive reference voltage. The reference voltage is passed into an opamp to act as a buffer and inverter, which yields a positive and negative reference. Transistors are used to drive the low impedance inputs of the ADC1175. 8.2.9 Self-Biased Low Power ADC Reference With Trim Current Sources Figure 37. Self-Biased Low Power ADC Reference With Trim Current Sources Schematic 8.2.9.1 Design Requirements Use ADC1175 internal reference, but increase accuracy with trimming currents. 8.2.9.2 Detailed Design Procedure The LM4140-2.5 sets a stable voltage source which is buffered and inverted, and the opamps are used as force and sense amplifiers. This application does not require the transistor to drive low impedance nodes as the internal reference voltages are still being used. The external circuitry is to increase the accuracy of the internal reference. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 19 LM4140 SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 www.ti.com 9 Power Supply Recommendations While an input capacitor is not required, TI recommends using a 0.1 F or larger capacitor to reduce noise on the input and improve transient response. 10 Layout 10.1 Layout Guidelines The simplest ways to reduce the stress related shifts are: 1. Mounting the device near the edges or the corners of the board where mechanical stress is at its minimum. The center of the board generally has the highest mechanical and thermal expansion stress. 2. Mechanical isolation of the device by creating an island by cutting a U shape slot on the PCB for mounting the device. This approach would also provide some thermal isolation from the rest of the circuit. Figure 39 is a recommended printed-circuit board layout with a slot cut on three sides of the circuit layout to serve as a strain relief. 10.2 Layout Example Figure 38. Suggested Schematic and External Components 2 6 VIN C2 1 F U1 LM4140 C1 3 5 EN 1, 4 VOUT TOUT 7 ,8 Copyright (c) 2016, Texas Instruments Incorporated Figure 39. Suggested PCB Layout With Slot 20 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 LM4140 www.ti.com SNVS053F - JUNE 2000 - REVISED SEPTEMBER 2016 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LM4140 21 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM4140ACM-1.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM1.0 LM4140ACM-1.2/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM1.2 LM4140ACM-2.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM2.0 LM4140ACM-2.5/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM2.5 LM4140ACM-4.1/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM4.1 LM4140ACMX-2.5/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM2.5 LM4140ACMX-4.1/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140A CM4.1 LM4140BCM-1.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM1.0 LM4140BCM-1.2/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM1.2 LM4140BCM-2.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM2.0 LM4140BCM-2.5/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM2.5 LM4140BCM-4.1/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM4.1 LM4140BCMX-1.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM1.0 LM4140BCMX-2.5/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM2.5 LM4140BCMX-4.1/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140B CM4.1 LM4140CCM-1.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM1.0 LM4140CCM-1.2/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM1.2 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 6-Feb-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM4140CCM-2.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM2.0 LM4140CCM-2.5/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM2.5 LM4140CCM-4.1/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM4.1 LM4140CCMX-1.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM1.0 LM4140CCMX-1.2/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM1.2 LM4140CCMX-2.5/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM2.5 LM4140CCMX-4.1/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 4140C CM4.1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM4140ACMX-2.5/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140ACMX-4.1/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140BCMX-1.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140BCMX-2.5/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140BCMX-4.1/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140CCMX-1.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140CCMX-1.2/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140CCMX-2.5/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4140CCMX-4.1/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4140ACMX-2.5/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140ACMX-4.1/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140BCMX-1.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140BCMX-2.5/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140BCMX-4.1/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140CCMX-1.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140CCMX-1.2/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140CCMX-2.5/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM4140CCMX-4.1/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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