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January 1999
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-
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1.0 Features
• Generates up to eighteen low-skew, non-inverting
clocks from one clock input
• Supports up to four SDRAM DIMMs
• Uses either I2C-bus or SMB us ser i al interface with
Read and Write capability for individual clock output
control
• Output enable pin tristates all clock outputs to facili-
tate board testing
• Clock outputs skew-matched to less than 250ps
• Less than 5ns propagation delay
• Output impedance: 17Ω at 0.5VDD
• Serial interface I/O meet I2C specifications; all other
I/O are LVTTL/LVCMOS-compatible
• Five differerent pin configurations available:
• FS6050: 18 clock outputs in a 48-pin SSOP
• FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
• FS6053: 13 clock outputs in a 28-pin SOIC
• FS6054: 14 clock outputs in a 28-pin SOIC
• FS6057: 17 clock outputs in a 32-pin SOIC
Figure 1: Block Diagram (FS6050)
Serial
Interface
SDRAM_(0:1)
SCL
SDA
CLK_IN
OE
FS6050
SDRAM_(2:3)
SDRAM_(4:5)
SDRAM_(6:7)
SDRAM_(8:9)
SDRAM_(10:11)
SDRAM_(12:13)
SDRAM_(14:15)
SDRAM_16
VSS_I
2
C
VDD_I
2
CVSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SDRAM_17
VSS
VDD
18
2.0 Description
The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium® II PC100-based systems with 100MHz
SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
Under I2C-bus control, individual clock outputs may be
turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.
Figure 2: Pin Configuration (FS6050)
148
2
3
4
5
6
7
8
47
46
45
44
43
42
41
(reserved)
(reserved)
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
(reserved)
VDD
(reserved)
9
10
11
12
13
14
15
16
SDRAM_3
VSS
CLK_IN
VDD
SDRAM_4
SDRAM_5
VSS
VDD
17
18
19
20
21
22
23
SDRAM_6
SDRAM_7
VSS
VDD
SDRAM_16
VSS
VDD_I
2
C
40
39
38
37
36
35
34
33
SDRAM_10
SDRAM_11
VDD
OE
SDRAM_13
SDRAM_12
VSS
VDD
32
31
30
29
28
27
26
VSS_I
2
C
VSS
SDRAM_17
VDD
SDRAM_9
SDRAM_8
VSS
24
SDA
25
SCL
VDD
VSS
FS6050
48-pin SSOP
Figure 3: Pin Configuration (FS6051)
1
2
3
4
5
6
7
8
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
VDD
9
10
11
12
13
14 15
16
SDRAM_3
VSS
CLK_IN
VDD
17
18
19
20
21
22
23
SDRAM_16
VSS
VDD_I
2
C
VDD
OE
SDRAM_13
SDRAM_12
VSS
VDD
28
27
26
VSS_I
2
C
VSS
SDRAM_17
24
SDA
25
SCL
FS6051
28-pin SOIC, SSOP
Additional pin configurations are noted on Page 3
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Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
(FS6050) PIN
(FS6051) PIN
(FS6053) PIN
(FS6054) PIN
(FS6057) TYPE NAME DESCRIPTION
11 9 9 9 9 DI CLK_IN Clock input f or SDRA M clock out puts
25 15 15 15 17 DIUSCL Serial clock input
24 14 14 14 16 DIUO SDA Serial data input/out put
4 2 2 2 2 DO SDRAM_0
5 3 3 3 3 DO SDRAM_1
8 6 6 6 6 DO SDRAM_2
9 7 7 7 7 DO SDRAM_3
13 - - - 10 DO SDRAM_4
14 - - - 11 DO SDRAM_5
17 - 10 10 12 DO SDRAM_6
18 - 11 11 13 DO SDRAM_7
SDRAM clock outputs (Byte 0)
31 - 18 18 20 DO SDRAM_8
32 - 19 19 21 DO SDRAM_9
35 - - - 22 DO SDRAM_10
36 - - - 23 DO SDRAM_11
40 22 22 22 26 DO SDRAM_12
41 23 23 23 27 DO SDRAM_13
44 26 26 26 30 DO SDRAM_14
45 27 27 27 31 DO SDRAM_15
SDRAM clock outputs (Byte 1)
21 11 12 12 14 DO SDRAM_16
28 18 - 17 - DO SDRAM_17 SDRAM feedback c l ock outputs (Byte 2)
38 20 - 20 - DIUOE Output enable tristates all clock outputs when low
3, 7, 12, 16,
20, 29, 33,
37, 42, 46
1, 5, 10, 19,
24, 28 1, 5, 20, 24,
28 1, 5, 24, 28 1, 5, 24, 28,
32 PVDD3.3V ± 5% power supply for SDRAM clock buffers
23 13 13 13 15 P VDD_I2C 3.3V ± 5% power supply for serial communi cations
6, 10, 15, 19,
22, 27, 30,
34, 39, 43
4, 8, 12, 17,
21, 25 4, 8, 17, 21,
25 4, 8, 21, 25 4, 8, 19, 25,
29 P VSS Ground for SDRAM clock buffers
26 16 16 16 18 P VSS_I2C Ground for serial comm unications
1, 2, 47, 48 - - - - - (res erved) Reserved
3.0 Programming Information
Table 2: Clock Enable Configuration
CONTROL INPUTS CLOCK OUTPUTS (MHz)
OE SDRAM_0:3 SDRAM_4:7 SDRAM_8:11 SDRAM_12:15 SDRAM_16:17
0 tristate tristate tristate tristate tristate
1 CLK_IN CLK_IN CLK_IN CLK_IN CLK_IN
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3.1 Power-Up Initialization
All outputs are enabled and act ive up on po wer - up, a nd a l l
output control register bits are initialized to one.
The outputs m ust be configured at power-up and are not
expected to be configured during normal operation. Inac-
tive outputs are held low and are disabled from switching.
3.1.1 Unused Outputs
Outputs that are not use d in v ersions of this de vice with a
reduced pinout are still operational internally. To reduce
power dis sip ati on a nd c ros s talk eff ec ts from the unlo ade d
outputs, it is recom mended th at these outputs be s hut of f
via the Control Registers.
3.2 Register Programming
A logic-one written to a valid bit location turns on the as-
signed output clock. Likewise, a logic-zero written to a
valid bit location turns off the assigned output clock.
Any unus ed or r eserve d reg ister b its sho uld be c leare d to
zero.
Serial bits are writt en to this de vice in the or der sho wn in
Table 3.
Table 3: Register Summary
SERI AL BIT DATA BYTE CLOCK OUTPUT
0
(MSB)
SDRAM_7
1 SDRAM_6
2 SDRAM_5
3 SDRAM_4
4 SDRAM_3
5 SDRAM_2
6
Byte 0
SDRAM Control Register 0
SDRAM_1
7
(LSB)
SDRAM_0
8
(MSB)
SDRAM_15
9 SDRAM_14
10 SDRAM_13
11 SDRAM_12
12 SDRAM_11
13 SDRAM_10
14
Byte 1
SDRAM Control Register 1
SDRAM_9
15
(LSB)
SDRAM_8
16
(MSB)
SDRAM_17
17 SDRAM_16
18 Reserved
19 Reserved
20 Reserved
21 Reserved
22
Byte 2
SDRAM Control Register 2
Reserved
23
(LSB)
Reserved
Figure 4: Pin Configuration
(FS6053) Figure 5: Pin Configuration
(FS6054) Figure 6: Pin Configuration
(FS6057)
1
2
3
4
5
6
7
8
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
VDD
9
10
11
12
13
14 15
16
SDRAM_3
VSS
CLK_IN
SDRAM_6
17
18
19
20
21
22
23
SDRAM_7
SDRAM_16
VDD_I
2
C
SDRAM_9
VDD
SDRAM_13
SDRAM_12
VSS
VDD
28
27
26
VSS_I
2
C
VSS
SDRAM_8
24
SDA
25
SCL
FS6053
28-pin SOIC
1
2
3
4
5
6
7
8
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
VDD
9
10
11
12
13
14 15
16
SDRAM_3
VSS
CLK_IN
SDRAM_6
17
18
19
20
21
22
23
SDRAM_7
SDRAM_16
VDD_I
2
C
SDRAM_9
OE
SDRAM_13
SDRAM_12
VSS
VDD
28
27
26
VSS_I
2
C
SDRAM_17
SDRAM_8
24
SDA
25
SCL
FS6054
28-pin SOIC
1
2
3
4
5
6
7
8
VDD
SDRAM_0
SDRAM_1
VSS
VDD
SDRAM_2
VSS
SDRAM_14
SDRAM_15
VDD
9
10
11
12
13
14
31
30
SDRAM_3
VSS
CLK_IN
SDRAM_4
17
18
19
20
21
22
23
SDRAM_5
SDRAM_6
VDD_I
2
C
VDD
SDRAM_13
SDRAM_12
VSS
VDD
28
27
26
VSS_I
2
C
VSS
SDRAM_8
24
SDA
25
SCL
FS6057
15
29
16
32
SDRAM_7
SDRAM_16
SDRAM_9
SDRAM_10
SDRAM_11
32-pin SOIC
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Table 4: Byte 0 - SDRAM Control Register 0
REGISTER
BIT CLOCK
OUTPUT DESCRIPTION OUTPUT PIN
(FS6050) OUTPUT PIN
(FS6051) OUTPUT PIN
(FS6053) OUTPUT PIN
(FS6054) OUTPUT PIN
(FS6057)
7 SDRAM_7 On (1) / Off (0) Pin 18 - Pin 11 Pin 11 Pin 13
6 SDRAM_6 On (1) / Off (0) Pin 17 - Pin 10 Pin 10 Pin 12
5 SDRAM_5 On (1) / Off (0) Pin 14 - - - P in 11
4 SDRAM_4 On (1) / Off (0) Pin 13 - - - P in 10
3 SDRAM_3 On (1) / Off (0) Pin 9 Pin 7 Pin 7 Pin 7 Pin 7
2 SDRAM_2 On (1) / Off (0) Pin 8 Pin 6 Pin 6 Pin 6 Pin 6
1 SDRAM_1 On (1) / Off (0) Pin 5 Pin 3 Pin 3 Pin 3 Pin 3
0 SDRAM_0 On (1) / Off (0) Pin 4 Pin 2 Pin 2 Pin 2 Pin 2
Table 5: Byte 1 - SDRAM Control Register 1
REGISTER
BIT CLOCK
OUTPUT DESCRIPTION OUTPUT PIN
(FS6050) OUTPUT PIN
(FS6051) OUTPUT PIN
(FS6053) OUTPUT PIN
(FS6054) OUTPUT PIN
(FS6057)
15 SDRAM_15 On (1) / Off (0) Pi n 45 Pin 27 Pin 27 Pin 27 Pin 31
14 SDRAM_14 On (1) / Off (0) Pi n 44 Pin 26 Pin 26 Pin 26 Pin 30
13 SDRAM_13 On (1) / Off (0) Pi n 41 Pin 23 Pin 23 Pin 23 Pin 27
12 SDRAM_12 On (1) / Off (0) Pi n 40 Pin 22 Pin 22 Pin 22 Pin 26
11 SDRAM_11 On (1) / Off (0) Pi n 36 - - - Pin 23
10 SDRAM_10 On (1) / Off (0) Pi n 35 - - - Pin 22
9 SDRAM_9 On (1) / Off (0) Pin 32 - Pin 19 Pin 19 Pin 21
8 SDRAM_8 On (1) / Off (0) Pin 31 - Pin 18 Pin 18 Pin 20
Table 6: Byte 2 - SDRAM Control Register 2
REGISTER
BIT CLOCK
OUTPUT DESCRIPTION OUTPUT PIN
(FS6050) OUTPUT PIN
(FS6051) OUTPUT PIN
(FS6053) OUTPUT PIN
(FS6054) OUTPUT PIN
(FS6057)
23 SDRAM_17 On (1) / Off (0) Pi n 28 Pin 18 - P i n 17 -
22 SDRAM_16 On (1) / Off (0) Pi n 21 Pin 11 Pin 12 Pin 12 Pin 14
21 Reserved (set to 0) - - - - -
20 Reserved (set to 0) - - - - -
19 Reserved (set to 0) - - - - -
18 Reserved (set to 0) - - - - -
17 Reserved (set to 0) - - - - -
16 Reserved (set to 0) - - - - -
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4.0 Dual Serial Interface Control
This integrated circuit is a read/write slave device that
supports both the Inter IC Bus (I2C-bus) and the System
Management Bus (SMBus) two-wire serial interface pro-
tocols. The unique device address that is written to the
device determines whether the part expects to receive
SMBus commands or I2C commands. Since SMBus is
derived from the I2C-bus, the protocol for both bus types
is very similar.
In general, the bus has to be controlled by a master de-
vice that generates the serial clock SCL, controls bus
access, and generates the START and STOP conditions
while the d evice work s as a slave. Bo th m as ter and sl ave
can operate as a transmitter or receiver, but the master
device d eterm ines whic h m ode is ac tivated. A de vice that
sends data o nto t he bus is define d as th e tr ans mitter, and
a device receiving data as the receiver.
Bus logic levels and timing parameters noted herein fol-
low I2C-bus convention. Logic levels are based on a per-
centage of VDD. A logic-one corresponds to a nominal
voltag e of VDD, whil e a logic -zero c orrespon ds to groun d
(VSS).
4.1 Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line when the clock line is
high is interpreted by the device as a START or STOP
condition. Both I2C-bus and SMBus protocols define the
following conditions on the bus. Refer to Figure 13: Bus
Timing Data for more information.
4.1.1 Not Busy
Both the dat a (SD A) a nd clock (SCL) lin es r em ain hi gh t o
indicate the bus is not bus y.
4.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condit ion. A ll c omm ands to
the device must be preceded by a START condition.
4.1.3 STOP Data Transfer
A low to high transit ion of the SD A line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
4.1.4 Data Valid
The state of the SD A l in e r epres e nts v alid d ata if the SD A
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the data registers are filled will overflow from
the last register into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
4.1.5 Acknowledge
W hen addressed, the rece iving dev ice is r equired to g en-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The mas ter mus t signal an end of data t o t he s l ave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave m ust leave the SDA line high to allow th e mas ter to
generate a STOP condition.
4.2 Bus Operation and Commands
All programmable registers can be accessed via the bi-
directional two wire digital interface. The device accepts
the Random Register Read/Write and the Sequential
Register Read/Write I2C commands. The device also
supports the Block Read/Write SMBus commands.
4.2.1 I
2
C-bus and SMBus Device Addressing
After generating a START condition, the bus master
broadcasts a s e ve n- bit de v ice ad dr es s f o llo wed by a R/W
bit. Note tha t every dev ice on an I2C-bus or SMBus must
have a unique address to avoid bus conflicts.
For an SMBus interface, the address of the device is:
A6 A5 A4 A3 A2 A1 A0
1101001
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For an I2C-bus interface, the device can support two de-
vice addresses to per mit m ultipl e de v ices on one I2C-bus.
The A2 address bit is ignored and can be set to either a
one or a zero.
Therefore, for an I2C-bus interface the device address is:
A6 A5 A4 A3 A2 A1 A0
1011X00
4.2.2 I
2
C-bus: Random Register Write Procedure
Random write operations, as shown in Figure
7, allow the master to directly write to any
register. T o initiate a write procedure, the R/W
bit that is transmitted after the seven-bit I2C
device address is a logic-low. This indicates to the ad-
dressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is written into the slave’s address
pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the ad-
dressed register. A final acknowledge is returned by the
device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs
during a Register Write, the data that has been trans-
ferred is ignored.
4.2.3 I
2
C-bus: Random Register Read Procedure
Random read operatio ns allo w the m aster to direc tly rea d
from any register. To perform a read procedure, as
shown in Figure 8, the R/W bit that is transmitted after the
seven-bit I2C address is a logic-low, as in the Register
Write procedure. This indicates to the addressed slave
device that a register address will follow after the slave
device acknowledges its device address. The register
address is then written into the slave’s address pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
the eight- bit word. T he master does not acknowledg e the
transfer but does generate a STOP condition.
4.2.4 I
2
C-bus: Sequential Register Write Procedure
Sequential write operations, as shown in Figure 9, allow
the master to write to each register in order. The register
pointer is automatically incremented after each write. This
procedure is more efficient than the Random Register
Write if several registers must be written.
To initiate a write pr ocedure, the R/W bit that is transmit-
ted after the seven-bit I2C device address is a logic-low.
This indicates to the addressed slave device that a reg-
ister address will follow after the slave device acknowl-
edges its device address. The register address is written
into the slave’s address pointer. Following an acknowl-
edge b y the slave, the master is allowed to write data up
to the las t addressed reg ister bef ore the re gister address
pointer overflows back to the beginning address. An ac-
knowledge by the dev ic e be t ween e ac h byte of data must
occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a Sequential
Register Write.
4.2.5 I
2
C-bus: Sequential Register Read Procedure
Sequent ial read operatio ns allow the m aster to r ead from
each register in order. The register pointer is automati-
cally incremented by one after each read. This proce-
dure, as shown in Figure 10, is more efficient than the
Random Register Read if several registers must be read
from.
To perform a read procedure, the R/W bit that is trans-
mitted af ter the se ven-bit I2C addr ess is a lo gic-low, as i n
the Register Write procedure. This indicates to the ad-
dressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is then written into the slave’s ad-
dress pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
all data starting with the initial addressed register. The
register address pointer will overflow if the initial register
address is lar ger t han zero. After the las t byte of data, the
master does not acknowledge the transfer but does gen-
erate a STOP condition.
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Figure 7: Random Register Write Procedure (I2C-bus)
AA DATAW A
From bus host
to device
S REGISTER ADDRESS P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge STOP Condition
Data
Acknowledge
Acknowledge
START
Command WRITE Command
7-bit Receive
Device Address
Figure 8: Random Register Read Procedure (I2C-bus)
AR AAAWS REGISTER ADDRESS PS DEVICE ADDRESS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS DATA
Repeat START
Figure 9: Sequential Register Write Procedure (I2C-bus)
AAAWS P
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
AcknowledgeAcknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS DATA DATA DATA
Figure 10: Sequential Register Read Procedure (I2C-bus)
AWS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge READ Command
NO Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS AR A PS DEVICE ADDRESS DATA DATA
Repeat START
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SMBus
4.2.6 SMBus: Block Write
The Block Write command permits the
master to write several bytes of data to
sequentia l regis ters, start ing b y defau lt at Re gister 0. T he
Block W rite comm and, as noted in Figure 1 1, beg ins with
the seven-bit SMBus device address followed by a logic-
low R/W bit to begin a Write comm and. Following an ac-
knowledge of the SMBus address and R/W bit by the
slave device, a command code is written.
It is defined
that all eight bits of the command code must be zero (0).
After the command code of zero and an acknowledge,
the host then issues a byte count that describes the
number of data bytes to be written. According to SMBus
convention, the byte count should be a value between 0
and 32; ho wever this s lave device ignores the byte count
value.
Following an acknowledge of the byte count, data bytes
may be written starting with Register 0 and incrementing
sequentially. An acknowledge by the device between
each byte of data m ust occur bef ore the next dat a b yte is
sent.
4.2.7 SMBus: Block Read
The Block Read command, shown in Figure 12, permits
the master to read several bytes of data from sequential
registers, starting by default at Register 0. To perform a
Block Read procedure the R/W bit that is transmitted af-
ter the seven-bit SMBus address is a logic-low, as in the
Block Write procedure. The write bit resets the register
address point er to zer o. Follo wing a n acknowle dge of the
SMBus address and R/W bit by the slave device, a com-
mand c ode is writ ten.
It is def ined that a ll eight bits of the
comm and code must be zero (0).
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave SMBus ad-
dress is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read.
The slave will ac knowledge the d evice addres s, and then
will expect a byte count value (which will be ignored).
Following the byte count value, the device will take com-
mand of the bus and will transmit all the data beginning
with Register 0. After the last byte of data, the master
does not acknowledge the transfer but does generate a
STOP condition.
If the master does not want to receive all the data, the
master can not acknowledge the last data byte and then
can issue a STOP condition of the next clock.
Figure 11: Block Write (SMBus)
AAA DATA BYTE 1
WRITE Command
Acknowledge
Command Code
Acknowledge
Data
Acknowledge
Data
STOP Command
DATA BYTE N
Acknowledge
Byte Count
Acknowledge
START
Command From bus host
to device From device
to bus host
7-bit Receive
Device Address
WS DEVICE ADDRESS A A BYTE COUNT = N P
Figure 12: Block Read (SMBus)
AW AR AA
START
Command WRITE Command
Acknowledge
Command Code
Acknowledge
Data
Acknowledge
Data
STOP CommandAcknowledge
Byte Count
NO Acknowledge
Repeat START READ Command
Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
S DEVICE ADDRESS A S DEVICE ADDRESS BYTE COUNT = N ADATA BYTE 1 DATA BYTE N P
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5.0 Electrical Specifications
Table 7: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage, dc, Clock Buffers (V SS = ground) VDD VSS-0.5 7 V
Supply Voltage, dc, Serial Communications VDD_I2C VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (V I < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage res ulting in a loss of functionali ty or performance may occur if this device i s subjected t o a high-energy ele c-
trostatic discharge.
Table 8: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Supply Voltage, Clock Buffers VDD 3.3V ± 5% 3.135 3.3 3.465 V
Supply Voltage, Seri al Communications V DD_I2C 3.3V ± 5% 3.135 3.3 3.465 V
Ambient Operating Temperature Range TA070°C
Input Frequency fCLK 0 133 MHz
Output Load Capacitance CL30 pF
Serial Data Transfer Rat e Standard mode 10 100 400 kb/s
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Table 9: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall (FS6050)
Supply Current, Dynamic, with Loaded
Outputs IDD fCLK = 100MHz; VDD = 3.47V 180 360 mA
Supply Current, St atic IDDL Outputs l ow; VDD = 3.47V 0.75 3 mA
Serial Communication Inputs/Output (SDA, SCL)
High-Level Input V olt age VIH Outputs low 2.31 VDD+0.3 V
Low-Level Input V oltage VIL Outputs low VSS-0.3 0.9 V
Hysteresis Voltage * Vhys Outputs l ow 1.0 V
High-Level Input Current IIH -1 1 µA
Low-Level Input Current (pul l -up) IIL
Outputs low; VIH = 0. 4V, VDD = 3.47V.
Note: SDA requires an external pull -up to
drive the data bus. 51115
µA
Low-Level Output Sink Current (SDA) I OL VOL = 0.4V 10 25 mA
Output Enable Input (OE)
High-Level Input V olt age VIH 2.0 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
High-Level Input Current IIH -1 1 µA
Low-Level Input Current (pul l -up) IIL VIH = 0. 4V; VDD = 3.47V 10 22 30 µA
Clock Input (CLK_IN)
High-Level Input V olt age VIH 2.0 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 0.8 V
Input Leakage Current II-1 1 µA
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)
IOH min VDD = 3.135V, VO = 2.0V -54 -65
High-Level Output Sourc e Current IOH ma x VDD = 3.465V, VO = 3.135V -28 -46 mA
IOL min VDD = 3.135V, VO = 1.0V 54 69
Low-Level Output Sink Current IOL max VDD = 3.465V, VO = 0.4V 33 53 mA
zOH VO = 0.5VDD; output driving high 10 17. 9 24
Output Impedance zOL VO = 0.5VDD; output driving low 10 16.3 24 Ω
Tristate Output Current IOZ -5 5 µA
Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -106 mA
Short Circuit S i nk Current * IOSL VO = 3.3V; shorted for 30s, max. 107 mA
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Table 10: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK
(MHz) MIN. TYP. MAX. UNITS
Overall
66.67 182
Clock Skew, Maximum;
SDRAM_0 to any SDRAM pin * tskw Measured on the rising edge at 1.5V;
CL = 20pF 100 228 ps
66.67 3.7
tPLH(min) Measured on the rising edge at 1.5V;
CL = 20pF 100 3.8
66.67 3.7
tPLH(max) Measured on the rising edge at 1.5V;
CL = 30pF 100 4.0
66.67 3.9
tPHL(min) Measured on the ris i ng edge at 1.5V;
CL = 20pF 100 3.8
66.67 4.2
Propagation Dela y, Average;
CLK_IN to any SDRAM pin *
tPHL(max) Measured on the rising edge at 1.5V;
CL = 30pF 100 4.0
ns
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)
66.67 1.0
tr(min) VO = 0.4V to 2.4V; CL = 20pF 100 0.9
66.67 1.2
Rise Time * tr(max) VO = 0.4V to 2.4V; CL = 30pF 100 1.0
ns
66.67 1.0
tf(min) VO = 2.4V to 0.4V; CL = 20pF 100 0.7
66.67 1.1
Fall Time * tf(max) VO = 2.4V to 0.4V; CL = 30pF 100 0.8
ns
66.67 6.5
tKH(min) VO = 2.4V; CL = 20pF 100 3.8
66.67 6.5
Clock High Tim e * tKH(max) VO = 2.4V; CL = 30pF 100 3.8
ns
66.67 6.5
tKL(min) VO = 0.4V; CL = 20pF 100 4.6
66.67 6.3
Clock Low Time * tKL(max) VO = 0.4V; CL = 30pF 100 4.5
ns
66.67 49
From rising edge to rising edge at
1.5V; CL = 20pF 100 45
66.67 50
Duty Cycle * From rising edge to rising edge at
1.5V; CL = 30pF 100 46
%
tPZL 4.7
Tristate Enable Delay * tPZH Output tristated to output active; CL = 20pF 4.6 ns
tPLZ 6.3
Tristate Disable Delay * tPHZ Output active to output tristated; CL = 20pF 7.9 ns
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Table 11: Serial Interface Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. MAX. UNITS
Clock frequency fSCL SCL 10 400 kHz
Bus free time between STOP and START tBUF 4.7 µs
Set up time, START (repeated) tsu:STA 4.7 µs
Hold time, START thd:STA 4.0 µs
Set up time, data input tsu:DAT SDA 250 ns
Hold time, data input thd:DAT SDA 300 ns
Output data valid from clock tAA Minimum delay to bridge undefined region of t he fall -
ing edge of SCL to avoid unintended START or STOP 3.5 µs
Rise time, dat a and clock trSDA, SCL 1000 ns
Fall time, data and clock tfSDA, SCL 300 ns
High time, clock tHSCL 4.0 µs
Low time, clock tLSCL 4.7 µs
Set up time, STOP tsu:STO 4.0 µs
Figure 13: Bus Timing Data
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 14: Data Transfer Sequence
SCL
SDA
IN
t
hd:DAT
~
~
t
hd:STA
t
su:STA
t
su:STO
t
L
t
H
SDA
OUT
t
su:DAT
~
~~
~
t
BUF
t
r
t
f
t
AA
t
AA
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Figure 15: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer)
Low Drive Current (mA) High Drive Curren t (mA)
Voltage
(V) MIN. TYP. MAX.
Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -72 -116 -198
0.4 23 34 53 1 -72 -116 -198
0.65 35 52 83 1.4 -68 -110 -188
0.85 43 65 104 1.5 -67 -107 -184
1 49 74 118 1.65 -64 -103 -177
1.4 61 93 152 1.8 -60 -98 -170
1.5 64 98 159 2 -54 -90 -157
1.65 67 103 168 2.4 -39 -69 -126
1.8 70 108 177 2.6 -30 -56 -107
1.95 72 112 184 3.135 0 -15 -46
3.135 72 112 204 3.3 0 -23
3.6 112 204 3.465 0
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
220
00.511.522.533.54
2XWSXW9ROWDJH9
2
X
W
S
X
W
&
X
U
U
H
Q
W
P
$
MIN.
TYP.
MAX.
30 Ω
50 Ω
90 Ω
Figure 16: DC Measurement Points
V
IH 3.3
= 2.0V
V
IL 3.3
= 0.8V
V
OL 3.3
= 0.4V
V
OH 3.3
= 2.4V
1.5V
3.3V
(device
interface) (system
interface)
Figure 17: Clock Skew Measurement Point
t
skw
3.3V
3.3V
1.5V
1.5V
Figure 18: Timing Measurement Points
t
KH
t
r
Duty Cycle
t
KL
τ
KP
2.4V
1.5V
0.4V
t
f
t
PLZ
V
OL
V
OH
V
SS
V
DD
10%
90%
t
PHZ
50% 50%
50%
50%
t
PZL
t
PHZ
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6.0 Package Information
Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.095 0.110 2.41 2.79
A10.008 0.016 0.203 0.406
A20.088 0.092 2.24 2.34
B 0.008 0.0135 0.203 0.343
C 0.005 0.010 0.127 0.254
D 0.620 0.630 15.75 16.00
E 0.292 0.299 7.42 7.59
e 0.025 BSC 0.64 BSC
H 0.400 0.410 10.16 10.41
h 0.010 0.016 0.254 0.410
L 0.024 0.040 0.610 1.02
Θ0°8°0°8°
Be
DA
1
SEATING PLANE
HE
48
1ALL RADII:
0.005" TO 0.01"
BASE PLANE
A
2
XT
C
L
7° typ.
θ
A
Table 13: 48-pin SSOP (7.5mm/0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 93 °C/W
Lead Inductance, S elf L11 Center lead 3.3 nH
Lead Inductance, Mutual L12 Center lead to any adjacent lead 1.6 nH
Lead Capacitance, Bulk C11 Center lead to VSS 0.6 pF
Lead Capacitance, Mutual C12 Center l ead to any adjacent lead 0.2 pF
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Table 14: 28-pin SOIC (7.5mm/0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.093 0.104 2.35 2.65
A10.004 0.012 0.10 0.30
A20.08 0.100 2.05 2.55
B 0.013 0.013 0.33 0.51
C 0.009 0.009 0.23 0.32
D 0.697 0.713 17.70 18.10
E 0.291 0.299 7.40 7.60
e 0.05 BSC 1.27 BSC
H 0.393 0.419 10.00 10.65
h 0.010 0.030 0.25 0.75
L 0.016 0.05 0.40 1.27
Θ0°8°0°8°
Be
DA
1
SEATING PLANE
HE
28
1ALL RADII:
0.005" TO 0.01"
BASE PLANE
A
2
XT
C
L
7° typ.
θ
A
h x 45°
Table 15: 28-pin SOIC (7.5mm/0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 80 °C/W
Lead Inductance, S elf L11 Center lead 2.5 nH
Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.85 nH
Lead Capacitance, Bulk C11 Center lead to VSS 0.42 pF
Lead Capacitance, Mutual C12 Center l ead to any adjacent lead 0.08 pF
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Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.068 0.078 1.73 2.00
A10.002 0.008 0.05 0.21
A20.066 0.07 1.68 1.78
B 0.01 0.015 0.25 0.38
C 0.005 0.008 0.13 0.20
D 0.396 0.407 10.07 10.33
E 0.205 0.212 5.20 5.38
e 0.028 BSC 0.65 BSC
H 0.301 0.311 7.65 7.90
L 0.022 0.037 0.55 0.95
Θ0°8°0°8°
HE
ALL RADII:
0.005" TO 0.01"
XT
1
28
Be
DA
1
SEATING PLANEBASE PLANE
A
2
AC
L
7° typ.
θ
Table 17: 28-pin SSOP (5.3mm/0.209") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 97 °C/W
Lead Inductance, S elf L11 Center lead 2.24 nH
Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.95 nH
Lead Capacitance, Bulk C11 Center lead to VSS 0.25 pF
Lead Capacitance, Mutual C12 Center l ead to any adjacent lead 0.07 pF
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Table 18: 32-pin SOIC (7.5mm/0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.090 0.100 2.29 2.54
A10.004 0.010 0.10 0.25
A20.086 0.090 2.18 2.29
B 0.014 0.020 0.36 0.51
C 0.006 0.012 0.15 0.32
D 0.810 0.822 20.57 20.88
E 0.292 0.299 7.42 7.60
e 0.05 BSC 1.27 BSC
H 0.405 0.419 10.29 10.64
h 0.010 0.030 0.25 0.75
L 0.021 0.041 0.53 1.04
Θ0°8°0°8°
Be
DA
1
SEATING PLANE
HE
32
1ALL RADII:
0.005" TO 0.0 1"
BASE PLANE
A
2
XT
C
L
7° typ.
θ
A
h x 45°
Table 19: 32-pin SOIC (7.5mm/0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 83 °C/W
Lead Inductance, S elf L11 Center lead 2.5 nH
Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.85 nH
Lead Capacitance, Bulk C11 Center lead to VSS 0.42 pF
Lead Capacitance, Mutual C12 Center l ead to any adjacent lead 0.08 pF
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7.0 Ordering Information
ORDERING CODE DEVICE
NUMBER FONT PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11257-801 FS6050 48-pin (7.5mm/0.300”) SSOP 0°C to 70°C (Commercial) Tape and Reel
11257-811 FS6050 48-pin (7.5mm/0.300”) SSOP 0°C to 70°C (Commercial) Tube
11257-802 FS6051 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel
11257-812 FS6051 28-pin (7.5mm/0.209”) SOIC 0°C to 70°C (Commercial) Tube
11257-806 FS6051 28-pin (5.3mm/0.209”) SSOP 0°C to 70°C (Commercial) Tape and Reel
11257-816 FS6051 28-pin (5.3mm/0.200”) SSOP 0°C to 70°C (Commercial) Tube
11257-803 FS6053 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel
11257-813 FS6053 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tube
11257-804 FS6054 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel
11257-814 FS6054 28-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tube
11257-805 FS6057 32-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tape and Reel
11257-815 FS6057 32-pin (7.5mm/0.300”) SOIC 0°C to 70°C (Commercial) Tube
Purchase of I2C components of American Mi crosystems, Inc., or one of its sublicensed Associated Companies conveys
a license under Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms
to the I2C Standard Specifi cat ion as defi ned by Philips.
Copyright © 1998 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Add ress:
http://www.amis.co
m
E-mail:
t
g
p@amis.co
m
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8.0 Application Information
8.1 Reduction of EMI
The prim ary concern whe n designin g the boar d la yout for
this device is the reduction of electromagnetic interfer-
ence (EMI) generated by the 18 copies of the 100MHz
SDRAM clock. It is assumed the reader is familiar with
basic transmission line theory.
8.1.1 Layout Guidelines
To obtain the best performance, noise should be mini-
mized on the power and ground supplies to the IC. Ob-
serve good high-speed board design practices, such as:
Use multi-layer circuit boards with dedicated low im-
pedance power and ground planes for the device
(denoted as CLK VDD and CLK GND in Figure 19).
The device power and ground planes should be
completely isolated from the motherboard power and
ground planes by a void in the power planes.
Several low-pass filters using low impedance ferrite
EHDGV DW 0+] DUH UHFRPPHQGHG WR GHFRu-
ple the device power and ground planes from the
mother board power and gr o un d p lan es ( MB VDD an d
MB GND). The beads should span the gap between
the power and ground planes. Seven beads for
power and seven beads for ground are suggested
(14 total) so that the clock rise times (1V/ns) can be
maintained.
Place 10 00pF b ypass c apacitors as c lose as pos si ble
to the power pins of the IC. Use RF-quality low-
inductance multi-layer ceramic chip capacitors. Six
capacitors is optimal, one on each power/ground
grouping as shown in Figure 19.
Load similar clock outputs equally, and keep output
loadin g as lig ht as pos s ib le t o h elp reduce c loc k sk ew
and power dissip ati on.
Use equal-length clock traces that are as short as
possible. Rounded trace corners help reduce reflec-
tions and ringing in the clock signal.
The clock traces must never cross the void area be-
tween power/ground planes. Each trace must have a
complete plane (either VDD or GND) under the com -
plete length of the trace.
Figure 19: Board Layout
1
2
4
5
8
9
11
13
14
17
18
21
48
45
41
40
36
28
25
47
MB GND
MB VDD
31
32
44
35
38
24
CLK GND
CLK VDD
VOID
R
S
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
CLK GND
CLK VDD
MB GNDMB GND
MB VDD MB VDD
Signal Layer
Component
Layer
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
8.1.2 Output Driver Termination
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applica-
tions, such as an increase in clock jitter and a rise in
electrom agnetic emissions from the board. Using a prop-
erly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflec-
tions.
Figure 20: Series Termination
R
S
z
L
z
O
DRIVER RECEIVE
LINE
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Januar y 1999
1.13.99
20
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,62
Series termination adds no dc loading to the driver, and
requires less power than other resistive termination
methods. Further, no extra impedance exists from the
signal line to a reference voltage, such as ground.
As shown in Figure 20, the sum of the driver’s output im -
pedance (zO) and the series termination resistance (RS)
must equal the line impedance (zL). That is,
OLS zzR −= .
Note that when the source impedance (zO+RS) is
matched to the line impedance, then by voltage division
the incident wave amplitude is one-half of the full signal
amplitude.
2)( )( V
zRz Rz
VV
LSO
SO
i=
++ +
=
The f ull signal am plitude m ay tak e up to twice as long as
the propagation delay of the line to develop, reducing
noise immunity during the half-amplitude period. Note
also that the volta ge at the receive end m ust add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal is also reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also note that the output driver
impedance will vary slightly with the output logic state
(high or low).
8.2 Dynamic Power Dissipation
High-speed clock drivers require careful attention to
power dissip ation. Transient power (PT) co nsumption c an
be derived from
SWCLKloadDDTNfCVP ×××= 2
where Cload is the load capacitance, VDD is the supply
voltage, fCLK is the clock frequency, and Nsw is the
number of switching outputs.
The internal heat (junction tem perature, TJ) generated b y
the power dissipation can be calculated from
ATJAJ TPT +×Θ=
where ΘJA is the package thermal resistance, TA is the
ambient temperature, and PT is der iv ed abo ve.
8.3 Serial Communications
Connection of devices to a standard-mode implementa-
tion of either the I2C-bus or the SMBus is similar to that
shown in F igure 21. Se lect ion of the p ull-up r esist ors (RP)
and the optional series resistors (RS) on the SDA and
SCL lines depends on the supply voltage, the bus ca-
pacitance, and the number of connected devices with
their associated input currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines. A guideline is
bus
r
PC
t
R×
<2,
where tr is the maximum rise time (minus some margin)
and Cbus is the total bus capacitance. Assuming an I2C
device on each DIMM, an I2C controller, the clock buffer,
and two o ther bus dev ices results in values in the 5kΩ to
7kΩ range. Use of a series resistor to provide protection
against high voltage spikes on the bus will alter the val-
ues for RP.
Figure 21: Connections to the Serial Bus
R
P
SDA
SCL
Data In
Data Out
Clock Out
TRANSMITTER
Data In
Data Out
RECEIVER
Clock In
R
P
R
S
(optional)
R
S
(optional)
R
S
(optional)
R
S
(optional)
8.3.1 For More Information
More detailed information on serial bus design can be
obtained f r om SMBus an d I2C Bus Design
,
avail able fr om
the Intel Corporation at
http://www.intel.com.
Inform ation on the I2C-bus can be found in the document
The I2C-bus And How To Use It (Including Specifica-
tions), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com.
Additional information on the System Management Bus
can be found in the System Management Bus Specifica-
tion, available from the Smart Battery System
Implementers’ Forum at
http://www.sbs-forum.org.
