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LM2664
SNVS005E –NOVEMBER 1999–REVISED DECEMBER 2014
LM2664 Switched Capacitor Voltage Converter
1 Features 3 Description
The LM2664 CMOS charge-pump voltage converter
1• Inverts Input Supply Voltage inverts a positive voltage in the range of 1.8 V to 5.5
• 6-Pin SOT-23 Package V to the corresponding negative voltage of −1.8 V to
• 12-ΩTypical Output Impedance −5.5 V. The device uses two low-cost capacitors to
provide up to 40 mA of output current.
• 91% Typical Conversion Efficiency at 40 mA
• 1-µA Typical Shutdown Current The LM2664 operates at 160-kHz oscillator frequency
to reduce output resistance and voltage ripple. With
an operating current of only 220 µA (operating
2 Applications efficiency greater than 91% with most loads) and 1-
• Cellular Phones µA typical shutdown current, the LM2664 provides
• Pagers ideal performance for battery-powered systems.
• PDAs Device Information(1)
• Operational Amplifier Power Suppliers PART NUMBER PACKAGE BODY SIZE (NOM)
• Interface Power Suppliers LM2664 SOT-23 (6) 2.90 mm x 1.60 mm
• Handheld Instruments (1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
space
Voltage Inverter
5 V to −10 V Converter
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2664
SNVS005E –NOVEMBER 1999–REVISED DECEMBER 2014
www.ti.com
Table of Contents
8.2 Functional Block Diagram......................................... 8
1 Features.................................................................. 18.3 Feature Description................................................... 8
2 Applications ........................................................... 18.4 Device Functional Modes.......................................... 8
3 Description............................................................. 19 Application and Implementation .......................... 9
4 Revision History..................................................... 29.1 Application Information.............................................. 9
5 Pin Configuration and Functions......................... 39.2 Typical Application - Voltage Inverter ....................... 9
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 13
6.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 13
6.2 Handling Ratings....................................................... 411.1 Layout Guidelines ................................................. 13
6.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 13
6.4 Thermal Information.................................................. 412 Device and Documentation Support................. 14
6.5 Electrical Characteristics........................................... 512.1 Device Support...................................................... 14
6.6 Typical Characteristics ............................................. 612.2 Trademarks........................................................... 14
7 Parameter Measurement Information .................. 712.3 Electrostatic Discharge Caution............................ 14
7.1 Test Circuit................................................................ 712.4 Glossary................................................................ 14
8 Detailed Description.............................................. 813 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 8Information........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2013) to Revision E Page
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision C (May 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 11
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SNVS005E –NOVEMBER 1999–REVISED DECEMBER 2014
5 Pin Configuration and Functions
SOT-23 (DBV)
6 Pins
Top View
Pin Functions
PIN TYPE DESCRIPTION
NUMBER NAME
1 GND Ground Power supply ground input.
2 OUT Power Negative voltage output.
3 CAP−Power Connect this pin to the negative terminal of the charge-pump capacitor.
4 SD Input Shutdown control pin, tie this pin to V+ in normal operation, and to GND for shutdown.
5 V+ Power Power supply positive voltage input.
6 CAP+ Power Connect this pin to the positive terminal of the charge-pump capacitor.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply voltage (V+ to GND, or GND to OUT) 5.8 V
SD (GND −0.3) (V+ + 0.3) V
V+ and OUT continuous output current 50 mA
Output short-circuit duration to GND(3) 1 sec.
Continuous power dissipation (TA= 25°C)(4) 600 mW
TJMax(4) 150 °C
Lead temp. (soldering, 10 seconds) 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be
avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged.
(4) The maximum allowable power dissipation is calculated by using PDMax = (TJMax −TA)/RθJA, where TJMax is the maximum junction
temperature, TAis the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000
V(ESD) V
discharge pins(1)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Operating junction temperature –40 85 °C
6.4 Thermal Information LM2664
THERMAL METRIC(1) DBV UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 210 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating temperature range. Unless otherwise specified: TJ= 25°C, V+ = 5 V, C1= C2
= 3.3 μF.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
V+ Supply voltage 1.8 5.5 V
IQSupply current No load 220 500 µA
ISD Shutdown supply current 1 µA
VSD Shutdown pin input voltage Normal operation 2(4) V
Shutdown mode 0.8(5)
ILOutput current 40 mA
RSW Sum of the Rds(on)of the four internal IL= 40 mA 4 8 Ω
MOSFET switches
ROUT Output resistance(6) IL= 40 mA 12 25 Ω
fOSC Oscillator frequency See(7) 80 160 kHz
fSW Switching frequency See(7) 40 80 kHz
PEFF Power efficiency RL(1 k) between GND and OUT 90% 94%
IL= 40 mA to GND 91%
VOEFF Voltage conversion efficiency No load 99% 99.96%
(1) In the test circuit, capacitors C1and C2are 3.3-µF, 0.3-Ωmaximum ESR capacitors. Capacitors with higher ESR will increase output
resistance, reduce output voltage and efficiency.
(2) Min. and Max. limits are ensured by design, test, or statistical analysis.
(3) Typical numbers are not ensured but represent the most likely norm.
(4) The minimum input high for the shutdown pin equals 40% of V+.
(5) The maximum input low for the shutdown pin equals 20% of V+.
(6) Specified output resistance includes internal switch resistance and capacitor ESR. See the details in Application and Implementation for
simple negative voltage converter.
(7) The output switches operate at one half of the oscillator frequency, ƒOSC = 2ƒSW.
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6.6 Typical Characteristics
(Circuit of Figure 9 V+ = 5 V unless otherwise specified)
Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs Temperature
Figure 3. Output Source Resistance vs Supply Voltage Figure 4. Output Source Resistance vs Temperature
Figure 5. Output Voltage Drop vs Load Current Figure 6. Oscillator Frequency vs Supply Voltage
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Typical Characteristics (continued)
(Circuit of Figure 9 V+ = 5 V unless otherwise specified)
Figure 7. Oscillator Frequency vs Temperature Figure 8. Shutdown Supply Current vs Temperature
7 Parameter Measurement Information
7.1 Test Circuit
*C1and C2are 3.3 µF, SC series OS-CON capacitors.
Figure 9. LM2664 Test Circuit
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SD
V+
CAP+
OUT
GND
OSCILLATOR Switch Array
Switch Drivers CAP-
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SNVS005E –NOVEMBER 1999–REVISED DECEMBER 2014
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8 Detailed Description
8.1 Overview
The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to
the corresponding negative voltage of −1.8 V to −5.5 V. The LM2664 uses two low-cost capacitors to provide up
to 40 mA of output current.
8.2 Functional Block Diagram
8.3 Feature Description
The LM2664 contains four large CMOS switches which are switched in a sequence to invert the input supply
voltage. Energy transfer and storage are provided by external capacitors. Figure 10 illustrates the voltage
conversion scheme. When S1and S3are closed, C1charges to the supply voltage V+. During this time interval,
switches S2and S4are open. In the second time interval, S1and S3are open; at the same time, S2and S4are
closed, C1is charging C2. After a number of cycles, the voltage across C2will be pumped to V+. Since the anode
of C2is connected to ground, the output at the cathode of C2equals −(V+) when there is no load current. The
output voltage drop when a load is added is determined by the parasitic resistance (Rds(on) of the MOSFET
switches and the ESR of the capacitors) and the charge transfer loss between capacitors. Details will be
discussed in the following application information section.
Figure 10. Voltage Inverting Principle
8.4 Device Functional Modes
8.4.1 Shutdown Mode
A shutdown (SD) pin is available to disable the device and reduce the quiescent current to 1 µA. Applying a
voltage less than 20% of V+ to the SD pin will bring the device into shutdown mode. While in normal operating
mode, the pin is connected to V+.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to
the corresponding negative voltage of −1.8 V to −5.5 V. The LM2664 uses two low cost capacitors to provide up
to 40 mA of output current. The LM2664 operates at 160-kHz oscillator frequency to reduce output resistance
and voltage ripple. With an operating current of only 220 µA (operating efficiency greater than 91% with most
loads) and 1 µA typical shutdown current, the LM2664 provides ideal performance for battery powered systems.
9.2 Typical Application - Voltage Inverter
Figure 11. Voltage Inverter
9.2.1 Design Requirements
Example requirements for typical voltage inverter applications:
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 1.8 V to 5.5 V
Output current 0 mA to 40 mA
Boost switching frequency 80 kHz
9.2.2 Detailed Design Requirements
The main application of LM2664 is to generate a negative supply voltage. The voltage inverter circuit uses only
two external capacitors as shown in Voltage Inverter and 5 V to −10 V Converter. The range of the input supply
voltage is 1.8 V to 5.5 V.
The output characteristics of this circuit can be approximated by an ideal voltage source in series with a
resistance. The voltage source equals −(V+). The output resistance ROUT is a function of the ON resistance of the
internal MOSFET switches, the oscillator frequency, the capacitance and equivalent series resistance (ESR) of
C1and C2. Since the switching current charging and discharging C1is approximately twice as the output current,
the effect of the ESR of the pumping capacitor C1will be multiplied by four in the output resistance. The output
capacitor C2is charging and discharging at a current approximately equal to the output current, therefore, its
ESR only counts once in the output resistance. A good approximation of ROUT is:
where
• RSW is the sum of the ON resistance of the internal MOSFET switches shown in Figure 10. (1)
High capacitance, low ESR capacitors will reduce the output resistance.
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The peak-to-peak output voltage ripple is determined by the oscillator frequency, the capacitance and ESR of the
output capacitor C2:
(2)
Again, using a low ESR capacitor will result in lower ripple.
9.2.2.1 Paralleling Devices
Any number of LM2664s can be paralleled to reduce the output resistance. Each device must have its own
pumping capacitor C1, while only one output capacitor COUT is needed as shown in Figure 12. The composite
output resistance is:
(3)
Figure 12. Lowering Output Resistance by Paralleling Devices
9.2.2.2 Cascading Devices
Cascading the LM2664 devices is an easy way to produce a greater negative voltage (a two-stage cascade
circuit is shown in Figure 13).
If n is the integer representing the number of devices cascaded, the unloaded output voltage Vout is (-nVin). The
effective output resistance is equal to the weighted sum of each individual device:
ROUT = nRout_1 + n/2 ROUT_2 + ... + ROUT_n (4)
NOTE
The number of n is practically limited since the increasing of n significantly reduces the
efficiency, and increases the output resistance and output voltage ripple.
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Figure 13. Increasing Output Voltage by Cascading Devices
9.2.2.3 Combined Doubler and Inverter
In Figure 14, the LM2664 is used to provide a positive voltage doubler and a negative voltage converter. Note
that the total current drawn from the two outputs should not exceed 50 mA.
Figure 14. Combined Voltage Doubler and Inverter
9.2.2.4 Regulating VOUT
It is possible to regulate the negative output of the LM2664 by use of a low dropout regulator (such as LP2980).
The whole converter is depicted in Figure 15. This converter can give a regulated output from −1.8 V to −5.5 V
by choosing the proper resistor ratio:
VOUT = Vref (1 + R1/R2) (5)
where, Vref = 1.23 V (6)
Note that the following conditions must be satisfied simultaneously for worst case design:
Vin_min > Vout_min + Vdrop_max (LP2980) (7)
+ Iout_max × Rout_max (LM2664) (8)
Vin_max < Vout_max + Vdrop_min (LP2980) (9)
+ Iout_min × Rout_min (LM2664) (10)
space
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Figure 15. Combining LM2664 with LP2980 to Make a Negative Adjustable Regulator
9.2.2.5 Output Capacitor Selection
As discussed in Detailed Design Requirements, the output resistance and ripple voltage are dependent on the
capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the
output resistance, and the power efficiency is
(11)
Where IQ(V+) is the quiescent power loss of the IC device, and IL2ROUT is the conversion loss associated with the
switch on-resistance, the two external capacitors and their ESRs.
The selection of capacitors is based on the specifications of the dropout voltage (which equals Iout ROUT), the
output voltage ripple, and the converter efficiency. Table 1 lists recommendations to maximize efficiency, reduce
the output voltage drop and voltage ripple.
Table 1. Low ESR Capacitor Manufacturers
MANUFACTURER CAPACITOR TYPE
Nichicon Corp. PL & PF series, through-hole aluminum electrolytic
AVX Corp. TPS series, surface-mount tantalum
Sprague 593D, 594D, 595D series, surface-mount tantalum
Sanyo OS-CON series, through-hole aluminum electrolytic
Murata Ceramic chip capacitors
Taiyo Yuden Ceramic chip capacitors
Tokin Ceramic chip capacitors
9.2.3 Application Curve
Figure 16. Efficiency vs Load Current
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OUT
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CAP+
V+
SD
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10 Power Supply Recommendations
The LM2664 is designed to operate from as an inverter over an input voltage supply range between 1.8 V and
5.5 V when the LV pin is grounded. This input supply must be well regulated and capable to supply the required
input current. If the input supply is located far from the LM2664 additional bulk capacitance may be required in
addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
The high switching frequency and large switching currents of the LM2664 make the choice of layout important.
The following steps should be used as a reference to ensure the device is stable and maintains proper LED
current regulation across its intended operating voltage and current range
• Place CIN on the top layer (same layer as the LM2664) and as close to the device as possible. Connecting
the input capacitor through short, wide traces to both the V+ and GND pins reduces the inductive voltage
spikes that occur during switching which can corrupt the V+ line
• Place COUT on the top layer (same layer as the LM2664) and as close as possible to the OUT and GND pin.
The returns for both CIN and COUT should come together at one point, as close to the GND pin as possible.
Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can
corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
• Place C1 on the top layer (same layer as the LM2664) and as close to the device as possible. Connect the
flying capacitor through short, wide traces to both the CAP+ and CAP– pins.
11.2 Layout Example
Figure 17. LM2664 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2664M6 NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 85 S03A
LM2664M6/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 S03A
LM2664M6X/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 S03A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM2664M6 SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM2664M6/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM2664M6X/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2664M6 SOT-23 DBV 6 1000 210.0 185.0 35.0
LM2664M6/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0
LM2664M6X/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/B 03/2018
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
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EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
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