74AC540SCX_NL - Fairchild Semiconductor

November 1988

Revised March 2005

74AC540 Octal Buffer/Line Driver with 3-STATE Outputs

74AC540

Octal Buffer/Line Driver with 3-STATE Outputs

General Descript ion

The AC540 is an octal buffer/line drivers designed to be

employed as memory and address drivers, clock drivers

and bus oriented transmitter/receivers.

These devices are similar in function to the AC240 while

providing flow-through architecture (inputs on opposite side

from outputs). This pinout arrangement makes these

devices especially useful as output ports for microproces-

sors, allowing ease of layout and greater PC board density.

Features

■ICC and IOZ reduced by 50%

■3-STATE inverting outputs

■Inputs and outputs opposite side of package, allowing

easier interface to microprocessors

■Output source/sink 24 mA

Ordering Code:

Device a l s o av ailable in Tape and R eel. Specify by appending su ffix le t ter “X” to th e ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Connection Diagram

Truth Table

HIGH Volt age Level X

Immaterial

LOW Voltage Level Z

High Impeda nc e

FACT

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC540SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC540SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II , 5.3mm Wide

74AC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC540PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Inputs Outputs

OE1OE2I

LLH L

HXX Z

XHX Z

LLL H

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74AC540

Absolute Maximum Ratings(N o te 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exc eption, to e nsure that the system des ign is reliabl e over its power

supply, temperatu re, and output /input lo ading variable s. Fairch ild do es not

recomm end operation of FACT

circuits outside databo ok s pecificat ions.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.

Note 4: IIN and ICC @ 3.0V are guara nt eed to be les s th an or equa l to th e respect iv e limit @ 5. 5V VCC.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current (IIK)



0.5V



20 mA

VCC



0.5V



20 mA

DC Input Voltage (VI)



0.5V to VCC



0.5V

DC Output Diode Current (IOK)



0.5V



20 mA

VCC



0.5V



20 mA

DC O utput Voltage ( VO)



0.5V to VCC



0.5V

DC Output Source

or Sink Current (IO)

50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)

50 mA

Storage Temperature (TSTG)



C to



150

Junction Temperature (TJ)

PDIP 140

Supply Voltage (VCC) 2.0V to 6.0V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Operating Temperature (TA)



C to



Minimum Input Edge Rate (

t) 125 mV/ns

VIN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5V

Symbol Parameter VCC TA





C to



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT

0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC



0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT

0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC



0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V IOUT



5.5 5.49 5.4 5.4 VIN

VIL or VIH

3.0 2.56 2.46 IOH



12 mA

4.5 3.86 3.76 V IOH



24 mA

5.5 4.86 4.76 IOH



24 mA (Note 2)

VOL Maximum LOW Level 3.0 0.002 0 .1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V IOUT

5.5 0.001 0.1 0.1 VIN

VIL or VIH

3.0 0.36 0.44 IOL

12 mA

4.5 0.36 0.44 V IOL

24 mA

5.5 0.36 0.44 IOL

24 mA (Note 2)

IIN Maximum Input 5.5

0.1

1.0

VCC, GND

(Note 4) Leakage Current

IOZ Maximum 3-STATE VI (OE)

VIL, VIH

Current 5.5

0.25

2.5

VCC, GND

IOLD Minimum Dynamic 5.5 75 mA VOLD

1.65V Max

IOHD Output Current (Note 3) 5.5



75 mA VOHD

3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0

VCC

(Note 4) Supply Current or GND

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74AC540

AC Electrical Characteristics

Note 5: Voltag e R ange 3.3 is 3. 3V

0.3V

Voltage Range 5.0 is 5.0V

0.5V

Capacitance

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 5) Min Typ Max Min Max

tPLH Propagation Delay 3.3 1.5 5.5 7.5 1.0 8.0 ns

Data to Output 5.0 1.5 4.0 6.0 1.0 6.5

tPHL Propagation Delay 3.3 1.5 5.0 7.0 1.0 7.5 ns

Data to Output 5.0 1.5 4.0 5.5 1.0 6.0

tPZH Output Enable Time 3.3 3.0 8.5 11.0 2.5 12.0 ns

5.0 2.0 6.5 8.5 2.0 9.5

tPZL Output Enable Time 3.3 2.5 7.5 10.0 2.0 11.0 ns

5.0 2.0 6.0 7.5 1.5 8.5

tPHZ Output Disable Time 3.3 2.5 8.5 13.0 1.5 14.0 ns

5.0 1.5 7.5 10.5 1.0 11.0

tPLZ Output Disable Time 3.3 2.5 7.0 10.0 2.0 11.0 ns

5.0 1.5 6.0 8.0 1.5 9.0

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC

OPEN

CPD Power Dissipation Capacitance 30.0 pF VCC

5.0V

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74AC540

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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74AC540

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74AC540

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

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74AC540 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided i n the labe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.