Revised March 2005 74AC540 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The AC540 is an octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. ICC and IOZ reduced by 50% These devices are similar in function to the AC240 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density. 3-STATE inverting outputs Inputs and outputs opposite side of package, allowing easier interface to microprocessors Output source/sink 24 mA Ordering Code: Order Number Package Number 74AC540SC 74AC540SJ 74AC540MTC 74AC540PC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC Truth Table Inputs OE1 Outputs OE2 I L L H L H X X Z X H X Z L L L H H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance FACT is a trademark of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation Ds009966 www.fairchildsemi.com 74AC540 Octal Buffer/Line Driver with 3-STATE Outputs November 1988 74AC540 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions 0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI 0.5V VCC 0.5V DC Input Voltage (VI) Supply Voltage (VCC) 20 mA 20 mA 0.5V to VCC 0.5V VO 0.5V VCC 0.5V DC Output Voltage (VO) 0V to VCC Output Voltage (VO) 0V to VCC 40qC to 85qC Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) DC Output Diode Current (IOK) VO 2.0V to 6.0V Input Voltage (VI) 20 mA 20 mA 0.5V to VCC 0.5V 125 mV/ns VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V DC Output Source r50 mA or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) r50 mA 65qC to 150qC Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Junction Temperature (TJ) 140qC PDIP DC Electrical Characteristics Symbol Parameter VCC (V) VIH VIL VOH VOL TA 25qC Typ TA 40q C to 85qC Units Conditions Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 VOUT V 0.1V or VCC 0.1V VOUT 0.1V V or VCC 0.1V V IOUT V 50 PA VIN VIL or VIH IOH 12 mA IOH 24 mA IOH 24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 r0.1 r1.0 PA VI Current 5.5 r0.25 r2.5 PA VI IOLD Minimum Dynamic 5.5 75 mA VOLD IOHD Output Current (Note 3) 5.5 75 mA VOHD ICC Maximum Quiescent 5.5 40.0 PA VIN (Note 4) Supply Current IIN Maximum Input (Note 4) Leakage Current IOZ Maximum 3-STATE V V 50 PA IOUT VIN VIL or VIH IOL 12 mA IOL 24 mA IOL 24 mA (Note 2) VCC, GND VI (OE) VO 4.0 Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com VCC, GND 1.65V Max 3.85V Min VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. 2 VIL, VIH VCC, GND Symbol Parameter VCC TA 25qC (V) CL 50 pF (Note 5) tPLH tPHL tPZH tPZL Max Min 50 pF 3.3 1.5 5.5 7.5 1.0 8.0 5.0 1.5 4.0 6.0 1.0 6.5 Propagation Delay 3.3 1.5 5.0 7.0 1.0 7.5 Data to Output 5.0 1.5 4.0 5.5 1.0 6.0 Output Enable Time 3.3 3.0 8.5 11.0 2.5 12.0 5.0 2.0 6.5 8.5 2.0 9.5 3.3 2.5 7.5 10.0 2.0 11.0 5.0 2.0 6.0 7.5 1.5 8.5 3.3 2.5 8.5 13.0 1.5 14.0 5.0 1.5 7.5 10.5 1.0 11.0 3.3 2.5 7.0 10.0 2.0 11.0 5.0 1.5 6.0 8.0 1.5 9.0 Output Disable Time Units Max Data to Output Output Disable Time tPLZ Typ 40qC to 85qC CL Propagation Delay Output Enable Time tPHZ Min TA ns ns ns ns ns ns Note 5: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC OPEN CPD Power Dissipation Capacitance 30.0 pF VCC 5.0V 3 Conditions www.fairchildsemi.com 74AC540 AC Electrical Characteristics 74AC540 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74AC540 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74AC540 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 74AC540 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com