ATBTLC1000 QFN SoC Ultra Low Power BLE 4.1 SoC DATASHEET Description The Atmel(R) ATBTLC1000 is an ultra-low power Bluetooth(R) SMART (BLE 4.1) System on a Chip with Integrated MCU, Transceiver, Modem, MAC, PA, TR Switch, and Power Management Unit (PMU). It can be used as a Bluetooth Low Energy link controller or data pump with external host MCU or as a standalone applications processor with embedded BLE connectivity and external memory. The qualified Bluetooth Smart protocol stack is stored in dedicated ROM. The firmware includes L2CAP service layer protocols, Security Manager, Attribute protocol (ATT), Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). Additionally, application profiles such as Proximity, Thermometer, Heart Rate, Blood Pressure, and many others are supported and included in the protocol stack. Features Complies with Bluetooth V4.1 2.4GHz transceiver and modem - -95dBm/-93dBm programmable receiver sensitivity - -20 to +3.5dBm programmable TX output power - Integrated T/R switch - Single wire antenna connection ARM(R) Cortex(R)-M0 32-bit processor - Single wire Debug (SWD) interface - Four-channel DMA controller - Brownout detector and Power On Reset - Watch Dog Timer Memory - 128KB embedded RAM (96KB available for application) - 128KB embedded ROM Hardware Security Accelerators - AES-128 - SHA-256 Peripherals - 12 digital and 2 mixed-signal GPIOs with 96k internal programmable pull-up or down resistors and retention capability, and one wakeup GPIO with 96k internal pull-up resistor - 2x SPI Master/Slave - 2x I2C Master/Slave and 1x I2C Slave - 2x UART - 1x SPI Flash - Three-axis quadrature decoder - 4x Pulse Width Modulation (PWM), three General Purpose Timers, and one Wakeup Timer Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 - 2-channel 11-bit ADC Clock - Integrated 26MHz RC oscillator - 26MHz crystal oscillator - Integrated 2MHz sleep RC oscillator - 32.768kHz RTC crystal oscillator Ultra Low power - 1.1A sleep current (8KB RAM retention and RTC running) - 3.0mA peak TX current (0dBm, 3.6V) - 4.0mA peak RX current (3.6V, -93dBm sensitivity) - 9.7A average advertisement current (three channels, 1s interval) Integrated Power management - 1.8 to 4.3V battery voltage range Fully integrated Buck DC/DC converter Bluetooth SIG Certification - QD ID Controller (see declaration D028678) - QD ID Host (see declaration D028679) 2 ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 Ta bl e of Conte nts 1 Ordering Information ................................................................................................... 5 2 Package Information ................................................................................................... 5 3 Block Diagram ............................................................................................................. 5 4 Pinout Information....................................................................................................... 6 5 Package Drawing ......................................................................................................... 8 6 Power Management ..................................................................................................... 9 6.1 6.2 6.3 6.4 6.5 6.6 7 Clocking ..................................................................................................................... 16 7.1 7.2 7.3 7.4 8 Overview ............................................................................................................................................. 16 26MHz Crystal Oscillator (XO) ............................................................................................................ 17 32.768kHz RTC Crystal Oscillator (RTC XO) ...................................................................................... 19 7.3.1 General Information ................................................................................................................ 19 7.3.2 RTC XO Design and Interface Specification ........................................................................... 21 7.3.3 RTC Characterization with Gm Code Variation at Supply 1.2V and Temp. = 25C ................ 21 7.3.4 RTC Characterization with Supply Variation and Temp. = 25C ............................................. 22 2MHz and 26MHz Integrated RC Oscillators ....................................................................................... 23 CPU and Memory Subsystem ................................................................................... 25 8.1 8.2 8.3 9 Power Architecture ................................................................................................................................ 9 DC/DC Converter ................................................................................................................................ 10 Power Consumption ............................................................................................................................ 11 6.3.1 Description of Device States................................................................................................... 11 6.3.2 Controlling the Device States ................................................................................................. 12 6.3.3 Current Consumption in Various Device States...................................................................... 12 Power Sequences ............................................................................................................................... 13 Power On Reset (POR) and Brown Out Detector (BOD) .................................................................... 14 Digital and Mixed-Signal I/O Pin Behavior during Power-Up Sequences ............................................ 15 ARM Subsystem ................................................................................................................................. 25 8.1.1 Features ................................................................................................................................. 25 8.1.2 Module Descriptions ............................................................................................................... 26 Memory Subsystem............................................................................................................................. 27 8.2.1 Shared Instruction and Data Memory ..................................................................................... 27 8.2.2 ROM ....................................................................................................................................... 28 8.2.3 BLE Retention Memory........................................................................................................... 28 Non-Volatile Memory ........................................................................................................................... 28 Bluetooth Low Energy (BLE) Subsystem ................................................................ 29 9.1 9.2 9.3 BLE Core............................................................................................................................................. 29 9.1.1 Features ................................................................................................................................. 29 BLE Radio ........................................................................................................................................... 29 9.2.1 Receiver Performance ............................................................................................................ 29 9.2.2 Transmitter Performance ........................................................................................................ 30 Atmel Bluetooth SmartConnect Stack ................................................................................................. 30 10 External Interfaces .................................................................................................... 32 10.1 Overview ............................................................................................................................................. 32 10.2 I2C Master/Slave Interface .................................................................................................................. 34 ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 3 3 10.2.1 Description.............................................................................................................................. 34 10.2.2 I2C Interface Timing ................................................................................................................ 34 10.3 SPI Master/Slave Interface .................................................................................................................. 35 10.3.1 Description.............................................................................................................................. 35 10.3.2 SPI Interface Modes ............................................................................................................... 36 10.3.3 SPI Slave Timing .................................................................................................................... 37 10.3.4 SPI Master Timing .................................................................................................................. 38 10.4 SPI Flash Master Interface .................................................................................................................. 38 10.4.1 Description.............................................................................................................................. 38 10.4.2 SPI Master Timing .................................................................................................................. 38 10.5 UART Interface ................................................................................................................................... 39 10.6 GPIOs ................................................................................................................................................. 40 10.7 Analog to Digital Converter (ADC)....................................................................................................... 40 10.7.1 Overview................................................................................................................................. 40 10.7.2 Timing ..................................................................................................................................... 41 10.7.3 Performance ........................................................................................................................... 42 10.8 Software Programmable Timer and Pulse Width Modulator ................................................................ 45 10.9 Clock Output ....................................................................................................................................... 45 10.9.1 Variable Frequency Clock Output Using Fractional Divider .................................................... 45 10.9.2 Fixed Frequency Clock Output ............................................................................................... 45 10.10 Three-axis Quadrature Decoder ........................................................................................................ 46 11 Reference Design ...................................................................................................... 47 12 Bill of Material (BOM) ................................................................................................ 48 13 Electrical Characteristics .......................................................................................... 49 13.1 Absolute Maximum Ratings ................................................................................................................. 49 13.2 Recommended Operating Conditions ................................................................................................. 49 13.3 DC Characteristics .............................................................................................................................. 49 14 Reflow Profile Information ........................................................................................ 51 14.1 Storage Condition................................................................................................................................ 51 14.1.1 Moisture Barrier Bag Before Opened ..................................................................................... 51 14.1.2 Moisture Barrier Bag Open ..................................................................................................... 51 14.2 Stencil Design ..................................................................................................................................... 51 14.3 Baking Conditions ............................................................................................................................... 51 14.4 Soldering and Reflow Condition .......................................................................................................... 51 14.4.1 Reflow Oven ........................................................................................................................... 51 15 ERRATA ..................................................................................................................... 53 16 Document Revision History ...................................................................................... 54 4 ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 1 Ordering Information Ordering code 2 Package Description ATBTLC1000A-MU-T 4x4mm QFN 32 ATBTLC1000 Tape & Reel ATBTLC1000A-MU-Y 4x4mm QFN 32 ATBTCL1000 Tray Package Information Table 2-1. ATBTLC1000 4x4 QFN 32 Package Information Parameter Value Units Tolerance Package Size 4x4 mm 0.1mm QFN Pad Count 32 Total Thickness 0.85 QFN Pad Pitch 0.4 Pad Width 0.2 +0.15/-0.05mm mm Exposed Pad size 3 2.7 x 2.7 Block Diagram Figure 3-1. ATBTLC1000 Block Diagram ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 5 5 4 Pinout Information ATBTLC1000 is offered in an exposed pad 32-pin QFN package. This package has an exposed paddle that must be connected to the system board ground. In Figure 4-1, the QFN package pin assignment is shown. The color shading is used to indicate the pin type as follows: Red - analog Green - digital I/O (switchable power domain) Blue - digital I/O (always-on power domain) Yellow - digital I/O power Purple - PMU Shaded green/red - configurable mixed-signal GPIO (digital/analog) The ATBTLC1000 pins are described in Table 4-1. Figure 4-1. 6 ATBTLC1000 Pin Assignment ATBTLC1000 QFN SoC [DATASHEET] 6 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 Table 4-1. ATBTLC1000 Pin Description Pin # Pin name Pin type Description / Default function 1 VDD_RF Analog/RF RF Supply 1.2V 2 RFIO Analog/RF RX input and TX output 3 VDD_AMS Analog/RF AMS Supply 1.2V 4 LP_GPIO_0 Digital I/O SWD Clock 5 LP_GPIO_1 Digital I/O SWD I/O 6 LP_GPIO_2 Digital I/O UART RXD 7 LP_GPIO_3 Digital I/O UART TXD 8 LP_GPIO_8 Digital I/O UART_CTS 9 LP_GPIO_9 Digital I/O UART_RTS 10 LP_GPIO_10 Digital I/O SPI SCK/SPI FLASH SCK 11 LP_GPIO_11 Digital I/O SPI MOSI/SPI FLASH TXD 12 LP_GPIO_12 Digital I/O SPI SSN/SPI FLASH SSN 13 LP_GPIO_13 Digital I/O SPI MISO/SPI FLASH RXD 14 VSW PMU DC/DC Converter Switching Node 15 VBATT_BUCK PMU DC/DC Converter Supply and General Battery Connection 16 VDDC_PD4 PMU DC/DC Converter 1.2V output and feedback node 17 GPIO_MS1 Mixed Signal I/O Configurable to be a GPIO Mixed Signal only (ADC interface) 18 GPIO_MS2 Mixed Signal I/O Configurable to be a GPIO Mixed Signal only (ADC interface) 19 CHIP_EN PMU Master Enable for chip 20 LP_LDO_OUT_1P2 PMU Low Power LDO output (connect to 1F decoupling cap) 21 RTC_CLK_P PMU RTC terminal + / 32.768kHz XTAL + 22 RTC_CLK_N PMU RTC terminal - / 32.768kHz XTAL - 23 AO_TEST_MODE Digital Input Test Mode Selection (SCAN ATE)/GND for normal operation 24 AO_GPIO_0 Digital I/O Always-on External Wakeup 25 LP_GPIO_16 Digital I/O GPIO 26 VDDIO Digital I/O Power I/O Supply can be less than or equal to VBATT_BUCK 27 LP_GPIO_18 Digital I/O GPIO 28 XO_P Analog/RF XO Crystal + 29 XO_N Analog/RF XO Crystal - 30 TPP Analog/RF Test MUX + output 31 VDD_SXDIG Analog/RF Synthesizer Digital Supply 1.2V 32 VDD_VCO Analog/RF Synthesizer VCO Supply 1.2V Paddle Paddle Pad Power Ground connection must be tied to system board ground ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 7 7 5 Package Drawing The ATBTLC1000 QFN package is RoHS/green compliant. Figure 5-1. 8 ATBTLC1000 4x4 QFN 32 Package Outline Drawing ATBTLC1000 QFN SoC [DATASHEET] 8 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 Power Management 6.1 Power Architecture ATBTLC1000 uses an innovative power architecture to eliminate the need for external regulators and reduce the number of off-chip components. The integrated power management block includes a DC/DC buck converter and separate Low Drop Out (LDO) regulators for different power domains. The DC/DC buck converter converts battery voltage to a lower internal voltage for the different circuit blocks and does this with high efficiency. The DC/DC requires three external components for proper operation (two inductors, L, 4.7H and 9.1nH, and one capacitor, C, 4.7F). Figure 6-1. ATBTLC1000 Power Architecture RF/AMS VDD_VCO LDO2 1.0V ~ SX VDD_AMS, VDD_RF, VDD_SXDIG RF/AMS Core VDDIO Digital RF/AMS Core Voltage Pads Digital Core eFuse dcdc_ena PMU 2.5V Digital Core Voltage Sleep Osc EFuse LDO LP LDO ena Dig Core LDO ena CHIP_EN VDDC_PD4 ena DC/DC Converter VBATT_BUCK Vin Vout VSW Off-Chip LC ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 9 9 6.2 DC/DC Converter The DC/DC Converter is intended to supply current to the BLE digital core and the RF transceiver core. The DC/DC consists of a power switch, 26MHz RC oscillator, controller, external inductor, and an external capacitor. The DCDC is utilizing pulse skipping discontinuous mode as its control scheme. The DC/DC specifications are shown in the following tables and figures. Table 6-1. DC/DC Converter Specifications (performance is guaranteed for (L) 4.7H and (C) 4.7F) Parameter Symbol Min. Typ. Max. Unit Note Output current capability IREG 0 10 30 mA Dependent on external component values and DC/DC settings with acceptable efficiency External capacitor range CEXT 2 4.7 20 F External capacitance range External inductor range LEXT 2 4.7 10 H External inductance range Battery voltage VBATT 1.8 3 4.3 Functionality and stability given V Output voltage range VREG Current consumption IDD 1.05 1.2 125 Startup time tstartup 20 Voltage ripple VREG 5 10 85 VOS 0 Line Regulation VREG 10 Load regulation VREG 5 Efficiency Overshoot at startup Figure 6-2. 1.47 25mV step size A DC/DC quiescent current 600 s Dependent on external component values and DC/DC settings 30 mV Dependent on external component values and DC/DC settings % No overshoot, no output pre-charge mV From 1.8 to 4.3V From 0 to 10mA DC/DC Converter Allowable Onboard Inductor and Capacitor Values (VBATT = 3V) Vripple [mV] Inductor [H] RX Sensitivity (1) [dBm] Efficiency [%] C=2.2F C=4.7F C=10F 2.2 83 N/A <5 <5 ~1.5dB degrade 4.7 85 9 5 <5 ~0.7dB degrade Note: 10 Measured at 3V VBATT, at load of 10mA 1. Degradation relative to design powered by external LDO and DC/DC disabled. ATBTLC1000 QFN SoC [DATASHEET] 1 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 0 Figure 6-3. DC/DC Converter Efficiency Efficiency vs. Battery Voltage 95.0 Efficeincy (%) 90.0 85.0 80.0 75.0 70.0 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.3 14 15 Battery Voltage (V) Efficiency vs. Load Current 86.0 85.0 Efficeincy (%) 84.0 83.0 82.0 81.0 80.0 79.0 78.0 77.0 3 4 5 6 7 8 9 10 11 12 13 Load Current (mA) 6.3 Power Consumption 6.3.1 Description of Device States ATBTLC1000 has multiple device states, depending on the state of the ARM processor and BLE subsystem. Note: The ARM is required to be powered on if the BLE subsystem is active. BLE_On_Transmit - Device is actively transmitting a BLE signal (Application may or may not be active) BLE_On_Receive - Device is actively receiving a BLE signal (Application may or may not be active) MCU_Only - Device has ARM processor powered on and BLE subsystem powered down Ultra_Low_Power - BLE is powered down and Application is powered down (with or without RAM retention) Power_Down - Device core supply off ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 11 1 1 6.3.2 Controlling the Device States The following pins are used to switch between the main device states: CHIP_EN - used to enable PMU VDDIO - I/O supply voltage from external supply In Power_Down state, VDDIO is on and CHIP_EN is low (at GND level). To switch between the Power_Down state and the MCU_Only state, CHIP_EN has to change between low and high (VDDIO voltage level). Once the device is the MCU_Only state, all other state transitions are controlled entirely by software. When VDDIO is off and CHIP_EN is low, the chip is powered off with no leakage. When no power is supplied to the device (the DC/DC Converter output and VDDIO are both off and at ground potential), a voltage cannot be applied to the ATBTLC1000 pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when a voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on, so the Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. 6.3.3 Current Consumption in Various Device States Table 6-2. Device State Current Consumption with VBATT = 3.6V Device State CHIP_EN VDDIO IVBAT (typical) IVDDIO (typical) Power_Down Off On <50nA <50nA Ultra_Low_Power Standby On On 900nA 50nA Ultra_Low_Power with 8KB retention, BLE timer, no RTC (1) On On 1.1A 0.2A Ultra_Low_Power with 8KB retention, BLE timer, with RTC (2) On On 1.25A 0.1uA MCU_Only, idle (waiting for interrupt) On On 0.85mA 12A BLE_On_Receive@-95dBm On On 4.5mA 12A BLE_On_Transmit, 0dBm output power On On 3.0mA 12A BLE_On_Transmit, 3.5dBm output power On On 4.0mA 12A Notes: 12 1. 2. Remark Sleep clock derived from internal 32kHz RC oscillator. Sleep clock derived from external 32.768kHz crystal specified for CL=7pF, using the default on-chip capacitance only, without using external capacitance. ATBTLC1000 QFN SoC [DATASHEET] 1 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 2 Figure 6-4. Note: 6.4 1. ATBTLC1000 Average Advertising Current(1) The Average advertising current is measured at VBATT = 3.6V, TX POUT=0dBm. Power Sequences The power sequences for ATBTLC1000 are shown in Figure 6-5. The timing parameters are provided in Table 6-3. Figure 6-5. ATBTLC1000 Power-up Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC XO Clock ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 13 1 3 Table 6-3. ATBTLC1000 Power-up Sequence Timing Parameter Min. tA 0 tB 0 tC 10 tA1 0 tB1 0 Max. Units Description VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. ms s Notes CHIP_EN rise to 31.25kHz (2MHz/64) oscillator stabilizing CHIP_EN fall to VDDIO fall CHIP_EN must fall before VDDIO. CHIP_EN must be driven high or low, not left floating. VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or be tied together ms 6.5 Power On Reset (POR) and Brown Out Detector (BOD) The ATBTLC1000 has a POR circuit for proper system power bring up and a brownout detector to reset the system's operation when a drop in battery voltage is detected. POR is a power on reset circuit that outputs a HI logic value when the VBATT_BUCK is below a voltage threshold. The POR output becomes a LO logic value when the VBATT_BUCK is above a voltage threshold. BOD is a brownout detector that outputs a HI logic value when the VBATT_BUCK voltage falls below a predefined voltage threshold. When the VBATT_BUCK voltage level is restored above a voltage threshold, the BOD output becomes a LO logic value. The counter creates a pulse that holds the chip in reset for 256*(64*T_2MHz) ~ 8.2ms Figure 6-6 and Figure 6-7 illustrate the system block diagram and timing. Table 6-4 shows the BOD thresholds. Figure 6-6. 14 ATBTLC1000 POR and BOD Block Diagram ATBTLC1000 QFN SoC [DATASHEET] 1 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 4 Figure 6-7. ATBTLC1000 POR and BOD Timing Sequence Table 6-4. ATBTLC1000 BOD Thresholds Parameter BOD threshold BOD threshold temperature coefficient 6.6 Min. Typ. Max. 1.73V 1.80V 1.92V Comment -1.09mV/C BOD current consumption 300nA tPOR 8.2ms Digital and Mixed-Signal I/O Pin Behavior during Power-Up Sequences The following table represents I/O pin states corresponding to device power modes. Table 6-5. I/O Pin Behavior in the Different Device States (1) VDDIO CHIP_EN Output Driver Input Driver Pull Up/Down Resistor (2) Power_Down: core supply off High Low Disabled (Hi-Z) Disabled Disabled Power-On Reset: core supply on, POR hard reset pulse on High High Disabled (Hi-Z) Disabled Disabled (3) Power-On Default: core supply on, device out of reset but not programmed yet High High Disabled (Hi-Z) Enabled (4) Enabled Pull-Up (4) High Programmed by firmware for each pin: Enabled or Disabled (Hi-Z) (5), when Enabled driving 0 or 1 Opposite of Output Driver state: Disabled or Enabled (5) Device State MCU_Only, BLE_On: core supply on, device programmed by firmware High Programmed by firmware for each pin: Enabled or Disabled, Pull-Up or Pull-Down (5) ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 15 1 5 Device State VDDIO Ultra_Low_Power: core supply on for always-on domain, core supply off for switchable domains Note: 1. 2. 3. 4. 5. 6. Output Driver Input Driver Pull Up/Down Resistor (2) High Retains previous state (4) for each pin: Enabled or Disabled (Hi-Z), when Enabled driving 0 or 1 Opposite of Output Driver state: Disabled or Enabled5 Retains previous state (6) for each pin: Enabled or Disabled, Pull-Up or PullDown This table applies to all three types of I/O pins (digital switchable domain GPIOs, digital always-on/wakeup GPIO, and mixed-signal GPIOs) unless otherwise noted Pull-up/down resistor value is 96k 10% In Power-On Reset state pull-up resistor is enabled in the always-on/wakeup GPIO only In Power-On Default state input drivers and pull-up/down resistors are disabled in the mixed-signal GPIOs only (mixed-signal GPIOs are defaulted to analog mode, see the note below) Mixed-signal GPIOs can be programmed to be in analog or digital mode for each pin: when programmed to analog mode (default), the output driver, input driver, and pull-up/down resistors are all disabled In Ultra_Low_Power state always-on/wakeup GPIO does not have retention capability and behaves same as in MCU_Only or BLE_On states, also for mixed-signal GPIOs programming analog mode overrides retention functionality for each pin 7 Clocking 7.1 Overview Figure 7-1. High CHIP_EN ATBTLC1000 Clock Architecture 26 MHz 26 MHz XO x2 52 MHz BLE Clock 26 MHz 26 MHz 26 MHz RC Osc ARM Clock Control ARM Clock Low Power Clock Control Low Power Clock 2 MHz 2 MHz RC Osc 2 MHz /64 32.768 kHz RTC XO 31.25 kHz 32.768 kHz Figure 7-1 provides an overview of the clock tree and clock management blocks. 16 ATBTLC1000 QFN SoC [DATASHEET] 1 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 The BLE Clock is used to drive the BLE subsystem. The ARM clock is used to drive the Cortex-M0 MCU and its interfaces (UART, SPI, and I2C); the nominal MCU clock speed is 26MHz. The Low Power Clock is used to drive all the low-power applications like the BLE sleep timer, always-on power sequencer, always-on timer, and others. The 26MHz Crystal Oscillator (XO) must be used for the BLE operations or in the event, a very accurate clock is required for the ARM subsystem operations. The 26MHz integrated RC Oscillator is used for most general purpose operations on the MCU and its peripherals. In cases when the BLE subsystem is not used, the RC oscillator can be used for lower power consumption. The frequency variation of this RC oscillator is up to 40% over process, voltage, and temperature. The 2MHz integrated RC Oscillator can be used as the Low Power Clock for applications that require fast wakeup of the ARM or for generating a ~31.25kHz clock for slower wakeup but lowest power in sleep mode. This 2MHz oscillator can also be used as the ARM Clock for low-power applications where the MCU needs to remain ON but run at a reduced clock speed. The frequency variation of this RC oscillator is up to 50% over process, voltage, and temperature. The 32.768kHz RTC Crystal Oscillator (RTC XO) is recommended to be used for BLE operations (although optional) as it will reduce power consumption by providing the best timing for wakeup precision, allowing circuits to be in low-power sleep mode for as long as possible until they need to wake up and connect during the BLE connection event. The ~31.25kHz clock derived from the 2MHz integrated RC Oscillator can be used instead of RTC XO but it has low accuracy over process, voltage, and temperature variations (up to 40%). Therefore, using the integrated RC Oscillator is NOT guaranteed to meet the 500ppm BLE specification on sleep timing. 7.2 26MHz Crystal Oscillator (XO) Table 7-1. ATBTLC1000 26MHz Crystal Oscillator Parameters Parameter Crystal Resonant Frequency Min. Typ. Max. Units N/A 26 N/A MHz 50 80 Crystal Equivalent Series Resistance Stability - Initial Offset (1) -50 50 ppm Stability - Temperature and Aging -40 40 ppm Note: 1. The initial offset must be calibrated to maintain 25ppm in all operating conditions. This calibration is performed during final production testing and calibration offset values are stored in eFuse. More details are provided in the calibration application note. The block diagram in Figure 7-2 (a) shows how the internal Crystal Oscillator (XO) is connected to the external crystal. The XO has up to 10pF internal capacitance on each terminal XO_P and XO_N (programmable in steps of 1.25pF). To bypass the crystal oscillator, an external Signal capable of driving 10pF can be applied to the XO_P terminal as shown in Figure 7-2 (b). The needed external bypass capacitors depend on the chosen crystal characteristics. Refer to the datasheet of the preferred crystal and take into account the on-chip capacitance. When bypassing XO_P from an external clock, XO_N is required to be floating. It is recommended that only crystals specified for CL=8pF be used in customer designs since this affects the sleep/wakeup timing of the device. CL other than 8pF may require upgraded firmware and device recharacterization. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 17 1 7 Figure 7-2. ATBTLC1000 Connections to XO (a) Crystal oscillator is used Table 7-2. (b) Crystal oscillator is bypassed ATBTLC1000 26MHz XTAL Cl_onchip Programming Register Cl_onchip rx_xo_regs[7,6,15] = 000 1.00 rx_xo_regs[7,6,15] = 001 2.25 rx_xo_regs[7,6,15] = 010 3.50 rx_xo_regs[7,6,15] = 011 4.75 rx_xo_regs[7,6,15] = 100 6.00 rx_xo_regs[7,6,15] = 101 7.25 rx_xo_regs[7,6,15] = 110 8.50 rx_xo_regs[7,6,15]= 111 9.75 [pF] If rx_reg7[1] = 1 add 5pF to above value Table 7-3 specifies the electrical and performance requirements for the external clock. Table 7-3. ATBTLC1000 XO Bypass Clock Specification Parameter 18 Min. Max. Unit Oscillation frequency 26 26 MHz Voltage swing 0.75 1.2 Vpp Stability - Temperature and Aging -25 +25 ppm Phase Noise -130 dBc/Hz Jitter (RMS) <1psec ATBTLC1000 QFN SoC [DATASHEET] 1 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 8 Comments Must be able to drive 5pF load @ desired frequency At 10kHz offset Based on integrated phase noise spectrum from 1kHz to 1MHz 7.3 32.768kHz RTC Crystal Oscillator (RTC XO) 7.3.1 General Information ATBTLC1000 has a 32.768kHz RTC oscillator that is preferably used for BLE activities involving connection events. To be compliant with the BLE specifications for connection events, the frequency accuracy of this clock has to be within 500ppm. Because of the high accuracy of the 32.768kHz crystal oscillator clock, the power consumption can be minimized by leaving radio circuits in low-power sleep mode for as long as possible until they need to wake up for the next connection timed event. The block diagram in Figure 7-3(a) shows how the internal low-frequency Crystal Oscillator (XO) is connected to the external crystal. The RTC XO has a programmable internal capacitance with a maximum of 15pF on each terminal, RTC_CLK_P, and RTC_CLK_N. When bypassing the crystal oscillator with an external signal, one can program down the internal capacitance to its minimum value (~1pF) for easier driving capability. The driving signal can be applied to the RTC_CLK_P terminal as shown in Figure 7-3 (b). The need for external bypass capacitors depends on the chosen crystal characteristics. Refer to the datasheet of the preferred crystal and take into account the on-chip capacitance. When bypassing RTC_CLK_P from an external clock, RTC_CLK_N is required to be floating. Figure 7-3. (a) ATBTLC1000 Connections to RTC XO Crystal oscillator is used Table 7-4. (b) Crystal oscillator is bypassed 32.768kHz XTAL C_onchip Programming Register: pierce_cap_ctrl[3:0] Cl_onchip 0000 0.0 0001 1.0 0010 2.0 0011 3.0 0100 4.0 0101 5.0 [pF] ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 19 1 9 Register: pierce_cap_ctrl[3:0] 20 Cl_onchip 0110 6.0 0111 7.0 1000 8.0 1001 9.0 1010 10.0 1011 11.0 1100 12.0 1101 13.0 1110 14.0 1111 15.0 ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 0 [pF] 7.3.2 RTC XO Design and Interface Specification The RTC consists of two main blocks: The Programmable Gm stage and tuning capacitors. The programmable Gm stage is used to guarantee oscillation startup and to sustain oscillation. Tuning capacitors are used to adjust the XO center frequency and control the XO precision for different crystal models. The output of the XO is driven to the digital domain via a digital buffer stage with a supply voltage of 1.2V. Table 7-5. RTC XO Interface Pin Name Function Register Default Digital Control Pins Control feedback resistance value: 0 = 20M Feedback resistance 1 = 30M Feedback resistance 0X4000F404<15>='1' Pierce_cap_ctrl<3:0> Control the internal tuning capacitors with step of 700fF: 0000=700fF 1111=11.2pF Refer to crystal datasheet to check for optimum tuning cap value 0X4000F404<23:20>="1000" Pierce_gm_ctrl<3:0> Controls the Gm stage gain for different crystal mode: 0011= for crystal with shunt cap of 1.2pF 1000= for crystal with shunt cap >3pF 0X4000F404<19:16>="1000" VDD_XO 1.2V RTC Characterization with Gm Code Variation at Supply 1.2V and Temp. = 25C This section shows the RTC total drawn current and the XO accuracy versus different tuning capacitors and different GM codes, at a supply voltage of 1.2V and temperature = 25C. Figure 7-4. RTC Drawn Current vs. Tuning Caps at 25C 600 500 Current in nA 7.3.3 Pierce_res_ctrl gm code=1 400 gm code=2 300 gm code=4 200 gm code=8 100 gm code=12 gm code=16 0 0 5 10 Tuning Caps in pF 15 20 ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 21 2 1 Figure 7-5. RTC Oscillation Frequency Deviation vs. Tuning Caps at 25C 450 400 ppm 350 300 gm code=1 250 gm code=2 200 gm code=4 150 gm code=8 100 gm code=12 50 gm code=16 0 0 2 4 6 8 10 12 14 16 18 Tuning Caps 7.3.4 RTC Characterization with Supply Variation and Temp. = 25C Figure 7-6. RTC Drawn Current vs. Supply Variation 1400 1200 Current in nA 1000 gm code=0 & Tuning Cap=8pF 800 gm code=0 & Tuning Cap=0pF 600 400 gm code=16 & Tuning Cap=16pF 200 gm code=16 & Tuning Cap =0pF 0 0.9 1 1.1 1.2 Supply voltage 22 ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 2 1.3 1.4 1.5 Figure 7-7. RTC Frequency Deviation vs. Supply Voltage 400 350 ppm 300 250 gm code=0 & Tuning Cap=8pF 200 gm code=0 & Tuning Cap=0pF 150 gm code=16 & Tuning Cap=16pF 100 gm code=16 & Tuning Cap=0 50 0 0.9 1 1.1 1.2 1.3 1.4 1.5 Supply Voltage 7.4 2MHz and 26MHz Integrated RC Oscillators The 2MHz integrated RC Oscillator circuit without calibration has a frequency variation of 50% over process, temperature, and voltage variation. The ~31.25kHz clock is derived from the 2MHz clock by dividing by 64 and provides for lowest sleep power mode with a real-time clock running. As described above, calibration over process, temperature, and voltage is required to maintain the accuracy of this clock. Figure 7-8. 32kHz RC Oscillator PPM Variation vs. Calibration Time at Room Temperature ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 23 2 3 Figure 7-9. 32kHz RC Oscillator Frequency Variation over Temperature The 26MHz integrated RC Oscillator circuit has a frequency variation of 50% over process, temperature, and voltage variation. 24 ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 4 8 CPU and Memory Subsystem 8.1 ARM Subsystem ATBTLC1000 has an ARM Cortex-M0 32-bit processor. It is responsible for controlling the BLE Subsystem and handling all application features. The Cortex-M0 Microcontroller consists of a full 32-bit processor capable of addressing 4GB of memory. It has a RISC-like load/store instruction set and internal 3-stage Pipeline Von Neumann architecture. The Cortex-M0 processor provides a single system-level interface using AMBA technology to provide high speed, low latency memory accesses. The Cortex-M0 processor implements a complete hardware debug solution, with four hardware breakpoint and two watchpoint options. This provides high system visibility of the processor, memory, and peripherals through a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. Figure 8-1. ATBTLC1000 ARM Cortex-M0 Subsystem PD1 Timer DualTimer AHB Slave AHB Master Watch Dog Timer x2 SPI x2 Ahb_to_sram BLE Retention Ahb_to_rom ROM Ahb_to_sram IDRAM1 Ahb_to_sram IDRAM2 GPIO Ctrl x3 System Level AHB Slave System Regs Security Cores I2C x2 Nested Vector IRQ Ctrl Control Registers EFUSE Registers LP Clock Calibration ARM APB DMA Controller UART x2 System Level AHB Master SPI Flash Ctrl LP CORTEX M0 AON Sleep Timer AON Power Sequencer 8.1.1 Features The processor features and benefits are: Tight integration with the system peripherals to reduce area and development costs Thumb instruction set combines high code density with 32-bit performance Integrated sleep modes using a Wakeup Interrupt Controller for low power consumption Deterministic, high-performance interrupt handling via Nested Vector Interrupt Controller for time-critical applications Serial Wire Debug reduces the number of pins required for debugging DMA engine for Peripheral-to-Memory, Memory-to-Memory, and Memory-to-Peripheral operation ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 25 2 5 8.1.2 Module Descriptions 8.1.2.1 Timer The 32-bit timer block allows the CPU to generate a time tick at a programmed interval. This feature can be used for a wide variety of functions such as counting, interrupt generation, and time tracking. 8.1.2.2 Dual Timer The APB dual-input timer module is an APB slave module consisting of two programmable 32-bit downcounters that can generate interrupts when they expire. The timer can be used in a Free-running, Periodic, or One-shot mode. 8.1.2.3 Watchdog The two watchdog blocks allow the CPU to be interrupted if it has not interacted with the watchdog timer before it expires. In addition, this interrupt will be an output of the core so that it can be used to reset the CPU in the event that a direct interrupt to the CPU is not useful. This will allow the CPU to get back to a known state in the event a program is no longer executing as expected. The watchdog module applies a reset to a system in the event of a software failure, providing a way to recover from software crashes. 8.1.2.4 Wake up Timer This timer is a 32-bit count-down timer that operates on the 32kHz sleep clock. It can be used as a general purpose timer for the ARM or as a wakeup source for the chip. It has the ability to be a one-time programmable timer, as it will generate an interrupt/wakeup on expiration and stop operation. It also has the ability to be programmed in an auto reload fashion where it will generate an interrupt/wakeup and then proceed to start another count down sequence. 8.1.2.5 SPI Controller See Section 10.3. 8.1.2.6 I2C Controller See Section 10.2. 8.1.2.7 SPI-Flash Controller The AHB SPI-Flash Controller is used to access an external SPI Flash device to access various instruction/data code needed for storing application code, code patches, and OTA images. Supports several SPI modes including 0, 1, 2, and 3. See Section Table 10-8. 8.1.2.8 UART See Section 10.5. 8.1.2.9 DMA Controller Direct Memory Access (DMA) allows certain hardware subsystems to access main system memory independently of the Cortex-M0 Processor. The DMA features and benefits are: 26 Supports any address alignment Supports any buffer size alignment Peripheral flow control, including peripheral block transfer The following modes are supported: - Peripheral to peripheral transfer - Memory to memory - Memory to peripheral - Peripheral to memory - Register to memory ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 Interrupts for both TX done and RX done in memory and peripheral mode Scheduled transfers Endianness byte swapping Watchdog timer 4-channel operation 32-bit Data width AHB MUX (on read and write buses) Command lists support Usage of tokens 8.1.2.10 Nested Vector Interrupt Controller External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0 processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. All NVIC registers are accessible via word transfers and are little-endian. Any attempt to read or write a halfword or byte individually is unpredictable. The NVIC allows the CPU to be able to individually enable, disable each interrupt source, and hold each interrupt until it has been serviced and cleared by the CPU. Table 8-1. NVIC Register Summary Name Description ISER Interrupt Set-Enable Register ICER Interrupt Clear-Enable Register ISPR Interrupt Set-Pending Register ICPR Interrupt Clear-Pending Register IPR0-IPR7 Interrupt Priority Registers For a description of each register, see the Cortex-M0 documentation from ARM. 8.1.2.11 GPIO Controller The AHB GPIO is a general-purpose I/O interface unit allowing the CPU to independently control all input or output signals on ATBTLC1000. These can be used for a wide variety of functions pertaining to the application. The AHB GPIO provides a 16-bit I/O interface with the following features: 8.2 Programmable interrupt generation capability Programmable masking support Thread-safe operation by providing separate set and clear addresses for control registers Inputs are sampled using a double flip-flop to avoid meta-stability issues Memory Subsystem The Cortex-M0 core uses a 128KB instruction/boot ROM along with a 128KB shared instruction and data RAM. 8.2.1 Shared Instruction and Data Memory The Instruction and Data Memory (IDRAM1 and IDRAM2) contains instructions and data used by the ARM. The size of IDRAM1 and IDRAM2 is 128KB that can be used for BLE subsystem as well as for the user application. IDRAM1 contains three 32KB and IDRAM2 contains two 16KB memories that are accessible to the ARM and used for instruction/data storage. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 27 2 7 8.2.2 ROM The ROM is used to store the boot code and BLE firmware, stack, and selected user profiles. ROM contains the 128KB memory that is accessible to the ARM. 8.2.3 BLE Retention Memory The BLE functionality requires 8KB (or more depending on the application) state, instruction, and data to be retained in memory when the processor either goes into Sleep Mode or Power Off Mode. The RAM is separated into specific power domains to allow tradeoff in power consumption with retention memory size. 8.3 Non-Volatile Memory ATBTLC1000 has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This non-volatile one-time-programmable memory can be used to store customer-specific parameters, such as BLE address, XO calibration information, TX power, and crystal frequency offset, as well as other software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. The bitmap of the first bank is shown in Figure 8-2. The purpose of the first 80 bits in bank 0 is fixed, and the remaining bits are general-purpose software dependent bits or reserved for future use. Since each bank and each bit can be programmed independently, this allows for several updates of the device parameters following the initial programming, e.g. updating BLE address (this can be done by invalidating the last programmed bank and programming a new bank). Refer to ATBTLC1000 Programming Guide for the eFuse programming instructions. Figure 8-2. ATBTLC1000 eFuse Bit Map 128 Bits Bank 0 Bank 1 Application Specific Configuration Bank 2 Bank 3 Bank 4 Bank 5 F BT ADDR 8 28 48 XO Calibration 3 Reserved 3 HW Config 1 BT ADDR Used Reserved 1 ATBTLC1000 QFN SoC [DATASHEET] 2 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 8 Tx Power Calibration HW Config 9 Bluetooth Low Energy (BLE) Subsystem The BLE subsystem implements all the critical real-time functions required for full compliance with Specification of the Bluetooth System, v4.1, Bluetooth SIG. It consists of a Bluetooth 4.1 baseband controller (core), radio transceiver and the Atmel Bluetooth Smart Stack, the BLE Software Platform. 9.1 BLE Core The baseband controller consists of a modem and a Medium Access Controller (MAC) and it encodes and decodes HCI packets, constructs baseband data packages, schedules frames, and manages and monitors connection status, slot usage, data flow, routing, segmentation, and buffer control. The core performs Link Control Layer management supporting the main BLE states, including advertising and connection. 9.1.1 9.2 Features Broadcaster, Central, Observer, Peripheral Simultaneous Master and Slave operation, connect up to eight slaves Frequency Hopping Advertising/Data/Control packet types Encryption (AES-128, SHA-256) Bitstream processing (CRC, whitening) Operating clock 52MHz BLE Radio The radio consists of a fully integrated transceiver, including Low Noise Amplifier, Receive (RX) down converter, and analog baseband processing as well as Phase Locked Loop (PLL), Transmit (TX) Power Amplifier, and Transmit/Receive switch. At the RF front end, no external RF components on the PCB are required other than the antenna and a matching component. The RX sensitivity and TX output power of the radio together with the 4.1 PHY core provide a 100dB RF link budget for superior range and link reliability. 9.2.1 Receiver Performance Table 9-1. ATBTLC1000 BLE Receiver Performance Parameter Minimum Frequency 2,402 Sensitivity with on-chip DC/DC -94.5 Typical Maximum Unit 2,480 MHz -93 dBm Maximum receive signal level CCI ACI (N1) +5 12.5 0 N+2 Blocker (Image) -20 N-2 Blocker -38 N+3 Blocker (Adj. Image) -35 N-3 Blocker -43 dB ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 29 2 9 Parameter Minimum Typical N4 or greater -45 Intermod (N+3, N+6) -32 OOB (2GHz<f<2.399GHz) -15 OOB (f<2GHz or f>2.5GHz) -10 1. Unit dBm dBm mA 4.00 (1) RX peak current draw Note: Maximum At -93dBm sensitivity setting. Add 0.2mA at 3.6V for best sensitivity setting. All measurements performed at 3.6V VBATT and 25C, with tests following the Bluetooth V4.1 standard tests. There are two gain settings for Sensitivity, high gain (-95dBm) and low gain (-93dBm). Low gain has lower current consumption. 9.2.2 Transmitter Performance The transmitter has fine step power control with Pout variable in <3dB steps below 0dBm and in <0.5dB steps above 0dBm. Table 9-2. ATBTLC1000 BLE Transmitter Performance Parameter Frequency Minimum Typical 2,402 Output power range -20 0 Maximum output power 3.5 In-band Spurious (N2) -45 In-band Spurious (N3) -50 2nd Maximum Unit 2,480 MHz 3.5 dBm harmonic Pout -41 3rd harmonic Pout -41 4th harmonic Pout -41 5th harmonic Pout -41 Frequency deviation 250 kHz TX peak current draw 3.0 (1) mA Note: 1. At 0dBm TX output power. All measurements performed at 3.6V VBATT and 25C, with tests following the Bluetooth V4.1 standard tests. 9.3 Atmel Bluetooth SmartConnect Stack The ATBTLC1000 has a completely integrated Bluetooth Low Energy stack on chip, fully qualified, mature, and Bluetooth V4.1 compliant. Customer applications interface with the BLE protocol stack through the Atmel BLE API, which supports direct access to the GAP, SMP, ATT, GATT client / server, and L2CAP service layer protocols in the embedded firmware. The stack includes numerous BLE profiles for applications like: 30 Smart Energy Consumer Wellness ATBTLC1000 QFN SoC [DATASHEET] 3 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 0 Home Automation Security Proximity Detection Entertainment Sports and Fitness Automotive Together with the Atmel Studio Software Development environment, additional customer profiles can be easily developed. The Atmel Bluetooth SmartConnect software development kit is based on Keil and IARTM compiler tools and contains numerous application code examples for embedded and hosted modes. In addition to the protocol stack, drivers for each peripheral hardware block are provided. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 31 3 1 10 External Interfaces 10.1 Overview ATBTLC1000 external interfaces include: 2xSPI Master/Slave (SPI0 and SPI1), 2xI2C Master/Slave (I2C0 and I2C1), 1xI2C Slave-only (I2C2), 2xUART (UART1 and UART2), 1xSPI Flash, 1xSWD, and General Purpose Input/Output (GPIO) pins. For specific programming instructions, refer to the ATBTLC1000 Programming Guide. Table 10-1 illustrates the different peripheral functions that are software selectable for each pin. This allows for maximum flexibility of mapping desired interfaces on GPIO pins. The MUX1 option allows for any MEGAMUX option from Table 10-2 to be assigned to a GPIO. Table 10-1. Pin Name ATBTLC1000 Pin-MUX Matrix of External Interfaces Pin # Pull MUX0 MUX1 MUX2 MUX3 LP_GPIO_0 4 Up/Down GPIO 0 MEGAMUX 0 SWD CLK LP_GPIO_1 5 Up/Down GPIO 1 MEGAMUX 1 SWD I/O LP_GPIO_2 6 Up/Down GPIO 2 MEGAMUX 2 UART1 RXD LP_GPIO_3 7 Up/Down GPIO 3 MEGAMUX 3 UART1 TXD LP_GPIO_8 8 Up/Down GPIO 8 MEGAMUX 8 I2C0 SDA I2C2 SDA LP_GPIO_9 9 Up/Down GPIO 9 MEGAMUX 9 I2C0 SCL I2C2 SCL LP_GPIO_10 10 Up/Down GPIO 10 MEGAMUX 10 LP_GPIO_11 11 Up/Down GPIO 11 MEGAMUX 11 LP_GPIO_12 12 Up/Down GPIO 12 LP_GPIO_13 13 Up/Down GPIO 13 LP_GPIO_16 25 Up/Down LP_GPIO_18 27 Up/Down AO_GPIO_0 24 GPIO_MS1 17 GPIO_MS2 18 MUX4 MUX5 MUX6 MUX7 TEST OUT 0 TEST OUT 1 SPI1 SCK SPI0 SCK SPI FLASH SCK TEST OUT 2 SPI1 MOSI SPI0 MOSI SPI FLASH TXD TEST OUT 3 SPI0 SSN SPI FLASH SSN TEST OUT 8 SPI0 MISO SPI FLASH RXD TEST OUT 9 SPI0 SCK SPI FLASH SCK TEST OUT 10 SPI0 MOSI SPI FLASH TXD TEST OUT 11 MEGAMUX 12 SPI0 SSN SPI FLASH SSN TEST OUT 12 MEGAMUX 13 SPI0 MISO SPI FLASH RXD TEST OUT 13 GPIO 16 MEGAMUX 16 SPI FLASH SCK GPIO 18 MEGAMUX 18 SPI FLASH SSN I2C2 SCL Up GPIO 31 WAKEUP RTC CLK IN 32KHZ CLK OUT Up/Down GPIO 47 Up/Down GPIO 46 SPI1 SSN SPI0 SCK SPI FLASH SSN TEST OUT 16 SPI1 MISO SPI0 SSN SPI FLASH RXD TEST OUT 18 Table 10-2 shows the various software selectable MEGAMUX options that correspond to specific peripheral functionality. Several MEGAMUX options provide an interface to manage Wi-Fi(R) BLE coexistence. Table 10-2. ATBTLC1000 Software Selectable MEGAMUX Options MUX_Sel 32 Function 0 UART1 RXD 1 UART1 TXD 2 UART1 CTS 3 UART1 RTS 4 UART2 RXD 5 UART2 TXD 6 UART2 CTS 7 UART2 RTS 8 I2C0 SDA 9 I2C0 SCL ATBTLC1000 QFN SoC [DATASHEET] 3 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 2 Notes MUX_Sel Function Notes 10 I2C1 11 I2C1 SCL 12 PWM 1 13 PWM 2 14 PWM 3 15 PWM 4 16 LP CLOCK OUT 32kHz clock output (RC Osc. or RTC XO) 17 WLAN TX ACTIVE Coexistence: Wi-Fi is currently transmitting 18 WLAN RX ACTIVE Coexistence: Wi-Fi is currently receiving 19 BLE TX ACTIVE Coexistence: BLE is currently transmitting 20 BLE RX ACTIVE Coexistence: BLE is currently receiving 21 BLE IN PROCESS Coexistence Signal 22 BLE MBSY Coexistence Signal 23 BLE SYNC Coexistence Signal 24 BLE RXNTX Coexistence Signal 25 BLE PTI 0 Coexistence: BLE Priority 26 BLE PTI 1 Coexistence: BLE Priority 27 BLE PTI 2 Coexistence: BLE Priority 28 BLE PTI 3 Coexistence: BLE Priority 29 QUAD DEC X IN A 30 QUAD DEC X IN B 31 QUAD DEC Y IN A 32 QUAD DEC Y IN B 33 QUAD DEC Z IN A 34 QUAD DEC Z IN B SDA An example of peripheral assignment using these MEGAMUX options is as follows: I2C0 pin-MUXed on LP_GPIO_8 and LP_GPIO_9 via MUX1 and MEGAMUX=8 and 9 (Table 10-2) I2C1 pin-MUXed on LP_GPIO_0 and LP_GPIO_1 via MUX1 and MEGAMUX=10 and 11 (Table 10-2) PWM pin-MUXed on LP_GPIO_16 via MUX1 and MEGAMUX=12 (Table 10-2) Another example is to illustrate the available options for pin LP_GPIO_3, depending on the pin-MUX option selected: MUX0: the pin will function as bit 3 of the GPIO bus and is controlled by the GPIO controller in the ARM subsystem MUX1: any option from the MEGAMUX table can be selected, for example, it can be a quad_dec, pwm, or any of the other functions listed in the MEGAMUX table MUX2: the pin will function as UART1 TXD; this can be also achieved with the MUX1 option via MEGAMUX, but the MUX2 option allows a shortcut for the recommended pinout ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 33 3 3 10.2 MUX3: this option is not used and thus defaults to the GPIO option (same as MUX0) MUX4: the pin will function as SPI1 MOSI (this option is not available through MEGAMUX) MUX5: the pin will function as SPI0 MOSI (this option is not available through MEGAMUX) MUX6: the pin will function as SPI FLASH SCK (this option is not available through MEGAMUX) MUX7: the pin will function as bit 3 of the test output bus, giving access to various debug signals I2C Master/Slave Interface 10.2.1 Description ATBTLC1000 provides I2C Interface that can be configured as Slave or Master. I2C Interface is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). ATBTLC1000 I2C supports I2C bus Version 2.1 - 2000 and can operate in the following speed modes: Standard mode (100kb/s) Fast mode (400kb/s) High-speed mode (3.4Mb/s) I2C The is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400pF. Data is transmitted in byte packages. For specific information, refer to the Philips Specification entitled "The I2C -Bus Specification, Ver2.1". 10.2.2 I2C Interface Timing The I2C Interface timing (common to Slave and Master) is provided in Figure 10-1. The timing parameters for Slave and Master modes are specified in Table 10-3 and Table 10-4 respectively. Figure 10-1. ATBTLC1000 I2C Slave Timing Diagram tPR tSUDAT tHDDAT tBUF tSUSTO SDA tHL tLH tWL SCL tHDSTA tLH tHL tWH tPR fSCL Table 10-3. tPR tSUSTA ATBTLC1000 I2C Slave Timing Parameters Parameter Symbol Min. Max. Units 400 kHz SCL Clock Frequency fSCL 0 SCL Low Pulse Width tWL 1.3 SCL High Pulse Width tWH 0.6 SCL, SDA Fall Time tHL 300 SCL, SDA Rise Time tLH 300 Remarks s ns 34 ATBTLC1000 QFN SoC [DATASHEET] 3 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 4 This is dictated by external components Parameter Symbol Min. START Setup Time tSUSTA 0.6 START Hold Time tHDSTA 0.6 SDA Setup Time tSUDAT 100 SDA Hold Time tHDDAT 0 40 STOP Setup time tSUSTO 0.6 Bus Free Time Between STOP and START tBUF 1.3 Glitch Pulse Reject tPR 0 Max. Units Remarks s ns Slave and Master Default Master Programming Option s Table 10-4. 50 ns ATBTLC1000 I2C Master Timing Parameters Parameter Symbol Standard Mode Fast Mode High-speed Mode Min. Max. Min. Max. Min. Max. 100 0 400 0 3400 SCL Clock Frequency fSCL 0 SCL Low Pulse Width tWL 4.7 1.3 0.16 SCL High Pulse Width tWH 4 0.6 0.06 SCL Fall Time tHLSCL 300 300 10 40 SDA Fall Time tHLSDA 300 300 10 80 SCL Rise Time tLHSCL 1000 300 10 40 SDA Rise Time tLHSDA 1000 300 10 80 START Setup Time tSUSTA 4.7 0.6 0.16 START Hold Time tHDSTA 4 0.6 0.16 SDA Setup Time tSUDAT 250 100 10 SDA Hold Time tHDDAT 5 40 0 STOP Setup time tSUSTO 4 0.6 0.16 Bus Free Time Between STOP and START tBUF 4.7 1.3 Glitch Pulse Reject tPR Units kHz s ns s ns 70 s 10.3 0 50 ns SPI Master/Slave Interface 10.3.1 Description ATBTLC1000 provides a Serial Peripheral Interface (SPI) that can be configured as Master or Slave. The SPI Interface pins are mapped as shown in Table 10-5. The SPI Interface is a full-duplex slave-synchronous serial interface. When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line. The SPI Slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. For the details of the SPI protocol and more specific instructions, refer to ATBTLC1000 Programming Guide. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 35 3 5 Table 10-5. ATBTLC1000 SPI Interface Pin Mapping Pin Name SPI Function SSN Active Low Slave Select SCK Serial Clock MOSI Master Out Slave In (Data) MISO Master In Slave Out (Data) 10.3.2 SPI Interface Modes The SPI Interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in Table 10-6 and Figure 10-2. The red lines in Figure 10-2 correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1. Table 10-6. Figure 10-2. ATBTLC1000 SPI Modes Mode CPOL CPHA 0 0 0 1 0 1 2 1 0 3 1 1 ATBTLC1000 SPI Clock Polarity and Clock Phase Timing CPOL = 0 SCK CPOL = 1 SSN CPHA = 0 RXD/TXD (MOSI/MISO) 36 CPHA = 1 z 1 z ATBTLC1000 QFN SoC [DATASHEET] 3 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 2 1 3 2 4 3 5 4 6 5 7 6 8 7 z 8 z 10.3.3 SPI Slave Timing The SPI Slave timing is provided in Figure 10-3 and Table 10-7. Figure 10-3. ATBTLC1000 SPI Slave Timing Diagram Table 10-7. ATBTLC1000 SPI Slave Timing Parameters (1) Parameter Symbol Min. Max. Units 2 MHz Clock Input Frequency (2) fSCK Clock Low Pulse Width tWL 55 Clock High Pulse Width tWH 55 Clock Rise Time tLH 0 7 Clock Fall Time tHL 0 7 tODLY 7 28 RXD Input Setup Time tISU 5 RXD Input Hold Time tIHD 10 SSN Input Setup Time tSUSSN 5 SSN Input Hold Time tHDSSN 10 TXD Output Delay (3) Note: 1. 2. 3. ns Timing is applicable to all SPI modes Maximum clock frequency specified is limited by the SPI Slave interface internal design, actual maximum clock frequency can be lower and depends on the specific PCB layout Timing based on 15pF output loading ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 37 3 7 10.3.4 SPI Master Timing The SPI Master Timing is provided in Figure 10-4 and Table 10-8. Figure 10-4. ATBTLC1000 SPI Master Timing Diagram fSCK tLH tWH tWL SCK tHL SSN, TXD tODLY tISU tIHD RXD ATBTLC1000 SPI Master Timing Parameters (1) Table 10-8. Parameter Min. Clock Output Frequency (2) fSCK Clock Low Pulse Width tWL 30 Clock High Pulse Width tWH 32 Clock Rise Time (3) Max. Units 4 MHz tLH 7 Clock Fall Time (3) tHL 7 RXD Input Setup Time tISU 23 RXD Input Hold Time tIHD 0 tODLY 0 SSN/TXD Output Delay (3) Notes: 1. 2. 3. 10.4 Symbol ns 12 Timing is applicable to all SPI modes Maximum clock frequency specified is limited by the SPI Master interface internal design, actual maximum clock frequency can be lower and depends on the specific PCB layout Timing based on 15pF output loading SPI Flash Master Interface 10.4.1 Description ATBTLC1000 provides an SPI Master interface for accessing external Flash memory. The TXD pin is the same as the Master Output, Slave Input (MOSI), and the RXD pin is the same as the Master Input, Slave Output (MISO). The SPI Master interface supports all four standard modes of clock polarity and clock phase shown in Table 10-6. External SPI Flash memory is accessed by a processor programming commands to the SPI Master interface, which in turn initiates an SPI master access to the Flash. Refer to the ATBTLC1000 Programming Guide for more specific instructions. 10.4.2 SPI Master Timing The SPI Master Timing is provided in Figure 10-5 and Table 10-9. 38 ATBTLC1000 QFN SoC [DATASHEET] 3 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 8 Figure 10-5. ATBTLC1000 SPI Master Timing Diagram fSCK tLH tWH tWL SCK tHL SSN, TXD tODLY tISU tIHD RXD Table 10-9. ATBTLC1000 SPI Master Timing Parameters (1) Parameter Clock Output Frequency Symbol Min. fSCK Clock Low Pulse Width tWL 25 Clock High Pulse Width tWH 27 Clock Rise Time (3) Max. Units 13 MHz tLH 11 Clock Fall Time (3) tHL 10 Input Setup Time tISU 19 Input Hold Time tIHD 0 Output Delay (3) tODLY 1 Notes: 1. 2. 3. 10.5 (2) ns 7 Timing is applicable to all SPI modes Maximum clock frequency specified is limited by the SPI Master interface internal design, the actual maximum clock frequency can be lower and depends on the specific PCB layout Timing based on 15pF output loading UART Interface ATBTLC1000 provides Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial communication. The Bluetooth subsystem has two UART interfaces: a 2-pin interface for data transfer only (TX and RX) and a 4-pin interface for hardware flow control handshaking (RTS and CTS), and data transfer (TX and RX). The UART interfaces are compatible with the RS-232 standard, where ATBTLC1000 operates as Data Terminal Equipment (DTE) The RTS and CTS are used for hardware flow control; they MUST be connected to the host MCU UART and enabled for the UART interface to be functional. The pins associated with each the UART interfaces can be enabled on several alternative pins by programming their corresponding pin-MUX control registers (see Table 10-1 and Table 10-2 for available options). The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The Bluetooth UART input clock is selectable between 26MHz, 13MHz, 6.5MHz, and 3.25MHz. The clock divider value is ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 39 3 9 programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 26MHz/8.0 = 3.25MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overhead transmission. FIFO size is 4 x 8 for both RX and TX direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. An example of UART receiving or transmitting a single packet is shown in Figure 10-6. This example shows 7bit data (0x45), odd parity, and two stop bits. Refer to the ATBTLC1000 Programming Guide for more specific instructions. Figure 10-6. 10.6 Example of UART RX or TX Packet GPIOs 15 General Purpose Input/Output (GPIO) pins total, labeled LP_GPIO, GPIO_MS, and AO_GPIO, are available to allow for application specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output. The host or internal processor can program the output values. LP_GPIO are digital interface pins, GPIO_MS are mixed signal/analog interface pins, and AO_GPIO is an always-on digital interface pin that can detect interrupt signals while in deep sleep mode for wake-up purposes. The LP_GPIO have interrupt capability, but only when in active/standby mode. In sleep mode, they are turned off to save power consumption. 10.7 Analog to Digital Converter (ADC) 10.7.1 Overview The ATBTLC1000 has an integrated Successive Approximation Register (SAR) ADC with 11-bit resolution and variable conversion speed up 1MS/s. The key building blocks are the capacitive DAC, comparator, and synchronous SAR engine as shown in Figure 10-7. 40 ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 0 Figure 10-7. ATBTLC1000 SAR ADC Block Diagram The ADC reference voltage can be either generated internally or set externally via one of the two available Mixed Signal GPIO pins on the ATBTLC1000. There are two modes of operation: A. High resolution (11-bit): Set the reference voltage to half the supply voltage or below. In this condition the input signal dynamic range is equal to twice the reference voltage (ENOB=10bit). B. Medium Resolution (10-bit): Set the reference voltage to any value below supply voltage (up to supply voltage - 300mV) and in this condition, the input dynamic range is from zero to the reference voltage (ENOB = 9bit). Four input channels are time multiplexed to the input of the SAR ADC. However, on the ATBTLC1000, only two channel inputs are accessible from the outside, through pins 17 and 18 (Mixed Signal GPIO pins). In power saving mode, the internal reference voltage is completely off and the reference voltage is set externally. The ADC characteristics are summarized in Table 10-10. Table 10-10. SAR ADC Characteristics Conversion rate 1ks 1MS Selectable Resolution 10 11bit Power consumption 13.5A (at 100KS/s) (1) Note: 1. With external reference. 10.7.2 Timing The ADC timing is shown in Figure 10-8. The input signal is sampled twice, in the first sampling cycle the input range is defined either to be above reference voltage or below it and in the second sampling instant the ADC start its normal operation. The ADC takes two sampling instants and N-1 conversion cycle (N=ADC resolution) and one cycle to sample the data out. Therefore, for the 11-bit resolution, it takes 13 clock cycles to do one Sample conversion. The Input clock equals N+2 the sampling clock frequency (N is the ADC resolution). CONV signal : Gives indication about end of conversion. SAMPL : The input signal is sampled when this signal is high. RST ENG : When High SAR Engine is in reset mode (SAR engine output is set to mid-scale). ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 41 4 1 Figure 10-8. SAR ADC Timing 10.7.3 Performance Table 10-11. Static Performance of SAR ADC Parameter Condition Input voltage range Min. 0 Resolution 11 Sample rate 100 Max. Unit VBATT V bits 1000 KSPS Input offset Internal VREF -10 +10 mV Gain error Internal VREF -4 +4 % DNL 100KSPS. Internal VREF=1.6V. Same result for external VREF. -0.75 +1.75 LSB INL 100KSPS. Internal VREF=1.6V. Same result for external VREF. -2 +2.5 LSB THD 1kHz sine input at 100KSPS 73 dB SINAD 1kHz sine input at 100KSPS 62.5 dB SFDR 1kHz sine input at 100KSPS 73.7 dB 13 cycles Using external VREF, at 100KSPS 13.5 A Using internal VREF, at 100KSPS 25.0 A Using external VREF, at 1MSPS 94 A Using internal VREF, at 1MSPS 150 A Using internal VREF, during VBATT monitoring 100 A Using internal VREF, during temperature monitoring 50 Conversion time Current consumption A (1) Internal reference voltage Mean value using VBATT=2.5V 1.026 Standard deviation across parts 10.5 VBATT Sensor Accuracy Without calibration -55 +55 mV With offset and gain calibration -17 +17 mV Without calibration -9 +9 C Temperature Sensor 42 Typ. ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 2 V mV Parameter Accuracy Note: Condition Min. With offset calibration 1. -4 Typ. Max. Unit +4 C Effective VREF is 2xInternal Reference Voltage. = 250 = 3.0 , . Figure 10-9. INL of SAR ADC INL 100KS/s 3V internal reference 3 INL (LSB) 2 1 0 -1 0 500 1000 1500 2000 -2 -3 Output Code Figure 10-10. DNL of SAR ADC DNL 100KS/s 3V internal reference 2 INL (LSB) 1.5 1 0.5 0 -0.5 0 500 1000 1500 2000 -1 -1.5 Output Code ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 43 4 3 Figure 10-11. Sensor ADC Dynamic Measurement with Sinusoidal Input Notes: 1. 2. 25C, 3.6V VBATT, and 100kS/s Input signal: 1kHz sine wave, 3Vp-p amplitude SNDR = 62.5dB SFDR = 73.7dB THD = 73.0dB Figure 10-12. Sensor ADC Dynamic Performance Summary at 100KSPS Dynamic performance summary 74 SNR SNDR SFDR THD 72 70 68 dB 66 64 62 60 58 56 54 44 0 0.5 1 1.5 2 input signal frequency in Hz ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 4 2.5 3 4 x 10 10.8 Software Programmable Timer and Pulse Width Modulator ATBTLC1000 contains four individually configurable pulse width modulator (PWM) blocks to provide external control voltages. The base frequency of the PWM block (fPWM_base) is derived from the XO clock (26MHz) or the RC oscillator followed by a programmable divider. The frequency of each PWM pulse (fPWM) is programmable in steps according to the following relationship: _ = = 0,1,2, ... , 8 64 2 The duty cycle of each PWM signal is configurable with 10-bit resolution (minimum duty cycle is 1/1024 and the maximum is 1023/1024). can be selected to have different values according to Table 10-12. Minimum and maximum frequencies supported for each clock selection are listed in the table as well. Table 10-12. fPWM Range for Different fPWM Base Frequencies 10.9 fPWM max. fPWM min. 26MHz 406.25kHz 1.586kHz 13MHz 203.125kHz 793.25Hz 6.5MHz 101.562kHz 396.72Hz 3.25MHz 50.781kHz 198.36Hz Clock Output ATBTLC1000 has an ability to output a clock. The clock can be output to any GPIO pin via the test MUX. Note that this feature requires that the ARM and BLE power domains stay on. If BLE is not used, the clocks to the BLE core are gated off, resulting in small leakage. The following two methods can be used to output a clock. 10.9.1 Variable Frequency Clock Output Using Fractional Divider ATBTLC1000 can output the variable frequency ADC clock using a fractional divider of the 26MHz oscillator. This clock needs to be enabled using bit 10 of the lpmcu_clock_enables_1 register. The clock frequency can be controlled by the divider ratio using the sens_adc_clk_ctrl register (12-bits integer part, 8-bit fractional part).The division ratio can vary from 2 to 4096 delivering output frequency between 6.35kHz to 13MHz. This is a digital divider with pulse swallowing implementation so the clock edges may not be at exact intervals for the fractional ratios. However, it is exact for integer division ratios. 10.9.2 Fixed Frequency Clock Output ATBTLC1000 can output the following fixed-frequency clocks: 52MHz derived from XO 26MHz derived from XO 2MHz derived from the 2MHz RC Osc. 31.25kHz derived from the 2MHz RC Osc. 32.768kHz derived from the RTC XO 26MHz derived from 26MHz RC Osc. 6.5MHz derived from XO 3.25MHz derived from 26MHz RC Osc. For clocks 26MHz and above, ensure that external pad load on the board is minimized to get a clean waveform. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 45 4 5 10.10 Three-axis Quadrature Decoder ATBTLC1000 has a three-axis Quadrature decoder (X, Y, and Z) that can determine the direction and speed of movement on three axes, requiring in total six GPIO pins to interface with the sensors. The sensors are expected to provide pulse trains as inputs to the quadrature decoder. Each axis channel input will have two pulses with 90 degrees phase shift depending on the direction of movement. The decoder counts the edges of the two waveforms to determine the speed and uses the phase relationship between the two inputs to determine the direction of motion. The decoder is configured to interrupt ARM based on independent thresholds for each direction. Each quadrature clock counter (X, Y, and Z) is an unsigned 16-bit counter and the system clock uses a programmable sampling clock ranging from 26MHz, 13, 6.5, to 3.25MHz. If a wakeup is desired from threshold detection on an axis input, the always-on GPIO needs to be used (there is only one always-on GPIO on the ATBTLC1000). 46 ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 11 Reference Design ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 47 4 7 12 Bill of Material (BOM) 48 ATBTLC1000 QFN SoC [DATASHEET] 4 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 8 13 Electrical Characteristics There are voltage ranges where different VDDIO levels apply. The reason for this separation is for the IO drivers whose drive strength is directly proportional to the IO supply voltage. In the ATBTLC1000 products, there is a large gap in the IO supply voltage range (1.8 to 4.3v). A guarantee on drive strength across this voltage range would be intolerable to most vendors who only use a subsection of the IO supply range. As such, these voltages are segmented into three manageable sections referenced as VDDIO L, VDDIOM, and VDDIOH in tables listed in this document. 13.1 Absolute Maximum Ratings The values listed in this section are ratings that can be peaked by the device, but not sustained without causing irreparable damage to the device. Table 13-1. Symbol Characteristics Min. Max. Unit VDDIO I/O Supply Voltage -0.3 5.0 VBATT Battery Supply Voltage -0.3 5.0 VIN (1) Digital Input Voltage -0.3 VDDIO VAIN (2) Analog Input Voltage -0.3 1.5 VESDHBM (3) ESD Human Body Model -1000, -2000 (see notes below) +1000, +2000 (see notes below) TA Storage Temperature -65 150 Notes: 1. 2. 3. 13.2 ATBTLC1000 Absolute Maximum Ratings V C VIN corresponds to all the digital pins VAIN corresponds to all the analog pins, RFIO, VDD_RF, VDD_AMS, VDD_SXDIG, VDD_VCO, XO_N, XO_P, TPP, RTC_CLK_N, RTC_CLK_P For VESDHBM, each pin is classified as Class 1, or Class 2, or both: The Class 1 pins include all the pins (both analog and digital) The Class 2 pins include all digital pins only VESDHBM is 1kV for Class1 pins. VESDHBM is 2kV for Class2 pins Recommended Operating Conditions Table 13-2. Symbol ATBTLC1000 Recommended Operating Conditions Characteristic Min. Typ. Max. VDDIOL I/O Supply Voltage Low Range 1.62 1.80 2.00 VDDIOM I/O Supply Voltage Mid-Range 2.00 2.50 3.00 VDDIOH I/O Supply Voltage High Range 3.00 3.30 4.30 VBATT Battery Supply Voltage (1) 1.80 3.60 4.30 Operating Temperature -40 Unit V Note: 13.3 1. 2. 85 C VBATT must not be less than VDDIO. When powering up the device, VBATT must be greater or equal to 1.9V to ensure BOD does not trigger. BOD threshold is typically 1.8V and the device will be held in reset if VBATT is near this threshold on startup. After startup, BOD can be disabled and the device can operate down to 1.8V. DC Characteristics Table 13-3 provides the DC characteristics for the ATBTLC1000 digital pads. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 49 4 9 Table 13-3. VDDIO Condition ATBTLC1000 DC Electrical Characteristics Characteristic Min. Typ. Max. Input Low Voltage VIL -0.30 0.60 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 Unit VDDIOL Output Low Voltage VOL Output High Voltage VOH 0.45 VDDIO-0.50 Input Low Voltage VIL -0.30 0.63 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 VDDIOM Output Low Voltage VOL Output High Voltage VOH 0.45 VDDIO-0.50 Input Low Voltage VIL -0.30 0.65 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 (up to 3.60) VDDIOH Output Low Voltage VOL Output High Voltage VOH V 0.45 VDDIO-0.50 Output Loading 20 Digital Input Load 6 All pF Pad drive strength (regular pads (1)) 1.7 2.5 VDDIOM Pad drive strength (regular pads) 3.4 6.6 VDDIOH Pad drive strength (regular pads) 10.5 14 VDDIOL mA Pad drive strength (high-drive pads (1)) 3.4 5.0 VDDIOM Pad drive strength (high-drive pads) 6.8 13.2 VDDIOH Pad drive strength (high-drive pads) 21 28 VDDIOL Note: 50 1. The following are high-drive pads: GPIO_8, GPIO_9; all other pads are regular. ATBTLC1000 QFN SoC [DATASHEET] 5 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 0 14 Reflow Profile Information This section provides guidelines for reflow processes in getting the Atmel module soldered to the customer's design. 14.1 Storage Condition 14.1.1 Moisture Barrier Bag Before Opened A moisture barrier bag must be stored in a temperature of less than 30C with humidity under 85% RH. The calculated shelf life for the dry-packed product shall be 12 months from the date the bag is sealed. 14.1.2 Moisture Barrier Bag Open Humidity indicator cards must be blue, < 30%. 14.2 Stencil Design The recommended stencil is laser-cut, stainless-steel type with a thickness of 100m to 130m and approximately a 1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taper with bottom opening 25m larger than the top can be utilized. Local manufacturing experience may find other combinations of stencil thickness and aperture size to get good results. 14.3 Baking Conditions This module is rated at MSL level 3. After sealed bag is opened, no baking is required within 168 hours so long as the devices are held at <= 30 oC/60% RH or stored at <10% RH. The module will require baking before mounting if: The sealed bag has been open for > 168 hours. Humidity Indicator Card reads >10%. SIPs need to be baked for 8 hours at 125 oC. 14.4 Soldering and Reflow Condition 14.4.1 Reflow Oven It is strongly recommended that a reflow oven equipped with more heating zones and Nitrogen atmosphere be used for lead-free assembly. Nitrogen atmosphere has shown to improve the wet-ability and reduce temperature gradient across the board. It can also enhance the appearance of the solder joints by reducing the effects of oxidation. The following items should also be observed in the reflow process: 1. Some recommended pastes include NC-SMQ(R) 230 flux and Indalloy(R) 241 solder paste made up of 95.5 Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, no clean paste. 2. Allowable reflow soldering times: Three times based on the following reflow soldering profile (as shown in Figure 14-1). 3. Temperature profile: Reflow soldering shall be done according to the following temperature profile (as shown in Figure 14-1). 4. Peak temperature: 250C. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 51 5 1 Figure 14-1. Solder Reflow Profile Slope: 1~2oC/sec max. (217oC to peak) (Peak: 250oC) Ramp down rate: Max. 2.5oC/sec. o 217 C Preheat:150 ~ 200oC 60 ~ 120 sec. 25oC 52 Ramp up rate: Max. 2.5oC/sec. ATBTLC1000 QFN SoC [DATASHEET] 5 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 2 40 ~ 70 sec. Time (sec) 15 ERRATA Issue: The measured current for the cases listed in Figure 6-3 will be higher than what is reported in the figure. This is because the Power number values in the SDK4.0 release have not been fully optimized to their final values. A small sample measurement has been performed on 10 samples and they show the following results: Measurement condition: - 1-sec adverting interval 37 byte advertising payload Connectable beacon Advertising on three channels (37, 38, 39) VBATT and VDDIO are set to 3.3V SAM L21 has a measurement floor of 80nA, which was compensated in the reported numbers (this number varies from board to board and needs to be compensated). The Average advertising current: 11.3A The Average sleep current between beacons: 1.17A The average current for the 10 boards was (including 80nA floor): Sample # Average Current (A) 1 11.55 2 11.45 3 11.45 4 11.7 5 11.4 6 11.25 7 10.95 8 11.2 9 11.6 10 11.4 Workaround: Will be resolved in an SDK update. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 53 5 3 16 Reference Documentation and Support 16.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following table list documents available on Atmel website or integrated into development tools. Table 16-1. Reference Documents Title Content Datasheet This document ATBTLC1000 BluSDK: Hardware Design Guidelines ATBLTC1000 hardware design guide with references for placement and routing, external RTC, restrictions on power states, type of information. ATBTLC1000 BluSDK Release Package This package contains the software development kit and all the necessary documentation including getting started guides for interacting with different hardware devices, device drivers, and API call references. For a complete listing of development support tools and documentation, visit http://www.atmel.com/, or contact the nearest Atmel field representative. 54 ATBTLC1000 QFN SoC [DATASHEET] 5 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 4 17 Document Revision History Document Revision History Doc Rev. Date Comments 1. 2. 3. 4. 5. 6. 42409D 42409C 08/2016 Updated Power sequence figures and tables in section 6.4. Changed 26MHz Crystal ESR in Table 7-1. Updated Chip POD drawing to include solder pad in Figure 5-1. Revised fpwm minimum frequency values in Table 10-12. Added RTC clocks to Absolute Maximum Ratings Table 13-1. Revised Features/Peripherals first page: 1). Removed Agency reference since this device does not have an antenna. 2). 95dBm Programmable receiver, 3.) Peak RX current, and 4). GPIO information. 7. Supplemented GPIO pin descriptions in Table 4-1. 8. Added GPIO state behavior section 6.6. 9. Revised resistor pull direction in Table 10-1. 10. Revised SPI Slave Timing info in Table 10-7. 11. Revised SPI Master Timing info in Table 10-8. 12. Revised SPI Flash Master Timing Info in Table 10-9. 13. Revised VDDIO current values in Table 6-2. 14. Added Reflow section 14. 15. Revised Absolute Maximum Ratings section 13.1. 16. Revised values in Receiver Performance in Table 9-1. 17. Clarified section 10.5 to describe the UART pins better. 18. Added Document Reference section 16. 19. Updated section 13 to clarify VDDIOL, VDDIOM, and VDDIOH ratings. 20. Corrected section 14 reflow iterations. 21. Changed VBAT to VBATT for consistency. 01/2016 1. Updated numbers in feature list. 2. Added UART flow control to LP_GPIO Pins in Table 4-1. 3. Removed 1H Row and updated cap and ripple values in Figure 6-2. 4. Updated BLE on Transmit/BLE on Receive values in Table 6-2. 5. Updated text in describing BOD handling in Section 6.5. 6. Removed BGR block from diagram in Figure 6-6. 7. Added Table 6-5 for Brownout Thresholds and POR time in Table 6-4. 8. Updated oscillator variations in Sections 7.1, 7.4, and Figure 7-9. 9. Removed Supply Pins row in Table 7-5. 10. Updated Table 9-2 TX peak current values in Table 9-2. 11. Updated Reference Design. In Section 11. 12. Updated BOM. In Section 12. 13. Added note 2, in Table 13-2. 14. Removed reference Table 12-3 in title in Table 13-3. 15. Revised Sensitivity values in the Features, Section 7.1, and 7.4. 16 Added text to Section 7.1 regarding BLE sleep and connections. 17. Updated Figure 7-2 and Figure 7-3. 18. Revised Table 6-2 for consistency. 19. Added Errata area. ATBTLC1000 QFN SoC [DATASHEET] Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 55 5 5 Doc Rev. 56 Date Comments 42409B 09/2015 1. Updated current numbers in the feature list. 2. Updated current numbers and added comments in Table 6-2. 3. Updated advertising current chart in Figure 6-4. 4. Updated capacitance value in Section 7.2. 5. Updated voltage value in Table 7-3. 6. Updated capacitance value and text in Section 7.3.1. 7. Added 32kHz RC Oscillator performance charts in Section 7.4. 8. Updated Receiver performance numbers and comments in Table 9-1. 9. Updated Transmitter performance numbers and comments in Table 9-2. 10. Updated ADC power consumption and added comment in Table 10-10. 11. Replaced the whole ADC performance Table 10-11. 12. Replaced ADC performance charts: Figure 10-9 and Figure 10-10. 13. Added new ADC performance charts: Figure 10-11 and Figure 10-12. 14. BTLC1000 corrected to ATBTLC1000. 42409A 09/2015 Initial document release ATBTLC1000 QFN SoC [DATASHEET] 5 Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 6 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 www.atmel.com (c) 2016 Atmel Corporation. / Rev.: Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016. 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SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in conne ction with any applications where the failure of such products would reasonably be expected to result in significant perso nal injury or death ("Safety-Critical Applications") without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation o f nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically desi gnated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade. Atmel-42409D-ATBTLC1000-QFN-SoC_Datasheet_08/2016 ATBTLC1000 QFN SoC [DATASHEET] 57 5 7