Advance Product Brief
April 2003
MRC2G13
Multirate CDR (MRC) Serializer/Deserializer Macro
Features
■Designed for SONET/SDH OC-3, OC-12, and
OC-48, and 1 Gigabit Ethernet (GbE) applications.
■Meets the SONET OC-3/12/48 jitter generation,
tolerance, and tra ns fer spec if ic ations .
■Selectable data rate:
— 155 Mbits/s.
— 622 Mbits/s.
— 1.2 5 Gbits/s.
— 2.488 Gbits/s.
■155.52 MHz reference clock frequency for SONET
and SDH and 125 MHz clock for GbE.
■Parallel I/O interface:
— 16 bit for OC-48.
— 4 bit for OC-12.
— 1 bit for OC-3.
— 20 bit for GbE.
■Programmable control and configuration interface
to define the various device configurations.
■Automatic lock-to-reference in absence of receive
data.
■CML high-speed interface I/O for use with back-
plane or cable media. Input tolerance of higher
voltages for support of optical transceiver inter-
faces.
■Multiple output amplitude modes for reduced
power consumption in chip-to-chip applications.
■1.2 V ± 5% power supply and 3.3 V ± 5% power
supply for the receiver.
Applications
■SONET OC-3.
■SONET OC-12.
■SONET OC-48.
■SDH.
■IEEE ® 802.3-2002 gigabit Ethernet.
Description
The MRC2G13 is a high-speed serializer/deserializer
(SerDes) macr ocell. This macrocell includ es a cur-
rent mode logic (CML) high-speed serial interface
and uses a proprietary CDR architecture. The specifi-
cations are targeted at devices that directly drive
OC-3, OC-12, and OC-48 small form-factor plugga-
ble (SFP) optical transceivers. The macrocell can
also drive small form-factor (SFF) pin through-hole
optical transceivers and one gigabit optical transceiv-
ers for Ethernet.
Modular Macrocell
■Consists of the following five smaller blocks:
— PLL.
— Transmit channel block (Tx).
— Receive channel block (Rx).
— Refere nce clock block.
— Voltage reference block.
■Initial configuration is 16 channels of OC-3/12 of
which four can run independently at OC-48. Other
configurations are available upon request.
■A channel is defined as one receiver and one
transmitter.
Interfaces
■High speed: current mode logic (CML) with ac and
dc coupling, and LV DS compatibility. LVPECL com-
patibility re quire s som e off-chi p comp one nts.
■Parallel data: CMOS selectable between 16 bit for
OC-48, 20 bit for 1GE, 4 bit for OC-12, and 1 bit for
OC-3.
■Registers and control logic: a four-line serial inter-
face, allowing each channel to be addressed indi-
vidually with minimal routing.
22 Agere Systems Inc.
Advance Product Brief
April 2003
Multirate CDR (MRC) Serializer/Deserializer Macro
MRC2G13
Reset
■Resets any macro or any Rx/Tx block within the
device.
■Includes a power-on-reset circuit within the macros.
This circuit is used solely to reset the SerDes blocks
within a macro after a powerup event. (No external
access to the output of this circuit is provided.)
Independent Power Down
■Independent user-selectable power down of the fol-
lowing:
— PLL.
— CML buffers.
— Individual transmit blocks.
— Individual receive blocks.
Power Consumption
■2.3 W for 16 channels of OC-12.
■730 mW for 4 channels of OC-48.
Phase-Locked Loop (PLL)
■PLL is based on an L C oscillator.
■PLL relock without reset: the PLL can relock without
requiring a reset (e.g., after switching reference
clocks).
■PLL lock indicator is provided.
Transmitter
■Each transmit (Tx) block serializes a parallel data
word with a width of 16 bits, 20 bits, 4 bits, or 1 bit,
depending on the control register setting.
■The Tx block transforms the parallel input word into a
serial data stream by using a high-speed clock that is
synthesized from the Tx reference clock by the PLL.
Transmit Pre-Emphasis
■The transmit block output buffer can be programmed
through the serial register interface to select between
no pre-emphasis and one of four levels of pre-
emphasis.
■Pre-emphasis boosts the high frequencies in the
transmitted data to compensate for losses present in
backplanes, therefore, extending the useful range of
transmission.
Reduced Amplitude Output
■The Tx block output buffer can be programmed
through the serial interface to provide one of four dif-
ferent levels of output amplitude: 1.0 V, 0.85 V, 0.7 V,
and 0.55 V.
■These amplitude modes meet most standard require-
ments and allow chip-to-chip applications and other
less stringent applications to reduce the power con-
sumption.
Receiver
■The receive block (Rx) transforms a high-speed
serial bit stream into a stream of parallel words, and
recovers a high-speed clock from the serial data.
■The receive block (Rx) further divides this clock
down to provide a clock that has a frequency equal
to the parallel word rate and that is phase-aligned to
the word boundary.
■The CDR block that forms the core of the receiver is
a proprietary design that results in significant power
and area savings.
■The Rx block input buffers are 3.3 V tolerant to han-
dle LVPECL inputs from SFF transceivers.
Agere Systems Inc. 3
Advance Product Brief
April 2003 Multirat e CDR (MRC ) Seri ali zer/D e serializer Ma cro
MRC2G13
Testability
■Allows tes tabili ty within the AS IC.
■Test modes are not encoded, allowing mixing and
matching of test modes.
■Self-synchronizing PRBS compatible with Agilent ®
and Anritsu ® bit error rate test systems.
■Internal loopback for parallel and serial data for Rx/
Tx macro option.
■Independent transmit and receive built-in self-test.
Digital Library Interface
Standard digital library interface allowing digital blocks
from the Agere library or custom blocks to be inte-
grated into the device.
Examples include PRBS, link state machine, 8b/10b
encoder, byte aligner, and custom blocks.
Figure 1. TSRD212G5 Block Diagram
CLOCK
DIVIDER VC FREQUENCY
DETECTOR
LOCK
DETECTOR
LP
DATA
RETIMING
VARIABLE
1:4, 10:16
MUX
RATE_SEL[1:0]
LPF_A/
DAT DATA
XCLK
REFCLK
16
2
CLOCK
DIVIDER
VCFREQUENCY
DETECTOR
LOCK
DETECTOR
LP
DATA
RETIMING
VARIABLE
1:4, 10:16
DEMUX
LPF_A/
RCLK DATA
RCLK
16
2
RATE
DETECT
RATE_SEL[1:0]
PHAS E AND
DIN 2SFP
LO
BIAS
REX
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright © 2003 Agere Systems Inc.
All Rights Reserved
April 2003
PB03-108SRDS
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