WINC1500-MR210PB DATASHEET
IEEE 802.11 b/g/n IoT Module
Datasheet
Description
The ATWINC1500-MR210PB is a low-power consumption 802.11 b/g/n IoT
(Internet of Things) module which is specifically optimized for low power IoT
applications. The highly integrated module features small form factor (21.5mm x
14.5mm x 2.1mm) while fully integrating Power Amplifier, LNA, Switch, Power
Management, and PCB antenna. With seamless roaming capabilities and
advanced secur ity, it could be interoperab le wit h vario us vendor s’ 802 .11 b/g/n
Access P oints in wireless LAN . The module provides SPI and UART to interface to
host controller.
Features
• IEEE® 802.11 b/g/n 20MHz (1x1) solution
• Single spatial stream in 2.4GHz ISM band
• Integrated PA and T/R Switch
• Integrated PCB antenna
• Superior Sens iti vity and Range via advanc ed PH Y sig nal proc es s ing
• Advanced Equalization and Channel Estimation
• Advanced Carrier and Timing Synchronization
• Wi-Fi Direct and Soft-AP support
• Supports IEEE 802.11 WEP, WPA, WPA2 Security
• Supports China WAPI security
• Superior MAC throughput via hardware accelerated two-level
A-MSDU/A-MPDU frame aggregation and block acknowledgement
• On-chip memory management engine to reduce host load
• SPI, UART, and I2C host interfaces
• 2- or 3-wire Bluetooth® coexistence interface
• Operating temperature range of -40°C to +85°C
• I/O operating voltage of 2.7V to 3.6V
• Integrated Flash memory for system software
• Power Save Modes
– <4µA Power Down mode typical @3.3V I/O
– 380µA Doze mode with chip settings preserved (used for beacon monitoring)1
1See Power Consumption for module power modes.
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– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or SPI transaction
• Fast Boot Options
– On-Chip Boot ROM (Firmware i nstant boot)
– SPI flash boot (firmware patches and state variables)
– Low-leakage on-chip memory for state variables
– Fast AP Re-Association (150ms)
• On-Chip Network Stack to offload MCU
– Integrated Network IP stack to minimize host CPU requirements
– Network features TCP, UDP, DHCP, ARP, HTTP, SSL, and DNS
• Hardware accelerators for WiFi and SSL security to improve connection time
• Hardware accelerator for IP checksum
• Hardware accelerators for OTA security
• Small footprint host driver (4KB flash – less than 1KB RAM)
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Table of Contents
Description 1
Features 1
Table of Contents ............................................................................................................... 3
1 Ordering Information and Module Marking ................................................................ 5
2 Block Diagram ............................................................................................................. 5
3 Pinout Information ....................................................................................................... 7
3.1 Pin Description ...................................................................................................................................... 7
3.2 Module Outline Drawing ........................................................................................................................ 9
4 Electrical Specifications ........................................................................................... 10
4.1 Absolute Ratings ................................................................................................................................. 10
4.2 Recommended Operating Conditions ................................................................................................. 11
5 CPU and Memory Subsystems ................................................................................. 11
5.1 Processor ............................................................................................................................................ 11
5.2 Memory Subsystem............................................................................................................................. 11
5.3 Non-Volatile Memory (eFuse) ............................................................................................................. 11
6 WLAN Subsystem ...................................................................................................... 12
6.1 MAC 12
6.1.1 Features ................................................................................................................................. 12
6.1.2 Description .............................................................................................................................. 13
6.2 PHY 13
6.2.1 Features ................................................................................................................................. 13
6.2.2 Description .............................................................................................................................. 13
6.3 Radio 14
6.3.1 Receiver Performance ............................................................................................................ 14
6.3.2 Transmitter Performance ........................................................................................................ 16
7 External Interfaces .................................................................................................... 17
7.1 SPI Interface ....................................................................................................................................... 17
7.1.1 Overview................................................................................................................................. 17
7.1.2 SPI Timing .............................................................................................................................. 17
7.2 UART Interface ................................................................................................................................... 19
7.3 Wi-Fi/Bluetooth Coexistence ............................................................................................................... 19
8 Power Consumption .................................................................................................. 20
8.1 Description of Device States ............................................................................................................... 20
8.2 Current Consumption in Various Device States .................................................................................. 20
8.3 Restrictions for Power States .............................................................................................................. 21
8.4 Power-Up/Down Sequence ................................................................................................................. 21
8.5 Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 22
9 Notes On Interfacing to the ATWINC1500-MR210PB .............................................. 23
9.1 Programmable Pull Up Resistors ........................................................................................................ 23
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10 Recommended Footprint (Unit: mm) ........................................................................ 24
11 RF Performance Placement Guidelines ................................................................... 24
12 Recommended Reflow Profile .................................................................................. 25
13 Module Schematic ..................................................................................................... 26
14 Module Bill of Materials (BOM) ................................................................................. 28
15 Application Schematic .............................................................................................. 29
16 Reference Documentation and Support................................................................... 30
16.1 Reference Documents ......................................................................................................................... 30
17 Revision History ........................................................................................................ 31
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1 Ordering Information and Module Marking
Table 1-1. Ordering Details
Ordering Code
Package
Description
ATWINC1500-MR210PB
22x15mm
Certified module with ATWINC1500B chip and PCB antenna
ATWINC1500-MR210UB
22x15mm
Certified module with ATWINC1500B chip and uFL connector
ATWINC1510-MR210PB 22x15mm
Certified module with ATWINC1510B chip (8Mb Flash) and
PCB antenna
Figure 1-1. Marking Information
2 Block Diagram
Figure 2-1. Block Diagram of the Module
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3 Pinout Information
3.1 Pin Description
Figure 3-1. Pin Assignment
GPIO_6
Table 3-1. Pin Description
NO Name Type Description
Pull-up Resistor
1
GPIO_6
I/O
General purpo se I/O .
2 I2C_SCL I/O
I2C Slave Clock. Currently used only for Atmel debug. Not for
customer use. Leave unconnected. Yes
3 I2C_SDA I/O
I2C Slave Data. Currently used only for Atmel debug. Not for cus-
tomer use. Leave unconnected. Yes
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NO Name Type Description
Pull-up Resistor
4 RESET_N I
Active-Low Hard Reset. When asserted to a low level, the module
will be placed in a reset state. When asserted to a high level, the
module will run normally. Connect to a host output that defaults
low at power up. If the host output is tri-stated, add a 1MΩ
pull-down resistor to ensure a low level at power up.
No
5
NC
-
No connect
6
NC
-
No connect
7 NC - No connect
8
NC
-
No connect
9
GND_1
-
GND
10 SPI_CFG I Tie to VDDIO through a 1MΩ resistor to enable the SPI interface No
11 WAKE I
Host Wak e contr ol. Ca n be us ed to w ake up th e modul e fro m Doz e
mode. Connect to a host GPIO. Yes
12
GND_2
-
GND
13 IRQN O
ATWINC1500-MR210P Device Interrupt output. Connect to host
interrupt input pin. Yes
14
UART_TXD
O
UART Transmit Output from ATWINC1500-MR210P
15 SPI_RXD I SPI MOSI (Master Out Slave In) pin Yes
16
SPI_SSN
I
SPI Slave Select. Active low
17
SPI_TXD
O
SPI MISO (Master In Slave Out) pin
18
SPI_SCK
I
SPI Clock
19
UART_RXD
I
UART Receive input to ATWINC1500-MR210P
20 VBATT - Battery power supply
21
GPIO_1/RTC
I
General Purpose I/O / RTC
22 CHIP_EN I
Module enable. High level enables module, low level places mod-
ule in Power Down mode. Connect to a host Output that defaults
low at power up. If the host output is tri-stated, add a 1MΩ
pull-down resistor to ensure a low level at power up.
No
23
VDDIO
-
I/O Power Supply. Must match host I/O voltage.
24
1P3V_TP
-
1.3V VDD Core Test Point. Leave unconnected.
25
GPIO_3
I/O
General purpo se I/O
26 GPIO_4 I/O General purpose I/O Yes
27
GPIO_5
I/O
General purpo se I/O
28
GND_3
-
GND
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3.2 Module Outline Draw ing
Figure 3-2. Module Drawings – WINC1500-MR210PB - Top and Bottom Views (unit = mm)
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Figure 3-3. Module Drawings – WINC1500-MR210UB - Top and Bottom Views (unit = mm)
4 Electrical Specifications
4.1 Absolute Ratings
Table 4-1. Voltages
Symbol
Max.
Unit
VBATT
5.0
V
VDDIO
4.6
V
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4.2 Recommended Operating Conditions
Table 4-2. Recommended Operating Conditions
Test conditions: -40ºC - +85ºC
Symbol
Max.
Unit
VBATT
4.2
V
VDDIO
3.6
V
5 CPU and Memory Subsystems
5.1 Processor
ATWINC1500B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of operation,
such as STA and AP modes.
5.2 Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data RAM.
ATWINC1500B also has 4Mb of flash memory, which can be used for system software. In addition, the device
uses a 128KB shared RAM, accessible by the processor and MAC, which allows the APS3 core to perform
various data management tasks on the TX and RX data packets.
5.3 Non-Volatile Memory (eFuse)
ATWINC1500B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This
non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such as
MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other
software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the
same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and the
remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank can
be programmed independently, this allows for several updates of the device parameters following the initial
programming, e.g. updating MAC address. Refer to ATWINC1500-MR210PB Programming Guide for the eFuse
programming instructions.
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Figure 5-1. eFuse Bit Map
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
FMAC ADDR
Used
Invalid
Version
Reserved
MAC ADDR
Used
FO
Flags
G
3
1 1 4 1
Used
TX
Gain
Correc
tion
Used
Freq.
Offset
1 7
48
8816
1 15
128 Bits
6 WLAN Subsyst e m
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
6.1 MAC
6.1.1 Features
The ATWINC1500-MR210PB IEEE802.11 MAC supports the following functions:
• IEEE 802.11b/g/n
• IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling
• Advanced IEEE 802.11n features:
– Transmission and reception of aggregated MPDUs (A-MPDU)
– Transmission and reception of aggregated MSDUs (A-MSDU)
– Immediate Block Acknowledgement
– Reduced Interframe Spacing (RIFS)
• Support for IEEE802.11i and WFA security with key management
– WEP 64/128
– WPA-TKIP
– 128-bit WPA2 CCMP (AES)
• Support for WAPI security
• Advanced power management
– Standard 802 .11 Po wer Sa ve Mode
– Wi-Fi Alliance WMM-PS (U-APSD)
• RTS-CTS and CTS-self support
• Supports either STA or AP mode in the infrastructure basic service set mode
• Supports independent basic service set (IBSS)
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6.1.2 Description
The ATWINC1500B MAC is designed to operate at low power while providing high data throughput. The IEEE
802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable
processor provides optimal power efficiency and real-time response while providing the flexibility to
accommodate evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement data path functions with heavy computational. For example,
an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs all the
required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI security
requirements.
Control functions which have real-time requirements are implemented using hardwired control logic modules.
These logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon T X
control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module,
aggregation/de-aggregation module, block ACK controller (implements the protocol requirements for burst block
communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher
engine, and the DMA interface to the TX/RX FIFOs).
The MAC functions implemented solely in software on the microprocessor have the following characteristics:
• Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing.
• Functions with low computational load or without critical real-time requirements. Examples are
authentication and association.
• Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling.
6.2 PHY
6.2.1 Features
The ATWINC1500B IEEE802.11 PHY supports the following functions:
• Single antenna 1x1 stream in 20MHz channels
• Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps
• Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18 , 24, 36, 48, 54Mbps
• Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0,
14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps
• IEEE 802.11n mixed mode operation
• Per packet TX power control
• Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and
frame detection
6.2.2 Description
The ATWINC1500BWLAN PHY is designed to achieve reliable and power-efficient physical layer communication
specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced algorithms have been
employed to achieve maximum throughput in a real world communication environment with impairments and
interference. The PHY implements all the required functions such as FFT, filtering, FEC (Viterbi decoder),
frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear
channel assessment, as well as the automatic gain control.
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6.3 Radio
Table 6-1. Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25ºC
Feature
Description
Module Part Number
ATWINC1500-MR210PB
WLAN Standard
IEEE 802.11b/g/n, Wi-Fi complia nt
Host Interface
SPI, UART
Dimension
L x W x H: 21.72 x 14.73 x 3.5 (typical) mm
Frequency Range
2.412GHz ~ 2.4835GHz (2.4GHz ISM Band)
Number of Channe ls
11 for North America, 13 for Europe, and 14 for Japan
Modulation 802.11b : DQPSK, DBPSK, CCK
802.11g/n : OFDM /64-QAM,16-QAM, QPSK, BPSK
Data Rate 802.11b : 1, 2, 5.5, 11Mbps
802.11g : 6, 9, 12, 18, 24, 36, 48, 54Mbps
Data Rate
(20MHz ,normal GI,800ns) 802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps
Data Rate
(20MHz ,short GI,400ns) 802.11n : 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65,72.2Mbps
Operating temperature2
-40°C to 85°C
Storage temperature -40°C to 85°C
Humidity
Operating Humidity 10% to 95% Non-Condensing
Storage Humidity 5% to 95% Non-Condensing
6.3.1 Receiver Performance
Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25°C.
Table 6-2. Receiver Performance
Parameter
Description
Unit
Minimum
Typical
Maximum
Frequency
MHz
2,412
2,484
Sensitivity
802.11b
1Mbps DSS
dBm
-98
2Mbps DSS
dBm
-94
5.5Mbps DSS
dBm
-92
11Mbps DSS
dBm
-88
Sensitivity
802.11g
6Mbps OFDM
dBm
-90
9Mbps OFDM dBm -89
12Mbps OFDM
dBm
-88
18Mbps OFDM
dBm
-85
24Mbps OFDM dBm -83
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Parameter
Description
Unit
Minimum
Typical
Maximum
36Mbps OFDM
dBm
-80
48Mbps OFDM
dBm
-76
54Mbps OFDM
dBm
-74
Sensitivity
802.11n
(BW=20MHz)
MCS 0
dBm
-89
MCS 1
dBm
-87
MCS 2
dBm
-85
MCS 3 dBm -82
MCS 4
dBm
-77
MCS 5
dBm
-74
MCS 6 dBm -72
MCS 7
dBm
-70.5
Maximum Receive
Signal Level
1-11Mbps DSS
dBm
0
6-54Mbps OFDM
dBm
0
MCS 0 – 7
dBm
0
Adjacent Channel
Rejection
1Mbps DSS (30MHz offset) dB 50
11Mbps DSS (25MHz offset)
dB
43
6Mbps OFDM (25MHz offset)
dB
40
54Mbps OFDM (25MHz offset) dB 25
MCS 0 – 20MHz BW (25MHz offset)
dB
40
MCS 7 – 20MHz BW (25MHz offset)
dB
20
Cellular Blocker Im-
munity
776-794MHz CDMA
dBm
-14
824-849MH z G SM
dBm
-10
880-915MH z G SM
dBm
-10
1710-1785MHz GS M
dBm
-15
1850-1910MHz GSM
dBm
-15
1850-1910M Hz WCDMA
dBm
-24
1920-1980MHz WCDMA
dBm
-24
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6.3.2 Transmitter Performance
Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25°C.
Table 6-3. Transmitter Performance
Parameter
Description
Unit
Minimum
Typical
Maximum
Frequency
MHz
2,412
2,484
Output Power1,
ON_Transmit_High_Power Mode
802.11b 1Mbps
dBm
18.5
802.11b 11Mbps
dBm
19.5
802.11g 6Mbps
dBm
18.5
802.11g 54Mbps
dBm
16.5
802.11n MCS 0
dBm
17.0
802.11n MCS 7 dBm 14.5
Output Power1,
ON_Transmit_Low_Power Mode
802.11b 1Mbps
dBm
17.0
802.11b 11Mbps
dBm
17.5
802.11g 6-18Mbps dBm 16.0
802.11g >18Mbps
dBm
N/A
802.11n MCS 0-3
dBm
14.5
802.11n >MCS 3
dBm
N/A
Tx Power Accuracy
dB
±1.52
Carrier Suppression dBc 30.0
Out of Band Transmit Power
76-108
dBm/Hz
-125
776-794
dBm/Hz
-125
869-960 dBm/Hz -125
925-960
dBm/Hz
-125
1570-1580
dBm/Hz
-125
1805-1880
dBm/Hz
-125
1930-1990
dBm/Hz
-125
2110-2170
dBm/Hz
-125
Harmonic Output Power
2nd
dBm/MHz
-41
3rd
dBm/MHz
-41
Notes: 1. Measured at 802.11 spec compliant EVM/Spectral Mask.
2. Measured after RF matching network. See reference design.
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7 External Interfaces
7.1 SPI Interface
7.1.1 Overview
ATWINC1500-MR210PB has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface
can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in T able 7-1. The
SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10
(SPI_CFG) is tied to VDDIO.
Table 7-1. SPI Interface Pin Mapping
Pin #
SPI Function
10
CFG: Must be tie d to VDDIO
16
SSN: Active Low Slave Select
15
MOSI(RXD): Serial Data Receive
18
SCK: Serial Clock
17
MISO(TXD): Serial Data Transmit
W hen the SPI is not selected, i.e., whe n SSN is high, t he SPI inter f ac e will not inter f ere with data transf er s
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buff er ed, result ing in a high im pedanc e driv e onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as
well as initiate DMA transfers.
The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC1500-MR210PB have internal programmable pull-up
resistors (See Section 9.1). These resistors should be programmed to be disabled. Otherwise, if any of the SPI
pins are driven to a low level while the ATWINC1500-MR210PBis in the low power sleep state, current will flow
from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
7.1.2 SPI Timing
The SPI timing is provided in Figure 7-1 and Table 7-2.
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Figure 7-1. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
tLH
SCK
TXD
RXD
SSN
tWH
tHL
tWL
tODLY
tISU tIHD
fSCK
tSSODLY
SSN
tSUSSN tHDSSN
SPI Master
SPI Slave
Table 7-2. SPI Slave Timing Parameters
Parameter
Symbol
Min
Max
Units
Remarks
Clock Input Frequency
f
SCK
48
MHz
Clock Low Pulse Width
t
WL
5
ns
Clock High Pulse Width
t
WH
5
ns
Clock Rise Time
t
LH
5
ns
Clock Fall Time
t
HL
5
ns
Input Setup Time
t
ISU
5
ns
Input Hold Time
t
IHD
5
ns
Output Delay
t
ODLY
0
20
ns
Slave Select Setup Time
t
SUSSN
5
ns
Slave Select Hold Time
t
HDSSN
5
ns
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7.2 UART Interface
The ATWINC1500-MR210PB has a Universal Asynchronous Receiver/Transmitter (UART) interface available
on pins 14 and 19. It can be used for control or data transfer if the baud rate is sufficient for a given application.
The UART is compatible with the RS-232 standard, where ATWINC1500-MR210PB operates as Data Terminal
Equipment (DTE). It has a two-pin RXD/TXD interface.
The UART features programmable baud rate generation with fractional clock division, which allows transmission
and reception at a wide var iety of standard and non-standard baud rates. The UART input clock is selectable
between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and
3 fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the
maximum supported baud rate of 10MHz/8.0 = 1.25MBd.
The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types
(odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable
high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx direction.
The UART also has status registers showing the number of received characters available in the FIFO and
various error conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in F igur e 7-2. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
See the ATWINC1500-MR210PB Programming Guide for information on configuring the UART.
Figure 7-2. Example of UART Rx of Tx Packet
7.3 Wi-Fi/Bluetooth Coexistence
ATWINC1500-MR210PB supports 2-w ire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the
IEEE 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2 or 3 wire) is chosen to be
compatible with the specific Bluetooth device used in a given application. Coexistence interface can be enabled
on the following pins: GPIO_1, GPIO_3, GPIO_4, GPIO_5, GPIO_6, I2C_SCL, I2C_SDA – each of these pins
can be configured for any function of the coexistence interface. Table 7-3 shows a usage example of the 2-wire
interface using the GPIO_3 and GPIO_4 pins; 3-wire interface using the GPIO_3, GPIO_4, and GPIO_5 pins; for
more specific instructions on configuring Coexistence refer to ATWINC1500-MR210PB Programming Guide.
Table 7-3. Coexistence Pin Assignment Example
Pin Name
Pin #
Function
Target
2-wire
3-wire
GPIO_3 25 BT_Req
BT is requesting to access the medium to transmit or
receive. Goes high on TX or RX slot Used Used
GPIO_4 26 WL_Act
Device response to the BT request. High - BT_req is
denied and BT slot blocked. Used Used
GPIO_5 27 BT_Pri
Priority of the BT packets in the requested slot. High to
indicate high priority and low for normal. Not Used Used
GPIO_6
1
Ant_SW
Direct control on Antenna (coex bypass)
Optional
Optional
ATWINC1500-MR210P [DATASHEET]
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8 Power Cons um pt ion
8.1 Description of Device States
ATWINC1500-MR210PB has several Devices States:
• ON_Transmit_High_Power – Device is actively transmitting an 802.11 signal. Highest output power and
nominal current consumption
• ON_Transmit_Low_Power – Device is actively transmitting an 802.11 signal. Reduced output power and
reduced current consumption
• ON_Receive_High_Power – Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal
current consumption
• ON_Receive_Low_Power – Device is actively receiving an 802.11 signal. Degraded sensitivity and
reduced current consumption
• ON_Doze – Device is on but is neither transmitting nor receiving
• Power_Down – Device core supply off (Leakage)
• IDLE connect – Device is connected with 1 DTIM beacon interval
The following pins are used to switch between the ON and Power_Down states:
• CHIP_EN – Device pin (pin #2 2) used to enable DC/DC Converter
• VDDIO – I/O supply voltage from external supply
In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between the ON states
and Power_Down state CHIP_EN has to change between high and low (GND) voltage. When VDDIO is off and
CHIP_EN is low, the chip is powered off with no leakage (also see Section 8.3).
8.2 Current Consumption in Var i ous Device States
Table 8-1. Current Consumption
Device State Code Rate Output
Power, dBm
Current Consumption1,2
I
VBATT
I
VDDIO
ON_Transmit_High_Power
802.11b 1Mbps
19.5
294mA
22mA
802.11b 11Mbps
20.5
290mA
22mA
802.11g 6Mbps
19.5
292mA
22mA
802.11g 54Mbps
17.5
250mA
22mA
802.11n MCS 0
18.0
289mA
22mA
802.11n MCS 7 15.5 244mA 22mA
ON_Transmit_Low_Power
802.11b 1Mbps
18,0
233mA
2mA
802.11b 11Mbps
18.5
231mA
2mA
802.11g 6-18Mbps 17.0 146mA 2mA
802.11g >18Mbps
N/A
N/A
N/A
802.11n MCS 0-3
15.5
132mA
2mA
802.11n >MCS 3
N/A
N/A
N/A
ON_Receive_High_Power
802.11b 1Mbps
N/A
52.5mA
22mA
ATWINC1500-MR210PB [DATASHEET]
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Device State
Code Rate
Output
Current Consumption1,2
802.11b 11Mbps
N/A
52.5 mA
22 mA
802.11g 6Mbps
N/A
55.0 mA
22 mA
802.11g 54Mbps
N/A
57.5 mA
22 mA
802.11n MCS 0
N/A
54.0 mA
22 mA
802.11n MCS 7
N/A
58.5 mA
22 mA
ON_Receive_Low_Power
802.11b 1Mbps
N/A
63.5 mA
2.4 mA
802.11b 11Mbps N/A 64.2 mA 2.4 mA
802.11g 6Mbps
N/A
65.4 mA
2.4 mA
802.11g 54Mbps
N/A
65.4 mA
2.4 mA
802.11n MCS 0 N/A 65.6 mA 2.4 mA
802.11n MCS 7
N/A
70.1mA
2.4 mA
ON_Doze
N/A
N/A
380µA
<10µA
Power_Down
N/A
N/A
<0.5µA
<3.5µA
Notes: 1. Conditions: VBATT @ 3.6V, VDDIO@ 3.3V, Temp 25°C
8.3 Restrictions for Power States
When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground
potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode
from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be
on, so the SLEEP or Power_Down state must be used.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
8.4 Power-Up/Down Sequence
The power-up/down sequence for ATWINC1500-MR210PB is shown in Figure 8-1. The timing parameters are
provided in Table 8-2.
ATWINC1500-MR210P [DATASHEET]
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Figure 8-1. Power Up/Down Sequence
VBATT
VDDIO
CHIP_EN
RESETN
t
A
t
B
t
C
XO Clock
t
B'
t
A'
t
C'
Table 8-2. Power-Up/Down Sequence Timing
Parameter
Min
Max
Units
Description
Notes
tA 0 ms VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously
or can be tied together. VDDIO must not
rise before VBAT T .
tB 0 ms VDDIO rise t o CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not
left floating.
tC 5 ms CHIP_EN rise to RESETN rise
This delay is needed because XO clock
must stabilize before RESETN removal.
RESET N must be driven high or low , not lef t
floating.
tA’ 0 ms VDDIO fall to VBATT fall
VBATT and VDDIO can fall simultaneously
or can be tied together. VBATT must not fall
before VDDIO.
tB’ 0 ms CHIP_EN fal l to VDDIO fall
VDDIO must not fall before CHIP_EN.
CHIP_EN and RESETN can fall simultane-
ously.
tC’ 0 ms RESETN fall to V DDIO fall
VDDIO must not fall before RESETN.
RESETN and CHIP_EN can fall simultane-
ously.
8.5 Digital I/O Pin Behavi or during Power-Up Sequences
Table 8-3 represents digital IO Pin states corresponding to device power modes.
Table 8-3. Digital I/O Pin Behavior in Different Device States
Device State VDDIO CHIP_EN RESETN
Output
Driver
Input
Driver
Pull-Up/Down
Resistor (96kΩ)
Power Down:
core supply off High Low Low Disabled (Hi-Z) Disabled Disabled
ATWINC1500-MR210PB [DATASHEET]
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Device State VDDIO CHIP_EN RESETN
Output
Driver
Input
Driver
Pull-Up/Down
Resistor (96kΩ)
Power-On Reset:
core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled
Power-On Default:
core supply on, device out of
reset but not progr ammed yet High High High Disabled (Hi-Z) Enabled Enabled
On Sleep/
On Transmit/
On Receive:
core supply on, devic e
programmed by firmware
High High High
Programmed by
firmware for
each pin:
Enabled or
Disabled
Opposite
of Output
Driver
state
Programmed by
firmware for
each pin:
Enabled or
Disabled
9 Notes On Int e rfacing to the ATWINC1 5 0 0 -MR210PB
9.1 Programmable Pull Up Resistors
The ATWINC1500-MR210PB provides programmable pull-up resistors on various pins. The purpose of these
resistors is to keep any unused input pins from floating which can cause excess current to flow through the input
buffer from the VDDIO supply. Any unused module pin on the ATWINC1500-MR210PB should leave these
pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be
enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if
any pins are driven to a low level while the ATWINC1500-MR210PB is in the low power sleep state, current will
flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
Since the value of the pull-up resistor is approximately 100KΩ, the current through any pull-up resistor that is
being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that is driven
low would be approximately 3.3V/100K = 33µA. Pins which are used and have had the programmable pull-up
resistor disabled should always be actively driven to either a high or low level and not be allowed to float.
See the ATWINC1500-MR210PB Programming Guide for information on enabling/disabling the programmable
pull up resistors.
ATWINC1500-MR210P [DATASHEET]
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10 Recomme nded Foot print ( Unit: mm )
Figure 10-1. Footprint Drawing
11 RF Performance Placement Guideli nes
It is critical to follow the recommendations listed below to achieve the best RF performance:
• Module must be placed on main board - printed antenna area must overlap with the carrier board. The
portion of the module containing the antenna should not stick out over the edge of the main board. The
antenna is de-signed to work properly when it is sitting directly on top of a 1.5mm thick printed circuit board.
• If the module is placed at the edge of the main board, a minimum 22mm by 5mm area directly under the
antenna must be clear of all metal on all layers of the board. “In-land” placement is acceptable; however
deepness of keep-out area must grove to: module edge to main board edge plus 5mm. DO NOT PLACE
MODULE IN THE MIDDLE OF THE MAIN BOARD OR FAR AWAY FROM THE MAIN BOARD EDGE.
• Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking.
• Do not enclose the antenna within a metal shield.
• Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band far
away from the antenna or better yet, shield those components. Any noise radiated from the main board in
this frequency band will degrade the sensitivity of the module.
• Contact Atmel for assistance if any other placement is required.
ATWINC1500-MR210PB [DATASHEET]
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12 Recomme nded Re f low Profil e
Referred to IPC/JEDEC standard. Peak Temperature: <25 0°C .
Number of Times: two times max imum.
Figure 12-1. Typical Reflow Profile
ATWINC1500-MR210P [DATASHEET]
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13 Modul e Sche m a tic
Figure 13-1. ATWINC1500-MR210PB Schematic
ATWINC1500-MR210PB [DATASHEET]
Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015
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Figure 13-2. ATWINC1500-MR210UB Schematic
ATWINC1500-MR210P [DATASHEET]
Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015
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14 Modul e Bill of Material s (BOM)
Table 14-1. ATWINC1500-MR210PB BOM
WiFi shielded module with discrete balun and printed antenna.
ATWINC1500-MR210PB
Item Qty Reference Value Description Manufacturer Part Num be r Footprint
1 2 C5,C12 1.0uF CAP,CER,1.0uF,20%,X5R,0402,6.3V Panasonic ECJ-0EB0J105M CS0402
2 7
C2,C3,C4,C8,C9,
C10, C11
0.1uF CAP,CER,0.1uF,10%,X5R,0402,10V AVX 0402ZD104KAT2A CS0402
3 1 C25 4.7uF CAP CER 4.7UF 4V 20% X5R 0402 Murata GRM155R60G475ME47D CS0402
4 2 C23,C24 1pF CAP CER 1PF 50V NP0 0201 Murata
GRM0335C1H1R0CA01D CS0201
5 2 C6,C7 10PF CAP CER 10PF 50V 1% NP0 0402 Murata
GRM1555C1H100FA01D CS0402
6 2 C15,C16 1.8PF CAP CER 1.8PF 50V NP0 0201 Murata
GRM0335C1H1R8CA01D CS0201
7 1 C20 1.2PF CAP CER 1.2PF 50V NP0 0201 Murata
GRM0335C1H1R2CA01D CS0201
8 1 C21 0RES 0.0 OHM 1/20W JUMP 0201 SMD Panasonic
ERJ-1GN0R00C RS0201
9C18,C22 DNI
10 1 C1 1.0uF CAP CER 1UF 4V 20% X6S 0201 Murata
GRM033C80G105MEA2D CS0201
11 3FB1,FB2,FB3 BLM15AG121SN1 FERRITE,120 OHM @100MHz,0402 Murata BLM15AG121SN1 FBS0402
12 1FB4
BLM03AG121SN1D FERRITE BEAD 120 OHM 200MA 0201 Murata BLM03AG121SN1D FBS0201
13 1L1 2.2uH POWER INDUCTOR,2.2uH,20%,750mA,0.3ohms,0603 Murata LQM18PN2R2MFRL LPS0603
14 1L4 15nH INDUCTOR 15NH 300MA 0402 Murata
LQG15HS15NJ02D LS0402
15 2L2,L5 3.3nH INDUCTOR 3.3+/-0.2NH 750MA 0201 Murata
LQP03TN3N3C02D LS0201
16 1R2 3.3PF CAP,CER,3.3pF,NPO,0402,50V Murata GRM1555C1H3R3CA01 CS0402
17 1U1 ATWINC1500B-MU-T IC, WiFi, 40QFN Atmel ATWINC1500B-MU-T 40QFN
18 1Y1 26.000MHz CRYSTAL 26MHZ 10PF SMD Abracon
ABM10-26.000MHZ-D30-T3 4 SMD
19 1PCB (Blue 21.7 x 14.7mm)
ATWINC1500-MR210PB
20 1RF SHIELD (12.70 x 13.66 x 1.3 mm)
ATWINC1500-MR210PB [DATASHEET]
Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015
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15 Application Schematic
Table 15-1. Application Schematic
ATWINC1500-MR210P [DATASHEET]
Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015
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16 Refer e nc e Doc umenta t ion and Support
16.1 Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
The following list of documents available on Atmel web or integrated into development tools.
Title
Content
Datasheet
This Document
Design Files
Package User Guide, Schematic, PCB layout, Gerber, BOM & System notes on: RF/Radio Full Test Report,
radiation patt ern, des ign gui de line s, temp erature performanc e, ESD.
Platform Getting
Started Guide How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guide-
lines.
HW Design
Guide
Best practices and recommendations to design a board with the product,
Including: Ant enn a Design f or Wi-Fi (layout recommendations, types of antennas, impedance match-
ing, using a power amplifier etc), SPI/UART protocol between Wi-Fi SoC and the Host MCU.
SW Design
Guide
Integration guide with clear description of: High level Arch, overview on how to write a networking
application, list all API, parameters and structures.
Features of the device, SPI/handshake protocol between device and host MCU, with
flow/sequence/state diagram, timing.
SW Program-
mer Guide
Explain in detail s the flow chart and how to use eac h API to i mpleme nt all gen eric use case s (e.g. start
AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer
recovery mechanism/state diagram) - usage & sampl e App note
For a complete listing of development-support tools & documentation, visit http://www.atmel.com/, or contact the
nearest Atmel field representative.
ATWINC1500-MR210PB [DATASHEET]
Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015
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17 Revisi on History
Doc Rev.
Date
Comments
42502A 07/2015
Updated due to changes from WINC1500A to WINC1500B:
1. Updated power numbers and description, added high-power and low-power modes
2. Updated radio performance numbers
4. Updated reference schematic and pin list to add GPIOs 3,4,5,6
5. Fixed typos in SPI interfac e t iming
6. Added hardware accelerators in feature list (security and checksum)
7. Increased instruction RAM size from 128KB to 160KB
8. Improved and corrected description of Coexistence interface
9. Miscellaneous minor updates and corrections
ATWINC1500-MR210P [DATASHEET]
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Atmel Co rporation 1600 Technology Driv e, S an Jos e, CA 951 10 U SA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015.
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