WINC1500-MR210PB DATASHEET IEEE 802.11 b/g/n IoT Module Datasheet Description The ATWINC1500-MR210PB is a low-power consumption 802.11 b/g/n IoT (Internet of Things) module which is specifically optimized for low power IoT applications. The highly integrated module features small form factor (21.5mm x 14.5mm x 2.1mm) while fully integrating Power Amplifier, LNA, Switch, Power Management, and PCB antenna. With seamless roaming capabilities and advanced security, it could be interoperable with various vendors' 802.11b/g/n Access Points in wireless LAN. The module provides SPI and UART to interface to host controller. Features * IEEE 802.11 b/g/n 20MHz (1x1) solution (R) * Single spatial stream in 2.4GHz ISM band * Integrated PA and T/R Switch * Integrated PCB antenna * Superior Sensitivity and Range via advanced PHY signal processing * Advanced Equalization and Channel Estimation * Advanced Carrier and Timing Synchronization * Wi-Fi Direct and Soft-AP support * Supports IEEE 802.11 WEP, WPA, WPA2 Security * Supports China WAPI security * Superior MAC throughput via hardware accelerated two-level A-MSDU/A-MPDU frame aggregation and block acknowledgement * On-chip memory management engine to reduce host load * SPI, UART, and I C host interfaces 2 * 2- or 3-wire Bluetooth coexistence interface (R) * Operating temperature range of -40C to +85C * I/O operating voltage of 2.7V to 3.6V * Integrated Flash memory for system software * Power Save Modes - <4A Power Down mode typical @3.3V I/O - 380A Doze mode with chip settings preserved (used for beacon monitoring)1 1 See Power Consumption for module power modes. Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 - On-chip low power sleep oscillator - Fast host wake-up from Doze mode by a pin or SPI transaction * Fast Boot Options - On-Chip Boot ROM (Firmware instant boot) - SPI flash boot (firmware patches and state variables) - Low-leakage on-chip memory for state variables - Fast AP Re-Association (150ms) * On-Chip Network Stack to offload MCU - Integrated Network IP stack to minimize host CPU requirements - Network features TCP, UDP, DHCP, ARP, HTTP, SSL, and DNS * Hardware accelerators for WiFi and SSL security to improve connection time * Hardware accelerator for IP checksum * Hardware accelerators for OTA security * Small footprint host driver (4KB flash - less than 1KB RAM) 2 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Ta bl e of Conte nts Description 1 Features 1 Table of Contents ............................................................................................................... 3 1 Ordering Information and Module Marking................................................................ 5 2 Block Diagram ............................................................................................................. 5 3 Pinout Information....................................................................................................... 7 3.1 3.2 4 Electrical Specifications ........................................................................................... 10 4.1 4.2 5 6.2 6.3 7.2 7.3 12 Features ................................................................................................................................. 12 Description.............................................................................................................................. 13 13 Features ................................................................................................................................. 13 Description.............................................................................................................................. 13 14 Receiver Performance ............................................................................................................ 14 Transmitter Performance ........................................................................................................ 16 SPI Interface ....................................................................................................................................... 17 7.1.1 Overview................................................................................................................................. 17 7.1.2 SPI Timing .............................................................................................................................. 17 UART Interface ................................................................................................................................... 19 Wi-Fi/Bluetooth Coexistence ............................................................................................................... 19 Power Consumption .................................................................................................. 20 8.1 8.2 8.3 8.4 8.5 9 MAC 6.1.1 6.1.2 PHY 6.2.1 6.2.2 Radio 6.3.1 6.3.2 External Interfaces .................................................................................................... 17 7.1 8 Processor ............................................................................................................................................ 11 Memory Subsystem............................................................................................................................. 11 Non-Volatile Memory (eFuse) ............................................................................................................. 11 WLAN Subsystem ...................................................................................................... 12 6.1 7 Absolute Ratings ................................................................................................................................. 10 Recommended Operating Conditions ................................................................................................. 11 CPU and Memory Subsystems ................................................................................. 11 5.1 5.2 5.3 6 Pin Description ...................................................................................................................................... 7 Module Outline Drawing ........................................................................................................................ 9 Description of Device States ............................................................................................................... 20 Current Consumption in Various Device States .................................................................................. 20 Restrictions for Power States .............................................................................................................. 21 Power-Up/Down Sequence ................................................................................................................. 21 Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 22 Notes On Interfacing to the ATWINC1500-MR210PB .............................................. 23 9.1 Programmable Pull Up Resistors ........................................................................................................ 23 ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 3 10 Recommended Footprint (Unit: mm) ........................................................................ 24 11 RF Performance Placement Guidelines ................................................................... 24 12 Recommended Reflow Profile .................................................................................. 25 13 Module Schematic ..................................................................................................... 26 14 Module Bill of Materials (BOM) ................................................................................. 28 15 Application Schematic .............................................................................................. 29 16 Reference Documentation and Support................................................................... 30 16.1 Reference Documents......................................................................................................................... 30 17 Revision History ........................................................................................................ 31 4 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 1 Ordering Information and Module Marking Table 1-1. Ordering Code Package Description ATWINC1500-MR210PB 22x15mm Certified module with ATWINC1500B chip and PCB antenna ATWINC1500-MR210UB 22x15mm Certified module with ATWINC1500B chip and uFL connector ATWINC1510-MR210PB 22x15mm Certified module with ATWINC1510B chip (8Mb Flash) and PCB antenna Figure 1-1. 2 Ordering Details Marking Information Block Diagram Figure 2-1. Block Diagram of the Module ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 5 6 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 3 Pinout Information 3.1 Pin Description Pin Assignment Table 3-1. Pin Description GPIO_6 Figure 3-1. NO Name Type Description Programmable Pull-up Resistor 1 GPIO_6 I/O General purpose I/O. Yes 2 I2C_SCL I/O I C Slave Clock. Currently used only for Atmel debug. Not for customer use. Leave unconnected. 3 I2C_SDA I/O I C Slave Data. Currently used only for Atmel debug. Not for customer use. Leave unconnected. 2 Yes 2 Yes ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 7 NO 8 Name Type Description Programmable Pull-up Resistor 4 RESET_N I Active-Low Hard Reset. When asserted to a low level, the module will be placed in a reset state. When asserted to a high level, the module will run normally. Connect to a host output that defaults low at power up. If the host output is tri-stated, add a 1M pull-down resistor to ensure a low level at power up. 5 NC - No connect 6 NC - No connect 7 NC - No connect 8 NC - No connect 9 GND_1 - GND 10 SPI_CFG I Tie to VDDIO through a 1M resistor to enable the SPI interface No 11 WAKE I Host Wake control. Can be used to wake up the module from Doze mode. Connect to a host GPIO. Yes 12 GND_2 - GND 13 IRQN O ATWINC1500-MR210P Device Interrupt output. Connect to host interrupt input pin. Yes 14 UART_TXD O UART Transmit Output from ATWINC1500-MR210P Yes 15 SPI_RXD I SPI MOSI (Master Out Slave In) pin Yes 16 SPI_SSN I SPI Slave Select. Active low Yes 17 SPI_TXD O SPI MISO (Master In Slave Out) pin Yes 18 SPI_SCK I SPI Clock Yes 19 UART_RXD I UART Receive input to ATWINC1500-MR210P Yes 20 VBATT - Battery power supply 21 GPIO_1/RTC I General Purpose I/O / RTC Yes No No 22 CHIP_EN I Module enable. High level enables module, low level places module in Power Down mode. Connect to a host Output that defaults low at power up. If the host output is tri-stated, add a 1M pull-down resistor to ensure a low level at power up. 23 VDDIO - I/O Power Supply. Must match host I/O voltage. 24 1P3V_TP - 1.3V VDD Core Test Point. Leave unconnected. 25 GPIO_3 I/O General purpose I/O 26 GPIO_4 I/O General purpose I/O Yes 27 GPIO_5 I/O General purpose I/O Yes 28 GND_3 - GND ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 3.2 Module Outline Drawing Figure 3-2. Module Drawings - WINC1500-MR210PB - Top and Bottom Views (unit = mm) ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 9 Figure 3-3. Module Drawings - WINC1500-MR210UB - Top and Bottom Views (unit = mm) 4 Electrical Specifications 4.1 Absolute Ratings Table 4-1. 10 Voltages Symbol Description Min. Max. Unit VBATT Input supply Voltage -0.3 5.0 V VDDIO I/O Voltage -0.3 4.6 V ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 4.2 Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Test conditions: -40C - +85C Symbol Min. Typ. Max. Unit VBATT 3.0 3.6 4.2 V VDDIO 2.7 3.3 3.6 V 5 CPU and Memory Subsystems 5.1 Processor ATWINC1500B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions, including but not limited to association, authentication, power management, security key management, and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of operation, such as STA and AP modes. 5.2 Memory Subsystem The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data RAM. ATWINC1500B also has 4Mb of flash memory, which can be used for system software. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows the APS3 core to perform various data management tasks on the TX and RX data packets. 5.3 Non-Volatile Memory (eFuse) ATWINC1500B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and the remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank can be programmed independently, this allows for several updates of the device parameters following the initial programming, e.g. updating MAC address. Refer to ATWINC1500-MR210PB Programming Guide for the eFuse programming instructions. ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 11 Bank 0 F 7 8 48 G MAC ADDR 1 15 Freq. Offset Reserved Version Flags 8 1 Used 1 TX Gain Correc tion 4 3 Used 1 Invalid Used 1 eFuse Bit Map MAC ADDR Used Figure 5-1. 16 FO Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 128 Bits 6 WLAN Subsystem The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The following two subsections describe the MAC and PHY in detail. 6.1 MAC 6.1.1 Features The ATWINC1500-MR210PB IEEE802.11 MAC supports the following functions: * IEEE 802.11b/g/n * IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling * Advanced IEEE 802.11n features: - * 12 Transmission and reception of aggregated MPDUs (A-MPDU) - Transmission and reception of aggregated MSDUs (A-MSDU) - Immediate Block Acknowledgement - Reduced Interframe Spacing (RIFS) Support for IEEE802.11i and WFA security with key management - WEP 64/128 - WPA-TKIP - 128-bit WPA2 CCMP (AES) * Support for WAPI security * Advanced power management - Standard 802.11 Power Save Mode - Wi-Fi Alliance WMM-PS (U-APSD) * RTS-CTS and CTS-self support * Supports either STA or AP mode in the infrastructure basic service set mode * Supports independent basic service set (IBSS) ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 6.1.2 Description The ATWINC1500B MAC is designed to operate at low power while providing high data throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable processor provides optimal power efficiency and real-time response while providing the flexibility to accommodate evolving standards and future feature enhancements. Dedicated datapath engines are used to implement data path functions with heavy computational. For example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI security requirements. Control functions which have real-time requirements are implemented using hardwired control logic modules. These logic modules offer real-time response while maintaining configurability via the processor. Examples of hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off timing, timing synchronization function, and slot management), MPDU handling module, aggregation/de-aggregation module, block ACK controller (implements the protocol requirements for burst block communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher engine, and the DMA interface to the TX/RX FIFOs). The MAC functions implemented solely in software on the microprocessor have the following characteristics: * Functions with high memory requirements or complex data structures. Examples are association table management and power save queuing. * Functions with low computational load or without critical real-time requirements. Examples are authentication and association. * Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS scheduling. 6.2 PHY 6.2.1 Features The ATWINC1500B IEEE802.11 PHY supports the following functions: 6.2.2 * Single antenna 1x1 stream in 20MHz channels * Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps * Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps * Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps * IEEE 802.11n mixed mode operation * Per packet TX power control * Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and frame detection Description The ATWINC1500BWLAN PHY is designed to achieve reliable and power-efficient physical layer communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC (Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control. ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 13 6.3 Radio Table 6-1. Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25C Feature Description Module Part Number ATWINC1500-MR210PB WLAN Standard IEEE 802.11b/g/n, Wi-Fi compliant Host Interface SPI, UART Dimension L x W x H: 21.72 x 14.73 x 3.5 (typical) mm Frequency Range 2.412GHz ~ 2.4835GHz (2.4GHz ISM Band) Number of Channels 11 for North America, 13 for Europe, and 14 for Japan Modulation 802.11b : DQPSK, DBPSK, CCK 802.11g/n : OFDM /64-QAM,16-QAM, QPSK, BPSK 802.11b : 1, 2, 5.5, 11Mbps Data Rate 802.11g : 6, 9, 12, 18, 24, 36, 48, 54Mbps Data Rate (20MHz ,normal GI,800ns) 802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps Data Rate (20MHz ,short GI,400ns) 802.11n : 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65,72.2Mbps 2 6.3.1 Operating temperature -40C to 85C Storage temperature -40C to 85C Humidity Operating Humidity 10% to 95% Non-Condensing Storage Humidity 5% to 95% Non-Condensing Receiver Performance Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25C. Table 6-2. Parameter Receiver Performance Description Frequency Sensitivity 802.11b Sensitivity 802.11g 14 Unit Minimum MHz 2,412 Typical 2,484 1Mbps DSS dBm -98 2Mbps DSS dBm -94 5.5Mbps DSS dBm -92 11Mbps DSS dBm -88 6Mbps OFDM dBm -90 9Mbps OFDM dBm -89 12Mbps OFDM dBm -88 18Mbps OFDM dBm -85 24Mbps OFDM dBm -83 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Maximum Parameter Sensitivity 802.11n (BW=20MHz) Maximum Receive Signal Level Adjacent Channel Rejection Cellular Blocker Immunity Description Unit Minimum Typical 36Mbps OFDM dBm -80 48Mbps OFDM dBm -76 54Mbps OFDM dBm -74 MCS 0 dBm -89 MCS 1 dBm -87 MCS 2 dBm -85 MCS 3 dBm -82 MCS 4 dBm -77 MCS 5 dBm -74 MCS 6 dBm -72 MCS 7 dBm -70.5 1-11Mbps DSS dBm 0 6-54Mbps OFDM dBm 0 MCS 0 - 7 dBm 0 1Mbps DSS (30MHz offset) dB 50 11Mbps DSS (25MHz offset) dB 43 6Mbps OFDM (25MHz offset) dB 40 54Mbps OFDM (25MHz offset) dB 25 MCS 0 - 20MHz BW (25MHz offset) dB 40 MCS 7 - 20MHz BW (25MHz offset) dB 20 776-794MHz CDMA dBm -14 824-849MHz GSM dBm -10 880-915MHz GSM dBm -10 1710-1785MHz GSM dBm -15 1850-1910MHz GSM dBm -15 1850-1910MHz WCDMA dBm -24 1920-1980MHz WCDMA dBm -24 Maximum ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 15 6.3.2 Transmitter Performance Radio Performance under Typical Conditions: VBATT=3.3V; VDDIO=3.3V; Temp: 25C. Table 6-3. Transmitter Performance Parameter Description Frequency Unit Minimum MHz 2,412 Typical 2,484 802.11b 1Mbps dBm 18.5 802.11b 11Mbps dBm 19.5 802.11g 6Mbps dBm 18.5 802.11g 54Mbps dBm 16.5 802.11n MCS 0 dBm 17.0 802.11n MCS 7 dBm 14.5 802.11b 1Mbps dBm 17.0 802.11b 11Mbps dBm 17.5 802.11g 6-18Mbps dBm 16.0 802.11g >18Mbps dBm N/A 802.11n MCS 0-3 dBm 14.5 802.11n >MCS 3 dBm N/A Tx Power Accuracy dB 1.5 Carrier Suppression dBc 30.0 76-108 dBm/Hz -125 776-794 dBm/Hz -125 869-960 dBm/Hz -125 925-960 dBm/Hz -125 1570-1580 dBm/Hz -125 1805-1880 dBm/Hz -125 1930-1990 dBm/Hz -125 2110-2170 dBm/Hz -125 1 Output Power , ON_Transmit_High_Power Mode 1 Output Power , ON_Transmit_Low_Power Mode Maximum 2 Out of Band Transmit Power 2 nd dBm/MHz -41 3 rd dBm/MHz -41 Harmonic Output Power Notes: 16 1. 2. Measured at 802.11 spec compliant EVM/Spectral Mask. Measured after RF matching network. See reference design. ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 7 External Interfaces 7.1 SPI Interface 7.1.1 Overview ATWINC1500-MR210PB has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 7-1. The SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10 (SPI_CFG) is tied to VDDIO. Table 7-1. SPI Interface Pin Mapping Pin # SPI Function 10 CFG: Must be tied to VDDIO 16 SSN: Active Low Slave Select 15 MOSI(RXD): Serial Data Receive 18 SCK: Serial Clock 17 MISO(TXD): Serial Data Transmit When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line. The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC1500-MR210PB have internal programmable pull-up resistors (See Section 9.1). These resistors should be programmed to be disabled. Otherwise, if any of the SPI pins are driven to a low level while the ATWINC1500-MR210PBis in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module. 7.1.2 SPI Timing The SPI timing is provided in Figure 7-1 and Table 7-2. ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 17 Figure 7-1. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0) fSCK tLH tWH SCK tWL tHL TXD t ODLY RXD tISU SSN SPI Master tSSODLY SSN SPI Slave Table 7-2. 18 tIHD t SUSSN t HDSSN SPI Slave Timing Parameters Parameter Symbol Clock Input Frequency f SCK Clock Low Pulse Width t WL 5 ns Clock High Pulse Width t WH 5 ns Clock Rise Time t LH 5 ns Clock Fall Time t HL 5 ns Input Setup Time t ISU 5 ns Input Hold Time t IHD 5 ns Output Delay t ODLY 0 Slave Select Setup Time t SUSSN 5 ns Slave Select Hold Time t HDSSN 5 ns ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Min Max Units 48 MHz 20 ns Remarks 7.2 UART Interface The ATWINC1500-MR210PB has a Universal Asynchronous Receiver/Transmitter (UART) interface available on pins 14 and 19. It can be used for control or data transfer if the baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where ATWINC1500-MR210PB operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface. The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and 3 fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 10MHz/8.0 = 1.25MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. An example of UART receiving or transmitting a single packet is shown in Figure 7-2. This example shows 7-bit data (0x45), odd parity, and two stop bits. See the ATWINC1500-MR210PB Programming Guide for information on configuring the UART. Figure 7-2. 7.3 Example of UART Rx of Tx Packet Wi-Fi/Bluetooth Coexistence ATWINC1500-MR210PB supports 2-wire and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2 or 3 wire) is chosen to be compatible with the specific Bluetooth device used in a given application. Coexistence interface can be enabled on the following pins: GPIO_1, GPIO_3, GPIO_4, GPIO_5, GPIO_6, I2C_SCL, I2C_SDA - each of these pins can be configured for any function of the coexistence interface. Table 7-3 shows a usage example of the 2-wire interface using the GPIO_3 and GPIO_4 pins; 3-wire interface using the GPIO_3, GPIO_4, and GPIO_5 pins; for more specific instructions on configuring Coexistence refer to ATWINC1500-MR210PB Programming Guide. Table 7-3. Pin Name Coexistence Pin Assignment Example Pin # Function Target 2-wire 3-wire GPIO_3 25 BT_Req BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot Used Used GPIO_4 26 WL_Act Device response to the BT request. High - BT_req is denied and BT slot blocked. Used Used GPIO_5 27 BT_Pri Priority of the BT packets in the requested slot. High to indicate high priority and low for normal. Not Used Used GPIO_6 1 Ant_SW Direct control on Antenna (coex bypass) Optional Optional ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 19 8 Power Consumption 8.1 Description of Device States ATWINC1500-MR210PB has several Devices States: * ON_Transmit_High_Power - Device is actively transmitting an 802.11 signal. Highest output power and nominal current consumption * ON_Transmit_Low_Power - Device is actively transmitting an 802.11 signal. Reduced output power and reduced current consumption * ON_Receive_High_Power - Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal current consumption * ON_Receive_Low_Power - Device is actively receiving an 802.11 signal. Degraded sensitivity and reduced current consumption * ON_Doze - Device is on but is neither transmitting nor receiving * Power_Down - Device core supply off (Leakage) * IDLE connect - Device is connected with 1 DTIM beacon interval The following pins are used to switch between the ON and Power_Down states: * CHIP_EN - Device pin (pin #22) used to enable DC/DC Converter * VDDIO - I/O supply voltage from external supply In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between the ON states and Power_Down state CHIP_EN has to change between high and low (GND) voltage. When VDDIO is off and CHIP_EN is low, the chip is powered off with no leakage (also see Section 8.3). 8.2 Current Consumption in Various Device States Table 8-1. Current Consumption 1,2 Device State Output Power, dBm Code Rate Current Consumption I VBATT I VDDIO 802.11b 1Mbps 19.5 294mA 22mA 802.11b 11Mbps 20.5 290mA 22mA 802.11g 6Mbps 19.5 292mA 22mA 802.11g 54Mbps 17.5 250mA 22mA 802.11n MCS 0 18.0 289mA 22mA 802.11n MCS 7 15.5 244mA 22mA 802.11b 1Mbps 18,0 233mA 2mA 802.11b 11Mbps 18.5 231mA 2mA 802.11g 6-18Mbps 17.0 146mA 2mA 802.11g >18Mbps N/A N/A N/A 802.11n MCS 0-3 15.5 132mA 2mA 802.11n >MCS 3 N/A N/A N/A 802.11b 1Mbps N/A 52.5mA 22mA ON_Transmit_High_Power ON_Transmit_Low_Power ON_Receive_High_Power 20 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Device State Code Rate Output 1,2 Current Consumption 802.11b 11Mbps N/A 52.5 mA 22 mA 802.11g 6Mbps N/A 55.0 mA 22 mA 802.11g 54Mbps N/A 57.5 mA 22 mA 802.11n MCS 0 N/A 54.0 mA 22 mA 802.11n MCS 7 N/A 58.5 mA 22 mA 802.11b 1Mbps N/A 63.5 mA 2.4 mA 802.11b 11Mbps N/A 64.2 mA 2.4 mA 802.11g 6Mbps N/A 65.4 mA 2.4 mA 802.11g 54Mbps N/A 65.4 mA 2.4 mA 802.11n MCS 0 N/A 65.6 mA 2.4 mA 802.11n MCS 7 N/A 70.1mA 2.4 mA ON_Doze N/A N/A 380A <10A Power_Down N/A N/A <0.5A <3.5A ON_Receive_Low_Power Notes: 8.3 1. Conditions: VBATT @ 3.6V, VDDIO@ 3.3V, Temp 25C Restrictions for Power States When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on, so the SLEEP or Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. 8.4 Power-Up/Down Sequence The power-up/down sequence for ATWINC1500-MR210PB is shown in Figure 8-1. The timing parameters are provided in Table 8-2. ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 21 Figure 8-1. Power Up/Down Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC t C' RESETN XO Clock Table 8-2. 8.5 Power-Up/Down Sequence Timing Parameter Min tA tB Max Units Description Notes 0 ms VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT. 0 ms VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. tC 5 ms CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. t A' 0 ms VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. t B' 0 ms CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. t C' 0 ms RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. Digital I/O Pin Behavior during Power-Up Sequences Table 8-3 represents digital IO Pin states corresponding to device power modes. Table 8-3. 22 Digital I/O Pin Behavior in Different Device States Device State VDDIO CHIP_EN RESETN Output Driver Input Driver Pull-Up/Down Resistor (96k) Power Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Device State VDDIO CHIP_EN RESETN Output Driver Input Driver Pull-Up/Down Resistor (96k) Power-On Reset: core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, device out of reset but not programmed yet High High High Disabled (Hi-Z) Enabled Enabled High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled On Sleep/ On Transmit/ On Receive: core supply on, device programmed by firmware High High 9 Notes On Interfacing to the ATWINC1500-MR210PB 9.1 Programmable Pull Up Resistors The ATWINC1500-MR210PB provides programmable pull-up resistors on various pins. The purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the VDDIO supply. Any unused module pin on the ATWINC1500-MR210PB should leave these pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if any pins are driven to a low level while the ATWINC1500-MR210PB is in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module. Since the value of the pull-up resistor is approximately 100K, the current through any pull-up resistor that is being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that is driven low would be approximately 3.3V/100K = 33A. Pins which are used and have had the programmable pull-up resistor disabled should always be actively driven to either a high or low level and not be allowed to float. See the ATWINC1500-MR210PB Programming Guide for information on enabling/disabling the programmable pull up resistors. ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 23 10 Recommended Footprint (Unit: mm) Figure 10-1. 11 Footprint Drawing RF Performance Placement Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: 24 * Module must be placed on main board - printed antenna area must overlap with the carrier board. The portion of the module containing the antenna should not stick out over the edge of the main board. The antenna is de-signed to work properly when it is sitting directly on top of a 1.5mm thick printed circuit board. * If the module is placed at the edge of the main board, a minimum 22mm by 5mm area directly under the antenna must be clear of all metal on all layers of the board. "In-land" placement is acceptable; however deepness of keep-out area must grove to: module edge to main board edge plus 5mm. DO NOT PLACE MODULE IN THE MIDDLE OF THE MAIN BOARD OR FAR AWAY FROM THE MAIN BOARD EDGE. * Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking. * Do not enclose the antenna within a metal shield. * Keep any components which may radiate noise or signals within the 2.4GHz - 2.5GHz frequency band far away from the antenna or better yet, shield those components. Any noise radiated from the main board in this frequency band will degrade the sensitivity of the module. * Contact Atmel for assistance if any other placement is required. ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 12 Recommended Reflow Profile Referred to IPC/JEDEC standard. Peak Temperature: <250C. Number of Times: two times maximum. Figure 12-1. Typical Reflow Profile ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 25 13 Module Schematic Figure 13-1. 26 ATWINC1500-MR210PB Schematic ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 Figure 13-2. ATWINC1500-MR210UB Schematic ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 27 14 Module Bill of Materials (BOM) Table 14-1. ATWINC1500-MR210PB BOM WiFi shielded module with discrete balun and printed antenna. ATWINC1500-MR210PB Item Qty 1 2 2 3 4 7 1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 2 1 1 28 1 3 1 1 1 2 1 1 1 1 1 Reference Value Description Manufacturer Part Number Footprint C5,C12 C2,C3,C4,C8,C9, C10, C11 C25 C23,C24 1.0uF CAP,CER,1.0uF,20%,X5R,0402,6.3V Panasonic ECJ-0EB0J105M CS0402 0.1uF 4.7uF 1pF CAP,CER,0.1uF,10%,X5R,0402,10V CAP CER 4.7UF 4V 20% X5R 0402 CAP CER 1PF 50V NP0 0201 AVX Murata Murata 0402ZD104KAT2A GRM155R60G475ME47D GRM0335C1H1R0CA01D CS0402 CS0402 CS0201 Murata Murata Murata Panasonic GRM1555C1H100FA01D GRM0335C1H1R8CA01D GRM0335C1H1R2CA01D ERJ-1GN0R00C CS0402 CS0201 CS0201 RS0201 Murata Murata Murata Murata Murata Murata Murata Atmel Abracon GRM033C80G105MEA2D BLM15AG121SN1 BLM03AG121SN1D LQM18PN2R2MFRL LQG15HS15NJ02D LQP03TN3N3C02D GRM1555C1H3R3CA01 ATWINC1500B-MU-T ABM10-26.000MHZ-D30-T3 ATWINC1500-MR210PB CS0201 FBS0402 FBS0201 LPS0603 LS0402 LS0201 CS0402 40QFN 4 SMD C6,C7 C15,C16 C20 C21 C18,C22 C1 FB1,FB2,FB3 FB4 L1 L4 L2,L5 R2 U1 Y1 10PF CAP CER 10PF 50V 1% NP0 0402 1.8PF CAP CER 1.8PF 50V NP0 0201 1.2PF CAP CER 1.2PF 50V NP0 0201 0 RES 0.0 OHM 1/20W JUMP 0201 SMD DNI 1.0uF CAP CER 1UF 4V 20% X6S 0201 BLM15AG121SN1 FERRITE,120 OHM @100MHz,0402 BLM03AG121SN1D FERRITE BEAD 120 OHM 200MA 0201 2.2uH POWER INDUCTOR,2.2uH,20%,750mA,0.3ohms,0603 15nH INDUCTOR 15NH 300MA 0402 3.3nH INDUCTOR 3.3+/-0.2NH 750MA 0201 3.3PF CAP,CER,3.3pF,NPO,0402,50V ATWINC1500B-MU-T IC, WiFi, 40QFN 26.000MHz CRYSTAL 26MHZ 10PF SMD PCB (Blue 21.7 x 14.7mm) RF SHIELD (12.70 x 13.66 x 1.3 mm) ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 15 Application Schematic Table 15-1. Application Schematic ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 29 16 Reference Documentation and Support 16.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. Title Content Datasheet This Document Design Files Package User Guide, Schematic, PCB layout, Gerber, BOM & System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD. Platform Getting Started Guide How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines. HW Design Guide Best practices and recommendations to design a board with the product, Including: Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance matching, using a power amplifier etc), SPI/UART protocol between Wi-Fi SoC and the Host MCU. SW Design Guide Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. SW Programmer Guide Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage & sample App note For a complete listing of development-support tools & documentation, visit http://www.atmel.com/, or contact the nearest Atmel field representative. 30 ATWINC1500-MR210P [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 17 Revision History Doc Rev. 42502A Date 07/2015 Comments Updated due to changes from WINC1500A to WINC1500B: 1. Updated power numbers and description, added high-power and low-power modes 2. Updated radio performance numbers 4. Updated reference schematic and pin list to add GPIOs 3,4,5,6 5. Fixed typos in SPI interface timing 6. Added hardware accelerators in feature list (security and checksum) 7. Increased instruction RAM size from 128KB to 160KB 8. Improved and corrected description of Coexistence interface 9. Miscellaneous minor updates and corrections ATWINC1500-MR210PB [DATASHEET] Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015 31 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 www.atmel.com (c) 2015 Atmel Corporation. / Rev.: Atmel-42502A-ATWINC1500-MR210PB-SmartConnect-Datasheet_072015. Atmel(R), Atmel logo and combinations thereof, Enabling Unlimited Possibilities(R), and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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