+/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Product Features Product Description * The Z9510 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datatcom, telecom and other high performance applications. It is ideal for use in SDRAM memory applications. * * * * * * * * * * Zero delay, 10-output buffer (PLL) with internal loop filter High frequency operation (25 - 150 MHz) Low jitter <+/- 100 pS Low skew <200 pS Extended Temperature Range 0 to 85C Spread Spectrum compatible Integrated series damping resistors specifically designed for registered SDRAM applications Externally controllable output delay 45-55% output duty cycle OE pin for output enable control 24 Pin TSSOP package The Z9510 has one bank of ten outputs with output enable control. Input to output delay can be adjusted by varying load/delay on feedback path. When OE is low, clock outputs are forced low. VDDA can be strapped low to force device into test mode (see page 3). Function Table OE CLK (0:9) Outputs FBOUT LOW LOW REF HIGH REF REF Note: See test mode description for additional logic configurations. REF is fixed frequency input. Pin Configuration Block Diagram FBOUT CLK0 CLK1 FBIN REF VDDA CLK2 CLK3 1 MUX 0 SEL CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 V SSA V DD CLK0 CLK1 CLK2 V SS V SS CLK3 CLK4 V DD OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF V DDA V DD CLK9 CLK8 V SS V SS CLK7 CLK6 CLK5 V DD FBIN OE INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 1 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Pin Description Pin No. I/O Description 24 12 13 Pin Name REF FBOUT FBIN I O I 11 OE I 22, 10, 14, 2 23 VDD PWR Input reference pin. Output feedback pin, no OE controls. This pin is to be connected to the FBOUT pin. A timing delay may be inserted to change the device's actual skew. Output Enable clocks (high active). OE low places CLK (0:9) into Low state. See diagram on page 1. 3.3V supply for core logic, inputs, and outputs. VDDA PWR CLK(0:9) O VSS PWR Ground pins for the core logic and I/Os. VSSA PWR Ground pin for analog circuitry. 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 6, 7, 18, 19 1 Power for internal analog circuitry. This supply should have separate decoupling. For test purposes, when VDDA is strapped to ground the internal PLL is bypassed and REF is buffered directly to device outputs (see Test Mode Table). Low skew clock outputs. Outputs enabled by OE in high state. Absolute Maximum Ratings(1) Symbol Rating Commercial Unit VDD, VDDA Supply Voltage Range -0.5 to +4.6 V VI (2) Input Voltage Range -0.5 to +6.5 V VO Voltage range applied to any output in the high or low state -0.5 to VDD + 0.5 V IIK (VI<0) Input clamp current -50 mA IOK (VO<0 or VO>VDD) Terminal Voltage with respect to VSS (inputs VIH2.5, VIL2.5) +/- 50 mA (2) IO (VO = 0 to VDD) Continuous Output Current +/- 50 mA VDD or VSS Continuous Current +/- 100 mA Maximum power dissipation 0.7 W Storage Temperature Range -65C to + 150C C TA = 50C (in still air) TSTG Notes: 1. 2. 3. 3 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 2 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Capacitance(1) Parameter Description Min CIN Input Capacitance Vin = VDD or VSS CO Output Capacitance VO = VDD or VSS Note: Unused inputs must be held high or low to prevent them from floating. Typ Max Unit 5 pF 6 pF Test Mode Table (VDDA = 0 V) Inputs OE LOW LOW HIGH HIGH REF LOW HIGH LOW HIGH Outputs CLK(0:9) FBOUT LOW LOW LOW HIGH LOW LOW HIGH HIGH DC Parameters (Tamb = 0 to + 85 C) (VDD = VDDA = 3.0 V to 3.6 V) Symbol Parameter VIH VIL HIGH level input voltage LOW level input voltage HIGH level output voltage VOH LOW level output voltage VOL IOH HIGH level output current IOL LOW level output current VIK II IDD Clamp Voltage Input leakage current per pin Supply Current IDD Additional quiescent supply current Test Conditions Min to Max VDD = 3 V VDD = 3 V Min to Max VDD = 3 V VDD = 3 V VDD = 3.135 V VDD = 3.3 V VDD = 3.465 V VDD = 3.135 V VDD = 3.3 V VDD = 3.465 V VDD = 3 V VDD = 3.6V VDD = 3.6V VDD = 3.6V IOH = -100 A IOH = - 12 mA IOH = - 6 mA IOL = 100 A IOL = 12 mA IOL = 6 mA VO = 1 V VO = 1.65 V VO = 3.135 V VO = 1.95 V VO = 1.65 V VO = 0.4 V IIN = -18 mA VI =VDD or VSS Io = 0 VIN = VDD or VSS Io = 0 input at VDD - .6V Min Typ(1) Max. Unit 2.0 -36 40 - V V - 0.8 0.2 0.8 0.55 -12 14 -1.2 5 10 - 500 VDD - 0.2 2.1 2.4 -32 34 - V V mA mA V A A A Notes: 1. All typical values are measured at Tamb = 25 C INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 3 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary AC Electrical Characteristics(3)(6) (Tamb = 0 to + 85 C) Parameters From (Input)/Condition Fout Operating Frequency (output) REF = 66 to 100 MHz FBIN Any clock out (100 MHz) Any clock out Ref = 100 MHz Any clock out or FBOUT Any clock out or FBOUT Any clock out or FBOUT tPHASE error (5)(8) To (Output) Duty cycle tSK(o) (1)(8) Jitter (cycle-tocycle) (6)(7) tR (6)(7) tF Tstabil Notes: 1. 2. 3. 4. 5. 6. 7. 8. VDD = 3.3V +/- 0.165V VDD = 3.3V +/- 0.3V Min Max Min 25 150 -50 45 Typ Max Unit 25 150 MHz 50 -50 50 pS 55 45 55 % 200 pS |100| pS 0.8 2.5 nS 0.8 2.7 nS 1 mS |100| (4) Stabilization Time Typ The tSK(0) specification is only valid for equal loading of all outputs (30 pF//500). The specifications for parameters in this table are applicable only after any appropriate stabilization time as elapsed. Ref Duty Cycle must be 50% +/- 10%. Time required for the integrated PLL circuit to obtain phase lock of its feed back signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. Uses the averaging feature of the scope to remove the jitter component. The test load is 30pF//500. TR/TF are measured at 0.4V to 2.0V. See Figure 2. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 4 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Parameter Measurement Information 3 V Input 50% VDD 0 V From Output Under Test tpd 30 pF 2 V 500 Ohm Output 0.4 V 50% VDD tr Load Circuit for Outputs VOH 2 V 0.4 V VOL tf Voltage Waveforms Propagation Delay Times Notes: A. B. C. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: Input Frequency < 100 MHz, ZO = 50 , tr <1.2 ns, tf<1.2ns. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 5 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Package Drawing and Dimensions D b R0.1 .08 8 A C B A R A2 c E1 BO c1 0.25 L20 L b1 A1 L1 DETAIL A DETAIL B -B385 24 Pin TSSOP Dimensions SURFACES ROUGHNESS: 6+ 27n(RZ) INCHES 4 RD [10 TYP SYMBOL -C- 0.07 NOM MILLIMETERS MAX MIN NOM MAX A - - 0.0279 - - 1.10 A1 0.0013 - 0.0038 0.05 - 0.15 A2 0.0216 0.0228 0.0267 0.85 0.90 1.05 L 0.0127 0.0152 0.0178 0.50 0.60 0.70 b 0.0048 - 0.0076 0.19 - 0.30 b1 0.0048 0.0056 0.0064 0.19 0.22 0.25 c 0.0023 - 0.0051 0.09 - 0.20 c1 0.0023 0.0032 0.0041 0.09 0.127 0.16 0 - 8 0 - 8 C B e MIN R1.30 0.10~0.15 1.0 0.00 ~ 0.05 SECTION V-V R0.15 14 TYP 1.0 e 0.026 BSC 0.65 BSC D 0.19812 BSC 7.80 BSC E 0.16256 6.40 BSC 0.05 MAX. E1 0.05 MAX. 0.168 0.173 0.178 4.3 4.4 4.5 1.0 E A INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 6 of 7 +/+ Z9510 ...when timing is critical Ten Output Zero Delay Buffer Preliminary Ordering Information Part Number Package Type Production Flow Z9510ATB 24 Pin TSSOP 0C to +85C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI Z9510ATB Date Code, Lot # Z9510ATB Flow B = 0C to + 85C Package T = TSSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 http://www.imicorp.com Rev. 1.0 11/1/1999 Page 7 of 7