High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data Used with high speed ADC evaluation boards 32 kB FIFO Depth at 133 MSPS (upgradeable to 256 kB) Simplifies evaluation of high speed ADCs Measures performance with ADC AnalyzerTM Real-time FFT and time domain analysis Analyze SNR, SINAD, SFDR, and harmonics Import raw text data for analysis Virtual ADC eval board support using ADIsimADCTM Simple USB port interface Compatible with Windows(R) 98 (2nd Ed), Windows 2000, Windows Me, or Windows XP ADC ANALYZERTM USB CABLE SINGLE OR DUAL HIGH SPEED ADC EVALUATION BOARD 3.3 V power supply Analog signal source and anti-aliasing filter Low jitter clock source High speed ADC evaluation board and ADC data sheet PC running Windows 98 (2nd Ed), Windows 2000, Windows Me, or Windows XP USB 2.0 port recommended (USB 1.1 compatible) Available ADIsimADC product model files PRODUCT DESCRIPTION The high speed ADC FIFO evaluation kit includes the latest version of ADC Analyzer and a memory board to capture blocks of digital data from Analog Devices' high speed analogto-digital converter (ADC) evaluation boards. This FIFO board can be connected to a PC through a USB port and used with ADC Analyzer to evaluate the performance of high speed ADCs quickly. Users can view an FFT for a specific analog input and encode rate and analyze SNR, SINAD, SFDR, and harmonic information. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices' high speed ADC evaluation board, a power supply, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC. Two versions of the FIFO are available. The HSC-ADC-EVALADC is used with dual ADCs and converters with demultiplexed digital outputs. The HSC-ADC-EVALA-SC evaluation board is used with single-channel ADCs. See Table 1, to choose the FIFO appropriate for your high speed ADC evaluation board. HSC-ADC-EVALA-SC OR HSC-ADC-EVALA-DC POWER SUPPLY 3.3V LOGIC ADC FILTERED ANALOG INPUT CLOCK CIRCUIT CLOCK INPUT n FIFO2 32K TIMING CIRCUIT FIFO1 32K 80-PIN CONNECTOR Figure 1. Functional Block Diagram (Simplified) PRODUCT HIGHLIGHTS 1. Easy to set up--Connect the power supplies and signal sources to the two evaluation boards. Then connect to the PC and evaluate the performance instantly. 2. ADIsimADC - The software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between multiple ADCs, with or without hardware evaluation boards. 3. USB Port Connection to PC--PC interface is a USB 2.0 connection (1.1 compatible) to PC. A USB cable is provided in the kit. 4. 32 kB FIFO(s)--This FIFO(s) stores data from the ADC(s) for processing. A pin compatible FIFO family is used for easy upgrading. 5. Up to 133 MSPS encode rate on each channel--Singlechannel ADCs with encode rates up to 133 MSPS can be used with the FIFO board. Dual and demultiplexed output ADCs also can be used with the FIFO board (with clock rates up to 133 MSPS on each output channel). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 04750-0-001 EQUIPMENT NEEDED One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TABLE OF CONTENTS FIFO Evaluation Board Quick Start............................................... 4 Average FFT ................................................................................ 17 Requirements ................................................................................ 4 Continuous Average FFT .......................................................... 17 Quick Start Steps ...................................................................... 4 Two Tone ..................................................................................... 18 Virtual Evaluation Board Quick Start With ADIsimADC.......... 5 Continuous Two Tone ............................................................... 18 Requirements ................................................................................ 5 Average Two Tone ...................................................................... 18 Quick Start Steps ...................................................................... 5 Stop............................................................................................... 18 FIFO 4 Data Capture Board ............................................................ 6 Zooming and Exporting Data .................................................. 18 FIFO 4 Supported ADC Evaluation Boards.............................. 6 Importing Data ........................................................................... 19 Terminology ...................................................................................... 8 .csv and ASCII files ................................................................ 19 Single Tone FFT............................................................................ 8 Printing ........................................................................................ 20 Two-Tone FFT .............................................................................. 9 Saving Files.................................................................................. 21 Theory of Operation ...................................................................... 10 Additional Functions (Virtual ADC only).............................. 21 Clocking Description................................................................. 10 Amplitude Sweep (Virtual ADC only) .................................... 21 Clocking with Interleaved Data................................................ 10 Analog Frequency Sweep (Virtual ADC only)....................... 22 Installing ADC Analyzer................................................................ 11 Troubleshooting.............................................................................. 23 Installation................................................................................... 11 Flat Line Signal Displayed......................................................... 23 Configuration File ...................................................................... 11 Displayed Signal Unlike Analog Input .................................... 23 Configuring an Evaluation Board ............................................ 11 FFT Noise Floor Higher Than Expected................................. 24 Additional Configuration Options .......................................... 14 Large Spur In FFT (Image Problem) ....................................... 24 Windowing.............................................................................. 14 MSBs Missing From Time Domain ......................................... 25 Power Supply........................................................................... 14 Upgrading FIFO Memory......................................................... 25 Y-Axis....................................................................................... 14 Jumpers ............................................................................................ 26 Installing ADC Analyzer With ADIsimADC.............................. 15 Default Settings........................................................................... 26 Installation................................................................................... 15 FIFO Schematices and PCB Layout ............................................. 28 Configuration File ...................................................................... 15 FIFO Connector ......................................................................... 28 Configuring a Model.................................................................. 15 PCB Schematic............................................................................ 29 ADC Analyzer Functions .............................................................. 17 Assembly--Primary Side........................................................... 35 Time Domain.............................................................................. 17 Assembly--Secondary Side....................................................... 36 Continuous Time Domain ........................................................ 17 Layer 1-- Primary Side.............................................................. 37 FFT ............................................................................................... 17 Layer 2--Ground Plane ............................................................. 38 Continuous FFT ......................................................................... 17 Layer 3--Power Plane................................................................ 39 Rev. 0 | Page 2 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Layer 4--Secondary Side............................................................40 Windowing Functions................................................................43 ESD Caution ................................................................................40 FFT Calculations.........................................................................43 Bill of Materials................................................................................41 Ordering Guide ...........................................................................44 Appendix: Sampling and FFT Fundamentals..............................43 Coherent Sampling .....................................................................43 REVISION HISTORY 5/04--Revision 0: Initial Version Rev. 0 | Page 3 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FIFO EVALUATION BOARD QUICK START Install ADC Analyzer from the CD provided in the FIFO evaluation kit. See the Installing ADC Analyzer section for more details. For the latest updates to the software, check the Analog Devices website at www.analog.com/hsc-FIFO. 5. Once the cable is connected to both the computer and FIFO and power is supplied, the USB drivers start to install. To complete the total installation of the FIFO drivers, you need to complete the new hardware sequence two times. The first Found New Hardware Wizard opens with the text message This wizard helps you install software for...PreFIFO 4. Click the recommended install, and go to the next screen. A Hardware Installation warning window should then be displayed. Click Continue Anyway. The next window that opens should finish the Pre-FIFO 4 installation. Click Finish to complete. Your computer should go through a second Found New Hardware Wizard, and the text message, This wizard helps you install software for...Analog Devices FIFO 4, should be displayed Continue as you did in the previous installation and click Continue Anyway, then click Finish on the next two windows. This should complete the installation. 6. (Optional) Verify in the device manager that "Analog Devices, FIFO4" is listed under the USB hardware. 7. Apply power to the evaluation board and check the voltage levels at the board level. 8. Connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. Make sure the evaluation boards are powered before connecting the analog input and clock. 9. Start ADC Analyzer (see the Installation section for installing the software). REQUIREMENTS Requirements include * FIFO evaluation board, ADC Analyzer, and USB cable * High speed ADC evaluation board and ADC data sheet * 3.3 V power supply for FIFO evaluation board * Power supply for ADC evaluation board * Analog signal source and appropriate filtering * Low jitter clock source applicable for specific ADC evaluation, typically < 1 ps rms * PC running Windows 98 (2nd Ed), Windows 2000, Windows Me, or Windows XP * PC with a USB 2.0 port recommended (USB 1.1 compatible) Quick Start Steps 1. 2. Connect the FIFO evaluation board to the ADC evaluation board. If an adapter is required, insert the adapter between the ADC evaluation board and the FIFO board. If using the HSC-ADC-EVALA-SC model, connect the evaluation board to the bottom half of the 80-pin connector (closest to the installed IDT FIFO chip). Connect the provided USB cable to the FIFO evaluation board and to an available USB port on the computer. 3. Refer to Table 4 for any jumper changes. Most evaluation boards can be used with the default settings. 4. After verification, connect the appropriate power supplies to the FIFO and ADC evaluation boards. The FIFO evaluation board requires a single 3.3 V power supply with 1 A current capability. Refer to the instructions included in the ADC data sheet for more information about the ADC evaluation board setup. 10. Choose a configuration file for the ADC evaluation board used or create one (see the Configuring an Evaluation Board section for more information). 11. Click Time Domain (left-most button under the pulldown menus). A reconstruction of the analog input is displayed. If the expected signal does not appear, or if there is only a flat red line, refer to the Troubleshooting section for more information. Rev. 0 | Page 4 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC VIRTUAL EVALUATION BOARD QUICK START WITH ADIsimADC REQUIREMENTS 5. On the ADC Modeling form, select the Device tab and click the ... button, adjacent to the dialog box. This opens a file browser and displays all of the models found in the default directory: c:\program files\adc_analyzer\models. If no model files are found, follow the on-screen directions or see Step 1 to install available models. If you have saved the models somewhere other than the default location, use the browser to navigate to that location and select the file of interest. 6. From the menu choose Config > FFT. In the FFT Configuration form, ensure that the Encode Frequency is set for a valid rate for the simulated device under test. If set too low or too high, the model will not run. 7. Once a model has been selected, information about the model displays on the Device tab. After ensuring that you have selected the right model, select the Input tab. This lets you configure the input to the model. From the drop down menu, select either Sine Wave or Two Tone for the input signal. 8. Click Time Domain (left-most button under the pulldown menus). A reconstruction of the analog input is displayed. The model may now be used just as a standard evaluation board would be. 9. The model supports additional features not found when testing a standard evaluation board. When using the modeling capabilities, it is possible to sweep either the analog amplitude or the analog frequency. See the Installing ADC Analyzer With ADISIMADC section for additional features. Requirements include * Completed installation of ADC Analyzer version 4.5.0 or later. * ADIsimADC product model files for the desired converter. Models are not installed with the software, but may be downloaded from the website at no charge. Go to www.analog.com/ADIsimADC or look under Design Tools for the product of interest. * No hardware is required. However, if you wish to compare results of a real evaluation board and the model, you may switch easily between the two, as outlined below. Quick Start Steps 1. To obtain ADC model files, go to www.analog.com/ADIsimADC or look under Design Tools for the product of interest. Download the files of interest to a local drive. The default location is c:\program files\adc_analyzer\models. 2. Start ADC Analyzer (see the Installation section for installing the software). 3. From the menu choose Config > Buffer and select Model from the drop down menu as the buffer memory. In effect, the model functions in place of the ADC and data capture hardware. 4. After selecting the Model, a small button, Model, is displayed next to the Stop button. Click Model to select and configure which converter will be modeled. This places a small form in the workspace where you can select and configure how the model will behave. Rev. 0 | Page 5 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FIFO 4 DATA CAPTURE BOARD JUMPERS UNUSED PINS TO GROUND ADC EVALUATION BOARD CONNECTION: 40 PIN INTERFACE FOR DATA AND CLOCK INPUT FOR TOP CHANNEL IDT72V283 32K x 16-BIT FIFO +3.3V POWER CONNECTION OPTIONAL SMA CLOCK INPUTS INVERT WRITE CLOCK OPTIONS ADDITIONAL TIMING DELAYS FOR WRITE CLOCK JUMPERS TIE TOP AND BOTTOM CLOCK INPUTS TOGETHER = IN FOR SINGLE CHANNEL OPTION, OUT FOR DUAL CHANNEL OPTION WRITE CLOCK SELECT TO GENERATE WEN SIGNAL JUMPERS UNUSED PINS TO GROUND INVERT WRITE CLOCK OPTIONS SET WEN TIMING FOR INTERLEAVE MODES OPTIONAL FINE TUNING ADJUST USB CONNECTION TO COMPUTER 04750-0-002 ADC EVALUATION BOARD CONNECTION: 40 PIN INTERFACE FOR DATA AND CLOCK INPUT FOR BOTTOM CHANNEL IDT72V283 32K x 16- BIT FIFO CYPRESS Fx2 HIGH SPEED USB 2.0 MICROCONTROLLER MICROCONTROLLER CRYSTAL CLOCK = 24MHz. OFF DURING DATA CAPTURE EEPROM TO LOAD USB FIRMWARE Figure 2. FIFO Components Description FIFO 4 SUPPORTED ADC EVALUATION BOARDS The evaluation boards in Table 1 can be used with the high speed ADC FIFO Evaluation Kit1. Some evaluation boards require an adapter between the ADC evaluation board connector and the FIFO connector. If an adapter is needed, send an email to highspeed.converters@analog.com with the part number of the adapter and a mailing address. Table 1 HSC-ADC-EVALA-DC: and HSC-ADC-EVALA-SC Compatible Evaluation Boards2 Evaluation Board Model AD6640ST/PCB AD6644ST/PCB AD6645/PCB AD9051/PCB AD9057/PCB AD9059/PCB AD9071/PCB AD9200SSOP-EVAL AD9200TQFP-EVAL AD9201-EVAL AD9203-EB AD9214-65PCB AD9214-105PCB AD9215BCP-65EB AD9215BCP-80EB AD9215BCP-105EB AD9215BRU-65EB AD9215BRU-80EB AD9215BRU-105EB Description of ADC 12-Bit, 65 MSPS ADC 14-Bit, 65 MSPS ADC 14-Bit, 80 MSPS ADC 10-Bit, 60 MSPS ADC 8-Bit, 80 MSPS ADC Dual 8-Bit, 60 MSPS ADC 10-Bit, 100 MSPS ADC 10-Bit, 20 MSPS ADC 10-Bit, 20 MSPS ADC Dual 10-Bit, 20 MSPS ADC4 10-Bit, 40 MSPS ADC 10-Bit, 65 MSPS ADC 10-Bit, 105 MSPS ADC 10-Bit, 65 MSPS ADC 10-Bit, 80 MSPS ADC 10-Bit, 105 MSPS ADC 10-Bit, 65 MSPS ADC 10-Bit, 80 MSPS ADC 10-Bit, 105 MSPS ADC FIFO Board Version SC SC SC SC SC DC SC SC SC SC SC SC SC SC SC SC SC SC SC Rev. 0 | Page 6 of 44 Comments Requires AD664xFFA3 Rev. C Requires AD664xFFA Rev. C Requires AD664xFFA Requires AD9051FFA Requires AD9283FFA Requires AD9059FFA Requires AD9071FFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Evaluation Board Model AD9218-65PCB AD9218-105PCB AD9220-EB AD9221-EB AD9223-EB AD9224-EB AD9225-EB AD9226-EB AD9226QFP-EB AD9235BRU-20EB AD9235BRU-40EB AD9235BRU-65EB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9236BCP-80EB AD9236BRU-80EB AD9236BCP-80EB AD9238-20PCB AD9238-40PCB AD9238-65PCB AD9240-EB AD9241-EB AD9243-EB AD9244-40PCB AD9244-65PCB AD9245BCP-80EB AD9260-EB AD9280-EB AD9281-EB AD9283/PCB AD9289BBC-65EB AD9410/PCB AD9430-CMOS/PCB AD9432/PCB AD9433/PCB AD9480BSU-250EB AD10200/PCB AD10201/PCB AD10226/PCB AD10235/PCB AD10265/PCB AD10401/PCB AD10465/PCB Description of ADC Dual 10-Bit, 65 MSPS ADC Dual 10-Bit, 105 MSPS ADC 12-Bit, 10 MSPS ADC 12-Bit, 1.25 MSPS ADC 12-Bit, 3 MSPS ADC 12-Bit, 40 MSPS ADC 12-Bit, 25 MSPS ADC 12-Bit, 65 MSPS ADC 12-Bit, 65 MSPS ADC 12-Bit, 20 MSPS ADC 12-Bit, 40 MSPS ADC 12-Bit, 65 MSPS ADC 12-Bit, 20 MSPS ADC 12-Bit, 40 MSPS ADC 12-Bit, 65 MSPS ADC 12-Bit, 20 MSPS ADC 12-Bit, 40 MSPS ADC 12-Bit, 65 MSPS ADC 12-Bit, 80 MSPS ADC 12-Bit, 80 MSPS ADC 12-Bit, 80 MSPS ADC Dual 12-Bit, 20 MSPS ADC Dual 12-Bit, 40 MSPS ADC Dual 12-Bit, 65 MSPS ADC 14-Bit, 40 MSPS ADC 14-Bit, 1.25 MSPS ADC 14-Bit, 3 MSPS ADC 14-Bit, 40 MSPS ADC 14-Bit, 65 MSPS ADC 14-Bit, 80 MSPS ADC 16-Bit, 2.5 MSPS ADC 8-Bit, 32 MSPS ADC Dual 8-Bit, 28 MSPS ADC 8-Bit, 100 MSPS ADC Quad 8-Bit, 65 MSPS ADC5 10-Bit, 210 MSPS ADC 12-Bit, 210 MSPS ADC 12-Bit, 105 MSPS ADC 12-Bit, 125 MSPS ADC 8-Bit, 250 MSPS ADC Dual 12-Bit, 105 MSPS ADC Dual 12-Bit, 105 MSPS ADC Dual 12-Bit, 125 MSPS ADC Dual 12-Bit, 215 MSPS ADC Dual 12-Bit, 65 MSPS ADC Dual 14-Bit, 105 MSPS ADC Dual 14-Bit, 65 MSPS ADC 4 FIFO Board Version DC DC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC DC DC DC SC SC SC SC SC SC SC SC SC SC DC DC DC SC SC DC DC DC DC DC DC DC DC 1 Comments Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD9283FFA Rev. 0 Requires AD9432FFA Requires LG-0204A Requires LG-0204A Requires LG-0204A Requires LG-0204A Requires LG-0204A Requires LG-0204A Requires LG-0204A Send an email to highspeed.converters@analog.com for information on evaluating the AD9288 with the High Speed ADC FIFO Evaluation Kit. Connector pin numbers and/or labeling on some evaluation boards (AD9214, AD9410, AD9430, AD9433, AD9235, and AD9244) may not match the FIFO connector numbering; however, the physical connections are correct. 3 The AD6640 evaluation board has a 40-pin output connector that should be left (MSB) justified when connected to the 50-pin AD664x FIFO adapter. 4 The AD9281 and AD9201 have a single output bus 5 The High Speed ADC FIFO Evaluation Kit can be used to evaluate two channels of the AD9289 at a time. 2 Rev. 0 | Page 7 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TERMINOLOGY SINGLE TONE FFT Harmonic Distortion, Image Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. It is reported in dBc. The ratio of the rms signal amplitude to the rms value of the nonharmonic component generated from the clocking phase difference of two ADCs, reported in dBc. Note: This measurement result is valid only when analyzing demultiplexed ADCs. Signal-to-Noise Ratio Full Scale (SNRFS) Harmonic Distortion, Second (2nd)-Sixth (6th) The ratio of the rms signal amplitude related to full scale (0 dB) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. It is reported in dBFS. The ratio of the rms signal amplitude to the rms value of the fundamental related harmonic component, reported in dBc. User Defined Signal-to-Noise Ratio (UDSNR) The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components within a specified band set by the user, excluding harmonics and dc. It is reported in dB. Noise Figure (NF) The noise figure is the ratio of the noise power at the output of a device to the noise power at the input to the device, where the input noise temperature is equal to the reference temperature (273 K). The noise figure is expressed in dB.1 Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components, including harmonics but excluding dc. It is reported in dB. Worst Other Spur (WoSpur) The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding all harmonically related components) reported in dBc. Total Harmonic Distortion (THD) The rms value of the sum of all spectral harmonics specified by the user. It is reported in dBc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It is reported in dBc. Noise Floor The rms value of the sum of all other spectral components, excluding the fundamental, its harmonics, and dc referenced to full-scale and reported in dBFS. 1 For Noise Figure for an ADC, the equation is V 2 rms /Z in Encode Frequency k xTxB - SNRFS - 10 x log Noise Figure = 10 x log - 10 x log 2 0.001 0.001 k= Boltzman's Constant = 1.38 x 10-23 T = Temperature in Kelvin = 273 K B = Bandwidth = 1 Hz Encode Frequency = ADC Clock Rate Vrms = RMS Fullscale Input Voltage ZIN= Input Impedance SNRFS= FullScale ADC SNR Rev. 0 | Page 8 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TWO-TONE FFT Two-Tone, Worst Other Spur (WoSpur) Two-Tone, Second Order Intermodulation Distortion Products (F1 + F2) The resulting rms distortion value, reported by the mixing of two analog input signals that is not related to the second or third order distortion products. The peak spurious component is not considered an IMD product. It is reported in dBc. The resulting rms second order distortion value reported by the mixing of two analog input signals. The peak spurious component is considered an IMD product. It is reported in dBc. Two-Tone, Second Order Intermodulation Distortion Products (F2-F1) The resulting rms second order distortion value reported by the mixing of two analog input signals. The peak spurious component is considered an IMD product. It is reported in dBc. Two-Tone, Third Order Intermodulation Distortion Products (2F1 + F2) Two-Tone, Second Order Input Intercept Point (IIP2) The measure of full-scale input signal power of the converter minus half the IMD second order products. It is reported in dBm. Two-Tone, Third Order Input Intercept Point (IIP3) The measure of full-scale input signal power of the converter minus half the IMD third order products. It is reported in dBm Two-Tone, SFDR The resulting rms third order distortion value reported by the mixing of two analog input signals. The peak spurious component is considered an IMD product. It is reported in dBc. Two-Tone, Third Order Intermodulation Distortion Products (2F2 + F1) The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component is not an IMD product. It is reported in dBc. . The resulting rms third order distortion value reported by the mixing of two analog input signals. The peak spurious component is considered an IMD product. It is reported in dBc. Rev. 0 | Page 9 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC THEORY OF OPERATION The FIFO evaluation board can be divided into several circuits, each of which plays an important part in acquiring digital data from the ADC and allows the PC to upload and process that data. The evaluation kit is based around the IDT72V283 FIFO chip from IDT. The system can acquire digital data at speeds up to 133 MSPS and data record lengths up to 32 kB using the HSC-ADC-EVALA-SC FIFO evaluation kit. The HSC-ADCEVALA-DC, which has two FIFO chips, is available to evaluate dual ADCs or demultiplexed data from ADCs sampling faster than 133 MSPS. A USB 2.0 microcontroller communicating with ADC Analyzer allows for easy interfacing to newer computers using the USB 2.0 (USB 1.1 compatible) interface. The process of filling the FIFO chip(s) and reading the data back requires several steps. First, ADC Analyzer initiates the FIFO chip(s) fill process. The FIFO chip(s) are reset using a master reset signal (MRS). The USB Microcontroller then is suspended, which turns off the USB oscillator, ensuring that it does not add noise to the ADC input. After the FIFO chip(s) completely fill, the full flags from the FIFO chip(s) send a signal to the USB microcontroller to wake up the microcontroller from suspend. ADC Analyzer waits for approximately 30 ms and begins the readback process. During the readback process, the acquisition of data from FIFO 1 (U201) or FIFO 2 (U101) is controlled via the signals OEA and OEB. Because the data outputs of both FIFO chips drive the same 16-bit data bus, the USB microcontroller controls the OEA and OEB signals to read data from the correct FIFO chip. From an application standpoint, ADC Analyzer sends commands to the USB microcontroller to initiate a read from the correct FIFO chip, or both FIFO chips in dual or interleaved mode. CLOCKING DESCRIPTION Each channel of the buffer memory requires a clock signal to capture data. These clock signals are normally provided by the ADC evaluation board and are passed along with the data through Connector J104/204 (Pin 37 for both Channel 1 and Channel 2). If only a single clock is passed for both channels, they can be connected together by Jumper J303. Jumpers J304 and J305 at the output of the LVDS receiver allow the output clock to be inverted by the LVDS receiver. By default, the clock outputs are inverted by the LVDS receiver. The single-ended clock signal from each data channel is buffered and converted to a differential CMOS signal by two gates of a low voltage differential signal (LVDS) receiver, U301. This allows the clock source for each channel to be CMOS, TTL, or ECL. The clock signals are ac-coupled by 0.1 F capacitors. Potentiometers R312 and R315 allow for fine tuning the threshold of the LVDS gates. In applications where fine-tuning the threshold is critical, these potentiometers may be replaced with a higher resistance value to increase the adjustment range. Resistors R303, R304, R307, R308, R311, R313, R314, and R316 set the static input to each of the differential gates to a dc voltage of approximately 1.5 V. At assembly, solder Jumpers J310-J313 are set to bypass the potentiometer. For fine adjustment using the pot, the solder jumpers must be removed. U302, an XOR gate array, is included in the design to let users add gate delays to the FIFO memory chips clock paths. They are not required under normal conditions and are bypassed at assembly by Jumpers J314 and J315. Jumpers J306 and J307 allow the clock signals to be inverted through an XOR gate. In the default setting, the clocks are not inverted by the XOR gate. The clock paths described above determine the WRT_CLK1 and WRT_CLK2 signals at each FIFO memory chip (U101 and U201, Pin 80). The timing options above should let you choose a clock signal that meets the setup and hold time requirements to capture valid data. A clock generator can be applied directly to S1 and/or S3. This clock generator should be the same unit that provides the clock for the ADC. These clock paths are ac-coupled, so that a sine wave generator can be used. DC bias can be adjusted by R301/R302 and R305/R306. Note that J301 and J302 (SMA connectors) and R301, R302, R305, and R306 are not installed at the factory and must be installed by the user. The DS90LV048A differential line receiver is used to square the clock signal levels applied externally to the FIFO evaluation board. The output of this clock receiver can either directly drive the write clock of the IDT72V283 FIFO(s), or first pass through the XOR gate timing circuitry described above. CLOCKING WITH INTERLEAVED DATA ADCs with very high data rates may exceed the capability of a single buffer memory channel (~133 MSPS). These converters often demultiplex the data into two channels to reduce the rate required to capture the data. In these applications, ADC Analyzer must interleave the data from both channels to process it as a single channel. The user can configure the software to process the first sample from Channel 1, the second from Channel 2, and so on, or vice versa, (see the Troubleshooting section for more information). The synchronization circuit included in the buffer memory forces a small delay between the write enable signals (WENA and WENB) to the FIFO memory chips (Pin 1, U101 and U201), ensuring that the data is captured in one FIFO before the other. Jumpers J401 and J402 determine which FIFO receives WENA and which FIFO receives WENB Rev. 0 | Page 10 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC INSTALLING ADC ANALYZER ADC Analyzer is designed to evaluate the performance of an Analog Devices analog-to-digital converter quickly and easily. Step 1 INSTALLATION 1. Copy the AnalyzerSetup.exe file to the hard drive. 2. Run the setup file and follow the instructions given in the installation wizard. Note that administrator privileges are required to install the software on Windows 2000/Windows Me/Windows XP machines. 3. Once the software is installed, run the executable file (the default location is in c:\program files\ ADC_Analyzer\ADC_Analyzer.exe). 04750-0-003 A copy of ADC Analyzer is included on the CD that comes with the FIFO Evaluation Kit. Check the Analog Devices website for updates to the software at www.analog.com/hsc-FIFO. 2. CONFIGURATION FILE A configuration file can be created for each high speed ADC evaluation board used with ADC Analyzer. A configuration file provides the software with important information about the data sent from the ADC evaluation board to the FIFO evaluation board, such as the number of bits, speed of the clock, and format of the data bits (binary or twos complement). Configuration files for some of the evaluation boards are included with the ADC Analyzer files. Each time ADC Analyzer is launched, a window opens where a configuration file can be specified. Click Yes to specify a configuration file and choose the file corresponding to the ADC being used. Choose Config > FFT from the pull-down menus or rightclick any of the analysis buttons to open the FFT Configuration screen. Use this menu to configure the Fast Fourier Transform plot. If needed, modify the options under Channel A to select the appropriate channel. Step 2 The default configuration files can be modified or a new configuration file can be created using the instructions in the Configuring An Evaluation Board section. CONFIGURING AN EVALUATION BOARD Follow Steps 1 through 5 to configure the software with the ADC evaluation board: From the pull-down menus in the upper left hand corner, choose Config > DUT. The screen, DUT Configuration opens. Enter the name of the ADC being evaluated in the Device dialog box and the number of bits (resolution of the ADC) in the Number of Bits dialog box. (Note: This information is used for display purposes only.) To specify a directory different than the default to store the configuration file, enter a new location in the Default Data Directory dialog box, and click OK. 04750-0-004 1. Note that Channel A in the software corresponds to Channel 1 on the FIFO schematics and the bottom FIFO on the evaluation Rev. 0 | Page 11 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO on the evaluation board (closest to the Analog Devices logo). See the Jumpers section for more information. Configuring FFT-- Defining Available Options in the Max # of Harmonics' box. Typically, this can be left at the default value of 3. DC Leakage: The number of bins (at dc) that are not used in calculating SNR and SINAD. Typically, this can be left at the default value of 6. Samples: Choose the number of samples taken to calculate an FFT. The default is 16 kB samples. Users can choose more or fewer samples, depending on the application. The maximum number of samples that can be selected in the software is 64 kB. However, the FIFO evaluation boards are configured with 32 kB FIFOs. For single ADCs evaluated with the HSC-ADC-EVALASC model, the maximum number of samples selected should match the FIFO memory on the evaluation board. For dual ADCs evaluated with the HSC-ADC-EVALA-DC model, the maximum number of samples should match the FIFO memory of each channel (a different number of samples can be selected for each channel). ADCs with demultiplexed outputs (such as the AD9430) can be used with a sample value of twice the FIFO memory. See the Upgrading FIFO Memory section. Maximum Number of Harmonics: The number of harmonics displayed by ADC Analyzer. The default value is 6 and the maximum number of harmonics that can be displayed is 12. Averages: Specify the number of averages taken for the average FFT functions. See the ADC Analyzer Functions section for more information. User Defined SNR Right (MHz): This is the amount of frequency specified to the right of the fundamental by the user to analyze SNR. The resulting value is called UDSNR and will show up after an FFT plot is captured. FullScale Input Power (dBm): This feature lets the user enter the amount of power (in dBm) needed on the input to determine the output fullscale. It applies only in noise figure and IIP2/IIP3 calculations. Enable Fundamental Override: ADC Analyzer automatically defaults the highest spur as the fundamental frequency of interest. However, in some applications, the user may have a very small analog input signal that could be equal to or below another spurious harmonic. This option lets the user specify the small analog input signal needed for evaluation. If Enable Fundamental Override is checked, the Fundamental Frequency (MHz) box is enabled for the user to specify. Fundamental Leakage: The number of bins that are neglected on either side of the fundamental signal when calculating the SNR and SINAD results. For example, if an encode rate is defined at 80 MSPS with 16384 samples, then 80M/21/(16384/21) = 4883 Hz/Bin is specified. The type of windowing selected determines the default value of the fundamental leakage. See the Windowing section for more information. The default values are 25, 10, and 1 for Hanning, Blackman Harris, and no windowing, respectively. User Defined SNR Left (MHz): This is the amount of frequency specified to the left of the fundamental by the user to analyze SNR. The resulting value is called UDSNR and will show up after an FFT plot is captured. After configuring the options for the Fast Fourier Transform plot in this window, click OK. 3. Choose Config > Buffer. HSC-ADC-EVAL(A), opening the Buffer Memory screen. Step 3 04750-0-005 Encode Frequency (MHz): Enter the speed of the sampling clock to the ADC. If evaluating a dual ADC, two different clock rates can be entered. Note: If the value is wrong, the analog fundamental frequency displayed will be wrong. Twos Complement: Check this box if the data from the ADC evaluation board is in twos complement format. Refer to the ADC data sheet to determine if the ADC outputs are configured for twos complement or offset binary. If the Twos Complement option is not checked, ADC Analyzer will expect the data outputs from the ADC to be in offset binary format. Click OK, and the Buffer Configuration window opens. ADC Analyzer automatically seeks a USB connection. If a USB connection is not found, it will assume that you want to use an older version FIFO board which has a parallel connection. If so, choose the appropriate parallel connection made to the computer and click OK. Harmonic Leakage: The number of bins that are neglected on either side of each harmonic of the fundamental signal defined Rev. 0 | Page 12 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Step 4 04750-0-006 Step 3a Choose Config > Bits > Data Bits to open the Bit Mask screen. Configure the number and location of the data bits used to calculate the FFTs. Make sure that the number of bits matches the resolution of the converter. All of the supported evaluation boards are MSB justified, so check the number of bits for the converter starting with Bit 15 (MSB). Exceptions to this are the AD9280, AD9281, AD9200, and AD9201. For these four ADCs, check the number of bits starting with Bit 13. If a single ADC is being evaluated, check only Channel A and the appropriate bits under Channel A. If a dual ADC is being evaluated, check Channel A and Channel B on the Channel Select screen. (Config > Channel Select). 04750-0-007 4. If evaluating a demultiplexed ADC, go to Config > Channel Select, opening the Channel Select pop-up menu, and check the Interleaved Data box. This automatically selects both Channel A and Channel B. When using a dual ADC, select only the appropriate channel that corresponds to the ADC that is being evaluated. Channel A is the default selected channel at startup. 04750-0-008 Step 4a Note that Channel A in the software corresponds to Channel 1 on the FIFO schematics and the bottom FIFO (U201) on the Rev. 0 | Page 13 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC evaluation board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO (U101) on the evaluation board (closest to the Analog Devices logo). See the Jumpers section for more information. Click OK. (For more information about the channel selection process, see the Troubleshooting section.) 5. As a last step, choose File > Configuration File > Save Configuration from the pull-down menu to save the configuration for future use. Choose a file name and a location to save the file. For the calculator to work properly, the correct sampling frequency must be entered under Config > FFT. Select either the desired approximate Analog Input Frequency or the # of Sine Wave Cycles. Enter the value in the dialog box (not labeled) and click Calculate to view the Coherent Frequency. The Coherent Frequency and Number of Integer Cycles will display in the gray boxes. Click OK to exit the Coherent Sampling Calculator. Power Supply ADDITIONAL CONFIGURATION OPTIONS Other options under the configuration pull-down menu include Windowing, Power Supply, and Y-Axis. This option opens under Config > Power Supply, and users can enter the value of the ADC analog and digital voltage supplies (see Figure 5). Note this for user documentation only. No external control is provided. ADC Analyzer displays this information when data is captured. See the ADC Analyzer Functions section for more information. Windowing 04750-0-011 Choose either the Hanning or Blackman Harris (default) windowing functions or turn windowing off. See the Windowing Functions section for a description of Hanning and Blackman Harris windowing. Click OK. Figure 5. Power Supply Configuration 04750-0-009 Y-Axis Figure 3. Select Windowing Function 04750-0-012 If you choose None, the Coherent Sampling Calculator window opens (see Figure 4). Use the Y Axis screen to configure the display of the FFT Y-Axis. Go to Config > YAxis to change the default value of - 130, which is a typical setting for the noise floor of a 14-bit ADC with 16,384 samples in the FFT calculation. 04750-0-010 Figure 6. Y Axis Configuration Figure 4. Coherent Sampling Calculator Rev. 0 | Page 14 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC INSTALLING ADC ANALYZER WITH ADIsimADC ADC Analyzer is useful also as an evaluation tool for simulated ADCs using ADIsimADC. INSTALLATION 2. From the menu, select Config > Buffer. From the drop down list, select Model. Then click OK. In effect, the model functions in place of the ADC and data capture hardware. Step 2 04750-0-013 The simulation tools are installed as part of the regular installation of ADC Analyzer (for instructions, see the Installing ADC Analyzer section). Before using these features, the desired model files must be installed. Locate the available models on the Analog Devices website www.analog.com/ADIsimADC or by locating the desired converter product and going to the Design Tools area for that product. 3. Download the desired model file to the models directory. The default is c:\program files\adc_analyzer\models. 2. Although the software is provided with the evaluation board, no hardware is required to use the modeling software. Updates to the software are posted periodically to www.analog.com as well as new and updated models. Check the website frequently to ensure that you have the latest for both files. 3. Once the software and models are installed, run the executable file (the default location is in c:\program files\adc_analyzer\adc_analyzer.exe. After selecting the Model, a small button, Model, is displayed next to the Stop button. Click Model to open the model selection form. Step 3 04750-0-014 1. 4. The ADC Modeling form lets you select the device to model and configure the analog input to the model. As with using an ADC evaluation board, a corresponding configuration file must be loaded before simulations can occur. This file provides the software with important information about the format in which the data is generated, and other information, such as the number of bits, speed of the clock, and format of the data bits (binary or twos complement). Configuration files for some of the evaluation boards are included with the ADC Analyzer files. Each time ADC Analyzer is launched, a window opens in which a configuration file can be specified. Click Yes to specify a configuration file and choose the file corresponding to the ADC evaluation board being used. For more details, see the Configuring an Evaluation Board section. 04750-0-015 Step 4 CONFIGURATION FILE CONFIGURING A MODEL To configure the software for use with ADIsimADC virtual evaluation board, follow Steps 1 through 8. 1. Choose Config > FFT from the pull-down menus or rightclick on any of the analysis buttons to bring up the FFT Configuration menu. In this window, set the encode rate to the desired rate that the converter can support. If an encode rate is specified outside the operating range of the converter, the model will not function as expected and erroneous results will be obtained. Make any other adjustments necessary. If you have questions, see the Configuring an Evaluation Board. Click OK when finished. Rev. 0 | Page 15 of 44 From the ADC Modeling form, select the Device tab and click the ... button, adjacent to the dialog box. This opens a file browser and displays all of the models found in the default directory. If you have not loaded models on your machine, see Step 1 under Installation. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 6. From the file browser, select the model of interest. Select the Input tab. From this tab, you may select the input stimulus of either a single or dual sine wave, the input signal level relative to the converter range, the input frequency, the signal offset, the signal range, external clock jitter and external analog dither. If two tone is selected, you also may specify the second tone. For the most accurate results, both signals should be in the same Nyquist zone. 04750-0-016 Step 6 Step 5a: 04750-0-053 When the model is selected, information about that device is filled in on the ADC Modeling form. Note that the amount of jitter, assumed at the time of characterization, automatically inserts in the External Jitter box on the Input tab. The model also returns a default Output Mode which is defined either as Offset Binary or Twos Complement. This setting automatically sets through the Config > FFT menu. If using a real part along with a model, note the correct Output Mode setting. If the windowing function under the Config > Windowing menu is set to None, a Coherent Sampling window opens. If you are in modeling mode and use this function, the calculated frequency inserts in the Analog In box on the Input tab 7. The Model is now fully configured and evaluations may begin. Any of the documented features of ADC Analyzer may be used for testing the virtual evaluation board as if a real evaluation board were connected. In addition, the virtual evaluation board supports sweeping of the analog input level and frequency. 8. To switch back to evaluate a real product, it is only required to specify the buffer memory by selecting Config > Buffer and select HSC_ADC_EVAL from the drop down list. 04750-0-052 5. Rev. 0 | Page 16 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC ADC ANALYZER FUNCTIONS A number of functions can be performed on the data collected by the FIFO evaluation board. These functions are represented by the row of buttons under the pull-down menus. The same functions also can be accessed under the Analyze pull-down menu. A description of each button is listed below. TIME DOMAIN This function displays a reconstruction of the captured data in the time domain. Several values are listed to the left of the signal, including AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only) Encode: ADC clock rate (MSPS), set under Config > FFT. Analog: Calculated analog input frequency (MHz). In IF sampling applications, the analog input is calculated back to the first Nyquist zone. Note that the encode rate must be set properly in the Config > FFT menu. SNR: Signal-to-noise ratio (dB) SNRFS: Signal-to-noise ratio full scale (dBFS) UDSNR: User defined signal-to-noise ratio (dB) NF: Noise figure (dB) DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only) SINAD: Signal-to-noise and distortion (dB) Encode: ADC clock rate (MSPS), set under Config > FFT Image: Level of image (nonharmonic) spur (dBc). Note that Image is valid only when using demultiplexed ADCs Analog: Calculated analog input frequency (MHz) Fund: Level of the fundamental (highest) tone (dBFS) Second: Level of the second harmonic (dBc) of the fundamental Min: Minimum output code produced by the analog input Max: Maximum output code produced by the analog input Third: Level of the third harmonic (dBc) of the fundamental Range: The range of the codes produced by the analog input Average: Average value of the codes; may be interpreted as the common mode Fourth: Level of the fourth harmonic (dBc) of the fundamental Fifth: Level of the fifth harmonic (dBc) of the fundamental F/S: Full-scale code range, equal to 2n, where n is the number of bits Sixth: Level of the sixth harmonic (dBc) of the fundamental Samples: Number of samples taken, determined by FFT Configuration (Config > FFT) THD: Total harmonic distortion (dBc) WoSpur: Level of the worst nonharmonic spur SFDR: Spurious-free dynamic range (dBc) CONTINUOUS TIME DOMAIN This function displays a continuous reconstruction of the captured data and is also useful for trouble- shooting. Click the STOP button to end the continuous display. Noise Floor: Level of the noise floor (dBFS) Samples: Number of samples taken, determined by FFT configuration, set under Config > FFT CONTINUOUS FFT FFT This function displays a reconstruction of the captured data in the frequency domain to analyze single-tone analog inputs. Several values are listed to the left of the signal, including AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only) This function displays a continuous FFT. AVERAGE FFT This function displays an average of a user-specified number of FFTs. Configure the number of FFTs under Config > FFT. The default value is 5. CONTINUOUS AVERAGE FFT DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only) Rev. 0 | Page 17 of 44 This function displays a continuous average of a user-specified number of FFTs. Configure the number of FFTs under Config > FFT. The default value is 5. HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TWO TONE STOP This function displays a reconstruction of the captured data in the frequency domain to analyze dual-tone analog inputs. Several values are listed to the left of the signal, including AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only) DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only) Encode: ADC clock rate (MSPS), set under Config > FFT Analog 1: First analog input frequency (MHz) Click this button to end any of the continuous display functions. ZOOMING AND EXPORTING DATA To zoom in on any portion of a displayed analog signal or FFT, select the portion of the signal by holding down the left mouse button and dragging across the area of interest. Bring up a hidden menu by clicking the right mouse button in the active window. The hidden menus are slightly different for the timedomain and FFT plots. These hidden menus have several options, including zooming and the capability to export timedomain data. Select from the menus using the left mouse button (see Figure 7and Figure 8) Analog 2: Second analog input frequency (MHz) Fundamental 1: First fundamental tone (dBFS) Fundamental 2: Second fundamental tone (dBFS) F1 + F2: Sum of the fundamental tones (dBFS) F2 - F1: Difference of the fundamental tones (dBFS) 2F1 - F2: 2 x Fundamental 1 - Fundamental 2 (dBFS) 04750-0-019 2F2 - F1: 2 x Fundamental 2 - Fundamental 1 (dBFS) 04750-0-020 2F1 + F2: 2 x Fundamental 1 + Fundamental 2 (dBFS) 2F2 + F1: 2 x Fundamental 2 + Fundamental 1 (dBFS) WoIMD: Worst intermodulation distortion (dBc) Figure 7. Time-Domain Plot Hidden Menu IIP2: Measure of the input intercept point in relation to the second order intermodulation distortion powers (dBm) Figure 8. FFT Plot Hidden Menu H-Zoom: Scales the selected section horizontally IIP3: Measure of the input intercept point in relation to the third order intermodulation distortion powers (dBm) V-Zoom: Scales the selected section vertically SFDR: Spurious-free dynamic range (dBc) Exact Zoom: Enter specific coordinates to view Noise Floor: Level of the noise floor (dBFS) Restore: Restores the graph to its original view Samples: Number of samples taken, determined by FFT configuration, set under Config > FFT Spawn: Produces an exact working copy of the active window that can be analyzed separately X-Y Zoom: Scales horizontally and vertically (two dimensions) CONTINUOUS TWO TONE This function displays a continuous dual-tone FFT. AVERAGE TWO TONE This function displays an average of a user-specified number of dual-tone FFTs. Configure the number of FFTs under Config > FFT. The default value is 5. Export Data: Writes all of the data points as well as the calculated information to a file. The information is saved as a .csv file that can be viewed in Microsoft Excel Comments: Lets the user enter comments about the graph. If the FFT is printed, the comments are included in the printout Lock Data (Time-Domain Plot Only): Once a time-domain sample of the data is taken, the user can "lock" this data and then perform an FFT. The FFT will be calculated based on this data instead of a new sample of data Rev. 0 | Page 18 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC EC1 Transition: Not applicable Encode Frequency (MHz): Enter the sampling clock rate used. FFT Data Write (FFT Plot Only): Writes the calculated FFT data to a file ASCII Text File to Import: Click the Browse... button to search for the file. Bin Boundaries (FFT Plot Only): Highlights the bins used to calculate the fundamental and harmonic energy. Configure the Fundamental Leakage and Harmonic Leakage under Config > FFT. See the Configuring an Evaluation Board section for more information 4. Click OK. The time-domain data is graphed in a new window. Right click the graph to open the hidden menu. Select Lock Data from the menu. (See Figure 7.) 5. To perform an FFT on this data, click the FFT button. FFT Bins: Changes the X-axis of the graph from frequency to bins IMPORTING DATA 04750-0-021 Data can be imported to ADC Analyzer to perform an FFT calculation. Two types of data can be imported: raw time domain text data in decimal format (from a logic analyzer, for example) and data exported from ADC Analyzer. Note that when importing data, double-check to make sure that the number of bits, sample size, and digital format (Twos Complement vs. Offset Binary) are selected appropriately under the Config menu. Figure 9. Import Data Dialog Box To import data previously exported from ADC Analyzer: 1. Choose File > Import Data. 2. Enter the file path in the dialog box shown in Figure 9, or click the Browse... button to search for the file. Click OK. 3. The time-domain data is graphed in a new window. Right click the graph to open the hidden menu. Choose Lock Data from the menu. See Figure 7 in the Zooming and Exporting Data section. 4. To perform an FFT on this data, click the FFT button. 1. Choose File > Import Data. 2. Click the ASCII File button shown in Figure 9. 3. The window in Figure 10 opens. This window is used to give ADC Analyzer information about how to interpret the text data file. If any of these input parameters are not correct, both the time and FFT data will not be correct. Data Bits: Select the resolution of the ADC. 04750-0-022 To import raw time domain text data in decimal format: Figure 10. Import ASCII Text File Dialog Box .csv and ASCII files The Comma Separated Value or Comma Delimited file format (.csv) is displayed in Figure 11 using Microsoft Excel. The .csv file includes extra parameters, including the raw time domain data. Samples: Select the number of samples in the file. Data Format: Select the format of the ADC output data. Justification: Normally, the data exported from ADC Analyzer is MSB_Justified. When importing data, be sure to select the proper justification. Rev. 0 | Page 19 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Only raw time domain data is used in an ASCII file format that is imported to ADC Analyzer. No specifications, words, extraneous characters, spaces, commas, or tabs can be placed in the ASCII file. 04750-0-023 Example portion of an ASCII file: (note that the entire ASCII file consists of time domain samples such as this.) Figure 11. Import .csv file using MS Excel If constructing a .csv file to import to ADC_Analyzer, the format of the sample .csv file must be followed. It is recommended that you use Microsoft Excel to paste the desired data and parameters over the example data and parameters. For example, the user has 16384 samples (16 kB samples). Paste the amount of samples (16384) into the cell directly below the cell labeled "Samples." Then paste the desired 16384 raw data samples under the cell labeled "RawTimeData." Other parameters can be changed just like "Samples" and "RawTimeData" if desired, but are not necessary for the import to work properly. Figure 13. ASCII File Sample PRINTING There are several printing options available in ADC Analyzer. To print the active window, choose File > Print > Print Active. To print more than one open window, choose File > Print > Print List. A dialogue box is displayed where the user can choose which windows to print. Choose multiple windows by clicking on each window while pressing the CTRL key or print all open windows with the Print All button. To print the entire screen, choose File > Print > Print Screen. 04750-0-051 The above procedure works most easily with Microsoft Excel. A .csv file can be constructed with a text editor such as Notepad, but Notepad does not provide the column alignment that Microsoft Excel provides, as shown in Figure 12. 04750-0-054 Parameters, such as Device, Device Number, Analog Frequency, Encode Frequency, Average (value), (number of) Bits, Max (value), Min (value), Range (of values), (amount of) Samples, AVCC, DVCC, XMaxTime, XMinTime, YMaxTime, YMinTime, Date, Time, Device Temperature, and Comments are included at the top of the file. 04750-0-024 Figure 14. Printing Options Figure 12. Import ASCII Text File using Notepad Rev. 0 | Page 20 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC SAVING FILES There are three ways to save an image in ADC Analyzer. Choose File > Save As > Save Active to save the active window in bitmap or jpeg format. Choose File > Save As > Save List to save each open window as a separate bitmap file. To save the entire screen as a bitmap file, choose File > Save As > Save Screen. ADDITIONAL FUNCTIONS (VIRTUAL ADC ONLY) The following function is available only while using the virtual evaluation board feature. This feature is disabled when operating in any of the normal buffer memory configurations. Start Amplitude (dB): This sets the starting level of the amplitude sweep. This is relative to the dc fullscale of the converter. This number should always be lower than the stop amplitude. Stop Amplitude (dB): This sets the stopping level of the amplitude sweep. This is relative to the dc fullscale of the converter. This number should always be larger than the start amplitude. 04750-0-025 Step Size (dB): This is the step size used for each amplitude step. This number should always be positive. There is no limit to the size of the step. However, the smaller the step, the longer the sweep will require to complete. Likewise, the larger the step, the lower the resolution of the sweep. Reference Line: This draws a reference line used for comparison of the SFDR of the unit. Figure 15. Sweep Mode Options SNR Reference Line: This draws a reference line used for comparison of the SNR of the unit. From the main menu, select Sweep. There are two choices: Analog Frequency Sweep and Analog Amplitude Sweep. Selecting either one of these opens the appropriate configuration window. FFT: The FFT selection determines if single or average FFTs are used during the sweep. AMPLITUDE SWEEP (VIRTUAL ADC ONLY) SFDR vs. Amplitude: Selecting this check box enables SFDR versus amplitude results. When this option is chosen, the form shown in Figure 16 is displayed. Use this form to select the options for an amplitude sweep. The frequency for the amplitude sweep is set on the ADC Modeling form under the Input tab, and must be set prior to selecting this option. SNR vs. Amplitude: Selecting this check box enables SNR versus amplitude results. 2nd Harmonic: Selecting this check box enables 2nd harmonics versus amplitude results. 3rd Harmonic: Selecting this check box enables 3rd harmonics versus amplitude results. 4th Harmonic: Selecting this check box enables 4th harmonics versus amplitude results. 5th Harmonic: Selecting this check box enables 5th harmonics. versus amplitude results. 6th Harmonic: Selecting this check box enables 6th harmonics versus amplitude results. Worst Other Spur: Selecting this check box enables worst other spur versus amplitude results. 04750-0-055 Results Fullscale: Selecting this check box refers all measurements to fullscale (dBFS). When this is not selected, the measurements are relative to the signal (dBc). Figure 16. Amplitude Sweep Mode Options Datalog to Disk: Selecting this check box writes all data to a file in the default data directory. The data format is an ASCII readable CSV file. Rev. 0 | Page 21 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Datalog to Screen: Selecting this check box causes graphs of each of the selected plots to be displayed on the screen after completion of the sweep. sweep will require to complete. Likewise, the larger the step, the lower the resolution of the sweep. Reference Line: This draws a reference line used for comparison of the SFDR of the unit. Datalog Plots to File: Selection of this check box causes each bitmap plot to be written to the default data directory. SNR Reference Line: This draws a reference line used for comparison of the SNR of the unit. Datalog Plots to Printer: Selection of this check box causes each bitmap plot to be sent to the printer. FFT: The selection in this box determines if single or average FFTs are used during the sweep. ANALOG FREQUENCY SWEEP (VIRTUAL ADC ONLY) When this option is chosen, the form shown in Figure 17 is displayed. This form is used to select the options for a frequency sweep. The amplitude for the frequency sweep is set on the ADC Modeling form under the Input tab, and must be set prior to selecting this option. SFDR vs. Frequency: Selecting this check box enables SFDR versus frequency results. SNR vs. Frequency: Selecting this check box enables SNR versus frequency results. 2nd Harmonic: Selecting this check box enables 2nd harmonics versus frequency results. 3rd Harmonic: Selecting this check box enables 3rd harmonics versus frequency results. 4th Harmonic: Selecting this check box enables 4th harmonics versus frequency results. 5th Harmonic: Selecting this check box enables 5th harmonics. versus frequency results. 6th Harmonic: Selecting this check box enables 6th harmonics versus frequency results. 04750-0-027 Worst Other Spur: Selecting this check box enables worst other spur versus frequency results. Figure 17. Frequency Sweep Mode Options Start Frequency (MHz): This sets the starting frequency of the frequency sweep. This number should always be lower than the stop amplitude. Stop Frequency (MHz): This sets the stopping frequency of the frequency sweep. This number should always be larger than the start amplitude. Step Size (MHz): This is the step size used for each frequency step. This number should always be positive. There is no limit to the size of the step. However, the smaller the step, the longer the Results Fullscale: Selecting this check box refers all measurements to fullscale (dBFS). When this is not selected, the measurement is relative to the signal (dBc). Datalog to Disk: Selecting this check box writes all data to a file in the default data directory. The data format is an ASCII readable CSV file. Datalog to Screen: Selecting this check box causes graphs of each of the selected plots to be displayed on the screen after completion of the sweep. Datalog Plots to File: Selection of this check box causes each bitmap plot to be written to the default data directory. Datalog Plots to Printer: Selection of this check box causes each bitmap plot to be sent to the printer. Rev. 0 | Page 22 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC TROUBLESHOOTING FLAT LINE SIGNAL DISPLAYED 9. Use the ADC data sheet to ensure all jumper connections are set appropriately on the ADC evaluation board. Ensure the ADC power-down option is not active. 10. Refer to Table 2, to ensure that all jumpers are set appropriately. 04750-0-029 DISPLAYED SIGNAL UNLIKE ANALOG INPUT Figure 19. Typical Time Domain Plot 04750-0-028 Scenario: After clicking Time Domain, the signal displayed does not look like the analog input signal. Figure 18. Bus Check for a 12-Bit ADC 1. A fast sinusoidal signal may look like a solid red block in the time-domain window (due to the number of sine waves shown). Right click the window to open a hidden menu where you can zoom in to a closer view of the signal. 2. Check the cable connection between the PC and the FIFO board. If applicable, ensure the correct parallel port is selected (LPT1 or LPT2) under Config > Buffer. 3. Check the signal connections. 4. Use the Analyze > Bus Check option to ensure all of the data bits are switching. 5. Ensure that the Twos Complement button is set correctly under Config > FFT. If the Twos Complement box is checked and the ADC outputs are not in Twos Complement format, a time-domain plot may look like Figure 20. 6. Adjust the timing to ensure that the data is captured correctly. Refer to the Clocking Description section in the Theory of Operation, and Table 2 for more information. Scenario: After clicking the time domain button, the signal displayed in the window is a flat line. 1. Check the power connections. 2. Verify that the USB cable does not exceed 5 feet in length or the parallel printer cable is IEEE-1284 compatible. 3. Check the cable connection between the PC and the FIFO board. If applicable, ensure the correct parallel port is selected (LPT1 or LPT2) under Config > Buffer. 4. If using a parallel port, make sure the Printer Port in the computer BIOS is set to Standard Bidirectional. 5. Make sure Channel A, Channel B, or both channels are selected under Config > FFT. 6. Check the signal connections and make sure that the clock is present at the output of the ADC evaluation board. 7. Verify that data bits are switching at the connection point between the FIFO and the ADC evaluation board. 7. Use the Analyze > Bus Check option to ensure all data bits are switching. See Figure 19 for an example of the AD6645, 14-bit single channel ADC. Note: The left-most bit is the MSB. Try using a very low frequency analog input (for example, 0.1 MHz to 1 MHz) to debug timing issues. For an exact number of cycles, such as 10, try (10xfs)/M, where fs = encode frequency and M = sample size (2N). 8. Check for problems with the common-mode level at the analog input by looking at the time data with no analog input signal. 8. Rev. 0 | Page 23 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-030 04750-0-032 LARGE SPUR IN FFT (IMAGE PROBLEM) Figure 22. AD9430 Timing Issue Figure 20. Incorrect Setting for Twos Complement 04750-0-031 FFT NOISE FLOOR HIGHER THAN EXPECTED Figure 21. Example of How Timing Issues Affect the Noise Floor 04750-0-033 Scenario: The noise floor of the FFT is higher than expected. Note that a higher than expected noise floor on the FFT can often be traced back to timing issues in the clock path. Figure 23. Channel Selection 1 Put a very slow sine wave signal into the ADC (such as 0.1 MHz to 1 MHz) and initiate a time-domain plot. If the plot looks similar to Figure 21, there are timing issues. Scenario: There is a large spur in the FFT (image of the fundamental) when evaluating the demultiplexed outputs (such as the AD9430). 2 Switch Jumpers J304 and/or J305 to their alternate positions to invert the clock. 1. 3 The four XOR gates of U302 can be used to insert delay into the high speed clock path or to invert the clock to optimize timing. Try moving jumpers J314 and J315 to their alternate position. This should allow enough flexibility for you to adjust timing under any conditions. Click Config > Channel Select, opening the window shown in Figure 23Double-check and make sure the Interleaved Data box is selected. Click OK. Note that Channel A in the software corresponds to Channel 1 on the FIFO schematics and the bottom FIFO on the evaluation board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO on the evaluation board (closest to the Analog Devices logo). See the Jumpers section for more information. 4 To gain even finer adjustments, use the installed trim pot, R312 and R315. To undo the default bypass, the solder jumpers J310-J313 must be removed first. 2. The interleaved priority menu shows either Channel A or Channel B checked. Rev. 0 | Page 24 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Scenario: The two MSBs are missing from the time domain plot. If evaluating the AD9200, AD9201, AD9280, or AD9281, make sure the appropriate bits are selected under Config > Bits > Data Bits. Bits 13 to 4 should be selected for the AD9200 and AD9201. Bits 13 to 6 should be selected for the AD9280 and AD9281. Default configuration files for these ADCs are installed with ADC Analyzer. 2. Make sure the bits are switching at the FIFO connector. 04750-0-056 1. Figure 24. Interleaved Priority 3. Perform another FFT. The spur should disappear. MSBs MISSING FROM TIME DOMAIN UPGRADING FIFO MEMORY The FIFO evaluation board includes one or two 32 kB FIFOs, depending on the model. Pin compatible FIFO upgrades (64 kB to 256 kB) are available from Integrated Device Technology, Inc. (IDT). The IDT part numbers are: * IDT72V283: 32 kB (included) 04750-0-034 * IDT72V293: 64 kB Figure 25. Incorrect Bit Mask Setting * IDT72V2103: 132 kB * IDT72V2113: 256 kB For more information, visit www.idt.com Rev. 0 | Page 25 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC JUMPERS Use the legends below to configure the jumpers. On the FIFO evaluation board, Channel 1 is associated with the bottom IDT FIFO chip, and Channel 2 is associated with the top IDT FIFO chip (closest to the Analog Devices logo). Table 2. Jumper Legend Position In Out Position 1 or Position 3 Description Jumper in place (2-pin header) Jumper removed (2-pin header) Denotes the position of a 3-pin header. Position 1 is marked on the board. Table 3 Solder Bridge Legend Position In Out Description Solder pads should be connected Solder pads should not be connected DEFAULT SETTINGS Table 4 lists the default settings for each model of the FIFO Evaluation Kit. The single channel (SC) model is configured to work with a single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single channel ADC. To align the timing properly, some evaluation boards may require modifications to these settings. Refer to the Clocking Description section in the Theory of Operation section for more information. Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under the Help > About HSC_ADC_EVALA, and click Setup Default Jumper Wizard. Then click the configuration setting that applies to the application of interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place. Table 4. Jumper Configurations Jumper No. J101 J102 J103 J105 J106 J107 J201 J202 J203 J205 J206 J207 J303 J304 J305 J306 J307 J310-13 J314 J315 J401 Single Channel Settings, Default (Bottom) Out Out In In Out Out Out Out In In Out Out In Position 3 Position 3 Out Out In Position 3 Position 1 Position 1 Demultiplexed Settings Out Out In In Out Out Out Out In In Out Out Out Position 3 Position 3 Out Out In Position 3 Position 1 Position 1 Dual Channel Settings Out Out In In Out Out Out Out In In Out Out Out Position 3 Position 3 Out Out In Position 3 Position 1 Position 1 Single Channel Settings1 (Top) Out Out In In Out Out Out Out In In Out Out In Position 3 Position 3 Out Out In Position 3 Position 1 Position 1 Rev. 0 | Page 26 of 44 Description Not Used Not Used Ground Unused Pins from Input Header Ground Unused Pins from Input Header Not Used Not Used Not Used Not Used Takes the FF Signal on FIFO1 out of the Circuit Takes the EF Signal on FIFO1 out of the Circuit Not Used Not Used OUT for Interleave and Dual/Ties Write Clocks Together POS3: Invert Clock out of DS90 POS3: Invert Clock out of DS90 NO Invert from XOR (U302) NO Invert from XOR (U302) All Solder Jumpers are Shorted No Timing Delay No Timing Delay WEN Select HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Jumper No. J402 J403 1 Single Channel Settings, Default (Bottom) Position 3 Position 1 Demultiplexed Settings Position 3 Position 1 Dual Channel Settings Position 3 Position 1 Single Channel Settings1 (Top) Position 3 Position 1 Description WEN Select J303 OUT: POS 1 bottom channel, POS 3 Top channel Can only be used with a dual channel FIFO board. This is essentially a single channel, but using the opposite channel (top FIFO) rather than the standard default (bottom FIFO). Rev. 0 | Page 27 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FIFO SCHEMATICES AND PCB LAYOUT 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND DR GND D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) FLOAT FLOAT FLOAT FLOAT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FLOAT 04750-0-037 FLOAT FLOAT FLOAT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FLOAT Figure 26. Single-Channel Connector Pin Diagram-- Top View (HSC-ADC-EVAL-SC) 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND DR GND D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) FLOAT GND DR GND D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) FLOAT 04750-0-038 FIFO CONNECTOR Figure 27. Dual-Channel Connector Pin Diagram-- Top View (HSC-ADC-EVAL-DC) Rev. 0 | Page 28 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC R502 100k + 1 Q1 Q0 44 PB0/FD0 Q2 45 PB1/FD1 Q3 46 PB2/FD2 Q4 47 PB3/FD3 Q5 54 PB4/FD4 Q6 55 PB5/FD5 Q7 56 PB6/FD6 Q8 57 PB7/FD7 Q9 102 104 Q10 105 Q11 121 Q12 103 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PA5/FIFOADR1 90 R525 24.9 OE1 PA6/*PKTEND 91 R526 24.9 OE2 11 XTALOUT 12 XTALIN PA7/*FLAG/SLCS 92 18 DPLUS PC0/GPIFADR0 72 Q16 19 DMINUS PC1/GPIFADR1 73 Q17 94 A0 PC2/GPIFADR2 74 95 A1 96 A2 97 A3 117 A4 U502 CY7C68013_128AC PC3/GPIFADR3 75 PC4//GPIFADR4 76 PC5/GPIFADR5 77 PC6/GPIFADR6 78 VCC;17,26,43,48,64,68,81,100,107 GND;20,27,49,58,65,80,93,116,125 A9 PE2/T2OUT 110 PE3/RXD0OUT 111 128 A10 PE4/RXD1OUT 112 21 A11 22 A12 PE5/INT6 113 PE6/T2EX 114 23 A13 PE7/GPIFADR8 115 24 A14 25 A15 PC7/GPIFADR7 79 NC1 14 D6 D7 88 87 D5 86 D4 63 D3 62 D2 61 D1 60 D0 59 T0 29 T1 30 T2 31 CTL5 R515 24.9 98 NC3 16 E503 CTL4 R516 2k REN2 R514 24.9 67 CTL3 NC2 15 RENEXT R513 24.9 66 R512 24.9 71 REN1 CTL0*FLAGA R511 24.9 70 VCC U503 VCC 8 A0 2 WP 7 A1 3 SCL 6 A2 4 5 VSS SDA 1 4 WENS 33 34 35 36 37 OE 38 INTERLEAVE_FIRSTWORD R524 0 CTL2/*FLAGC 127 CTL1/*FLAGB A8 RESERVED PE1/T1OUT 109 126 BKPT A7 EA PE0/T0OUT 108 120 SCL A6 SDA 119 PSEN A5 AGND 118 7 VCC R517 2k VCC C506 0.1F 122 Q13 RDY5 2 U505 PD4/FD12 R520 24.9 INTERLEAVE_FIRSTWORD 9 13 CLK Q GND 123 Q14 PA4/FIFOADR0 89 R523 2k 3 PD5/FD13 RDY4 C507 0.1F C508 0.1F C509 0.1F C510 0.1F C511 0.1F C512 0.1F C513 0.1F C514 0.1F C515 0.1F C516 0.1F Figure 28. PCB Schematic Rev. 0 | Page 29 of 44 C517 0.1F 04750-0-039 FF2 R521 332 Q 124 Q15 8 6 5 U505 PD6/FD14 R507 24.9 CTRL_D FF2 R510 24.9 69 14 1 5 53 PA3/*WU2 85 MRS VCC CLR PD7/FD15 RDY3 VCC MRS 52 7 1 J501 6 RXD1 R506 24.9 CTRL_C EF2 R509 10k VCC U504 8 VCC 7 PRE 2 D 51 PA2/*SLOE 84 VCC R522 332 4 50 RDY2 R508 10k 3 U505 RXD0 R505 24.9 CTRL_B 6 USB_VBUS E502 VCC 101 FF_USB R504 24.9 CTRL_A PA1/INT1 83 39 2 TXD0 PA0/INT0 82 RDY1/*SLWR 2 3 2 RDY0/*SLRD 5 CR501 R503 LED_SS 499 FF1 10 4 FF1 RD 4 INT5 106 INT4 28 EF1 40 C505 22pF Y501 24MHz IFCLK WR 1 CLKOUT CS C504 22pF 32 RESET RCLK E501 DVCC 1 3 R519 10k AVCC 4 FF_USB 41 R519 10k 5 +V GND GND 2 3 1 FF2 42 U501 C503 0.1F 99 VCC + C502 2.2F *WAKEUP R501 0 VCC FF1 C501 1F CR502 VAL VCC TXD1 VCC HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC WRT_CLK2 5 4 3 2 1 J207 1 2 2 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 43 Q9 42 Q8 41 Q7 RCLK REN2 62 61 EF2 FF2 REN RCLK 63 RM 64 65 PFM EF/OR 67 66 PAE VCC 69 68 IP BE 70 71 HF FSEL1 72 73 OW FSEL0 75 76 74 PAF FF/IR FWFT/SI 78 77 LD MRS PRS 79 CTRL_D J206 1 57 04750-0-040 7 6 OE2 Q6 9 8 GND 11 10 59 58 40 13 12 39 15 14 60 Q6 17 16 Q5 19 18 38 20 U201 Q5 21 Q7 VCC Q4 23 22 Q8 VCC 25 24 Q9 D8 37 26 D9 Q4 27 20 VCC 36 28 19 Q10 D10 Q3 29 18 D11 Q2 30 17 35 31 16 2 Q3 33 32 1 GND 34 34 J203 Q11 D12 Q1 35 GND GND 37 36 15 Q2 BUTT UP WITH J103 TO MAKE 80 PIN HEADER R202 10k 38 14 2 DUT_CLK2 Q12 GND 33 2 1 39 Q13 D13 32 1 J205 J204 40 VCC D14 Q1 D2_16 R201 10k 2 J202 D15 D7 1 13 D16 Q0 J201 D2_17 IDT72V283 TQFP80 BOTTOM FIFO GND 12 OPTION TO USE EXTRA BITS ON FIFO Q14 31 11 Q15 VCC Q0 10 D17 30 D2_16 GND D0 9 GND GND D1 8 IW 29 D2_17 Q16 28 7 Q17 DNC D2 6 VCC 27 5 D3 C208 0.1F D4 C207 0.1F 26 C206 0.1F VCC 25 C205 0.1F OE DNC 21 C204 0.1F RT SEN D5 4 C203 0.1F WEN 24 2 D6 1 GND WEN2 23 E202 WCLK 80 VCC 3 C202 0.1F MRS E201 VCC C201 0.1F DRAFTMAN MAY REORDER BIT ASSIGNMENTS ON FIFO TO SIMPLIFY LAYOUT 22 POPULATE WITH PIN SOCKET PCB SCHEMATIC (Continued) CTRL_C Figure 29. PCB Schematic (Continued) Rev. 0 | Page 30 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC WRT_CLK1 7 6 5 4 3 2 1 57 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 43 Q9 42 Q8 41 Q7 RCLK REN1 62 61 EF1 FF1 REN RCLK 64 63 RM EF/OR 65 66 PAE PFM 67 68 IP VCC 70 69 BE FSEL1 72 71 HF FSEL0 73 OW 75 76 74 PAF FF/IR FWFT/SI 78 77 LD 79 PRS D1_9 D1_8 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 J107 1 2 CTRL_B 04750-0-041 8 OE1 Q6 9 GND 11 10 59 58 40 12 39 13 60 Q6 15 14 U101 Q5 16 D1_10 Q4 17 D1_11 38 19 18 Q7 Q5 20 VCC 37 21 Q8 Q4 23 22 Q9 D8 Q3 25 24 D1_12 D9 VCC 26 20 VCC 36 27 19 D1_13 Q10 D10 35 BUTT UP WITH J203 TO MAKE 80 PIN HEADER 28 29 18 D1_14 D11 Q3 30 17 Q2 31 16 2 GND 33 32 1 GND 34 34 J103 D1_15 Q11 D12 Q2 35 GND 33 37 36 15 Q1 R102 10k 38 14 2 DUT_CLK1 Q12 GND Q0 2 1 39 Q13 D13 32 1 J105 J104 40 VCC D14 Q1 D1_16 R101 10k 2 J102 D15 D7 1 13 D16 31 J101 D1_17 IDT72V283 TQFP80 TOP FIFO Q0 12 OPTION TO USE EXTRA BITS ON FIFO Q14 D0 11 Q15 VCC GND 10 D17 30 D1_16 GND D1 9 GND GND 29 8 IW 28 D1_17 Q16 D2 7 Q17 DNC 27 6 VCC D3 5 D4 C108 0.1F 26 C107 0.1F 25 C106 0.1F VCC D5 C105 0.1F OE DNC 21 C104 0.1F RT SEN 24 4 C103 0.1F WEN D6 2 GND 1 23 WEN1 22 E102 MRS 80 VCC 3 C102 0.1F MRS E101 VCC C101 0.1F DRAFTMAN MAY REORDER BIT ASSIGNMENTS ON FIFO TO SIMPLIFY LAYOUT WCLK POPULATE WITH PIN SOCKET PCB SCHEMATIC (Continued) J106 1 2 CTRL_A Figure 30. PCB Schematic (Continued) Rev. 0 | Page 31 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued) EXT_CLK1 R303 331 C302 0.1F TOP FIFO DUT_CLK1 VCC C305 0.1F R304 331 C303 0.1F R302 DNP 9 BOTTOM FIFO DUT_CLK2 6 EN EN 13 VCC 1 DS90LV048A 2 1 3 J303 1 2 3 R305 DNP EXT_CLK2 R307 331 6 4 5 HEADER J4 7 8 R308 331 R306 DNP VCC R311 331 J310 JMP0508 R312 J311 JMP0508 C310 0.1F ROUT2 RIN3+ ROUT3 RIN3- 11 RIN4+ RIN4- GND U301 ROUT4 2 J307 1 74VCX86 U302 8 13 74VCX86 R314 331 JMP0508 1 2 RCLK WRT_CLK1 3 4 WRT_CLK2 5 6 FF1 7 8 9 10 EF1 11 12 EF2 E303 J313 JMP0508 R316 331 C307 10F C308 + 0.1F 11 74VCX86 E305 1 J308 VCC R315 C311 0.1F U302 12 12 VCC J312 3 J315 WRT_CLK2 1 C306 0.1F 9 1 E306 3 J314 WRT_CLK1 VCC R310 1k 10 3 TOP FIFO BOTTOM FIFO OE1 13 14 OE2 15 16 REN2 MRS 17 18 WENS 19 20 C309 10F Figure 31. PCB Schematic (Continued) Rev. 0 | Page 32 of 44 E304 FF2 REN1 VCC + J306 1 6 R309 1k J305 10 J309 CON_2P_5MM 2 14 RIN2- U302 5 74VCX86 1 J304 3 RIN2+ 3 2 15 2 R313 331 ROUT1 RIN1- 1 J302 C304 0.1F 4 VCC PLACE JUMPERS BETWEEN PADS ON TOP SIDE VCC RIN1+ 4 U302 HEADER 20 04750-0-042 J301 C301 0.1F POPULATE WITH PIN SOCKET E302 E301 HEADER J3 R301 DNP VCC HEADER J3 VCC HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued) VCC WENS R405 162 R406 130 R402 DNP R401 20k 10 1 2 R403 DNP U401 MC100EPT22 1 D0 2 D0 4 5 R411 162 R412 130 3 VCC 7 C401 0.001F R410 162 VCC VBB D R S CLK0 CLK CLK0 Q R0 19 S0 18 1 Q0 17 2 Q0 16 U403 MC100EPT23 15 J401 WEN1 Q J403 WRT_CLK2 HEADER J3 WRT_CLK1 U401 MC100EPT22 3 3 6 4 1 R407 162 6 CLK 7 CLK 8 D1 9 D1 WEN2 7 VCC;20 D R S CLK Q Q1 Q1 14 S1 13 R1 12 Q R408 162 GND 4 3 R413 162 1 1 3 3 J402 6 U403 R414 MC100EPT23 162 11 U402 R409 130 R415 130 VCC C402 0.1F C403 0.1F C404 0.1F C405 0.1F Figure 32. PCB Schematic (Continued) Rev. 0 | Page 33 of 44 04750-0-043 R404 162 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC PCB SCHEMATIC (Continued) D1_9 D1_10 D1_11 D1_12 D1_13 D1_14 D1_15 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1 DC0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DC3 R603 0 D1_17 2 2 37 QL1 3 3 4 DC2 4 38 QL2 DC6 5 39 QL3 5 DC8 6 40 QL4 6 DC7 7 41 QL5 7 42 QL6 8 43 QL7 9 DC12 DC13 DC14 DC15 DC0 DC13 DC1 8 9 10 44 DC14 11 45 DC15 DC2 DC4 12 46 DC3 DC5 13 47 DC16 14 48 DC1 DC4 DC5 DC9 15 49 DC6 DC17 16 50 17 51 18 52 DC7 R602 D1_16 36 QL0 DC11 DC10 D1_0 RENEXT 1 DC10 R601 16 35 DC9 DC11 1 U601 J601 DC8 Q0 D0 Q1 D1 D2 Q2 D3 Q3 Q4 D4 D5 Q5 Q6 D6 Q7 D7 GND CLOCK 20 VCC 19 1 16 Q0 18 2 15 Q1 17 3 14 Q2 16 4 13 Q3 15 5 12 Q4 14 6 11 Q5 13 7 10 Q6 12 8 9 11 RCLK Q7 RZ605 74LCX574 VCC DC12 19 53 20 54 DC17 21 55 22 56 23 57 REN1 24 58 RCLK EF1 25 59 FF1 26 60 MRS 27 61 WEN1 WRT_CLK1 28 62 QL0 29 63 QL1 30 64 QL2 QL3 31 65 QL4 32 66 QL5 33 67 QL6 34 68 QL7 VCC C601 0.1F DC16 R604 0 10 OUT_EN Figure 33. PCB Schematic (Continued) Rev. 0 | Page 34 of 44 04750-0-044 D1_8 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-045 ASSEMBLY--PRIMARY SIDE Figure 34. Assembly--Primary Side Rev. 0 | Page 35 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-046 ASSEMBLY--SECONDARY SIDE Figure 35. Assembly--Secondary Side Rev. 0 | Page 36 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-047 LAYER 1-- PRIMARY SIDE Figure 36. Layer 1--Primary Side Rev. 0 | Page 37 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-048 LAYER 2--GROUND PLANE Figure 37. Layer 2--Ground Plane Rev. 0 | Page 38 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-049 LAYER 3--POWER PLANE Figure 38. Layer 3--Power Plane Rev. 0 | Page 39 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC 04750-0-050 LAYER 4--SECONDARY SIDE Figure 39. Layer 4--Secondary Side ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 40 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC BILL OF MATERIALS Table 5. HSC-ADC-EVAL-SC/HSC-ADC-EVAL-DC Bill of Materials Quantity Item SC DC Reference Designation C101-108, C201-208, C301-304, C306, C402-405, C503, C506-517, C601 1 39 39 2 4 4 3 4 5 6 7 8 9 2 1 1 1 2 1 1 2 1 1 1 2 1 1 10 14 14 11 1 1 J104/J204 12 1 1 J303 13 7 7 J304-305, J314-315, J401-403 14 1 1 J309 15 4 4 J310-313 16 1 1 J501 17 2 2 J301-302 18 1 1 J308 19 1 1 J601 20 6 6 21 8 8 22 23 2 1 2 1 24 8 8 25 26 27 28 4 2 1 1 4 2 1 1 C305, C308, C310-311 C307 ,C309 C401 C501 C502 C504-505 CR501 CR502 J101-103, J105-107, J201-203, J205-207, J306-307 R101-102, R201-202, R518-519 R303-304, R307-308, R311, R313-314, R316 R309-310 R401 R404-405, R407-408, R410-411, R413-414 R406, R409, R412, R415 R501, R524 R502 R503 Description Package Value Capacitor 0805 0.1 F Capacitor, 50 V, 20% 1206 0.1 F Capacitor, 16 V, 10% Capacitor, 50 V, 20% Capacitor, 16 V, 20% Capacitor, 20% Capacitor LED Diode, 100 V 6032 0805 3216 6032 0805 0603 SOD-123 10 F 0.001 uF 1 F 2.2 F 22 pF Green 1N4148W-7 2-Pin Jumper Header 80-Pin Connector Header, Right Angle 4-Pin Connector, Straight 3-Pin Connector, Straight 2-Pin Terminal Strip, Straight Solder Bridge (No Component) 4-Pin USB Connector, Right Angle SMA Connector (Not Populated) 20-Pin Connector Header, Straight (Not Populated) 68-Pin Connector, Right Angle (Not Populated) Female SSW-140-03-S-D-RA Male TSW-1-10-08-GD Male TWS-103-08-G-S Male Z5.530.0225.0 0508 Female 787780-1 Male 142-0701-201 Male TSW-110-08-T-D Male 787082-7 Resistor, 1/8 W, 1% 1206 10 k Resistor, 1/8 W, 1% 1206 331 Resistor, 1/8 W, 1% Resistor, 1/8 W, 1% 1206 1206 1 k 20 k Resistor, 1/8 W, 1% 1206 49.9 Resistor, 1/8 W, 1% Resistor, 1/10 W, 1% Resistor, 1/8 W, 1% Resistor, 1/10 W, 1% 1206 0805 1206 0805 40.2 0 100 k 499 Rev. 0 | Page 41 of 44 Manufacture HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC Quantity Reference Designation R504-507, R510-515, R520, R525-526 R508-509 R516-517 R521-522 R523 R603-604 R312, R315 R301-302, R305-306, R402-403 Item SC DC 29 13 13 30 31 32 33 34 35 2 2 2 1 2 2 2 2 2 1 2 2 36 6 6 37 2 2 R601-602 38 1 1 RZ605 39 40 41 42 43 44 45 46 47 48 49 50 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 U101, U201 U301 U302 U401 U402 U403 U501 U502 U503 U504 U505 U601 51 1 1 Y501 Description Package Value Resistor, 1/8 W, 1% 1206 24.9 Resistor, 1/10 W, 1% Resistor, 1/8 W, 1% Resistor, 1/10 W, 1% Resistor, 1/10 W, 1% Resistor, 1/16 W, 5% Potentiometer, 10% Resistor (Not Populated) Resistor (Not Populated) Resistor Array, 8 pcs, 1/4 W, 5% IC IC IC IC IC IC IC IC IC IC IC IC Crystal Oscillator, 24 MHz 0805 1206 0805 0805 0402 10 k 2 k 0 2k 0 1 k 0402 0 k TQFP80 SOIC16 SOIC14 SO8M1 TSSOP20 SO8M1 SOT23L5 TQFP128 PDIP8 SSOP8 SOIC14 IDT72V283L7-5PF DS90LV048ATM 74VCX86M MC100EPT22D MC100EP29DT MC100EPT23D NC7SZ32M5 CY7C68013-128AC 24LC00P SN74LVC2G74DCTR 74LVQ04SC 74LCX574WM IDT National Semi Fairchild OnSemi OnSemi OnSemi Fairchild Cypress MicroChip TI Fairchild Fairchild 2-Pin Can ECS-240-20-4 ECS Rev. 0 | Page 42 of 44 Manufacture HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC APPENDIX: SAMPLING AND FFT FUNDAMENTALS COHERENT SAMPLING M = Sample Size (2N) In a coherent system, the analog and clock sources must be synchronized, and the analog and clock input frequencies must be selected such that given 2N (N is an integer number) samples, there is an integer number of whole sine wave cycles. The number of cycles should ideally be a prime number. Selecting a prime number ensures that the same converter codes are not repeated over and over, therefore exercising as many converter codes as possible. Although a crystal oscillator can be used as an clock source in this technique, two synchronized signal synthesizers are generally preferred because special hardware may be required to ensure the crystal oscillator is synchronized with the analog source. The following equation can be used to mathematically calculate the correct analog and clock frequencies for a coherent system: n = Indexed Sample Number fin M = fs Mc where: fin = Analog Input Frequency fs = Sampling Clock (encode) Frequency M = Sample Size (2N) Mc = Number of Cycles of Sine Wave If the requirements of the coherent system defined above are not met, the discrete time samples will appear discontinuous at the end of the captured samples and the results will be invalid. The weighting function for a Hanning window is: 2 x n Wn = 0.5 - 0.5 x cos M where: M = Sample Size(2N) n = Indexed Sample Number FFT CALCULATIONS Whether a system is coherent or a windowing function has been applied, the resulting data will be processed via a discrete fourier analysis that translates the discrete time-domain samples into the frequency domain. Because in practice processing the data quickly is desired, a Fast Fourier Transform (FFT) is used, which is simply an algorithm that reduces the required mathematical calculations. There are many FFT algorithms available but the most popular is the radix 2 algorithm. Regardless of the algorithm, for each time-domain sample a complex conjugate pair (r jx) will be generated from the FFT. For example, if the time-domain sample size is 16,384, the resulting FFT array will contain 16,384 complex samples. To generate a frequency domain plot from this data, the magnitude of each complex sample must be calculated. The magnitude can be computed using the following equation: Magnitude = Re 2 + Im 2 WINDOWING FUNCTIONS It is sometimes desirable to use a windowing function instead of coherent sampling to reduce the restrictions on the analog and encode sources. Two popular windowing functions are the Blackman Harris 4-Term and the Hanning window. With windowing, the time-domain samples are multiplied by the appropriate weighting function that weights the time-domain data such that the discontinuities at the end of the captured samples have less significance. The weighting function for a Blackman Harris 4-Term window is: 2 x n 2 x 3n 2x 2n - a3 x cos Wn = a0 - a1 x cos + a2 x cos M M M where: If the input data to the FFT is complex, the FFT will contain 16,384 magnitudes representing frequencies between plus and minus fs/2. Although complex ADCs are not available, it is very common to use two ADCs to synchronously sample the I and Q data streams from a quadrature demodulator. If the data input to the FFT is real, representing the data from a single ADC, the last 8192 samples represent a mirror image of the first 8192 samples. Because this is an exact mirror image, the last 8192 samples can be ignored. With the data set processed, there are two ways to evaluate the ADC performance, graphically and computationally. To plot the data in a meaningful way, the magnitude data must be converted to decibels (dB). This can be done with the formula: a0 = 0.35875 Magnitude dB = 10 x log10 FullScale a1 = 0.48829 a2 = 0.14128 a3 = 0.01168 where Magnitude is the individual array elements computed above, and FullScale is the FullScale magnitude. It is important to note that the computation for dB assumes the square root Rev. 0 | Page 43 of 44 HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC was not actually taken in the equation above, leaving the magnitude expressed as the sum of two squares. Therefore 10 x log is used instead of 20 x log, eliminating the time required to compute the square root. Fundamental_Energy dB SNR = 20 x log 10 Noise_Energy Based on Nyquist Theory, the encode rate must be at least twice the signal bandwidth to faithfully represent the signal when sampled. Therefore, if the encode rate is 80 MHz, an ADC can only represent 40 MHz of continuous bandwidth. Knowing the encode rate and the number of time-domain samples, the frequency representation per bin can be established. In this example, the encode rate is 80 MHz and there are 16,384 timedomain samples; therefore, 4880 Hz/bin is represented. If the encode rate is doubled or the number of time-domain samples is doubled, a 3 dB improvement in the noise floor is observed. This does not represent an improvement in ADC performance, but simply represents an increased resolution per bin. From the computations above, it is now possible to define and calculate SNR, SINAD, harmonics, SFDR, ENOB, and noise figure. The signal-to-noise ratio can be expressed as the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components, excluding the first six harmonics and dc, or by the equation: Noise_Energy represents the summation of all the noise energy in the spectrum, and Fundamental_Energy represents the summation of the fundamental energy. The fundamental energy resides in a single bin if a coherent system is used; however, in the case of a windowing function, it may be spread over 10 to 25 bins, depending on the windowing technique. Harmonics can be defined as the ratio of the rms signal amplitude to the rms value of the harmonic component, reported in dBc. Harmonics represent the nonlinearities within the ADC and are integer multiples of the fundamental. If the harmonic exceeds fs/2, it will be aliased back into the first Nyquist zone. A concept closely related to harmonics is SFDR. For an ADC, SFDR is defined as the ratio between the rms amplitude of a single tone and the rms amplitude of the worst spur as the tone is swept through the entire ADC input range. It is very common for the worst spur to be harmonically related. Whereas SNR excludes the first five harmonics, SINAD includes these harmonics as part of the Noise_Energy summation, otherwise known as THD or Total Harmonic Distortion. If the harmonic performance of the ADC is excellent, there is very little difference between the SNR value and the SINAD value. ORDERING GUIDE Model HSC-ADC-EVALA-SC HSC-ADC-EVALA-DC AD922XFFA1 AD664XFFA1, 2 AD9432FFA1 AD9283FFA1 AD9071FFA1 AD9059FFA1 AD9051FFA1 LG-0204A1 1 2 Description Single FIFO Version of USB Evaluation Kit Dual FIFO Version of USB Evaluation Kit Adapter for AD922x Family (Not included in Evaluation Kit) Adapter for AD664x Family (Not included in Evaluation Kit) Adapter for the AD9432 (Not included in Evaluation Kit) Adapter for the AD9283 and AD9057 (Not included in Evauation Kit) Adapter for the AD9071 (Not included in Evaluation Kit) Adapter for the AD9059 (Not included in Evaluation Kit) Adapter for the AD9051 (Not included in Evaluation Kit) Adapter for the AD10xxx and AD13xxx Families (Not included in Evaluation Kit) If an adapter is needed, send an email to highspeed.converters@analog.com with the part number of the adapter and a mailing address. Required for Revision C of AD6644 and AD6645 evaluation boards. Revision D and greater are directly compatible with e HSC-ADC-EVALA-SC evaluation board (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04750-0-5/04(0) Rev. 0 | Page 44 of 44