PE46130
Document Category: Product Specification
Monolithic Phase & Amplitude Controller, 2.3–2.7 GHz
©2014–2016, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-64169-4 – (08/2016)
www.psemi.com
Features
• 90° phase splitter
• 4-bit digital step attenuator, 7.5 dB range, 0.5 dB
resolution
• 5-bit digital phase shifter, 87.2° range, 2.8°
resolution
• High power handling and linearity
▪P0.1dB of +35 dBm
▪Input IP3 of +70 dBm
• 3-bit insertion loss stabilizer (ILS)
▪0.35 dB range, 0.05 dB resolution
• Packaging – 32-lead 6 × 6 × 0.85 mm QFN
Applications
• Wireless infrastructure
▪Macro cells
▪Small cells (micro, pico)
▪Distributed antenna systems (DAS)
• Precision phase shifter
• Dual polarization antenna alignment
• Analog linearization techniques
Product Description
The PE46130 is a HaRP™ technology-enhanced monolithic phase and amplitude controller (MPAC) designed
for precise phase and amplitude control of two independent RF paths. It optimizes system performance while
reducing manufacturing costs of transmitters that use symmetric or asymmetric power amplifier designs to
efficiently process signals with large peak-to-average ratios.
This monolithic RFIC integrates a 90° RF splitter, digital phase shifters and a digital step attenuator along with a
low voltage CMOS serial interface. It can cover a phase range of 87.2° in 2.8° steps and an attenuation range of
7.5 dB in 0.5 dB steps, while providing excellent phase and amplitude accuracy from 2.3–2.7 GHz.
The PE46130 also features exceptional linearity, high output port-to-port isolation and extremely low power
consumption relative to competing module solutions. It is offered in a 32-lead 6 × 6 mm QFN package.
The PE46130 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-on-insulator
(SOI) technology on a sapphire substrate, of fering the perf ormance of GaAs with th e economy and integration of
Figure 1 • PE46130 Functional Diagram
RFIN
VDD
GND
SDI
CLK
LE
DS
SDO
RFOUT2
-90°
0°
RFOUT1
SPENB
7.5 dB
0.5 dB LSB
0 dB
87.2°
2.8° LSB
87.2°
2.8° LSB
Digital Interface
3
Serial
Interface
PE46130
MPAC
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conventional CMOS. Peregrine’ s HaRP technology enhancement s deliver high linearity and excellent harmonics
performance.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE46130
Parameter/Condition Min Max Unit
Supply voltage, VDD –0.3 5.5 V
Digital input voltage –0.3 3.6 V
Maximum input power 35 dBm
Storage temperature range –65 +150 °C
ESD voltage HBM(1)
All pins 1500 V
ESD voltage CDM, RF pins to ground(2) 500 V
Notes:
1) Human body m ode l ( MI L-S TD 883 M eth od 3015 .7 ).
2) Charged de vice model (JEDEC JESD 22 -C10 1) .
PE46130
MPAC
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Recommended Operating Conditions
Table 2 lists the recommending operating condition for PE46130. Devices should not be operated outside the
recommended operating conditions listed below.
Table 2 • Recommended Operating Condition for PE46130
Parameter Min Typ Max Unit
Supply voltage, VDD(1) 2.3 5.5 V
Supply current 350 500 µA
Digital input high 1.17 3.6 V
Digital input low 0 0.6 V
Digital input leakage 10 20 µA
RF input power, CW 29 dBm
RF input power, pulsed(2) 32 dBm
Operating temperature range –40 +25 +105 °C
Notes:
1) Product perfor mance doe s n ot vary o ver V DD.
2) Pulsed, 5% duty cycle of 4620 µs period.
PE46130
MPAC
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Electrical Specifications
Table 3 provides the PE46130 key electrical specifications at +25 °C, VDD = 2.3–5.5V, 50Ω, unless otherwise
specified.
Table 3 • PE46130 Electrical Specifications at +25 °C
Parameter Path Condition Min Typ Max Unit
Operating frequency 2.3 2.7 GHz
Insertion loss RFIN to RFOUTX Reference phase and minimum attenuation state.
Includes 3 dB from power divider. 7.2 7.7 dB
Input return loss RFIN 2.3–2.7 GHz 15 dB
Output return loss RFOUT1 or RFOUT2 2.3–2.7 GHz 15 dB
Isolation RFOUT1 to RFOUT2 2.3–2.7 GHz
Reference phase and minimum attenuation state. 26.5 30 dB
Input 0.1dB compression
point(1) RFIN to RFOUTX 2.3–2.7 GHz 35 dBm
Input IP3 RFIN to RFOUTX 2.3–2.7 GHz 70 dBm
Switching time(2) 50% LE to 90% or 10% RF final value 980 1220 ns
Phase shift range RFIN to RFOUTX 87.2 Deg
Phase step 2.8 Deg
Relative phase shift RFOUT1 to RFOUT2 Phase (RFOUT1)–Phase (RFOUT2) [same state] –90 Deg
Attenuation range RFIN to RFOUT2 7.5 dB
Attenuation step 0.5 dB
Notes:
1) The input 0.1dB compressio n point is a lin earity figur e of merit. Ref er to Table 2 for th e operatin g R F inp ut p ow er (50 Ω).
2) Worst case state transition. All bits changing.
PE46130
MPAC
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Table 4 provides the PE46130 key electrical specifications at +105 °C, VDD = 2.3–5.5V, 50Ω, unless otherwise
specified.
Table 4 • PE46130 Electrical Specifications at +105 °C
Parameter Path Condition Min Typ Max Unit
Operating frequency 2.3 2.7 GHz
Insertion loss RFIN to RFOUTX Reference phase and minimum attenuation state.
Includes 3 dB from power divider. 7.2 8.6 dB
Input return loss RFIN 2.3–2.7 GHz 15 dB
Output return loss RFOUT1 or RFOUT2 2.3–2.7 GHz 15 dB
Isolation RFOUT1 to RFOUT2 2.3–2.7 GHz
Reference phase and minimum attenuation state. 26.5 30 dB
Input 0.1dB compression
point(1) RFIN to RFOUTX 2.3–2.7 GHz 35 dBm
Input IP3 RFIN to RFOUTX 2.3–2.7 GHz 70 dBm
Switching time(2) 50% LE to 90% or 10% RF final value 980 1220 ns
Phase shift range RFIN to RFOUTX 87.2 Deg
Phase step 2.8 Deg
Relative phase shift RFOUT1 to RFOUT2 Phase (RFOUT1)–Phase (RFOUT2) [same state] –90 Deg
Attenuation range RFIN to RFOUT2 7.5 dB
Attenuation step 0.5 dB
Notes:
1) The input 0.1 dB com pr ession p oint is a linear ity figu re o f mer it. R ef er to Table 2 for the operating RF input power (50Ω).
2) Worst case state transition. All bits changing.
PE46130
MPAC
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Switching Frequency
The PE46130 has a maximum 25 kHz switching
frequency.
The switching frequency is defined to be the rate at
which the PE46130 can be continuously toggled
across attenuation and phase states.
Thermal Data
Psi-JT (JT), junction top-of-package, is a thermal
metric to estimate junction temperature of a device on
the customer application PCB (JEDEC JESD51-2).
JT = (TJ – TT)/P
where
JT = junction-to-top of package characterization
parameter, °C/W
TJ = die junction temperature, °C
TT = package temperature (top surface, in the
center), °C
P = power dissipated by device, Watts
Table 5 • Thermal Data for PE46130
Parameter Typ Unit
Maximum junction temperature, T JMAX
+105°C ambient 123.3 °C
JT 3.1 °C/W
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MPAC
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Control Logic
Table 6–Table 13 provide the control logic truth tables for the PE46130.
Table 6 • Bit Descriptions
C0 Channel register select
C0 = L, channel RFOUT1 register select
C0 = H, channel RFOUT2 register select
M0–M3 Attenuation setting per channel in dB
P0–P4 Phase shift setting per channel in deg
S0–S3 Insertion loss stabilizer setting per channel
Table 7 • 14-bit Word
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
1 — —————4522.511.25.62.8——
2 — 0.2 4 2 1 0.5 45 22.5 11.2 5.6 2.8 0.1 0.05
Table 8 • Serial Truth Table – Phase Setting
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Phase
Shift
Setting
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
1/2 —0.2 4210.5 45 22.5 11.2 5.6 2.8 0.1 0.05
X L XXXXXLLLLLXXRef Phase
X L XXXXXLLLLHXX2.8 deg
X L XXXXXLLLHLXX5.6 deg
X L XXXXXLLHLLXX11.25 deg
X L XXXXXLHLLLXX22.5 deg
X L XXXXXHLLLLXX45 deg
X L XXXXXHHHHHXX87.2 deg
PE46130
MPAC
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Table 9 • Serial Truth Table – Attenuation Setting (RFOUT2)
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Amplitude
Setting
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
2—0.2 4210.5 45 22.5 11.2 5.6 2.8 0.1 0.05
H L XLLLLXXXXXXXRef Insertion Loss
H L XLLLHXXXXXXX 0.5 dB
H L XLLHLXXXXXXX 1 dB
H L XLHLLXXXXXXX 2 dB
H L X HLLLXXXXXXX 4 dB
H L XHHHHXXXXXXX 7.5 dB
Table 10 • Default State Settings at Power Up (RFOUT1)
DS
Setting
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Default
Setting
at Power
Up
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
1/2 —0.2 4210.5 45 22.5 11.2 5.6 2.8 0.1 0.05
DS = 0— — ————— LLLLL—— 0 dB
0 deg
DS = 1— — —————H LLLL—— 0 dB
45 deg
Table 11 • Default State Settings at Power Up (RFOUT2)
DS
Setting
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Default
Setting
at Power
Up
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
1/2 —0.2 4210.5 45 22.5 11.2 5.6 2.8 0.1 0.05
DS = 0— L LLLLLLLLLLLL 0 dB
0 deg
DS = 1— L LHHHHHLLLLLL7.5 dB
45 deg
PE46130
MPAC
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Insertion Loss Stabilizer
The PE46130 offers greater insertion loss stability by compensating for known variations between phase states.
Three attenuation bits are used to reduce the variation seen in the insertion loss across all phase states for the
RFOUT2 path. ILS bits S0–S2 are accessible for creating a custom lookup table in applications where insertion
loss variation between phase states is critical.
Table 12 • Insertion Loss Stabilizer Bit Definition
Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Amplitude
Setting
C0 S3 S2 M3 M2 M1 M0 P4 P3 P2 P1 P0 S1 S0
2—0.2 4210.5 45 22.5 11.2 5.6 2.8 0.1 0.05
X X XXXXXXXXXXXX
H L LXXXXXXXXXLL Ref IL
H L LXXXXXXXXXLH .05 dB
H L LXXXXXXXXXHL .1 dB
H L HXXXXXXXXXLL .2 dB
H L HXXXXXXXXXHH .35 dB
Table 13 • Serial Interface Timing Characteristics (1)
Parameter/Condition Min Max Unit
Serial clock frequency, FCLK(2) 0.032 26 MHz
Serial clock period, TSCLK 40 ns
Serial clock HIGH time, TSCLKH 20 ns
Serial clock LOW time, TSCLKL 20 ns
Serial data output propagation delay from CLK falling edge, TOV (10 pF) 9ns
Latch clock pulse width high, TLCLKH 10 ns
Serial data input setup time from CLK rising edge, TSU 5ns
Serial data input hold time from CLK rising edge, TH2ns
Serial data output hold time from CLK rising edge, TOH 1.6 ns
Serial clock rising edge setup time to latch clock rising edge, T SETTLE 27 ns
SDO drive strength(3) 15 pF
Notes:
1) VDD = 2.3V–5.5V, –40 °C < TA < +105 °C, unless otherwise specified.
2) Limited by test dur ation no t static log i c design . Syn chr onou s to clo ck. M inimu m clock fr eq uency test ed = 3 2 kHz.
3) SDO maximum capacitive lo ad drive str ength f or FCLK = 26 MH z wi th a 1. 8V swing .
PE46130
MPAC
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Programming Options
Serial Interface
The serial interface is a 14-bit serial-in shift register
with two parallel-out channel registers RFOUT1 and
RFOUT2 buffered by a transparent latch. The 14 bits
comprise four bits defining the atte nuation setting, five
bits for the phase shift setting and three bits for the
insertion loss stabilization feature. Channel register
RFOUT1 and RFOUT2 selection is determined by the
value of the C0 bit contained as part of the 14-bit
program word.
The serial interface is controlled using three CMOS
compatible signals: serial data in (SDI), clock (CLK)
and latch enable (LE). The SDI and CLK inputs allow
data to be serially entered into the shif t register. Serial
data is clocked in starting with two ILS LSB bits first
and then the phase setting LSB. The shift register
must be loaded while LE is held LOW to prevent the
internal channel register values from changing as
data is entered. The LE input should then be toggled
HIGH, latching the new data into the PE46130. SDO
is a clock delayed reply of the user ’s input SDI
command for functional confirmation.
Phase shift, attenuation and insertion loss stabilizer
setting truth tables are listed in Table 8, Table 9 and
Table 12. The serial timing diagram is illustrated in
Figure 2 and associated AC characteristics are listed
in Table 13.
Power-up Control Settings
The PE46130 will power up in one of two default
states depending upon the setting of the default state
(DS) pin, as defined in Table 10 and Table 11. No
specific signal sequencing is required for the default
state to be set and active once VDD is applied.
Figure 2 • Latched Buffered SDO Serial Interface
SCLK
SDI
SDO
Channel 1
Register Data
Channel 2
Register Data
LE
S0 S1 P0 P1 P2 P3 P4 M0M1M2M3 S2 S3 C0
01
S0 S1 P0 P1 P2 P3 P4 M0M1M2M3 S2 S3 C0
S0
TOV TSCLK TSU THTSCLKH
TLCLKH
TSettle
TOH
Default/Current Value
Default/Current Value
New Value
New Value
TSCLKL
S1 P0 P1 P2 P3 P4 M0M1M2M3 S2 S3 C0 S0 S1 P0 P1 P2 P3 P4 M0M1M2M3 S2 S3 C0
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MPAC
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Typical Performance Data
Figure 3–Figure 21 show the typical performance data at 25 °C, VDD = 2.3–5.5V. 50Ω, unless otherwise
specified.
Figure 3 • Relative Phase Shift (RFOUT1–RFOUT2)
-100
-98
-96
-94
-92
-90
-88
-86
-84
-82
-80
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Phase Delta (Deg)
Frequency (GHz)
Phase (S21) - Phase (S31)
PE46130
MPAC
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Figure 4 • Insertion Loss (RFIN–RFOUT1)
-8
-7.8
-7.6
-7.4
-7.2
-7
-6.8
-6.6
-6.4
-6.2
-6
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Insertion Loss (dB)
Magnitude (S21)
Frequency (GHz)
Figure 5 • Insertion Loss (RFIN–RFOUT2)
-8
-7.8
-7.6
-7.4
-7.2
-7
-6.8
-6.6
-6.4
-6.2
-6
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Insertion Loss (dB)
Magnitude (S31)
Frequency (GHz)
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Figure 6 • Insertion Loss RFIN–RFOUT2 (All RFOUT2 Attenuation States)
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Insertion Loss (dB)
Frequency (GHz)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
Figure 7 • Relative Phase RFIN–RFOUT1 (All RFOUT1 Phase States)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Phase (Deg)
Frequency (GHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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MPAC
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Figure 8 • Relative Phase RFIN–RFOUT2 (All RFOUT2 Phase States)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Phase (Deg)
Frequency (GHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Figure 9 • Input Return Loss (All States)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Return Loss (dB)
Frequency (GHz)
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Figure 10 • Output Return Loss RFOUT1 (All RFOUT1 Phase States)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Return Loss (dB)
Frequency (GHz)
Figure 11 • Output Return Loss RFOUT2 (All RFOUT2 Phase States)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Return Loss (dB)
Frequency (GHz)
PE46130
MPAC
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Figure 12 • Isolation Output Ports (All States)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Isolation (dB)
Frequency (GHz)
Figure 13 • RFOUT1 Insertion Loss Variation Across RFOUT2 Phase State
-9
-8.6
-8.2
-7.8
-7.4
-7
-6.6
-6.2
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Insertion Loss (dB)
Frequency (GHz)
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Figure 14 • RFOUT1Phase Variation Across all RFOUT2 Phase States
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
22.12.22.3 2.4 2.5 2.6 2.7 2.8 2.9 3
Phase (Deg)
Frequency (GHz)
Figure 15 • RFOUT1 Insertion Loss Variation Across RFOUT1 Phase State
-9
-8.6
-8.2
-7.8
-7.4
-7
-6.6
-6.2
0 102030405060708090
Insertion Loss (dB)
Phase State (Deg)
2.3 GHz 2.5 GHz 2.7 GHz
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Figure 16 • RFOUT2 Insertion Loss Variation Across RFOUT2 Phase State
-9
-8.6
-8.2
-7.8
-7.4
-7
-6.6
-6.2
0 102030405060708090
Insertion Loss (dB)
Phase State (Deg)
2.3 GHz 2.5 GHz 2.7 GHz
Figure 17 • RFOUT2 Phase Variation Across RFOUT2 Attenuation State
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
Phase (Deg)
Attenuation State (dB)
2.3 GHz 2.5 GHz 2.7 GHz
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Figure 18 • RFOUT2 Insertion Loss Across RFOUT2 Attenuation State vs VDD, Frequency = 2.5 GHz
-16
-14
-12
-10
-8
-6
-4
-2
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
Insertion Loss (dB)
Attenuation State (dB)
2.3V 3.3V 5.5V
Figure 19 • RFOUT2 Insertion Loss Across RFOUT2 Attenuation State vs Temperature, Frequency = 2.5 GHz
-16
-14
-12
-10
-8
-6
-4
-2
0
00.511.522.533.544.555.566.577.5
Insertion Loss (dB)
Attenuation State (dB)
-40 °C +25 °C +85 °C +105 °C
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MPAC
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Figure 20 • RFOUT2 Relative Phase State Across RFOUT2 Phase State vs VDD, Frequency = 2.5 GHz
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 102030405060708090
Relative Phase (Deg)
Phase State (Deg)
2.3V 3.3V 5.5V
Figure 21 • RFOUT2 Relative Phase State Across RFOUT2 Phase State vs Temperature, Frequency = 2.5 GHz
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 102030405060708090
Relative Phase (Deg)
Phase State (Deg)
+105 °C-40 °C +25 °C +85 °C
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Pin Information
This section provides pinout information for the
PE46130. Figure 22 shows the pin map of this device
for the available package. Table 14 provides a
description fo r each pin.
Figure 22 • Pin Configuration (Top View)
Exposed
Ground Pad
RFOUT2
NC
NC
NC
NC
NC
NC
NC
VDD
LE
SDI
VDD
LE
SDI
NC
DS
SPENB
GND
RFOUT1
RFOUT1
NC
RFOUT2
CLK
NC
RFIN
RFIN
NC
SDO
CLK
SDO 1
3
4
5
6
7
8
2
9
11
12
13
14
15
16
10
32
30
29
28
27
26
25
31
24
22
21
20
19
18
17
23
NC
NC
Pin 1 Dot
Marking
Table 14 • Pin Descriptions for PE46130
Pin No. Pin
Name Description
1, 8 CLK(1) Clock input
2, 7 SDO(2) Serial data output
3, 6, 12–16,
22, 25–29 NC No connect
4, 5 RFIN(3) RF input
9, 32 SDI(1) Serial data input
10, 31 LE(1) Latch enable
11, 30 VDD(1) Supply voltage
17, 18 RFOUT1(3) RF output 1
19 GND(4) Ground
20 SPENB(5)(6) Serial port enable
21 DS(6) Default state at power up select
23, 24 RFOUT2(3) RF output 2
Pad GND Exposed pad: ground for proper oper-
ation
Notes:
1) Pins are internally connected, signal on ly need s to be app lie d to
one of the pins. The alter n ate unu s ed pin ne eds to be left floatin g.
2) SDOs are independ en tly b uffered ou tp uts of th e same sig nal.
3) RF pins 4, 5, 17 and 18 mu st be at 0 VDC. T he RF pins do no t
require DC blocking capacitors for pr oper opera tion if the 0 VDC
requirement is met.
4) Pin 19 must be grounded fo r proper function .
5) Must be active low for norm al SPI operation. Lo gi c hig h p ro gr ams
0 dB attenuation setting and 0° phase sett ing. Sett ing back to
logic low ret urns to the p r eviou sly pr ogr amm ed state.
6) Pin has an intern al 1 00 kΩ pull-up resistor.
PE46130
MPAC
Page 22 DOC-64169-4 – (08/2016)
www.psemi.com
Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape-and-reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE46130 in the 32-lead 6 × 6 × 0.85 mm QFN package is MSL1.
Package Drawing
Top-Marking Specification
Figure 23 • Package Mechanical Drawing for 32-lead 6 × 6 × 0.85 mm QFN
TOP VIEW BOTTOM VIEW
SIDE VIEW
RECOMMENDED LAND PATTERN
A0.10 C
(2X)
C
0.10 C
0.05 C
SEATING PLANE
B
0.10 C
(2X)
0.10 CA B
0.05 C
ALL FEATURES
PIN #1 CORNER
6.00±0.05
6.00±0.05 4.30±0.05
4.30±0.05
0.50
0.20±0.05
(x32)
0.40±0.05
(x32)
3.50
Ref.
0.85±0.05
0.05 MAX
0.203
Ref.
(x28)
4.35
4.35
0.85
(x32)
0.25
(x32) 0.50
(x28)
6.75
6.75
Figure 24 • Package Marking Specifications for PE46130
=
YY =
WW =
ZZZZZZZZ =
Pin 1 indicator
Last two digits of assembly year
Assembly work week
Assembly lot code (maximum eight characters)
PPPPPPPP
YYWW
ZZZZZZZZ
PE46130
MPAC
DOC-64169-4 – (08/2016) Page 23
www.psemi.com
Tape and Reel Specification
Product Specification
Figure 25 • Tape and Reel Specifications for 32-lead 6 × 6 × 0.85 mm QFN
Device Orientation in Tape
Pin 1
T
K0 A0
B0
P0 P1 D1 A
Section A-A
A
Direction of Feed
D0
E
W0
P2
see note 3
see
note 1
F
see note 3
A0
B0
K0
D0
D1
E
F
P0
P1
P2
T
W0
6.30 ± 0.10
6.30 ± 0.10
1.10 ± 0.10
1.50 + 0.1/ -0.0
1.5 min
1.75 ± 0.10
7.50 ± 0.10
4.00
12.00 ± 0.10
2.00 ± 0.10
0.30 ± 0.05
16.00 ± 0.30
Notes:
1. 10 Sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Dimensions are in millimeters unless otherwise specified
PE46130 MPAC
Product Specification www.psemi.com DOC-64169-4 – (08/2016)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications
and features may change in any manner without notice.
Preliminary Specification
The datasheet contains prelimin ary data. Addition al data may be ad ded
at a later date. Peregrine reserves the right to change specifications at
any time withou t not ice in or der to supp ly th e b est po ssible pr oduct .
Product Specification
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the
intended changes by issuing a CNF (Customer Notification Form).
Product Brief
This document contains a shortened version of the datasheet. For the
full datasheet, contact sales@psemi.com.
Not Recommended for New Designs (NRND)
This product is in production but is not recommended for new designs.
End of Life (EOL)
This product is currently going through the EOL process. It has a
specific last-time buy date.
Obsolete
This product is discontinued. Orders are no longer accepted for this
product.
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2014–2016, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trade-
marks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Ordering Information
Table 15 lists the available ordering codes for the PE46130 as well as available shipping methods.
Table 15 • Order Codes for PE46130
Order Codes Description Packaging Shipping Method
PE46130A–X PE46130 monolithic phase and
amplitude controller Green 32-lead 6 × 6 mm QFN 500 units/T&R
EK46130–02 PE46130 Evaluation kit Evaluation kit 1/box
