LTC6409
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For more information www.linear.com/LTC6409
LTC6409 Driving LTC2262-14 ADC,
fIN = 70MHz, –1dBFS,
fS = 150MHz, 4096-Point FFT
TYPICAL APPLICATION
DESCRIPTION
10GHz GBW, 1.1nV/√Hz
Differential Amplifier/ADC Driver
The LTC
®
6409 is a very high speed, low distortion, dif-
ferential amplifier. Its input common mode range includes
ground, so that a ground-referenced input signal can be
DC-coupled, level-shifted, and converted to drive an ADC
differentially.
The gain and feedback resistors are external, so that the
exact gain and frequency response can be tailored to each
application. For example, the amplifier could be externally
compensated in a no-overshoot configuration, which is
desired in certain time-domain applications.
The LTC6409 is stable in a differential gain of 1. This
allows for a low output noise in applications where gain
is not desired. It draws 52mA of supply current and has
a hardware shutdown feature which reduces current con-
sumption to 100µA.
The LTC6409 is available in a compact 3mm × 2mm
10-pin leadless QFN package and operates over a –40°C
to 125°C temperature range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of
AnalogDevices, Inc. All other trademarks are the property of their respective owners.
DC-Coupled Interface from a Ground-Referenced Single-Ended
Input to an LTC2262-14 ADC
FEATURES
APPLICATIONS
n 10GHz Gain-Bandwidth Product
n 88dB SFDR at 100MHz, 2VP-P
n 1.1nV/√Hz Input Noise Density
n Input Range Includes Ground
n External Resistors Set Gain (Min 1V/V)
n 3300V/µs Differential Slew Rate
n 52mA Supply Current
n 2.7V to 5.25V Supply Voltage Range
n Fully Differential Input and Output
n Adjustable Output Common Mode Voltage
n Low Power Shutdown
n Small 10-Lead 3mm × 2mm × 0.75mm QFN Package
n Differential Pipeline ADC Driver
n High Speed Data-Acquisition Cards
n Automated Test Equipment
n Time Domain Reflectometry
n Communications Receivers
+
–
–
+
150Ω
1.3pF
LTC6409
VOCM = 0.9V
VIN
33.2Ω
33.2Ω
10Ω
10Ω
150Ω
150Ω
150Ω
6409 TA01
AIN+
AIN–
LTC2262-14 ADC
GND
VDD
1.8V
3.3V
1.3pF
39pF
39pF
FREQUENCY (MHz)
6409 TA01b
AMPLITUDE (dBFS)
0
–80
–70
–60
–50
–40
–30
–20
–10
–90
–100
–110
–120 0 704010 5020 6030
VS = 3.3V
VOUTDIFF = 1.8VP-P
HD2 = –86.5dBc
HD3 = –89.4dBc
SFDR = 81.6dB
SNR = 71.1dB
LTC6409
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For more information www.linear.com/LTC6409
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOSDIFF Differential Offset Voltage (Input Referred) VS = 3V
VS = 3V
VS = 5V
VS = 5V
l
l
±300
±300
±1000
±1200
±1100
±1400
µV
µV
µV
µV
ΔVOSDIFF
ΔT Differential Offset Voltage Drift (Input Referred) VS = 3V
VS = 5V
l
l
2
2µV/°C
µV/°C
IBInput Bias Current (Note 6) VS = 3V
VS = 5V
l
l
–140
–160 –62
–70 0
0µA
µA
IOS Input Offset Current (Note 6) VS = 3V
VS = 5V
l
l
±2
±2 ±10
±10 µA
µA
RIN Input Resistance Common Mode
Differential Mode 165
860 kΩ
Ω
CIN Input Capacitance Differential Mode 0.5 pF
enDifferential Input Noise Voltage Density f = 1MHz, Not Including RI/RF Noise 1.1
nV/√Hz
inInput Noise Current Density f = 1MHz, Not Including RI/RF Noise 8.8
pA/√Hz
NF Noise Figure at 100MHz Shunt-Terminated to 50Ω, RS = 50Ω, RI = 25Ω,
RF = 10kΩ 6.9 dB
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ – V–) .................................5.5V
Input Current (+IN, –IN, VOCM, SHDN)
(Note 2) ................................................................ ±10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range
(Note 4) .................................................. –40°C to 125°C
Specified Temperature Range
(Note 5) .................................................. –40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. –65°C to 150°C
TOP VIEW
UDB PACKAGE
10-LEAD (3mm × 2mm) PLASTIC QFN
–OUT
+IN
+OUT
–IN
V–
V+
V–
SHDN
V+
VOCM
7
11,V–
6
10 9 8
1
2
345
TJMAX = 150°C, θJA = 138°C/W, θJC = 5.2°C/W
EXPOSED PAD (PIN 11) CONNECTED TO V–
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open. VS is
defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
(Note 1)
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6409CUDB#TRMPBF LTC6409CUDB#TRPBF LFPF 10-Lead (3mm × 2mm) Plastic QFN 0°C to 70°C
LTC6409IUDB#TRMPBF LTC6409IUDB#TRPBF LFPF 10-Lead (3mm × 2mm) Plastic QFN –40°C to 85°C
LTC6409HUDB#TRMPBF LTC6409HUDB#TRPBF LFPF 10-Lead (3mm × 2mm) Plastic QFN –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC6409#orderinfo
LTC6409
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For more information www.linear.com/LTC6409
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
enVOCM Common Mode Noise Voltage Density f = 10MHz 12
nV/√Hz
VICMR
(Note 7) Input Signal Common Mode Range VS = 3V
VS = 5V
l
l
0
01.5
3.5 V
V
CMRRI
(Note 8) Input Common Mode Rejection Ratio
(Input Referred) ΔVICM/ΔVOSDIFF
VS = 3V, VICM from 0V to 1.5V
VS = 5V, VICM from 0V to 3.5V
l
l
75
75 90
90 dB
dB
CMRRIO
(Note 8) Output Common Mode Rejection Ratio (Input
Referred) ΔVOCM/ΔVOSDIFF
VS = 3V, VOCM from 0.5V to 1.5V
VS = 5V, VOCM from 0.5V to 3.5V
l
l
55
60 80
85 dB
dB
PSRR
(Note 9) Differential Power Supply Rejection (ΔVS/ΔVOSDIFF) VS = 2.7V to 5.25V l60 85 dB
PSRRCM
(Note 9) Output Common Mode Power Supply Rejection
(ΔVS/ΔVOSCM)VS = 2.7V to 5.25V l55 70 dB
VSSupply Voltage Range (Note 10) l2.7 5.25 V
GCM Common Mode Gain (ΔVOUTCM/ΔVOCM) VS = 3V, VOCM from 0.5V to 1.5V
VS = 5V, VOCM from 0.5V to 3.5V
l
l
1
1V/V
V/V
ΔGCM Common Mode Gain Error, 100 × (GCM – 1) VS = 3V, VOCM from 0.5V to 1.5V
VS = 5V, VOCM from 0.5V to 3.5V
l
l
±0.1
±0.1 ±0.3
±0.3 %
%
BAL Output Balance
(ΔVOUTCM/ ΔVOUTDIFF)ΔVOUTDIFF = 2V
Single-Ended Input
Differential Input
l
l
–65
–70
–50
–50
dB
dB
VOSCM Common Mode Offset Voltage (VOUTCM – VOCM) VS = 3V
VS = 5V
l
l
±1
±1 ±5
±6 mV
mV
ΔVOSCM
ΔT Common Mode Offset Voltage Drift l4µV/°C
VOUTCMR
(Note 7) Output Signal Common Mode Range
(Voltage Range for the VOCM Pin) VS = 3V
VS = 5V
l
l
0.5
0.5 1.5
3.5 V
V
RINVOCM Input Resistance, VOCM Pin l30 40 50 kΩ
VOCM Self-Biased Voltage at the VOCM Pin VS = 3V, VOCM = Open
VS = 5V, VOCM = Open
l
0.9 0.85
1.25
1.6 V
V
VOUT Output Voltage, High, Either Output Pin VS = 3V, IL = 0
VS = 3V, IL = –20mA
VS = 5V, IL = 0
VS = 5V, IL = –20mA
l
l
l
l
1.85
1.8
3.85
3.8
2
1.95
4
3.95
V
V
V
V
Output Voltage, Low, Either Output Pin VS = 3V, 5V; IL = 0
VS = 3V, 5V; IL = 20mA
l
l
0.06
0.2 0.15
0.4 V
V
ISC Output Short-Circuit Current, Either Output Pin
(Note 11) VS = 3V
VS = 5V
l
l
±50
±70 ±70
±95 mA
mA
AVOL Large-Signal Open Loop Voltage Gain 65 dB
ISSupply Current
l
52 56
58 mA
mA
ISHDN Supply Current in Shutdown VSHDN ≤ 0.6V l100 500 µA
RSHDN SHDN Pull-Up Resistor VSHDN = 0V to 0.5V l115 150 185 kΩ
VIL SHDN Input Logic Low l0.6 V
VIH SHDN Input Logic High l1.4 V
tON Turn-On Time 160 ns
tOFF Turn-Off Time 80 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open. VS is
defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
LTC6409
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SR Slew Rate Differential Output, VOUTDIFF = 4VP-P
+OUT Rising (–OUT Falling)
+OUT Falling (–OUT Rising)
3300
1720
1580
V/µs
V/µs
V/µs
GBW Gain-Bandwidth Product RI = 25Ω, RF = 10kΩ, fTEST = 100MHz
l
9.5
810 GHz
GHz
f–3dB –3dB Frequency RI = RF = 150Ω, RLOAD = 400Ω, CF = 1.3pF 2 GHz
f0.1dB Frequency for 0.1dB Flatness RI = RF = 150Ω, RLOAD = 400Ω , CF = 1.3pF 600 MHz
FPBW Full Power Bandwidth VOUTDIFF = 2VP-P 550 MHz
HD2
HD3 25MHz Distortion Differential Input, VOUTDIFF = 2VP-P,
RI = RF = 150Ω, RLOAD = 400Ω
2nd Harmonic
3rd Harmonic
–104
–106
dBc
dBc
100MHz Distortion Differential Input, VOUTDIFF = 2VP-P,
RI = RF = 150Ω, RLOAD = 400Ω
2nd Harmonic
3rd Harmonic
–93
–88
dBc
dBc
HD2
HD3 25MHz Distortion Single-Ended Input, VOUTDIFF = 2VP-P,
RI = RF = 150Ω, RLOAD = 400Ω
2nd Harmonic
3rd Harmonic
–101
–103
dBc
dBc
100MHz Distortion Single-Ended Input, VOUTDIFF = 2VP-P,
RI = RF = 150Ω, RLOAD = 400Ω
2nd Harmonic
3rd Harmonic
–88
–93
dBc
dBc
IMD3 3rd Order IMD at 25MHz
f1 = 24.9MHz, f2 = 25.1MHz VOUTDIFF = 2VP-P Envelope, RI = RF = 150Ω,
RLOAD = 400Ω –110 dBc
3rd Order IMD at 100MHz
f1 = 99.9MHz, f2 = 100.1MHz VOUTDIFF = 2VP-P Envelope, RI = RF = 150Ω,
RLOAD = 400Ω –98 dBc
3rd Order IMD at 140MHz
f1 = 139.9MHz, f2 = 140.1MHz VOUTDIFF = 2VP-P Envelope, RI = RF = 150Ω,
RLOAD = 400Ω –88 dBc
OIP3 Equivalent OIP3 at 25MHz (Note 12)
Equivalent OIP3 at 100MHz (Note 12)
Equivalent OIP3 at 140MHz (Note 12)
59
53
48
dBm
dBm
dBm
tSSettling Time VOUTDIFF = 2VP-P Step, RI = RF = 150Ω,
RLOAD = 400Ω
1% Settling
1.9
ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open. VS is
defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins (+IN, –IN, VOCM, and SHDN) are protected by steering
diodes to either supply. If the inputs should exceed either supply voltage,
the input current should be limited to less than 10mA. In addition, the
inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6409C/LTC6409I are guaranteed functional over the
temperature range of –40°C to 85°C. The LTC6409H is guaranteed
functional over the temperature range of –40°C to 125°C.
Note 5: The LTC6409C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6409C is designed, characterized and expected to
meet specified performance from –40°C to 85°C, but is not tested or
QA sampled at these temperatures. The LTC6409I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6409H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 6: Input bias current is defined as the average of the input currents
flowing into the inputs (–IN and +IN). Input offset current is defined as the
difference between the input currents (IOS = IB+ – IB–).
LTC6409
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For more information www.linear.com/LTC6409
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage Supply Current vs SHDN Voltage
Shutdown Supply Current vs
Supply Voltage
Differential Input Offset Voltage
vs Temperature
Differential Input Offset Voltage
vs Input Common Mode Voltage
Common Mode Offset Voltage
vs Temperature
ELECTRICAL CHARACTERISTICS
Note 7: Input common mode range is tested by testing at both VICM = 1.25V
and at the Electrical Characteristics table limits to verify that the differential
offset (VOSDIFF) and the common mode offset (VOSCM) have not deviated by
more than ±1mV and ±2mV respectively from the VICM = 1.25V case.
The voltage range for the output common mode range is tested by
applying a voltage on the VOCM pin and testing at both VOCM = 1.25V and
at the Electrical Characteristics table limits to verify that the common
mode offset (VOSCM) has not deviated by more than ±6mV from the
VOCM = 1.25V case.
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred offset voltage. Output CMRR is defined as the ratio of
the change in the voltage at the VOCM pin to the change in differential
input referred offset voltage. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs and it is difficult to measure actual amplifier performance (See
Effects of Resistor Pair Mismatch in the Applications Information section
of this data sheet). For a better indicator of actual amplifier performance
independent of feedback component matching, refer to the PSRR
specification.
Note 9: Differential power supply rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
offset voltage. Common mode power supply rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
output common mode offset voltage.
Note 10: Supply voltage range is guaranteed by power supply rejection
ratio test.
Note 11: Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 12: Refer to Relationship Between Different Linearity Metrics in the
Applications Information section of this data sheet for information on how
to calculate an equivalent OIP3 from IMD3 measurements.
TEMPERATURE (°C)
6409 G01
DIFFERENTIAL V
OS
(mV)
VS = 5V
VOCM = VICM = 1.25V
RI = RF = 150Ω
FIVE REPRESENTATIVE UNITS
–50 50
125
100–25 0 25 75
1.5
1.0
0.5
0
–0.5
INPUT COMMON MODE VOLTAGE (V)
6409 G02
DIFFERENTIAL V
OS
(mV)
VS = 5V
VOCM = 1.25V
RI = RF = 150Ω
0.1% FEEDBACK NETWORK RESISTORS
REPRESENTATIVE UNIT
0 2
4
30.5 1 1.5 2.5 3.5
2.0
1.5
1.0
0.5
–0.5
0
–1.0
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = –40°C
SUPPLY VOLTAGE (V)
6409 G04
TOTAL SUPPLY CURRENT (mA)
VSHDN = OPEN
0 2
5.5
3.530.5 1 1.5 2.5 4 54.5
60
20
15
25
30
35
40
45
50
55
10
5
0
TA = 125°C
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = –40°C
SHDN VOLTAGE (V)
6409 G05
VS = 5V
TOTAL SUPPLY CURRENT (mA)
0 2
5
3.530.5 1 1.5 2.5 4 4.5
60
20
15
25
30
35
40
45
50
55
10
5
0
TA = 125°C
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = –40°C
SUPPLY VOLTAGE (V)
6409 G06
SHUTDOWN SUPPLY CURRENT (µA)
VSHDN = V–
0 2
5.5
3.530.5 1 1.5 2.5 4 54.5
140
120
100
80
60
20
40
0
TA = 125°C
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = –40°C
TEMPERATURE (°C)
6409 G03
COMMON MODE OFFSET VOLTAGE (mV)
VS = 5V
VOCM = VICM = 1.25V
RI = RF = 150Ω
FIVE REPRESENTATIVE UNITS
2.5
2.0
1.5
1.0
0.5
0
–0.5
–50 50
125
100–25 0 25 75
LTC6409
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For more information www.linear.com/LTC6409
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Step Response
Overdriven Output Transient
Response
CMRR vs Frequency Differential PSRR vs Frequency Small Signal Step Response
Differential Output Voltage Noise
vs Frequency
Differential Output Impedance
vs Frequency
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
1k 1G1M1
6409 G07
VS = 5V
RI = RF = 150Ω
INCLUDES RI/RF NOISE
1000
100
10
1
20ns/DIV 6409 G14
VOLTAGE (V)
4.0
0.5
3.5
2.5
1.5
3.0
2.0
1.0
0
+OUT
–OUT
VS = 5V
VOCM = 1.25V
RLOAD = 200Ω TO
GROUND PER
OUTPUT
FREQUENCY (MHz)
6409 G09
OUTPUT IMPEDANCE (Ω)
VS = 5V
RI = RF = 150Ω
1000
100
10
1
0.01
0.1
1 10010 1000
10000
1 10010 1000
10000
FREQUENCY (MHz)
6409 G10
CMRR (dB)
VS = 5V
VOCM = 1.25V
RI = RF = 150Ω, CF = 1.3pF
0.1% FEEDBACK NETWORK
RESISTORS
100
90
80
70
60
50 1 10010 1000
10000
FREQUENCY (MHz)
6409 G11
PSRR (dB)
VS = 5V
90
80
70
60
50
10
30
20
40
2ns/DIV 6409 G12
20mV/DIV
+OUT
–OUT
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω, CF = 1.3pF
CL = 0pF
VIN = 200mVP-P, DIFFERENTIAL
0.2V/DIV
2ns/DIV
6409 G13
+OUT
–OUT
VS = 5V
RLOAD = 400Ω
VIN = 2VP-P, DIFFERENTIAL
Input Noise Density vs Frequency
FREQUENCY (Hz)
INPUT VOLTAGE NOISE DENSITY (nV/√Hz)
INPUT CURRENT NOISE DENSITY (pA/√Hz)
1k 1G1M1
6409 G18
in
en
VS = 5V
1000
100
10
1
1000
100
10
1
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Frequency Response vs Closed
Loop Gain Frequency Response vs Load
Capacitance
Gain 0.1dB Flatness
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion vs Frequency
Harmonic Distortion vs Output
Common Mode Voltage
Harmonic Distortion vs Input
Amplitude
FREQUENCY (MHz)
6409 G19
DISTORTION (dBc)
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω
VOUTDIFF = 2VP-P
DIFFERENTIAL INPUTS
–50
–60
–70
–80
–90
–120
–110
–100
1
1000
10010
HD2
HD3
OUTPUT COMMON MODE VOLTAGE (V)
6409 G20
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–110
–100
0.5
3.5
32.521.51
VS = 5V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
VOUTDIFF = 2VP-P
DIFFERENTIAL INPUTS
HD2
HD3
INPUT AMPLITUDE (dBm)
6409 G21
DISTORTION (dBc)
–80
–90
–120
–110
–100
–4
(0.4VP-P)
–2 10
(2VP-P
)
86420
VS = 5V
VOCM = VICM = 1.25V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
DIFFERENTIAL INPUTS
HD2
HD3
1 10010 1000 10000
FREQUENCY (MHz)
6409 G15
GAIN (dB)
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
60
50
40
30
20
10
0
–30
–20
–10
AV = 1
AV = 2
AV = 5
AV = 10
AV = 20
AV = 100
AV = 400
AV (V/V) CF (pF)RI (Ω) RF (Ω)
1
2
5
10
20
100
400
150
100
50
50
25
25
25
150
200
250
500
500
2.5k
10k
1.3
1
0.8
0.4
0.4
0
0
10 1000100
10000
FREQUENCY (MHz)
6409 G16
GAIN (dB)
20
10
0
–30
–20
–10 VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω, CF = 1.3pF
CAPACITOR VALUES ARE FROM
EACH OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
CL = 0pF
CL = 0.5pF
CL = 1pF
CL = 1.5pF
CL = 2pF
1 10010 1000
10000
FREQUENCY (MHz)
6409 G17
GAIN (dB)
0.5
0.1
0.2
0.3
0.4
0
–0.5
–0.4
–0.3
–0.2
–0.1
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω, CF = 1.3pF
Slew Rate vs Temperature
–50 50
125
100–25 0 25 75
TEMPERATURE (°C)
6409 G08
SLEW RATE (V/µs)
VS = 5V
3400
3200
3225
3250
3275
3300
3325
3350
3375
LTC6409
8
6409fb
For more information www.linear.com/LTC6409
PIN FUNCTIONS
+IN, –IN (Pins 2, 6): Non-Inverting and Inverting Input
Pins.
SHDN (Pin 3): When SHDN is floating or directly tied to
V+, the LTC6409 is in the normal (active) operating mode.
When the SHDN pin is connected to V–, the part is dis-
abled and draws approximately 100µA of supply current.
V+, V– (Pins 4, 9 and Pins 8, 10): Positive and Negative
Power Supply Pins. Similar pins should be connected to
the same voltage.
VOCM (Pin 5): Output Common Mode Reference Voltage.
The voltage on this pin sets the output common mode
voltage level. If left floating, an internal resistor divider
develops a default voltage of 1.25V with a 5V supply.
+OUT, –OUT (Pins 7, 1): Differential Output Pins.
Exposed Pad (Pin 11): Tie the bottom pad to V–. If split
supplies are used, DO NOT tie the pad to ground.
Intermodulation Distortion vs
Frequency
Intermodulation Distortion vs
Output Common Mode Voltage
Intermodulation Distortion vs
Input Amplitude
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–60
–70
–80
–90
–120
–110
–100
FREQUENCY (MHz)
6409 G25
THIRD ORDER IMD (dBc)
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω
2 TONES, 200kHz TONE
SPACING, 2VP-P COMPOSITE
DIFFERENTIAL INPUTS
10
1000
100
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω
VOUTDIFF = 2VP-P
SINGLE-ENDED INPUT
0.5
3.5
32.521.51
OUTPUT COMMON MODE VOLTAGE (V)
6409 G26
THIRD ORDER IMD (dBc)
VS = 5V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
2 TONES, 200kHz TONE
SPACING, 2VP-P COMPOSITE
DIFFERENTIAL INPUTS
–30
–40
–50
–60
–70
–80
–90
–110
–100
INPUT AMPLITUDE (dBm)
–80
–90
–120
–110
–100
2
(0.8VP-P)
10
(2VP-P
)
864
6409 G27
THIRD ORDER IMD (dBc)
VS = 5V
VOCM = VICM = 1.25V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
2 TONES, 200kHz TONE SPACING
DIFFERENTIAL INPUTS
Harmonic Distortion vs Frequency
Harmonic Distortion vs Output
Common Mode Voltage
Harmonic Distortion vs Input
Amplitude
FREQUENCY (MHz)
6409 G22
DISTORTION (dBc)
VS = 5V
VOCM = VICM = 1.25V
RLOAD = 400Ω
RI = RF = 150Ω
VOUTDIFF = 2VP-P
SINGLE-ENDED INPUT
–50
–60
–70
–80
–90
–120
–110
–100
1
1000
10010
HD2
HD3
OUTPUT COMMON MODE VOLTAGE (V)
6409 G23
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–110
–100
0.5
3.5
32.521.51
VS = 5V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
VOUTDIFF = 2VP-P
SINGLE-ENDED INPUT
HD2
HD3
INPUT AMPLITUDE (dBm)
6409 G24
DISTORTION (dBc)
–80
–90
–120
–110
–100
–4
(0.4VP-P)
–2 10
(2VP-P
)
86420
VS = 5V
VOCM = VICM = 1.25V
fIN = 100MHz
RLOAD = 400Ω
RI = RF = 150Ω
SINGLE-ENDED INPUT
HD2
HD3
LTC6409
9
6409fb
For more information www.linear.com/LTC6409
BLOCK DIAGRAM
APPLICATIONS INFORMATION
Functional Description
The LTC6409 is a small outline, wideband, high speed,
low noise, and low distortion fully-differential amplifier
with accurate output phase balancing. The amplifier is
optimized to drive low voltage, single-supply, differential
input analog-to-digital converters (ADCs). The LTC6409
input common mode range includes ground, which makes
it ideal to DC-couple and convert ground-referenced,
single-ended signals into differential signals that are ref-
erenced to the user-supplied output common mode volt-
age. This is ideal for driving these differential ADCs. The
balanced differential nature of the amplifier also provides
even-order harmonic distortion cancellation, and low
susceptibility to common mode noise (like power sup-
ply noise). The LTC6409 can operate with a single-ended
input and differential output, or with a differential input
and differential output.
The outputs of the LTC6409 are capable of swinging from
close-to-ground to 1V below V+. They can source or sink
up to approximately 70mA of current. Load capacitances
should be decoupled with at least 10Ω of series resistance
from each output.
Input Pin Protection
The LTC6409 input stage is protected against differential
input voltages which exceed 1.4V by two pairs of series
diodes connected back to back between +IN and –IN.
Moreover, the input pins, as well as VOCM and SHDN
pins, have clamping diodes to either power supply. If
these pins are driven to voltages which exceed either
supply, the current should be limited to 10mA to prevent
damage to the IC.
SHDN Pin
The SHDN pin is a CMOS logic input with a 150k inter-
nal pull-up resistor. If the pin is driven low, the LTC6409
powers down. If the pin is left unconnected or driven
high, the part is in normal active operation. Some care
should be taken to control leakage currents at this pin to
prevent inadvertently putting the LTC6409 into shutdown.
The turn-on and turn-off time between the shutdown and
active states is typically less than 200ns.
General Amplifier Applications
In Figure 1, the gain to VOUTDIFF from VINP and VINM is
given by:
VOUTDIFF =V+OUT – V–OUT ≈
R
F
RI
• VINP – VINM
( )
(1)
Note from Equation (1), the differential output voltage
(V+OUT – V–OUT) is completely independent of input and
output common mode voltages, or the voltage at the com-
mon mode pin. This makes the LTC6409 ideally suited
for pre-amplification, level shifting and conversion of
V+
V–
V+
V–
–
+
6–IN
5
VOCM
4
V+
V+
3
SHDN
10
V–
V–
9
V+
V+
8
V–
V–
7+OUT
2+IN 1–OUT
200k
50k
6409 BD
LTC6409
10
6409fb
For more information www.linear.com/LTC6409
APPLICATIONS INFORMATION
that can be processed is even wider. The input common
mode range at the op amp inputs depends on the circuit
configuration (gain), VOCM and VCM (refer to Figure 1). For
fully differential input applications, where VINP = –VINM,
the common mode input is approximately:
VICM =V+IN
+
V–IN
2≈VOCM •RI
R
I
+R
F
+VCM •RF
R
I
+R
F
With single-ended inputs, there is an input signal compo-
nent to the input common mode voltage. Applying only
VINP (setting VINM to zero), the input common mode volt-
age is approximately:
VICM =
V
+IN
+V
–IN
2≈VOCM •
R
I
RI+RF
+
VCM •RF
R
I
+R
F
+VINP
2•RF
R
I
+R
F
(2)
This means that if, for example, the input signal (V
INP
)
is a sine, an attenuated version of that sine signal also
appears at the op amp inputs.
Input Impedance and Loading Effects
The low frequency input impedance looking into the VINP
or VINM input of Figure 1 depends on how the inputs are
driven. For fully differential input sources (VINP = –VINM),
the input impedance seen at either input is simply:
RINP = RINM = RI
For single-ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
the balanced differential case. The input impedance look-
ing into either input is:
RINP =RINM =
R
I
1– 1
2•RF
R
I
+R
F
Input signal sources with non-zero output impedances
can also cause feedback imbalance between the pair of
feedback networks. For the best performance, it is rec-
ommended that the input source output impedance be
compensated. If input impedance matching is required
Figure 1. Circuit for Common Mode Range
–
+
R
F
V–
OUT
V
+OUT
VVOCM VOCM
6409 F01
RF
R
I
RI
+
–
VINP
+
–
V
CM –
+
VINM
V–IN
V+IN
single-ended signals to differential output signals for
driving differential input ADCs.
Output Common Mode and VOCM Pin
The output common mode voltage is defined as the aver-
age of the two outputs:
VOUTCM =VOCM =
V
+OUT
+V
–OUT
2
As the equation shows, the output common mode voltage
is independent of the input common mode voltage, and
is instead determined by the voltage on the VOCM pin, by
means of an internal common mode feedback loop.
If the V
OCM
pin is left open, an internal resistor divider
develops a default voltage of 1.25V with a 5V supply. The
VOCM pin can be overdriven to another voltage if desired.
For example, when driving an ADC, if the ADC makes a
reference available for setting the common mode voltage,
it can be directly tied to the VOCM pin, as long as the ADC
is capable of driving the 40k input resistance presented
by the V
OCM
pin. The Electrical Characteristics table speci-
fies the valid range that can be applied to the VOCM pin
(VOUTCMR).
Input Common Mode Voltage Range
The LTC6409’s input common mode voltage (V
ICM
) is
defined as the average of the two input pins, V+IN and
V–IN. The valid range that can be used for VICM has been
specified in the Electrical Characteristics table (VICMR).
However, due to external resistive divider action of the
gain and feedback resistors, the effective range of signals
LTC6409
11
6409fb
For more information www.linear.com/LTC6409
APPLICATIONS INFORMATION
by the source, a termination resistor RT should be chosen
(see Figure 2) such that:
RT=RINM •RS
R
INM
–R
S
According to Figure 2, the input impedance looking into
the differential amp (RINM) reflects the single-ended
source case, given above. Also, R2 is chosen as:
R2 =RT||RS=
R
T
•R
S
R
T
+R
S
Figure 2. Optimal Compensation for Signal Source Impedance
Δb is defined as the difference in the feedback factors:
∆b =
R
I2
R
I2
+R
F2
–
R
I1
R
I1
+R
F1
Here, VCM and VINDIFF are defined as the average and
the difference of the two input voltages VINP and VINM,
respectively:
VCM =VINP
+
VINM
2
VINDIFF = VINP – VINM
When the feedback ratios mismatch (Δb), common mode
to differential conversion occurs. Setting the differential
input to zero (VINDIFF = 0), the degree of common mode
to differential conversion is given by the equation:
VOUTDIFF =V+OUT – V–OUT ≈(VCM – VOCM ) •
∆b
b
AVG
(3)
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of
both signals and noise. Using 0.1% resistors or better
will mitigate most problems and will provide about 54dB
worst case of common mode rejection. A low impedance
ground plane should be used as a reference for both the
input signal source and the VOCM pin.
There may be concern on how feedback factor mismatch
affects distortion. Feedback factor mismatch from using
1% resistors or better, has a negligible effect on distor-
tion. However, in single supply level shifting applications
where there is a voltage difference between the input com-
mon mode voltage and the output common mode voltage,
VS
+
–
–
+
RF
RF
RI
R
INM
RS
RI
R2 = RS || RT
R
T CHOSEN SO THAT RT || RINM = RS
R2 CHOSEN TO BALANCE R
T || RS
RT
6409 F02
Effects of Resistor Pair Mismatch
Figure 3 shows a circuit diagram which takes into consid-
eration that real world resistors will not match perfectly.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
VOUTDIFF =V+OUT – V–OUT ≈VINDIFF •
R
F
RI
+
VCM •∆b
b
AVG
– VOCM •∆b
b
AVG
where RF is the average of RF1, and RF2, and RI is the
average of RI1, and RI2.
bAVG is defined as the average feedback factor from the
outputs to their respective inputs:
bAVG =1
2•RI1
RI1 +RF1
+RI2
RI2 +RF2
Figure 3. Real-World Application with Feedback
Resistor Pair Mismatch
–
+
R
F2 V
–OUT
V
+OUT
VVOCM VOCM
6409 F03
RF1
R
I2
RI1
+
–
VINP
–
+
V
INM
V–IN
V+IN
LTC6409
12
6409fb
For more information www.linear.com/LTC6409
resistor mismatch can make the apparent voltage offset
of the amplifier appear worse than specified.
The apparent input referred offset induced by feedback
factor mismatch is derived from Equation (3):
VOSDIFF(APPARENT) ≈ (VCM – VOCM) • Δb
Using the LTC6409 in a single 5V supply application with
0.1% resistors, the input common mode grounded, and
the VOCM pin biased at 1.25V, the worst case mismatch
can induce 1.25mV of apparent offset voltage.
Noise and Noise Figure
The LTC6409’s differential input referred voltage and
current noise densities are 1.1nV/√Hz and 8.8pA/√Hz,
respectively. In addition to the noise generated by the
amplifier, the surrounding feedback resistors also contrib-
ute noise. A simplified noise model is shown in Figure 4.
The output noise generated by both the amplifier and the
feedback components is given by the equation:
eno =
eni • 1+RF
RI
2
+2 • in•RF
( )
2+
2 • enRI •RF
RI
2
+2 • enRF 2
If the circuits surrounding the amplifier are well balanced,
common mode noise (enVOCM) of the amplifier does not
appear in the differential output noise equation given
above. A plot of this equation and a plot of the noise
generated by the feedback components for the LTC6409
are shown in Figure 5.
The LTC6409’s input referred voltage noise contributes
the equivalent noise of a 75Ω resistor. When the feedback
network is comprised of resistors whose values are larger
than this, the output noise is resistor noise and amplifier
current noise dominant. For feedback networks consist-
ing of resistors with values smaller than 75Ω, the output
noise is voltage noise dominant (see Figure 5).
Lower resistor values always result in lower noise at the
penalty of increased distortion due to increased loading
by the feedback network on the output. Higher resistor
values will result in higher output noise, but typically
improved distortion due to less loading on the output.
For this reason, when LTC6409 is configured in a differ-
ential gain of 1, using feedback resistors of at least 150Ω
is recommended.
To calculate noise figure (NF), a source resistance and the
noise it generates should also come into consideration.
Figure 6 shows a noise model for the amplifier which
includes the source resistance (RS). To generalize the
APPLICATIONS INFORMATION
Figure 4. Simplified Noise Model
–
+
eno
2
RF
VOCM
enRI2
RF
RI
RI
enRF2
enRI2eni2
enRF2
in+2
in–2
6409 F04
Figure 5. LTC6409 Output Noise vs Noise
Contributed by Feedback Network Alone
RI = RF (Ω)
NOISE DENSITY (nV/√Hz)
6409 F05
1000
100
10
1
0.110 1000
10000
100
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
FEEDBACK
NETWORK
NOISE
LTC6409
13
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For more information www.linear.com/LTC6409
Finally, noise figure can be obtained as:
NF =10log 1+eno
2
eno2(RS)
Figure 7 specifies the measured total output noise (eno),
excluding the noise contribution of source resistance, and
noise figure (NF) of LTC6409 configured at closed loop
gains (A
V
= R
F
/R
I
) of 1V/V, 2V/V and 5V/V. The circuits
in the left column use termination resistors and trans-
formers to match to the 50Ω source resistance, while the
circuits in the right column do not have such matching.
For simplicity, DC-blocking and bypass capacitors have
not been shown in the circuits, as they do not affect the
noise results.
Relationship Between Different Linearity Metrics
Linearity is, of course, an important consideration in many
amplifier applications. This section relates the inter-mod-
ulation distortion of fully differential amplifiers to other
linearity metrics commonly used in RF style blocks.
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g., ampli-
fiers, mixers, etc.). Intercept points, like noise figures,
can be easily cascaded back and forth through a signal
chain to determine the overall performance of a receiver
chain, thus resulting in simpler system-level calculations.
Traditionally, these systems use primarily single-ended RF
amplifiers as gain blocks designed to operate in a 50Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an associ-
ated impedance of 50Ω.
However, for LTC6409 as a differential feedback amplifier
with low output impedance, a 50Ω resistive load is not
required (unlike an RF amplifier). This distinction is impor-
tant when evaluating the intercept point for LTC6409. In
fact, the LTC6409 yields optimum distortion performance
when loaded with 200Ω to 1kΩ (at each output), very
similar to the input impedance of an ADC. As a result,
terminating the input of the ADC to 50Ω can actually be
detrimental to system performance.
APPLICATIONS INFORMATION
Figure 6. A More General Noise Model Including
Source and Termination Resistors
calculation, a termination resistor (RT) is included and
its noise contribution is taken into account.
Now, the total output noise power (excluding the noise
contribution of RS) is calculated as:
eno 2=eni • 1+RF
RI+RT||RS
2
2
+2 • in•RF
( )
2+
2 • enRI •RF
RI+RT||RS
2
2
+2 • enRF 2+
enRT •RF
RI
•2RI||RS
RT+2RI||RS
( )
2
Meanwhile, the output noise power due to noise of RS is
given by:
eno 2(RS) =enRS •RF
RI
•2RI||RT
RS+2RI||RT
( )
2
–
+
eno
2
RF
VOCM
enRI
2
RF
RI
RI
RS
enRF
2
enRS2
RT
enRT2
enRI2eni2
enRF2
in+2
in–2
6409 F06
LTC6409
14
6409fb
For more information www.linear.com/LTC6409
APPLICATIONS INFORMATION
The definition of 3rd order intermodulation distortion
(IMD3) is shown in Figure 8. Also, a graphical repre-
sentation of how to relate IMD3 to output/input 3rd
order intercept points (OIP3/IIP3) has been depicted in
Figure 9. Based on this figure, Equation (4) gives the
definition of the intercept point, relative to the intermodu-
lation distortion.
OIP3 =PO+IMD3
2
(4)
PO is the output power of each of the two tones at which
IMD3 is measured, as shown in Figure 9. It is calculated
in dBm as:
PO=10log V2PDIFF
2 •RL• 10–3
(5)
where RL is the differential load resistance, and VPDIFF is
the differential peak voltage for a single tone. Normally,
intermodulation distortion is specified for a benchmark
composite differential peak of 2VP-P at the output of the
50Ω
VIN +
–
50Ω
VIN +
–
–
+
150Ω
1.3pF
150Ω
150Ω
150Ω
50Ω
1:4
6409 F07
1.3pF
VOCM
VIN +
–
600Ω eno = 4.70nV/√Hz
NF = 14.41dB
–
+
200Ω
1pF
200Ω
100Ω
100Ω
50Ω
1:4
1pF
VOCM
VIN +
–
eno = 5.77nV/√Hz
NF = 10.43dB
–
+
500Ω
500Ω
100Ω
100Ω
50Ω
1:4
VOCM
VIN +
–
eno = 11.69nV/√Hz
NF = 8.81dB
–
+
150Ω
1.3pF
150Ω
150Ω
150Ω
50Ω
1.3pF
VOCM
VIN +
–
eno = 5.88nV/√Hz
NF = 17.59dB
–
+
200Ω
1pF
200Ω
100Ω
100Ω
1pF
0.4pF
0.4pF
0.8pF
0.8pF
VOCM eno = 9.76nV/√Hz
NF = 16.66dB
–
+
250Ω
250Ω
50Ω
50Ω
VOCM eno = 14.23nV/√
Hz
NF = 13.56dB
Figure 7. LTC6409 Measured Output Noise and Noise Figure at Different Closed Loop Gains with and without Source Impedance Matching
LTC6409
15
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For more information www.linear.com/LTC6409
RS
50Ω
VS
RF
LTC6409
100Ω
100Ω
RF
CF
RI
RI
RT
RL
50Ω
C
BA
6409 F10
1dB
LOSS
IDEAL
4:1
IDEAL
1:4
1dB
LOSS
+
–
CF
RT
APPLICATIONS INFORMATION
Figure 8. Definition of IMD3
Figure 9. Graphical Representation of the
Relationship between IMD3 and OIP3
amplifier, implying that each single tone is 1VP-P, result-
ing in VPDIFF = 0.5V. Using RL = 50Ω as the associated
impedance, PO is calculated to be close to 4dBm.
As seen in Equation (5), when a higher impedance is used,
the same level of intermodulation distortion performance
results in a lower intercept point. Therefore, it is impor-
tant to consider the impedance seen by the output of the
LTC6409 when working with intercept points.
Comparing linearity specifications between different
amplifier types becomes easier when a common imped-
ance level is assumed. For this reason, the intercept
points for LTC6409 are reported normalized to a 50Ω
load impedance. This is the reason why OIP3 in the
Electrical Characteristics table is 4dBm more than half
the absolute value of IMD3.
If the top half of the LTC6409 demo board (DC1591A,
shown in Figure 12) is used to measure IMD3 and OIP3,
one should make sure to properly convert the power seen
at the differential output of the amplifier to the power that
appears at the single-ended output of the demo board.
Figure 10 shows an equivalent representation of the top
half of the demo board. This view ignores the DC-blocking
and bypass capacitors, which do not affect the analysis
here. The transmission line transformers (used mainly
for impedance matching) are modeled here as ideal 4:1
impedance transformers together with a –1dB block. This
separates the insertion loss of the transformer from its
ideal behavior. The 100Ω resistors at the LTC6409 output
create a differential 200Ω resistance, which is an imped-
ance match for the reflected RL.
As previously mentioned, IMD3 is measured for 2V
P-P
dif-
ferential peak (i.e. 10dBm) at the output of the LTC6409,
corresponding to 1VP-P (i.e. 4dBm) at each output alone.
From LTC6409 output (location A in Figure 10) to the
input of the output transformer (location B), there is
a voltage attenuation of 1/2 (or –6dB) formed by the
Figure 10. Equivalent Schematic of the Top Half of the LTC6409 Demo Board
PS
POWER
FREQUENCY
IMD3 = PS – P
O
∆f = f2 – f1 = f1 – (2f1 – f2) = (2f2 – f1) – f2
6409 F08
PS
POPO
2f1 – f2 2f2 – f1f1 f2
IMD3
1×
IIP3
PO
OIP3
POUT
(dBm)
PIN
(dBm)
6409 F10
PS
3×
LTC6409
16
6409fb
For more information www.linear.com/LTC6409
APPLICATIONS INFORMATION
resistive divider between the RL • 4 = 200Ω differential
resistance seen at location B and the 200Ω formed by
the two 100Ω matching resistors at the LTC6409 output.
Thus, the differential power at location B is 10 – 6 = 4dBm.
Since the transformer ratio is 4:1 and it has an insertion
loss of about 1dB, the power at location C (across RL) is
calculated to be 4 – 6 – 1 = –3dBm. This means that IMD3
should be measured while the power at the output of the
demo board is –3dBm which is equivalent to having 2V
P-P
differential peak (or 10dBm) at the output of the LTC6409.
GBW vs f–3dB
Gain-bandwidth product (GBW) and –3dB frequency
(f–3dB) have been both specified in the Electrical
Characteristics table as two different metrics for the speed
of the LTC6409. GBW is obtained by measuring the gain
of the amplifier at a specific frequency (fTEST) and cal-
culate gain • fTEST. To measure gain, the feedback factor
(i.e. b = RI/(RI + RF)) is chosen sufficiently small so that
the feedback loop does not limit the available gain of the
LTC6409 at fTEST, ensuring that the measured gain is the
open loop gain of the amplifier. As long as this condition
is met, GBW is a parameter that depends only on the
internal design and compensation of the amplifier and is
a suitable metric to specify the inherent speed capability
of the amplifier.
f–3dB, on the other hand, is a parameter of more practi-
cal interest in different applications and is by definition
the frequency at which the gain is 3dB lower than its low
frequency value. The value of f–3dB depends on the speed
of the amplifier as well as the feedback factor. Since the
LTC6409 is designed to be stable in a differential signal
gain of 1 (where RI = RF or b = 1/2), the maximum f–3dB
is obtained and measured in this gain setting, as reported
in the Electrical Characteristics table.
In most amplifiers, the open loop gain response exhibits a
conventional single-pole roll-off for most of the frequen-
cies before crossover frequency and the GBW and f–3dB
numbers are close to each other. However, the LTC6409
is intentionally compensated in such a way that its GBW
is significantly larger than its f–3dB. This means that at
lower frequencies (where the input signal frequencies
typically lie, e.g. 100MHz) the amplifier’s gain and thus
the feedback loop gain is larger. This has the important
advantage of further linearizing the amplifier and improv-
ing distortion at those frequencies.
Looking at the Frequency Response vs Closed Loop Gain
graph in the Typical Performance Characteristics section
of this data sheet, one sees that for a closed loop gain
(AV) of 1 (where RI = RF = 150Ω), f–3dB is about 2GHz.
However, for AV = 400 (where RI = 25Ω and RF = 10kΩ),
the gain at 100MHz is close to 40dB = 100V/V, implying
a GBW value of 10GHz.
Feedback Capacitors
When the LTC6409 is configured in low differential gains,
it is often advantageous to utilize a feedback capacitor (CF)
in parallel with each feedback resistor (RF). The use of CF
implements a pole-zero pair (in which the zero frequency
is usually smaller than the pole frequency) and adds posi-
tive phase to the feedback loop gain around the amplifier.
Therefore, if properly chosen, the addition of CF boosts
the phase margin and improves the stability response of
the feedback loop. For example, with RI = RF = 150Ω, it is
recommended for most general applications to use CF =
1.3pF across each R
F
. This value has been selected to
maximize f–3dB for the LTC6409 while keeping the peaking
of the closed loop gain versus frequency response under
a reasonable level (<1dB). It also results in the highest
frequency for 0.1dB gain flatness (f0.1dB).
However, other values of CF can also be utilized and tailored
to other specific applications. In general, a larger value
for CF reduces the peaking (overshoot) of the amplifier in
both frequency and time domains, but also decreases the
closed loop bandwidth (f–3dB). For example, while for a
closed loop gain (A
V
) of 5, C
F
= 0.8pF results in maximum
f
–3dB
(as previously shown in the Frequency Response vs
Closed Loop Gain graph of this data sheet), if CF = 1.2pF
is used, the amplifier exhibits no overshoot in the time
domain which is desirable in certain applications. Both the
circuits discussed in this section have been shown in the
Typical Applications section of this data sheet.
LTC6409
17
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For more information www.linear.com/LTC6409
APPLICATIONS INFORMATION
Board Layout and Bypass Capacitors
For single supply applications, it is recommended that
high quality 0.1µF||1000pF ceramic bypass capacitors
be placed directly between each V+ pin and its closest
V– pin with short connections. The V– pins (including the
Exposed Pad) should be tied directly to a low impedance
ground plane with minimal routing.
For dual (split) power supplies, it is recommended that
additional high quality 0.1µF||1000pF ceramic capaci-
tors be used to bypass V+ pins to ground and V– pins to
ground, again with minimal routing.
For driving heavy differential loads (<200Ω), additional
bypass capacitance may be needed for optimal perfor-
mance. Keep in mind that small geometry (e.g., 0603)
surface mount ceramic capacitors have a much higher
self-resonant frequency than do leaded capacitors, and
perform best in high speed applications.
To prevent degradation in stability response, it is highly
recommended that any stray capacitance at the input
pins, +IN and –IN, be kept to an absolute minimum by
keeping printed circuit connections as short as possible.
This becomes especially true when the feedback resistor
network uses resistor values greater than 500Ω in circuits
with RI = RF.
At the output, always keep in mind the differential nature
of the LTC6409, because it is critical that the load imped-
ances seen by both outputs (stray or intended), be as bal-
anced and symmetric as possible. This will help preserve
the balanced operation of the LTC6409 that minimizes the
generation of even-order harmonics and maximizes the
rejection of common mode signals and noise.
The VOCM pin should be bypassed to the ground plane
with a high quality ceramic capacitor of at least 0.01µF.
This will prevent common mode signals and noise on this
pin from being inadvertently converted to differential sig-
nals and noise by impedance mismatches both externally
and internally to the IC.
Driving ADCs
The LTC6409’s ground-referenced input, differential out-
put and adjustable output common mode voltage make
it ideal for interfacing to differential input ADCs. These
ADCs are typically supplied from a single-supply voltage
and have an optimal common mode input range near mid-
supply. The LTC6409 interfaces to these ADCs by provid-
ing single-ended to differential conversion and common
mode level shifting.
The sampling process of ADCs creates a transient that is
caused by the switching in of the ADC sampling capaci-
tor. This momentarily shorts the output of the amplifier
as charge is transferred between amplifier and sampling
capacitor. The amplifier must recover and settle from this
load transient before the acquisition period has ended, for
a valid representation of the input signal. The LTC6409
will settle quickly from these periodic load impulses. The
RC network between the outputs of the driver and the
inputs of the ADC decouples the sampling transient of
the ADC (see Figure 11). The capacitance serves to pro-
vide the bulk of the charge during the sampling process,
while the two resistors at the outputs of the LTC6409
are used to dampen and attenuate any charge injected
by the ADC. The RC filter gives the additional benefit of
band limiting broadband output noise. Generally, longer
time constants improve SNR at the expense of settling
time. The resistors in the decoupling network should be
at least 10Ω. These resistors also serve to decouple the
LTC6409 outputs from load capacitance. Too large of a
resistor will leave insufficient settling time. Too small of
a resistor will not properly dampen the load transient of
the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require
a minimum of eleven RC time constants. For lowest dis-
tortion, choose capacitors with low dielectric absorption
(such as a C0G multilayer ceramic capacitor).
LTC6409
18
6409fb
For more information www.linear.com/LTC6409
–
+
3
SHDN
6–IN 7+OUT
2+IN 1–OUT
AIN+
AIN–
150Ω
4
V+
V+
V+
5V
VOCM
VOCM
10
V–
8
V–
V–
V–
6409 F11
LTC6409
ADC
LTC2262-14
VIN
SHDN
150Ω150Ω 100Ω
150Ω
0.1µF
33.2Ω
33.2Ω
10Ω
10Ω
5V
5
0.1µF||1000pF
0.1µF||1000pF
CONTROL
GND VDD
VCM
D13
•
•
D0
0.1µF||1000pF
39pF
39pF
1.8V
1µF
1.3pF
1.3pF
1µF
9
V+
APPLICATIONS INFORMATION
Figure 11. Driving an ADC
LTC6409
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6409fb
For more information www.linear.com/LTC6409
J5
+IN
J6
–IN R38
OPT
R37
0Ω
R32
OPT
R31
0Ω
R39
150Ω, 0.1%
R33
150Ω, 0.1%
R6
OPT
J8
+OUT
R7
0Ω
JP1
EN
DIS
E2
VCM
E4
VOCM
E3
GND
E1
V+
–IN
+IN
+OUT
–OUT
R5
150Ω, 0.1%
C22
1.3pF
VOCM LTC6409UDB
6
2
5
3
810
49
11
1
7
R3
100Ω
R4
100Ω
R11
300Ω
R9
150Ω, 0.1%
R10
150Ω, 0.1%
6409 F12
C18
0.1µF
C19
0.1µF
C23
0.1µF
C24
0.1µF
C26
0.1µF
C27
1.3pF
C28
0.1µF
R15
OPT
R16
OPT
R13
OPT
R12
300Ω
C32
0.1µF
R8
150Ω, 0.1%
R17
10Ω
SHDN
SHDN1
V–
V+
V–
V+
V+
V+
T1
TCM4-19
1:4
XFMR MINI-CIRCUITS
V–
J1
IN
1
2
3
C25
0.1µF
Sd 3
CT 2
S
Pd
P1
R14
0Ω
R2
OPT
T2
TCM4-19
4:1
XFMR MINI-CIRCUITS
J2
OUT
C29
0.1µF
S1
CT2
Sd
P
Pd
4
6
6
43
R1
0Ω
JP2
EN
DIS
–IN
+IN
+OUT
–OUT
R28
150Ω, 0.1%
C13
1.3pF
VOCM
VOCM LTC6409UDB
6
2
5
3
810
49
11
1
7
C2
0.01µF
C4
0.47µF
C6
0.01µF
C8
0.47µF
C1
100pF
C3
0.1µF
C5
100pF
C7
0.1µF
C11
0.1µF
C12
10µF
C9
1000pF
C10
1000pF
C17
1.3pF
C16
0.1µF
R29
150Ω, 0.1%
R30
10Ω
SHDN
SHDN2
V–
V+
V–
V+
V+
V+
V–
1
2
3
R35
OPT
J7
–OUT
R36
0Ω
R40
50Ω
R34
50Ω
R23
300Ω
R21
75Ω
R24
75Ω
C14
0.1µF
C15
0.1µF
C31
0.1µF
C20
0.1µF
R19
OPT
R20
300Ω
R25
300Ω
R22
300Ω
T3
TCM4-19
1:4
XFMR MINI-CIRCUITS
J3
CAL IN C30
0.1µF
Sd 3
CT 2
S
Pd
P1
R18
0Ω
R26
OPT
T4
TCM4-19
4:1
XFMR MINI-CIRCUITS
J4
CAL OUT
CALIBRATION PATH
C21
0.1µF
S1
CT2
Sd
P
Pd
4
6
6
43
R27
0Ω
Figure 12. Demo Board DC1591A Schematic
APPLICATIONS INFORMATION
LTC6409
21
6409fb
For more information www.linear.com/LTC6409
TYPICAL APPLICATIONS
DC-Coupled Level Shifting of an I/Q Demodulator Output
6409 TA02
C2
10pF
C1
10pF
RF IN
1900MHz
–10dBm
200mV
P-P
C3
12pF
R5
620Ω
R6
620Ω
C5
0.9pF
C4
0.9pF
DIFF OUTPUT Z
130Ω
| |
2.5pF
DC LEVEL
1.25V
DC LEVEL
3.9V
DC LEVEL
3.4V
GAIN: 12.3dBGAIN: 1.1dB
R3
75Ω
R4
75Ω
R1
75Ω
R2
75Ω
–OUT
+OUT
IDENTICAL
Q CHANNEL
5V
5pF
65Ω
5pF
65Ω
–
+
+
–
5V
LTC6409
VOCM
1.25V
5V
I
5V
5pF
65Ω
5pF
65Ω
5V
Q
5V
LT5575
LO
1920MHz
0dBm
–8.9dBm
227mVP-P
3.4dBm
936mVP-P
Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown)
LTM9011-14
F3
F1
F2
C1
C2
B3
B1
B2
VCM12
AIN2+
AIN2–
AIN3+
AIN3–
VCM34
AIN4+
AIN4–
AIN8+
AIN8–
AIN1+
AIN1–
O1A+
O1A–
DCO+
DCO–
FR+
FR–
G2
G1
N1
N2
H7
H8
G8
G7
E7
E8
CLK+
CLK–
P5 P6
B6C5
1.8V
1.8V
SENSE
VDD
VREF
OVDD
33pF
150pF
180nH180nH
3.3V
180nH
180nH
150pF
150Ω 474Ω
37.4Ω
37.4Ω
–OUT
+OUT
VOCM
+IN
V+
–IN
474Ω
75Ω
75Ω
66.5Ω
66.5Ω
0.1µF
0.8pF
0.8pF
68pF
68pF
6409 TA03
• • •
–
+
150Ω SHDN
GND
INPUT
49.9Ω
LTC6409
LTC6409
22
6409fb
For more information www.linear.com/LTC6409
PACKAGE DESCRIPTION
0.40 ±0.10
0.50 ±0.10
0.80
BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
0.75 ±0.05
R = 0.13
TYP
0.20 REF
(UDB10) DFN 0910 REV A
0.70 ±
0.10
1
2
35
6
7
8 10
0.60 ±
0.10
3.00 ±0.05
0.90 ±0.10
DETAIL A
0.25 ±0.10
0.05 ±0.10
2.00 ±0.05 DETAIL A
0.25 ±0.05
0.50 BSC
UDB Package
10-Lead Plastic QFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1848 Rev A)
0.00 – 0.05
0.90 ±0.05
DETAIL B
0.25 ±0.05
0.05 ±0.05
0.25 ±0.05
0.85 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.50 ±0.05
1.10 ±0.05
0.65 ±0.05
0.75 ±0.05
2.50
±0.05
PACKAGE
OUTLINE
0.50 BSC
DETAIL B
0.95 ±0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
Please refer to http://www.linear.com/product/LTC6409#packaging for the most recent package drawings.
LTC6409
23
6409fb
For more information www.linear.com/LTC6409
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/10 Revised Typical Application drawing 21
B 05/17 Corrected spelling of “reflectometry” 1
LTC6409
24
6409fb
For more information www.linear.com/LTC6409 www.linear.com/LTC6409
LINEAR TECHNOLOGY CORPORATION 2010
LT 0517 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIONS
LTC6409 Externally Compensated for Maximum Gain Flatness and for No-Overshoot Time-Domain Response
PART NUMBER DESCRIPTION COMMENTS
LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26 1.8GHz Low Noise, Low Distortion, Differential
ADCDrivers –71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA,
AV = 8dB/14dB/20dB/26dB
LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26 1.3GHz Low Noise, Low Distortion, Differential
ADCDrivers –74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA,
AV = 8dB/14dB/20dB/26dB
LTC6406/LTC6405 3GHz/2.7GHz Low Noise, Rail-to-Rail Input
DifferentialAmplifier/Driver –70dBc/–65dBc Distortion at 50MHz, IS = 18mA, 1.6nV/
√
Hz Noise,
3V/5V Supply
LTC6416 2GHz Low Noise, Differential 16-Bit ADC Buffer –72.5dBc IM3 at 300MHz 2VP-P Composite, 150mW on 3.6V Supply
LTC2209 16-Bit, 160Msps ADC 100dB SFDR, VDD = 3.3V, VCM = 1.25V
LTC2262-14 14-Bit, 150Msps Ultralow Power 1.8V ADC 88dB SFDR, 149mW, VDD = 1.8V, VCM = 0.9V
1 10010 1000
10000
FREQUENCY (MHz)
GAIN (dB)
0.5
0.1
0.2
0.3
0.4
0
–0.5
–0.4
–0.3
–0.2
–0.1
+
–
–
+
250Ω
1.2pF
LTC6409
VOCM = 1.25V
150Ω
150Ω
CHANNEL 1
50Ω
CHANNEL 2
50Ω
49.9Ω
VIN
50Ω
50Ω
250Ω
6409 TA04
TEKTRONIX
CSA8200 SCOPE
5V 0.1µF
0.1µF
0.1µF
0.1µF
0.4V
P-P
1.2pF
50Ω
+
–
–
+
150Ω
1.3pF
LTC6409
VOCM = 1.25V
150Ω
150Ω
PORT 3
50Ω
PORT 4
50Ω
75Ω
150Ω
150Ω
150Ω
1/2 AGILENT
E5071A
PORT 1
50Ω
PORT 2
50Ω
1/2 AGILENT
E5071A 5V 0.1µF
0.1µF
0.1µF
0.1µF
1.3pF
75Ω
0.2V/DIV
2ns/DIV
+
–
+OUT
–OUT
Gain 0.1dB Flatness
No-Overshoot Step Response
