CY7C1334H-133AXC - Cypress Semiconductor Corp.

2-Mbit (64K x 32) Pipelined SRAM with

NoBL™ Architecture

CY7C1334H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05678 Rev. *B Revised February 6, 2006

Features

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 64K x 32 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed write

• Asynchronous output enable (OE)

• Offered in Lead-Free JEDEC-standard 100-pin TQFP

package

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Functional Description[1]

The CY7C1334H is a 3.3V/2.5V, 64K x 32

synchronous-pipelined Burst SRAM designed specifically to

support unlimited true back-to-back Read/Write operations

without the insertion of wait states. The CY7C1334H is

equipped with the advanced No Bus Latency™ (NoBL™) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of the SRAM, especially

in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 3.5 ns (166-MHz device)

Write operations are controlled by the four Byte Write Select

(BW[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

BWA

CE1

CE2

CE3

OE READ LOGIC

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC A0'

A1'

D0 Q1

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram

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CY7C1334H

Document #: 38-05678 Rev. *B Page 2 of 13

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time (tCO)3.5 4.0 ns

Maximum Operating Current (IDD)240 225 mA

Maximum CMOS Standby Current 40 40 mA

Pin Configuration

NC/288M

NC/144M

VSS

VDD

NC/36M

NC/4M

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

CEN

100

ADV/LD

MODE

NC/72M

NC/18M

NC/9M

CY7C1334H

100-Pin TQFP Pinout

BYTE B

BYTE A

BYTE C

BYTE D

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CY7C1334H

Document #: 38-05678 Rev. *B Page 3 of 13

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge

of the CLK. A[1:0] are fed to the two-bit burst counter.

BW[A:D] Input-

Synchronous Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK.

WE Input-

Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a Write sequence.

ADV/LD Input-

Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. Wh en LOW , a

new address can be loaded into the devi ce for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE1Input-

Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3 to select/deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device.

OE Input-

Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic

block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are

allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input

data pi ns. OE is masked during the data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been desele cted.

CEN Input-

Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasser ting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved. During normal operation, this pin can be connected to

VSS or left floating.

DQs I/O-

Synchronous Bidirectional Dat a I/O Lines. As inputs, they feed into an on-c hip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A[16:0] during the clock rise of the read cycle. The direction of the pins is controlled

by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.

When HIGH, DQs are placed in a tri-state condition. The outputs are automatically tri-stated

during the data portion of a write sequence, during the first clock when emerging from a

deselected state, and when the device is deselected, regardless of the state of OE.

MODE Input

Strap pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects inter-

leaved burst sequence.

VDD Power Supply Power supply inputs to the core of the device.

VDDQ I/O Power

Supply Power supply for the I/O circuitry.

VSS Ground Ground for the device.

VSSQ I/O Ground Ground for the I/O circuitry. Should be connected to the ground of the system

NC No Connects. Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and

1G are address expansion pins and are not internally connected to the die.

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 4 of 13

Functional Overview

The CY7C1334H is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous op erations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximu m

access delay from the clock rise (tCO) is 3.5 ns (166-MHz

device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a Read or Write operation, depending on

the status of the Write Enable (WE). BW[A:D] can be used to

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enab le (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Regi ster and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initia ted. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signa ls, its

output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1334H has an on-chip burst counter that allows the

user the ability to supply a si ngle address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address in to the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of Chip Enables inputs or WE. WE is latched a t the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logi c block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQs and

DQP[A:D]. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQs (or a subset

for Byte Write operations, see Write Cycle Description table for

details) inputs is latched into the device and the write is

complete.

The data written during the Write operation is controlled by

BW[A:D] signals. The CY7C1334H provides Byte Write

capability that is described in the Write Cycle Description table.

Asserting the Write Enable input (WE) with the selected Byte

Write Select (BW[A:D]) input will selectively write to only the

desired bytes. Bytes not selected during a Byte Write

operation will remain unaltered. A synchronous self-timed

write mechanism has been provided to simplify the Write

operations. Byte write capability has been included in order to

greatly simplify Read/Modify/Write sequences, which can be

reduced to simple Byte Write operations.

Because the CY7C1334H is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQs. Doing so will tri-state the

output drivers. As a safety precaution, DQs are automaticall y

tri-stated during the data portion of a Write cycle, regardless of

the state of OE.

Burst Write Accesses

The CY7C1334H has an on-chip burst counter that allows the

user the ability to supply a singl e address and conduct up to

four Write operations without reasserting the address inpu ts .

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct

BW[A:D] inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected p rior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive

for the duration of tZZREC after the ZZ input returns LOW.

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 5 of 13

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Tri-State

Continue Deselect Cycle None X L H X X X L L-H Tri-State

Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)

Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)

NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State

Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State

Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)

Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)

NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State

WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State

IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H -

Sleep MODE None X H X X X X X X Tri-State

Notes:

2. X = “Don't Care.” H = HIGH, L = LOW. CE st ands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies

that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.

4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.

5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycl es. During a read cycle DQs and DQP[A:D] = T ri-State when

OE is inactive or when the device is deselected, and DQs = data when OE is active.

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 6 of 13

Write Cycle Description[2, 3]

Function WE BWDBWCBWBBWA

Read H X X X X

Write − No bytes written L H H H H

Write Byte A − (DQA) LHHHL

Write Byte B − (DQB)LHHLH

Write Bytes A, B L H H L L

Write Byte C − (DQC)LHLHH

Write Bytes C,A L H L H L

Write Bytes C, B L H L L H

Write Bytes C, B, A L H L L L

Write Byte D − (DQD)LLHHH

Write Bytes D, A L L H H L

Write Bytes D, B L L H L H

Write Bytes D, B, A L L H L L

Write Bytes D, C L L L H H

Write Bytes D, C, A L L L H L

Write Bytes D, C, B L L L L H

Write All Bytes L L L L L

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 7 of 13

Maximum Rating

(Above which the useful life may be impaired. For user guide-

lines not tested.)

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

Supply Voltage on VDDQ Relative to GND.......−0.5V to +VDD

DC Voltage Appli ed to Outputs

in Tri-State................................................−0.5V to VDDQ + 0.5V

DC Input Voltage....................................... −0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range Ambient

Tem perature (TA) VDD VDDQ

Com’l 0°C to +70°C 3.3V - 5%/+10% 2.5V - 5% to

VDD

Ind’l –40°C to +85°C

Electrical Characteristics Over the Operating Range[9, 10]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage for 3.3V I/O 3.135 VDD V

for 2.5V I/O 2.375 2.625 V

VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V

for 2.5V I/O, IOH = –1.0 mA 2.0

VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V

for 2.5V I/O, IOL = 1.0 mA 0.4

VIH Input HIGH Voltage[9] for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V

VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V

for 2.5V I/O –0.3 0.7

IXInput Leakage Current

except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5µA

Input Current of MODE Input = V SS −30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS −5µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −5 5 µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 240 mA

7.5-ns cycle, 133 MHz 225 mA

ISB1 Automatic CE

Power-Down

Current—TTL Inputs

VDD = Max, Device

Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

6-ns cycle, 166 MHz 100 mA

7.5-ns cycle, 133 MHz 90 mA

ISB2 Automatic CE

Power-Down

Current—CMOS Inputs

VDD = Max, Device

Deselected, VIN ≤ 0.3V or

VIN > VDDQ – 0.3V, f = 0

All speeds 40 mA

ISB3 Automatic CE

Power-Down

Current—CMOS Inputs

VDD = Max, Device

Deselected, or VIN ≤ 0.3V or

VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

6-ns cycle, 166 MHz 85 mA

7.5-ns cycle, 133 MHz 75 mA

ISB4 Automatic CE

Power-Down

Current—TTL Inputs

VDD = Max, Device

Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All Speed s 45 mA

Notes:

9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse wid th less than tCYC/2).

10.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 8 of 13

Capacitance[11]

Parameter Description Test Conditions 100 TQFP

Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V,

VDDQ = 2.5V

5pF

CCLK Clock Input Capacitance 5 pF

CI/O Input/Output Capacitance 5 pF

Thermal Resistance[11]

Parameter Description Test Conditions 100 TQFP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51

30.32 °C/W

ΘJC Thermal Resistance

(Junction to Case) 6.85 °C/W

AC Test Loads and Waveforms

Notes:

11.Tested initially and aft er any design or process changes that may affect these parameters.

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

2.5V I/O Test Load

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 9 of 13

Switching Characteristics Over the Operating Range [12, 13]

166 MHz 133 MHz

Parameter Description Min. Max. Min. Max. Unit

tPOWER VDD (typical) to the First Access[14] 11ms

Clock

tCYC Clock Cycle Time 6.0 7.5 ns

tCH Clock HIGH 2.5 3.0 ns

tCL Clock LOW 2.5 3.0 ns

Output Times

tCO Data Output Valid after CLK Rise 3.5 4.0 ns

tDOH Data Output Hold after CLK Rise 1.5 1.5 ns

tCLZ Clock to Low-Z[15, 16, 17] 00ns

tCHZ Clock to High-Z[15, 16, 17] 3.5 4.0 ns

tOEV OE LOW to Output Valid 3.5 4.0 ns

tOELZ OE LOW to Output Low-Z[15, 16, 17] 00ns

tOEHZ OE HIGH to Output High-Z[15, 16, 17] 3.5 4.0 ns

Set-up Times

tAS Address Set-up before CLK Rise 1.5 1.5 ns

tALS ADV/LD Set-up before CLK Rise 1.5 1.5 ns

tWES GW, BW[A:D] Set-up before CLK Rise 1.5 1.5 ns

tCENS CEN Set-up before CLK Rise 1.5 1.5 ns

tDS Data Input Set-up before CLK Rise 1.5 1.5 ns

tCES Chip Enable Set-Up before CLK Rise 1.5 1.5 ns

Hold Times

tAH Address Hold after CLK Rise 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.5 0.5 ns

tWEH GW, BW[A:D] Hold after CLK Rise 0.5 0.5 ns

tCENH CEN Hold after CLK Rise 0.5 0.5 ns

tDH Data Input Hold after CLK Rise 0.5 0.5 ns

tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns

Notes:

12.Test conditions shown in (a), (b) and (c) of AC Test Loads.

13.Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.

14.This p art has a voltage regulator internally; t POWER is the time that the power nee ds to be supplied ab ove VDD minimu m initially before a Read or Write op eration

can be initiated.

15.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC te st conditions shown i n part (b) of AC Test Loads. T ransitio n is measured ± 200 mV from steady-st ate voltage.

16.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is le ss than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not i mply a b us content ion condit ion , b ut ref lect parameters guar anteed over wo rst case user condit ions. Device is d esigned

to achieve Tri-State prior to Low-Z under the same system conditions

17.This parameter is sampled and not 100% tested.

[+] Feedback

CY7C1334H

Document #: 38-05678 Rev. *B Page 10 of 13

Switching Waveforms

Read/Write Timing[18, 19, 20]

Notes:

18.For this waveform ZZ is tied LOW.

19.When CE is LOW, CE1 is LOW, C E2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

20.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

tCEH

tCES

CEN

tCENH

tCENS

[A:D]

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

Data

n-Out (DQ)

tCLZ

D(A1) D(A2) D(A5)Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCO

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

tOEV

tOELZ

tOEHZ tDOH

DON’T CARE UNDEFINED

Q(A6)

Q(A4+1)

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CY7C1334H

Document #: 38-05678 Rev. *B Page 11 of 13

NOP, STALL, and Des elect Cycles[18, 19, 21]

ZZ Mode Timing[22, 23]

Notes:

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode . See cycle description table for all possible signal conditions to deselect the device.

23.I/Os are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

READ

Q(A3)

45678910

CLK

CEN

[A:D]

ADV/LD

ADDRESS A3 A4 A5

D(A4)

Data

In-Out (DQ)

Q(A5)

WRITE

D(A4) STALLWRITE

D(A1)

123

READ

Q(A2) STALL NOP READ

Q(A5) DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

CHZ

D(A1) Q(A2) Q(A3)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

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CY7C1334H

Document #: 38-05678 Rev. *B Page 12 of 13

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, Inc. All prod uct and company names mentioned in this document are the trademarks of their respective ho lders.

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered”.

Speed

(MHz) Order ing Code Package

Diagram Package Type Operating

Range

166 CY7C1334H-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1334H-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

133 CY7C1334H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1334H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

Package Diagram

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

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CY7C1334H

Document #: 38-05678 Rev. *B Page 13 of 13

Document History Page

Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architectu re

Document Number: 38-05678

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 347357 See ECN PCI New Data Sheet

*A 424 820 See ECN RXU Changed address of Cypress Semiconductor Corporation on Pag e# 1 from

“3901 North First Street” to “198 Champion Court”

Changed Three-State to Tri-State.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.

Modified test condition from VDDQ < VDD to VDDQ < VDD

Replaced Package Name column with Packag e Diagram in the Ordering

Information table.

Replaced Package Diagram of 51-85050 from *A to *B

*B 459 347 See ECN NXR Converted from Preliminary to Final

Included 2.5V I/O option

Updated the Ordering Information table.

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