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Doc. No. MV-S102944-00, Rev. E
January 21, 2008
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Cover
88PL810/88PL815/88PL830
High Current, Adjustable 8 Level
LDO Regulator
Datasheet
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88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 2 Document Classificatio n: Proprietary January 21, 2008, 1.00
Table of Contents
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 1
Table of Contents
Table of Contents .......................................................................................................................................1
List of Tables ..............................................................................................................................................1
List of Figures.............................................................................................................................................1
1 Signal Description.........................................................................................................................5
1.1 Pin Configuration...............................................................................................................................................5
1.2 Pin Description..................................................................................................................................................6
1.2.1 Pin Types............................................................................................................................................6
2 Electrical Specifications ...............................................................................................................7
2.1 Absolute Maximum Ratings ..............................................................................................................................7
2.2 Recommended Operating Conditions...............................................................................................................7
2.3 Electrical Characteristics...................................................................................................................................8
3 Functional Description................................................................................................................11
3.1 Output Voltage – AnyVoltage™ Technology...................................................................................................12
3.2 Soft Start.........................................................................................................................................................13
3.3 Hiccup Current Limit..................... ...................................................................................................................14
3.4 Output Capacitor (COUT) Selection................................................................................................................15
3.5 Input Capacitor................................................................................................................................................15
3.6 Enable.............................................................................................................................................................15
3.7 Minimum Load Current....................................................................................................................................15
3.8 Undervoltage Lockout (UVLO)........................ ... .......................................... ...................................................16
3.9 Thermal Shutdown..........................................................................................................................................16
3.10 Thermal Considerations..................................................................................................................................17
4 Functional Characteristics .........................................................................................................19
5 Typical Characteristics ...............................................................................................................21
5.1 IC Case and Board Temperature....................................................................................................................21
6 Mechanical Drawings..................................................................................................................25
6.1 Mechanical Dimensions ..................................................................................................................................25
6.1.1 MSOP-8 Package.............................................................................................................................25
6.1.2 5x5mm QFN-5L Package.................................................................................................................27
6.2 Typical Pad Layout Dimensions......................................................................................................................29
7 Ordering Information............................ ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ... ...................33
7.1 Ordering Part Numbers and Package Markings..............................................................................................33
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
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7.2 Sample Ordering Part Number........................................................................................................................33
7.3 Package Markings..................... ...................... .......................................... ......................................................34
7.3.1 5 X 5 QFN-5 Package Marking.................. .. .......................................... ...........................................34
7.3.2 3 X 3 MSOP-8 Package Marking.................... ... ... ...................... ....................... ...................... .........34
A Revision History ..........................................................................................................................35
List of Tables
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 1
List of Tables
Table 1: Product Table .....................................................................................................................................5
Table 2: Pin Type Definitions............................................................................................................................6
Table 4: Absolute Maximum Ratings................................................................................................................7
Table 5: Recommended Operating Conditions.................................................................................................7
Table 6: Electrical Characteristics ....................................................................................................................8
Table 7: Output Voltage..................................................................................................................................12
Table 8: Recommended Capacitors ...............................................................................................................15
Table 9: MSOP-8L Dimensions......................................................................................................................26
Table 10: 5x5mm QFN-5L Dimensions ............................................................................................................28
Table 11: Order Samples Table........................................................................................................................33
Table 12: Revision History................................................................................................................................35
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
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List of Figures
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 1
List of Figures
Figure 1: Typical LDO Regulator .......................................................................................................................3
Figure 2: 3x3mm MSOP-8 - Top View...............................................................................................................5
Figure 3: 5x5mm QFN-5 - Top View..................................................................................................................5
Figure 4: 88PL810/88PL815 /88PL830 Simplifie d Block Diagram....................................................................11
Figure 5: Startt-Up Sequence..........................................................................................................................12
Figure 6: VSET Voltage Steps for 2.5V Output................................................................................................12
Figure 7: Rise Time with COUT = 10mF..........................................................................................................13
Figure 8: Rise Time with COUT = 1000mF......................................................................................................13
Figure 9: Hiccup Period ...................................................................................................................................14
Figure 10: Current Limit Response Time...........................................................................................................14
Figure 11: Startt-Up Using the Enable Pin................................................... ... ...................................................19
Figure 12: Turn Off Using the Enable Pin........................ ... ...................... ....................... ..................................19
Figure 13: Input Voltage Soft Start.....................................................................................................................19
Figure 14: Input Voltage Hot Plug......................................................................................................................19
Figure 15: UVLO Thresholds .............................................................................................................................20
Figure 16: Load Transient Response.................................................................................................................20
Figure 17: 5x5mm QFN-5L Package.................................................................................................................21
Figure 18: Input Voltage Graphs........................................................................................................................22
Figure 19: Temperature Graphs ........................................................................................................................23
Figure 20: Temperature Graphs (Continued).....................................................................................................24
Figure 21: 88PL810/88PL815/88PL830 MSOP Mechanical Dimensions..........................................................25
Figure 22: 88PL810/88PL815/88PL830 5x5mm QFN-5L Mechanical Dimensions...........................................27
Figure 23: Recommended Solder Pad Layout for MSOP-8...............................................................................29
Figure 24: Recommended Solder Pad Layout for QFN-5..................................................................................30
Figure 25: Ordering Part Numbers and Package Markings...............................................................................33
Figure 26: Package Marking and Pin 1 Location for 5 X 5mm QFN-5...............................................................34
Figure 27: Package Marking and Pin 1 Location for 3 X 3mm MSOP-8............................................................34
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 2 Document Classificatio n: Proprietary January 21, 2008, 1.00
88PL810/88PL815/88PL830
High Current, Adjustable 8 Level LDO Regulator
Datasheet
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 3
PRODUCT OVERVIEW
The 88PL810/88PL815/88PL830 family of devices are
high current ultra-low-dropout linear (LDO) regulators,
featuring up to 235mV at 3A dropout voltage and very
low ground current. Quiescent current is typically 1.5mA
and drops to 0.1A in shutdown. The devices protect
themselves from short circuit conditions by turning OFF
for about 6ms and ON ("hiccup"), thereby limiting
temperature rise. In "Hot-Swap" applications, no
additional circuitry is required since these devices have
an integrated "Soft Start" mode. Additionally, a unique
output voltage programming technique is used to provide
eight output voltage options.
The whole 88PL810/15/30 family’s output voltage can be
adjusted to 8 different levels between 2.4V and 2.75V
(2% or 50mV per step), for an input voltage range of
2.7V to 3.6V. This voltage is defined by the user with a
single external resistor (RVSET). The 88PL810 device is
adjustable in 30mV steps and the 88PL815 device is
adjustable in 36mV steps.
The 88PL810/88PL815/88PL830 devices are stable with
a 10µF ceramic output capacitor. However, any other
type of capacitor up to 1000µF can be placed in parallel
with it as long as the 10µF ceramic output capacitor is
placed next to the 88PL810/88PL815/88PL830.
Features
88PL810: 1.5V/1.0A; 88PL815: 1.8V/1.5A; 88PL830:
2.5V/3.0A
Ultra-low dropout (235mV @ 3A typ.)
Input voltage range 2.7V to 3.6V
One resistor sets the output voltage level
Fixed Soft start ramp with any output capacitor up to
1000µF
"Hiccup" sho rt circuit protecti on
Stable with ceramic output capacitors
Adjustable 8 level, programmable output voltage in
2% steps
Logic controlled shutdown
0.1µA supply current in shutdown
Stable with 0A load current
Lead-free MSOP-8L and QFN-5L packages
-40°C to +125°C junction temperature range
Applications
Adjustable linear regulator for low-voltage digital ICs
PC add-in cards
Backup power supplies and 3.3V PCI Express Bus
Figure 1: Typical LDO Regulator
Vin Vout
VIN
4
TAB EP
VSET
1
VOUT
2
GND
3
EN
5
88PL830
10uF/6.3V 10uF/6.3V
Disable
Enable
C2C1
2.5V/3A3.3V
88PL810/88PL815/88PL830
Datasheet
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Signal Description
Pin Configuration
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 5
1Signal Description
1.1 Pin Configuration
Figure 2: 3x3mm MSOP-8 - Top View
Figure 3: 5x5mm QFN-5 - Top View
Table 1: Product Table
Product Number Output Voltage Output Current
88PL830 2.40, 2.45, 2.50 , 2. 55, 2.60, 2.65, 2.70, 2.75 3.0A
88PL815 1.728, 1.764, 1.80, 1.836, 1.872, 1.908, 1.94 4, 1.980 1.5A
88PL810 1.44, 1.47, 1.50, 1.53, 1.56, 1.59, 1.62, 1.65 1.0A
88PL810/88PL815/88PL830
Datasheet
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1.2 Pin Description
1.2.1 Pin Types
This section provides the pin description of the 88PL810/88PL815/88PL830 devices. Table 2 shows
the pin types used in Table 3.
Table 2: Pin Type Definitions
Pin Type Definition
I Input only
O Output Only
S Supply
NC Not Connected
GND Ground
Table 3: Pin Description
5x5 QFN-5
Pin # 3x3 MSOP-8
Pin # Pin Name Pin Type Pin Function
5 1, 2 PVIN S Input Voltage:
Input voltage supplies current to output. Connect a 10μF
decouple capacitor (CIN) between this pin and GND pin.
4 3 EN I Enable:
CMOS compatible input. Logic low = Disable, Logic high =
Enable.
3 4 GND GND Ground:
Tab is connected to GND.
1 5 VSET Voltage Setting:
Connect to an external resistor that is connected to ground to
set the output voltage of the resistor.
The total capacitance across this pin and GND should be less
than 25pF. Use a resistor with tolerance better than 2%. If this
pin is connected to GND, the output voltage will be set to 2.5V.
If this pin is PVIN, the output voltage will be set to 3.3V. Do not
float this pin.
2 6, 7, 8 VOUT O Output Voltage:
Adjustable regulator output. A 10μF cap acitor is connected
between this pin and the GND pin.
Electri ca l Specific at io ns
Absolute Maximum Ratings
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 7
2Electrical Specifications
2.1 Absolute Maximum Ratings
2.2 Recommended Operating Conditions
Table 4: Absolute Maximum Ratings1
1. Exceeding the absolute the maximum rating may damage the device.
Parameter Symbol Range Units
Input Voltage to GND VIN -0.6 to 4.2 V
Enable voltage (VEN) to GND VEN -0.6 to max (VIN + 0.6, 4.2) V
Voltage set to GND VSET -0.6 to max (VIN + 0.6, 4.2) V
Output Voltage to GND VOUT -0.6 to max (VIN + 0.6, 4.2) V
Operating Temperature Range2
2. Specifications over the -40C to 85C operating temper ature ranges are assured by design, characterization and
correlation with statistical process controls.
TOP -40 to 85 C
Storage Temperature Range TSTOR -65 to 150 C
Maximum Junction Temperature TJMAX 150 C
ESD Rating3
3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5kΩ, in series with 100pF.
2kV
Table 5: Recommended Operating Conditions1
1. This device is not guaranteed to function outside the specified operating range
Parameter Symbol Range Units
Input Voltage VIN 2.7 to 3.6 V
MSOP Package Thermal Resistance θJA 150.88 C/W
5 X 5mm QFN-5L Package Thermal Resist ance θJA See Secti o n 5 C/W
Maximum Operating Junction Temperature TJMAX 125 C
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
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2.3 Electrical Characteristics
Table 6: Electrical Characteristics
NOTE: The following table applies unless otherwise noted: CIN = 10μF; COUT = 10μF (Ceramic); IOUT = 10mA; TA = 25C;
VIN = 3.3V. Bold values indicate -40C ≤ TA≤ 85C.
Parameter Symbol Condition Min Typ Max Units
Input Voltage Range VIN 2.7 3.6 V
Output Voltage Accuracy VOUT
1mA [ IOUT[ 3A
(88PL830)
-2 2 %
1mA [ IOUT [ 1.5A
(88PL815)
1mA [ IOUT [ 1A
(88PL810)
Output Voltage Load Regulation DVOUT/VOUT
10mA [ IOUT [ 3A
(88PL830)
0.1 %
10mA [ IOUT [ 1.5A
(88PL815)
10mA [ IOUT [ 1A
(88PL810)
Output Voltage Line Regulation DVOUT/VOUT VIN = 3.0V-3.6V, IOUT = 10
mA 0.01 %
Dropout Voltage
(88PL830 only) VIN-VOUT
IOUT = 1A, Output voltage
variation=1% 75 mV
IOUT = 2A, Output voltage
variation=1% 156 mV
IOUT = 3A, Output voltage
variation=1% 235 mV
Quiescent Current (88PL810)
IQIOUT = 0mA
1.0
mAQuiescent Current (88PL815) 1.2
Quiescent Current (88PL830) 1.5
Shutdown Input Current ISHDN VEN = GND 0.1 50 mA
Output Current Limit (88PL810)
IOUT(LIM)
VOUT = 1.5V 3.0
AOutput Current Limit (88PL815) VOUT = 1.8V 3.0
Output Current Limit (88PL830) VOUT = 2.5V 7.0
Enable Input
Enable Input Logic low VEN LDO Shutdown 1.1 V
Enable Input Logic high LDO Enable 2.2 V
Enable Pin Input Current IEN VEL = 1.1V 1 10 mA
VEH = 2.2V 1 10 mA
Under Voltage Lockout
Under Voltage Lockout VUVLO
High threshold (UTH), VIN
increasing 2.60 2.70 V
Low threshold (UTL), VIN
increasing 2.45 V
Under Voltage Lockout Hysteresis 150 mV
Electri ca l Specific at io ns
Electrical Characteristics
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 9
LDO Output Voltage
Output Voltage (88PL830)
RSET = 11KΩ2.352 2.40 2.448 V
RSET = 18.7KΩ2.401 2.45 2.499 V
RSET = 31.6kΩ or 0Ω2.450 2.50 2.550 V
RSET = 53.6KΩ2.499 2.55 2.601 V
RSET = 97.6KΩ2.548 2.60 2.652 V
RSET = 165KΩ2.597 2.65 2.703 V
RSET = 280KΩ2.646 2.70 2.754 V
RSET = 475KΩ2.695 2.75 2.805 V
Output Voltage (88PL815)
RSET = 11KΩ1.693 1.728 1.763 V
RSET = 18.7KΩ1.729 1.764 1.799 V
RSET = 31.6kΩ or 0Ω1.764 1.800 1.836 V
RSET = 53.6KΩ1.799 1.836 1.873 V
RSET = 97.6KΩ1.835 1.872 1.909 V
RSET = 165KΩ1.870 1.908 1.946 V
RSET = 280KΩ1.905 1.944 1.983 V
RSET = 475KΩ1.940 1.980 2.020 V
Output Voltage (88PL810)
RSET = 11KΩ1.411 1.44 1.469 V
RSET = 18.7KΩ1.441 1.47 1.499 V
RSET = 31.6kΩ or 0Ω1.470 1.50 1.530 V
RSET = 53.6KΩ1.499 1.53 1.561 V
RSET = 97.6KΩ1.529 1.56 1.591 V
RSET = 165KΩ1.558 1.59 1.622 V
RSET = 280KΩ1.588 1.62 1.652 V
RSET = 475KΩ1.617 1.65 1.683 V
Soft Start
Start-up Time (88PL830) tSS VOUT = 2.5V 3
msStart-up Time (88PL815) VOUT = 1.8V 2.2
Start-up Time (88PL810) VOUT = 1.5V 2.1
Low Drop Out Auto-restart
LDO Auto-restart1Time to restart after current
limit shut down 630ms
Over Temperature Protection
Over-temperature Protection TOT TJ inc reasing (Disable IC) 150 C
TJ decreasing (Enable IC) 120 C
1. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization, and
correlation with statistical process controls.
Table 6: Electrical Characteristics
NOTE: The following table applies unless otherwise noted: CIN = 10μF; COUT = 10μF (Ceramic); IOUT = 10mA; TA = 25C;
VIN = 3.3V. Bold values indicate -40C ≤ TA≤ 85C.
Parameter Symbol Condition Min Typ Max Units
88PL810/88PL815/88PL830
Datasheet
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Functional Description
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 11
3Functional Description
Figure 4: 88PL810/88PL815/88PL830 Simplified Block Diagram
VSET
THERMAL
SHUTDOWN
150
°
C
Vin
2.7V to 3.6V
EN
C2
R1
ON
OFF
GND
HICCUP
CURRENT
LIMIT
-
+
UNDER-
VOLTAGE
LOCK-OUT
BAND-GAP
VOLTAGE
REFERENCE
&
SOFTSTART
RESISTOR
SENSIN G
CIRCUITRY
C1
Vout
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 12 Document Classification: Proprietary January 21, 2008, 1.00
3.1 Output Voltage – AnyVoltage™ Technology
For 88PL830, the output voltage is set by using a single resistor (RVSET) to provide eight output
voltage options from 2.40V to 2.75V in 50mV steps (See Table 4). The Rresistor is only read once
during start-up before the output voltage is turned on; therefore, the output voltage cannot be
changed on-the-fly. To configure the outp ut to a different voltage either power has to recycle or the
enable input has to turn OFF and back ON.
Figure 3 shows the startup sequence of the 88PL830. Once the input voltage (VIN) is above the
under voltage lockout (UVLO) upper threshold (UTH) of 2.65V, the VSET pin becomes active.
Current is sourced out of this pin in exponentially increasing steps. After each step there is a
blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET
voltage is below this reference voltage, the current source proceeds to the next set. Once the VSET
voltage is above the reference voltage the sequen ce stops and the output voltage (Vout) is allowed
to turn-on. Figure 4 shows the VSET waveform for a 2.5V output. The 88PL830 keeps track of how
many steps were required to determine the appropriate output voltage. Table 4 provides the number
of steps necessary for each output voltage option. Using a 31.6kΩ resistor requires the current
source to step 7 times, see Figure 4.
Table 7: Output Voltage
Step VOUT
88PL830
(V)
VOUT
88PL815
(V)
VOUT
88PL810
(V)
RVSET (kΩ)
12.50 1.80 1.50 0
22.75 1.980 1.65 475
32.70 1.944 1.62 280
42.65 1.908 1.59 165
52.60 1.872 1.56 97.6
62.55 1.836 1.53 53.6
72.50 1.80 1.50 31.6
82.45 1.764 1.47 18.8
92.40 1.728 1.44 11
VOUT
VIN
VSET
Figure 5: Startt-Up Sequence
2V/DIV
1V/DIV
1V/DIV
VSET
Figure 6: VSET Volta ge Step s for 2.5V
Output
0.5V/DIV
2ms/DIV 100 µs/DIV
Functional Description
Soft Start
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 13
The 88PL810/88PL815/88PL830 devices provide an innovative technique to set the output voltage.
The output voltage is determined during startup by the device reading the value of an external
resistor that is located outside the regulator's feedback loop. By placing the output
voltage-programming resistor outside the regulator's feedback loop, its tolerance does not affect the
accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output
voltage. However, these resistors are located inside the feedback loop, introducing as much as 2%
of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. The
88PL810/88PL815/88PL83 0 initial accuracy is 2% for any of the eight output voltages.
The VSET pin is sensitive to excessive leakage currents and stray capacitance. The output voltage
can potentially be programmed to the lower output voltage if there is contamination that introduces
excessive leakage current on the VSET pin, especially for a RVSET of 475kΩ. The parasitic
resistance on the node must be greater than 3MΩ and the stray capacitance must be equal to 25pF
or less.
3.2 Soft Start
Soft st art is a highly desirable property in "Hot-Swap" applications. Most LDOs start-up within 100μs,
producing large inrush currents on the input power supply. The 88PL810/88PL815/88PL830 device
controls the rise time of the output voltage, thereby dramati c ally reducing the inrush current. The
88PL830 device rise time is typically 3ms and it is independent of output capacitance and load
current. Figure 5 shows the rise time with a 10μF output capacitor at 50mA load and Figure 6 shows
the rise time with a 1000μF output capacitor at 500mA load. Even with these extreme loading
conditions and different inrush current, the output voltage rise time difference is less than 0.1ms.
Also note that the output voltage starts at near 0V while other LDO soft start techniques typically
start at 1.25V.
.
VOUT
IIN
ILOAD
= 50mA
Figure 7: Rise Time with COUT =
10μF
1V/DIV
100mV/DIV
VOUT
IIN
ILOAD
= 50mA
Figure 8: Rise Ti me with COUT =
1000μF
1V/DIV
500mV/D
IV
1ms/DIV 1ms/DIV
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 14 Document Classification: Proprietary January 21, 2008, 1.00
3.3 Hiccup Current Limit
The "Hiccup" short-circuit protection is a feature that is not common among other LDOs. When the
current-sense circuit sees an over-current condition , the 88PL 810/88PL815/88PL83 0 device shuts
off for about 6ms and then tries to start up again, see Figure 7. If the over-load condition is removed,
the 88PL810/88PL815/88PL830 devices will start-up normally; otherwise, the
88PL810/88PL815/88PL830 device will see another over-current event and shut off again, repeating
the previous cycle.
.
Hiccup mode protection offers protection against over current situations, since it limits the average
current to the load at a low level, reducing power dissipation and case temperature of the IC. The
88PL810/88PL815/88PL830 device case temperature will only rise about 20°C and have a case
temperature of around 45°C at room, reducing the thermal stress on the device.
Figure 8 shows the response ti me of the current limit circuitry. The response time of the protection
circuit must be quick enough to prevent damage from overloads, yet allow enough time to response
to transient loads without prematurely tripping the protecti on circuit.
IOUT
Figure 9: Hiccup Period
5A/DIV
IOUT
Figure 10: Current Limit Response
Time
5A/DIV
2ms/DIV 200μs/DIV
Functional Description
Output Capacitor (COUT) Selection
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 15
3.4 Output Capacitor (COUT) Selection
The 88PL810/88PL815/88 P L830 device requires a 10μF ceramic output capacitor as part of the
frequency compensation. However, any other type of capacitor up to 1000μF can be pla ced in
parallel with it as long as the 10μF ceramic output capacitor is placed next to the
88PL810/88PL815/88PL83 0 device. Additional output capacitance further improves load-transient
response and power supply rejection.
X7R and X5R type ceramic capacitors are recommended because of their performance over
temperature. Capacitance of the X7R type capacitors changes only 15% over their operating
temperature range. Y5V and Z5U type ceramic capacitors change value by as much as 60% and
50%, respectively, over their operating temperature range. If Y5V type ceramic capacitors are used,
then higher value capacitor in comparison with X7R and X5R capacitors must be used to ensure a
sufficient capacitance value over the operating temperature range. The following capacitors are
some of the capacitors recommended to be used with the 88PL810/88PL815/88PL830.
3.5 Input Capacitor
An input capacitor of 1μF or greater is required between the 88PL810/88PL815/88PL830 device's
VIN pin and ground. It must be placed as close as possible to the 88PL810/88PL815/88PL830
device for stable operation. While 1μF will provide adequate bypassing of the VIN supply, larger
value input capacitors (10μF) can improve bypassing to handle fast transient response
requirements.
3.6 Enable
The 88PL810/88PL815/88 P L830 devices feature an active high enable (EN) inpu t that allows
ON/OFF control of the device. Near "zero" current drain is achieved when the device is disabled,
with only microamperes of leakage current flow. The EN input includ es TTL/CMOS compatible
thresholds for simple interfacing with logic, or that may be directly tied to VIN for a constant ON state.
The enable input must not be left floating; it must be tied either high or low.
3.7 Minimum Load Current
The 88PL810/88PL815/88PL830 device, unlike most other high current regulators, does not require
a minimum load to maintain output voltage regulation.
Table 8: Recommended Capacitors
Manufacturer Part Number Dielectric Capacitance
(μF) Voltage
(V) Case
Size
(inch)
Max
Height
(mm)
Murata GRM188R60G106M X5R 10 4.0 0603 0.9
Murata GRM219R60J106K X5R 10 6.3 0805 0.95
Murata GRM21BR60J106K X5R 10 6.3 0805 1.35
Taiyo-Yuden CE JMK212BJ106MG-T X5R 10 6.3 0805 1.40
TDK C2012X5R0J106MT X5R 10 6.3 0805 1.55
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
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3.8 Undervoltage Lockout (UVLO)
The 88PL810/88PL815/88PL830 incorporates undervoltage-lockout circuitry to disable the LDO
when the input voltage is below 2.45V (typical). The LDO is enabled when the input voltage is above
2.60V (typical).
3.9 Thermal Shutdown
When the junction temperature of the 88 PL810/88PL815/88PL830 de vice exceeds 150C (typical),
the thermal shutdown circuitry disables the LDO. The LDO is enabled when the junction
temperature is decreased to 120C (typical).
Functional Description
Thermal Considerations
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 17
3.10 Thermal Considerations
The power handling capability of the device is limited by the maximum rated junction temperature
(125°C). The power dissipated by the device is made up of two components:
1. Output current multiplied by the differential of input and outpu t voltage: (IOUT) (V IN-VOUT).
2. Input current into the device (used by internal circuitry in mA) multiplied by the input voltage:
(IQ)(VIN)
The actual power dissipation (PD) will be the sum of the two components listed above:
PD = (IOUT) (VIN - VOUT) + (IQ) (VIN)
To determine the maximum power dissipation (PD (max)) of the p ackage, use the junction-to-ambient
thermal resistance ( θJA) of the device and the following equation:
Where TJ (max) is the maximum junction temperature of the die (125C) and TA (max) is the ambient
operating temperature. Note that θJA is layout dependent.
A heat sink effectively increases the surface area of the package to improve the flow of heat away
from the IC and into the air. Each material in the heat flow between the IC and the outside
environment has a thermal resistance. Starting from the die, we have θJC (junction to case), θCS
(case to heat sink), and θSA (heat sink to ambient). These thermal resistances are added together to
determine the total thermal resistance between the die and the air, θJA.
θJA = θJC + θCS+ θSA
The value for θSA is dependent on the heat sink, where the θCS is dependent on the package type
and contact between heat sink and package. The proper heat sink can be selected based on the
following equation:
The θJA can be calculated after the proper heat sink is selected.
To prevent the device from entering Thermal Shutdown, the actual power dissipation needs to be
equal or less than the maximum power dissipation:
PDmax()
TJmax()
TAmax()
–()
θJA
----------------------------------------------
=
θSA TJmax()
TAmax()
–
PDmax()
----------------------------------------- θJC θCS
+()–=
TJmax()
TAmax()
–
θJA
-------------------------------------------IOUT
()VIN VOUT
–()×≥
88PL810/88PL815/88PL830
Datasheet
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Functional Characteristics
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 19
4Functional Characteristics
The following is used CIN = 10μF; COUT = 10μF (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise
noted.
.
.
.
VOUT
VSET
EN
Figure 11: Startt-Up Using the
Enable Pin
1V/DIV
1V/DIV
2V/DIV
VSET
EN
Figure 12: Turn Off Using the Enable
Pin
1V/DIV
2V/DIV
1ms/DIV 1ms/DIV
ILOAD = 50ΩILOAD = 50Ω
VIN
VOUT
VSET
Figure 13: Input Voltag e Soft Start
1V/DIV
1V/DIV
1V/DIV
VIN
VOUT
VSET
Figure 14: Input Voltag e Hot Plug
1V/DIV
1V/DIV
1V/DIV
2ms/DIV 1ms/DIV
ILOAD = No Load ILOAD = No Load
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 20 Document Classification: Proprietary January 21, 2008, 1.00
VOUT
VIN
Figure 15: UVLO Thresholds
1V/DIV
1V/DIV
VOUT
ILOAD
Figure 16: Load Transient Response
20mV/D
1A/DIV
100ms/DIV 200 µs/DIV
VHTH = 2.60V
VLTH = 2.45V ILOAD = 0.01A to 3.0A
COUT = 10μF
Typica l Ch ara cteris t ics
IC Case and Board Temperature
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 21
5Typical Characteristics
5.1 IC Case and Board Temperature
Actual results depend upon the size of the PCB and proximity to other heat emitting components.
The following test data used a ¾ in2 PCB, 1 oz copper, and 88PL830 part.
Figure 17: 5x5mm QFN-5L Package
IC Power Loss vs. Output Current
Vin = 3. 3V, Vout = 2. 5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
00.511.522.533.5
Output Curre nt (A)
IC Ploss (W)
85°C
65°C
45°C
25°C
IC Case Temprature vs. Output Current
Vi n = 3. 3 V, Vout = 2 . 5V
20
40
60
80
100
120
140
160
00.511.522.53
Outpu t Current (A)
IC Temprature (°C)
85°C
65°C
45°C
25°C
PCB Board & IC Temperat ure vs. Power
Dissipation
Vin = 3. 3V, Vout = 2. 5V, @ 25°C
y = 20 . 783 x + 26.90 5
y = 30. 184x + 26.597
20
30
40
50
60
70
80
90
100
110
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IC Pow er Loss (W)
Board Temprature (°C)
PCB_25°C
IC_25°C
Line ar (PCB_25°C)
Line ar (IC_25°C)
IC Case Temprature vs. Power Dissipation
Vi n = 3.3V
y = 30. 184x + 26. 597
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IC Pow er Loss (W)
IC Temprature (°C)
85°C
65°C
45°C
25°C
Linear (25°C)
IC Temperature vs. Output Current
Vi n = 3.3V, @25° C
0
20
40
60
80
100
120
00.511.522.53
Iout(A)
IC Temp(C)
Vout=2.4V
Vout=2.5V
Vout=2.6V
Vout=2.75V
Dropout v s. Loa d Cur r ent
Vi n = 2. 7 , Vout = 2.7V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 0.5 1 1.5 2
Output Current (A)
LDO Dropout (V)
85°C
25°C
-40°C
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 22 Document Classification: Proprietary January 21, 2008, 1.00
Figure 18: Input Voltage Graphs
The following data applies to 88PL830; CIN = 10μF; COUT = 10μF (Ceramic); unless otherwise noted.
Supply Current vs. Input Voltage
1.2
1.3
1.4
1.5
1.6
2.73.03.33.6
Input Voltage (V)
Supply Current (mA)
Output Voltage vs. Input Voltage
2.400
2.450
2.500
2.550
2.600
2.7 3.0 3.3 3.6
Input Voltage (V)
Output Voltage (V)
Load Regulation vs. Input Voltage
-0.20%
-0.10%
0.00%
0.10%
0.20%
2.7 3.0 3.3 3.6
I np ut V oltage (V)
Load Regulation (%
)
Output Current Limit vs. Input Voltage
0.0
2.0
4.0
6.0
8.0
10.0
2.7 3.0 3.3 3.6
Input Voltage (V)
Curre nt Limit (A)
88PL830
88PL815/10
Shutdown Current vs. Input Voltage
0.0
0.1
0.2
0.3
0.4
2.7 3.0 3.3 3.6
Input Voltage (V)
Shutdown Current (uA)
Enable Threshold vs. Input Voltage
1.10
1.20
1.30
1.40
1.50
1.60
1.70
2.7 3.0 3.3 3.6
Input Voltage (V)
Enable Threshold (V)
Load = No Load
V
OUT(LDO)
= 2.5V
I
OUT(LDO)
= 10mA – 3.0A
I
OUT(LDO)
= 10mA
Typica l Ch ara cteris t ics
IC Case and Board Temperature
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 23
Figure 19: Temperature Graphs
The following data applies to 88PL830; CIN = 10μF; COUT = 10μF (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise
noted.
Supply Current vs. Temperature
1.2
1.3
1.4
1.5
-40 -20 0 20 40 60 80
Temperature (°C)
Supply Current (mA)
Output Voltage vs. Temperature
2.425
2.450
2.475
2.500
2.525
2.550
2.575
-40-20020406080
Temperature (°C)
Output Voltage (V)
Load Regulation vs. Temperature
-0.20%
-0.10%
0.00%
0.10%
0.20%
0.30%
0.40%
-40-20020406080
Temperature (°C)
Load Regulation (%)
Line Regulation vs. Temperature
-0.30%
-0.20%
-0.10%
0.00%
0.10%
0.20%
-40-200 20406080
Temperature (°C)
Line Re gulat ion (%)
Shutdow n Current vs. Te mperature
0
0.25
0.5
0.75
1
-40-200 20406080
Temperature (°C)
Shutdown Current (uA)
Enab le T hreshol d vs. Temp erature
1.00
1.25
1.50
1.75
2.00
-40-200 20406080
Temperature (°C)
Enable Threshold (V)
I
OUT(LDO)
= No Load I
OUT(LDO)
= 1 0mA
I
OUT(LDO)
= 10mA V
IN
= 3.0 V – 3.6V
I
OUT(LDO)
= 10mA – 3A
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 24 Document Classification: Proprietary January 21, 2008, 1.00
Figure 20: Temperature Graphs (Continued)
The following data applies to 88PL830; CIN = 10μF; COUT = 10μF (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise
noted.
UVLO vs. Temperature
2.3
2.4
2.5
2.6
2.7
2.8
-40-200 20406080
Temperature (°C)
UVLO (V)
Current Limit vs. Temperature
0
1
2
3
4
5
6
7
8
-40-200 20406080
Temperature (°C)
Current Limit (A )
88PL830
88PL815/10
I
OUT(LDO)
= 10mA
Mechanical Drawings
Mechanical Dimensions
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 25
6Mechanical Drawings
6.1 Mechanical Dimensions
6.1.1 MSOP-8 Package
Figure 21: 88PL810/88PL815/88PL830 MSOP Mechanical Dimensions
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 26 Document Classification: Proprietary January 21, 2008, 1.00
Notes:
3. Controlling Dimension: mm
4. Lead Frame Material: OLIN C7025
5. Dimension "D" does not include mold flash, tie bar burrs and gate burrs. Mold flash, tie bar burrs
and gate burrs shall not exceed 0.006" [0.15mm] per end. Dimension "E1" does not include
interlead flash. Interlead flash shall not exceed 0.010" [0.25mm] per side.
6. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.003"
[0.08mm] total in excess of the "b" dimension at maximum material condition. Dambar cannot
be located on the lower radius or the foot. Minimum space between protrusion and an adjacent
lead to be 0.0028" [0.07mm].
7. Tolerance: 60.010" [0.25mm] unless otherwise specified.
8. Otherwise dimensions follow acceptable specificati ons.
Table 9: MSOP-8L Dimensions
Symbol Dimension in mm Dimension in inch
MIN NOM MAX MIN NOM MAX
A1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.76 0.85 0.95 0.030 0.033 0.037
b0.25 0.30 0.35 0.010 0.012 0.014
C0.13 0.15 0.23 0.005 0.006 0.09
D2.90 3.00 3.10 0.114 0.118 0.122
E4.80 4.90 5.00 0.189 0.193 0.197
E1 2.90 3.00 3.10 0.114 0.118 0.122
e0.65 0.0256
L0.40 0.53 0.66 0.016 0.021 0.026
y0.10 0.004
036036
Mechanical Drawings
Mechanical Dimensions
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 27
6.1.2 5x5mm QFN-5L Package
Figure 22: 88PL810/88PL815/88PL830 5x5mm QFN-5L Mechanical Dimensions
Notes:
1. Controlling Dimension: Millimeter
2. Refence Document: JEDEC MO-229
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 28 Document Classification: Proprietary January 21, 2008, 1.00
Table 10: 5x5mm QFN-5L Dimensions
Symbol Dimension in mm Dimension in inch
MIN NOM MAX MIN NOM MAX
A0.80 0.85 1.00 0.031 0.033 0.039
A1 0.00 0.02 0.05 0.00 0.001 0.002
A2 0.60 0.65 0.50 0.024 0.026 0.031
A3 0.020 REF 0.008 REF
b1 0.25 0.30 0.35 0.010 0.012 0.014
B2 0.45 0.50 0.55 0.018 0.020 0.022
D/E 5.00 BSC 0.197 BSC
D1/E1 4.95 BSC 0.187 BSC
D2A 3.43 3.58 3.73 0.135 0.141 0.147
D2B 2.03 2.18 2.33 0.080 0.086 0.092
E2A 3.90 4.05 4.20 0.154 0.159 0.165
E2B 2.95 3.10 3.25 0.116 0.122 0.128
e1.00 BSC 0.039 BSC
L0.35 0.55 0.75 0.014 0.022 0.030
K0.20 0.008
012012
aaa 0.15 0.006
bbb 0.10 0.004
ccc 0.10 0.004
ddd 0.05 0.002
Mechanical Drawings
Typical Pad Layout Dimensions
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 29
6.2 Typical Pad Layout Dimensions
Figure 23: Recommended Solder Pad Layout for MSOP-8
Notes:
1. Top View
2. Drawing Not to Scale
3. Dimensions are in millimeters
4. To lerance ±0.05mm
3X3 MSOP-8L
L an d P a ttern (mm )
2.37
0.90
5.23
3.43
0.42
0.65
11.34
1.40
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 30 Document Classification: Proprietary January 21, 2008, 1.00
Figure 24: Recommended Solder Pad Layout for QFN-5
Notes:
1. Top View
2. Drawing Not to Scale
3. Dimensions are in millimeters
4. To lerance ±0.05mm
5X5 QFN-5L
La n d P a tte rn (mm )
Package
Outline
5.15
0.30
1.00
0.70
4.05
3.10
3.58
2.18
1.50
0.475
0.50
88PL810/88PL815/88PL830
Datasheet
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88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 32 Document Classification: Proprietary January 21, 2008, 1.00
Ordering Information
Ordering Part Numbers and Package Markings
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 33
7Ordering Information
7.1 Ordering Part Numbers and Package Markings
Figure 11 shows the ordering part numbering scheme of the 88PL810/88PL815/88PL830. For
complete information, contact Marvell FAE or sales representative.
Figure 25: Ordering Part Numbers and Package Markings
7.2 Sample Ordering Part Number
The standard ordering part numbers for the respective solutions are as follows:
Table 11: Order Samples Table
Part Number Marking LDO Output
Voltage LDO Output
Current Ambient Temp
Range1Package2
88PL810-NAK1 L10 1.5V 1.0A -40C to +85C5x5 QFN-5
88PL815-NAK1 L15 1.8V 1.5A -40C to +85C5x5 QFN-5
88PL830-NAK1 L30 2.5V 3.0A -40C to +85C5x5 QFN-5
88PL810-MAE1 L10 1.5V 1.0A -40C to +85C3x3 MSOP-8
88PL815-MAE1 L15 1.8V 1.5A -40C to +85C3x3 MSOP-8
88PL830-MAE1 L30 2.5V 3.0A -40C to +85C3x3 MSOP-8
1. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and
correlation with statistical process controls.
2. Package dimensions are in milimeters.
88PL810/88PL815/88PL830
Datasheet
Doc. No. MV-S102944-00 Rev. E Copyright © 2008 Marvell
Page 34 Document Classification: Proprietary January 21, 2008, 1.00
7.3 Package Markings
Figures 12 and 13 show a typical package marking and pin 1 location for the
88PL810/88PL815/88PL83 0 part in 5 X 5mm QFN-5 and 3 X 3mm MSOP-8.
7.3.1 5 X 5 QFN-5 Package Marking
Figure 26: Package Marking and Pin 1 Locat ion for 5 X 5mm QFN-5
7.3.2 3 X 3 MSOP-8 Package Marking
Figure 27: Package Marking and Pin 1 Locat ion for 3 X 3mm MSOP-8
MRVL
L30 L
YY W W Marking
Pin 1 Location
Assembly Code
Work Week
Last two Digits of the year
Copyright © 2008 Marvell Doc. No. MV-S102944 -00 Rev. E
January 21, 2008, 1.00 Document Classification: Proprietary Page 35
ARevision History
Table 12: Revision History
Document Type Document Revision
Release Rev. E
Document brought over from MS Word
Updated Template
Added new MSOP-8 package and removed DPAK p ackage. Changes included:
Section 1. Signal Description
Section 2. Electrical Specifications
Section 6. Mechanical Drawings
Section 7. Or dwering Info rm a ti o n
