HI-1818A, HI-1828A TM Data Sheet Low Resistance, Single 8-Channel, and Differential 4-Channel, CMOS Analog Multiplexers The Hl-1818A and HI-1828A are monolithic, high performance CMOS analog multiplexers offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. Dielectric Isolation (Dl) processing is used for enhanced reliability and performance (see Application Note 521). Substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. Low output leakage (typically 0.1nA) and low channel ON resistance (250) assure optimum performance in low level or current mode applications. July 1999 File Number 3141.2 Features * Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V * "ON" Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 * Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . 50nA * Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns * Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 5mW * DTL/TTL Compatible Address * Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Applications * Data Acquisition Systems The HI-1818A is a single-ended, 8-Channel multiplexer, while the HI-1828A is a differential 4-Channel version. Either device is ideally suited for medical instrumentation, telemetry systems, and microprocessor based data acquisition systems. * Precision Instrumentation For MIL-STD-883 compliant parts, request the HI-1818A/883. Ordering Information * Demultiplexing * Selector Switch PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE HI1-1818A-2 -55 to 125 16 Ld CERDIP F16.3 HI1-1818A-5 0 to 75 16 Ld CERDIP F16.3 HI1-1828A-2 -55 to 125 16 Ld CERDIP F16.3 HI3-1828A-5 0 to 75 16 Ld PDIP E16.3 Pinouts HI-1818A (CERDIP) TOP VIEW HI-1828A (CERDIP, PDIP) TOP VIEW 16 ADDRESS A0 ADDRESS A1 1 +5V SUPPLY 2 15 -VSUPPLY ENABLE 3 14 +VSUPPLY ADDRESS A1 1 16 ADDRESS A0 +5V SUPPLY 2 15 -VSUPPLY ENABLE 3 14 +VSUPPLY ADDRESS A2 4 13 IN 1 OUT 5 THRU 8 4 IN 8 5 12 OUT IN 8 5 12 OUT 1 THRU 4 IN 7 6 11 IN 2 IN 7 6 11 IN 2 IN 6 7 10 IN 3 IN 6 7 10 IN 3 IN 5 8 9 IN 4 IN 5 8 9 IN 4 1 13 IN 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 HI-1818A, HI-1828A Truth Tables HI-1818A TRUTH TABLE HI-1828A TRUTH TABLE ADDRESS A2 A1 A0 L L L L L H L H L L H H ADDRESS EN "ON" CHANNEL A1 L 1 L L L 1 and 5 L 2 L H L 2 and 6 L 3 H L L 3 and 7 L 4 H H L 4 and 8 X X H None H L L L 5 H L H L 6 H H L L 7 H H H L 8 X X X H None A0 EN "ON" CHANNEL Functional Block Diagrams HI-1818A DIGITAL ADDRESS ENABLE A0 A1 A2 ADDRESS INPUT BUFFERS ENABLE BUFFER MULTIPLEX SWITCHES N IN 1 P DECODERS OUT IN 8 N P HI-1828A ENABLE A0 ADDRESS INPUT BUFFERS A1 ENABLE BUFFER MULTIPLEX SWITCHES N IN 1 P DECODERS OUT 1-4 IN 4 N P IN 5 N P OUT 5-8 IN 8 N 2 P HI-1818A, HI-1828A Schematic Diagrams ADDRESS INPUT BUFFER P3 P5 P1 N1 V+ P4 VCC A D1 200 All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified P6 P7 P8 P9 P10 N6 N7 N8 N9 N10 D2 ADDRESS INPUT V- P2 N4 A N2 N5 N3 V- ADDRESS DECODER V+ EN P11 A2 OR A2 P12 A1 OR A1 All N-Channel Bodies to VAll P-Channel Bodies to V+ A2 or A2 not used for HI-1828A TO P-CHANNEL SWITCH P13 A0 OR A0 P15 P14 P16 TO N-CHANNEL SWITCH N11 N12 N15 N14 N13 V- N16 IN SWITCH CELL MULTIPLEXER SWITCH FROM DECODE N18 V+ All N-Channel Bodies to VAll P-Channel Bodies to V+ Unless Otherwise Specified IN N17 OUT N19 V+ P17 P18 FROM DECODE 3 HI-1818A, HI-1828A Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . (V-) to (V+) Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 85 32 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Ranges HI-1818A/HI-1828A-2. . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-1818A/HI-1828A-5. . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified PARAMETER -2 -5 TEST CONDITIONS TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Note 4 25 - 350 500 - 350 - ns DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) - - 1000 - - 1000 ns 25 - 25 - - 100 - ns 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns To 0.1% 25 - 1.08 - - 1.08 - s To 0.025% 25 - 2.8 - - 2.8 - s 25 - 4 - - 4 - pF Enable Delay (OFF), tOFF(EN) Settling Time Full Channel Input Capacitance, CS(OFF) - Channel Output Capacitance, CD(OFF) HI-1818A 25 - 20 - - 20 - pF 25 - 10 - - 10 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.6 - - 0.6 - pF Digital Input Capacitance, CA 25 - 5 - - 5 - pF Full - - 0.4 - - 0.4 V HI-1828A DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Note 3 Input Leakage Current, IA Full 4.0 - - 4.0 - - V Full - - 1 - - 1 A Full -15 - +15 -15 - +15 V ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VlN 25 - 250 400 - 250 400 Full - - 500 - - 500 OFF Input Leakage Current, IS(OFF) Full - - 50 - - 50 nA ON Channel Leakage Current, lD(ON) Hl-1818A Full - - 250 - - 250 nA Full - - 125 - - 125 nA Full - - 250 - - 250 nA Full - - 125 - - 125 nA Note 2 ON Resistance, rON HI-1828A OFF Output Leakage Current, ID(OFF) HI-1818A HI-1828A 4 HI-1818A, HI-1828A Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified (Continued) TEST CONDITIONS -2 -5 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Power Dissipation, PD Full - - 27.5 - - 27.5 mW Current, I+ Full - - 0.5 - - 0.5 mA Current, I- Full - - 1 - - 1 mA Current, IL Full - - 1 - - 1 mA PARAMETER POWER SUPPLY CHARACTERISTICS NOTES: 2. VOUT = 10V, IOUT = 1mA. 3. To drive from DTL/TTL circuits, 1k pull-up resistors to 5.0V supply are recommended. 4. Time measured to 90% of final output level; VOUT = -5.0V to 5.0V, Digital Inputs = 0V to 4.0V. Test Circuits and Waveforms +15V -15V +5V A2 V+ VAH = 4.0V 50% A1 ENABLE DRIVE (VA) VAL = 0V tON (EN) A0 V- EN OUTPUT 10% +5V ENABLED (S1 ON) OUT 90% VA ENABLE DRIVE 2V/DIV. VL IN 1 HI-1818A (NOTE 5) IN 2-8 50 200 12.5 pF DISABLED OUTPUT 2V/DIV. tOFF (EN) 100ns/DIV. NOTE: 5. Similar connections for HI-1828A. FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1C. WAVEFORMS FIGURE 1. ENABLE DELAYS +15V -15V +5V A2 V+ 4.0V 50% VA 50% OUTPUT 50 VA INPUT 2V/DIV. VL +5V IN 1 A1 HI-1818A (NOTE 6) IN 2 EN IN 3-8 A0 OUT ADDRESS DRIVE (VA) 0V V- S1 ON S2 ON OUTPUT 1V/DIV. 200 12.5 pF tOPEN 100ns/DIV. NOTE: 6. Similar connections for HI-1828A. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. BREAK-BEFORE-MAKE DELAY 5 FIGURE 2C. WAVEFORMS HI-1818A, HI-1828A 1mA V2 IN OUT OUT VIN V2 RON = 1mA 60 350 SWITCH CURRENT (mA) 300 ON RESISTANCE () A V 125oC 250 25oC 200 -55oC 150 -55oC 40 125oC 20 25oC 0 -20 125oC -40 100 -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE OFF LEAKAGE EN -8 4V OUT +10V -6 +10V A ID(ON) EN A1 IN 1 IN 2 -5V IN 3-8 OUT HI-1818A 10V 10 k A0 A1 A2 EN 0.4V NOTE: OUT EN A 10V 50 0V TO 4V Two measurements per channel: 10V and 10V S(OFF) 4V Two measurements per device for ID(OFF): 10V and 10V +10V Similar connection for HI-1828A. 100nA 4V A0 INPUT 10nA 50% ID(ON) - ID(OFF) 2V/DIV. HI-1818A HI-1828A 1nA +5V IS(OFF) HI-1818A HI-1828A 100pA OUTPUT 5V/DIV. -5V 10% 10pA 25 50 75 TEMPERATURE (oC) 100 125 FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE 6 8 FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE +5V A0 -4 -2 0 2 4 6 VOLTAGE ACROSS SWITCH (V) ACCESS TIME TEST CIRCUIT OUT 10V -10 ON LEAKAGE A ID(OFF) 25oC -55oC -60 tA 100ns/DIV. FIGURE 6. ACCESS TIME 50pF 10 HI-1818A, HI-1828A Die Characteristics DIE DIMENSIONS: PASSIVATION: 67.7 mils x 103.5 mils Type: Nitride/Silox Thickness: Silox: 12kA 2kA, Nitride: 3.5kA 1kA METALLIZATION: WORST CASE CURRENT DENSITY: Type: CuAl Thickness: 16kA 2kA 1.43 x 105 A/cm2 at 25mA Metallization Mask Layout HI-1818A VL A1 HI-1828A A0 VL A1 A0 -VSUPPLY EN -15VSUPPLY EN +VSUPPLY A2 OUT 5 THRU 8 +VSUPPLY IN 1 OUTPUT IN 8 IN 7 IN 1 OUT 1 THRU 4 IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 7 IN 6 IN 5 IN 4 IN 3 IN 2 HI-1818A, HI-1828A Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - E 0.300 0.325 E1 0.240 0.280 6.10 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 8 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 0.204 0.355 18.66 - 19.68 5 0.13 - 5 7.62 8.25 6 7.11 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 16 10.92 7 3.81 4 9 Rev. 0 12/93 HI-1818A, HI-1828A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) LEAD FINISH c1 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - eA e ccc M C A - B S eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 16 16 8 Rev. 0 4/94 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 9 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369