1
TM
File Number 3141.2
HI-1818A, HI-1828A
Low Resistance, Single 8-Channel, and
Differential 4-Channel, CMOS Analog
Multiplexers
The Hl-1818A and HI-1828A are monolithic, high
performance CMOS analog multiplexers offering built-in
channel selection decoding plus an inhibit (enable) input for
disabling all channels. Dielectric Isolation (Dl) processing is
used for enhanced reliability and performance (see
Application Note 521). Substrate leakage and parasitic
capacitance are much lower, resulting in extremely low static
errors and high throughput rates. Low output leakage
(typically 0.1nA) and low channel ON resistance (250Ω)
assure optimum performance in low level or current mode
applications.
The HI-1818A is a single-ended, 8-Channel multiple xer, while
the HI-1828A is a diff erential 4-Channel v ersion. Either de vice
is ideally suited for medical instrumentation, telemetry systems,
and microprocessor based data acquisition systems.
F or MIL-STD-883 compliant parts, request the HI-1818A/883.
Features
• Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
• “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Ω
• Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . 50nA
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns
• Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 5mW
• DTL/TTL Compatible Address
• Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HI1-1818A-2 -55 to 125 16 Ld CERDIP F16.3
HI1-1818A-5 0 to 75 16 Ld CERDIP F16.3
HI1-1828A-2 -55 to 125 16 Ld CERDIP F16.3
HI3-1828A-5 0 to 75 16 Ld PDIP E16.3
Pinouts HI-1818A (CERDIP)
TOP VIEW HI-1828A (CERDIP, PDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
ADDRESS A1
+5V SUPPLY
ENABLE
ADDRESS A2
IN 8
IN 7
IN 5
IN 6
ADDRESS A0
+VSUPPLY
IN 1
OUT
IN 2
IN 3
IN 4
-VSUPPLY
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
ADDRESS A1
+5V SUPPLY
ENABLE
OUT 5 THRU 8
IN 8
IN 7
IN 5
IN 6
ADDRESS A0
+VSUPPLY
IN 1
OUT 1 THRU 4
IN 2
IN 3
IN 4
-VSUPPLY
Data Sheet July 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 1999
2
Truth Tables
Functional Block Diagrams HI-1818A
HI-1828A
HI-1818A TRUTH TABLE
ADDRESS
“ON” CHANNELA2A1A0EN
LLLL 1
LLHL 2
LHLL 3
LHHL 4
HLLL 5
HLHL 6
HHLL 7
HHHL 8
X X X H None
HI-1828A TRUTH TABLE
ADDRESS
“ON” CHANNELA1A0EN
L L L 1 and 5
L H L 2 and 6
H L L 3 and 7
H H L 4 and 8
X X H None
N
A0A1A2ENABLE
DIGITAL ADDRESS
ENABLE
BUFFER
DECODERS P
MULTIPLEX
SWITCHES
N P
IN 1
OUT
IN 8
ADDRESS
INPUT
BUFFERS
N
A0A1ENABLE
ENABLE
BUFFER
DECODERS P
MULTIPLEX
SWITCHES
N P
IN 1
OUT 1-4
IN 4
ADDRESS
INPUT
BUFFERS
N P
N P
IN 5
OUT 5-8
IN 8
HI-1818A, HI-1828A
3
Schematic Diagrams
All N-Channel Bodies to V-
All P-Channel Bodies to V+
Unless Otherwise Specified
ADDRESS INPUT BUFFER
All N-Channel Bodies to V-
All P-Channel Bodies to V+
A2 or A2 not used for HI-1828A
ADDRESS DECODER
All N-Channel Bodies to V-
All P-Channel Bodies to V+
Unless Otherwise Specified
MULTIPLEXER SWITCH
N9
P9
N10
P10
N8
P8
N7
P7
N6
P6
N5
N4
N3
V-
N1
P1
P2
N2
P5
P4
VCC
V+
V-
ADDRESS
INPUT
D1
D2
200Ω
P3
A
A
V+
V-
A0 OR
A0
N14
N13
A1 OR
A1
N12N11
A2 OR
A2
EN
P14
P13
P12
P11
N15
P15
N16
P16
TO P-CHANNEL
SWITCH
TO N-CHANNEL
SWITCH
IN SWITCH CELL
V+
N18
N17
N19
P17
P18
FROM DECODE
FROM DECODE
V+
OUTIN
HI-1818A, HI-1828A
4
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . (V-) to (V+)
Operating Conditions
Temperature Ranges
HI-1818A/HI-1828A-2. . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-1818A/HI-1828A-5. . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 85 32
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5
UNITSMIN TYP MAX MIN TYP MAX
DYNAMIC CHARACTERISTICS
Access Time, tANote 4 25 - 350 500 - 350 - ns
Full - - 1000 - - 1000 ns
Break-Before-Make Delay, tOPEN 25 - 25 - - 100 - ns
Enable Delay (ON), tON(EN) 25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Enable Delay (OFF), tOFF(EN) 25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Settling Time To 0.1% 25 - 1.08 - - 1.08 - µs
To 0.025% 25 - 2.8 - - 2.8 - µs
Channel Input Capacitance, CS(OFF) 25 - 4 - - 4 - pF
Channel Output Capacitance, CD(OFF) -
HI-1818A 25 - 20 - - 20 - pF
HI-1828A 25 - 10 - - 10 - pF
Input to Output Capacitance, CDS(OFF) 25 - 0.6 - - 0.6 - pF
Digital Input Capacitance, CA25 - 5 - - 5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL Full - - 0.4 - - 0.4 V
Input High Threshold, VAH Note 3 Full 4.0 - - 4.0 - - V
Input Leakage Current, IAFull - - 1 - - 1 µA
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, VlN Full -15 - +15 -15 - +15 V
ON Resistance, rON Note 2 25 - 250 400 - 250 400 Ω
Full - - 500 - - 500 Ω
OFF Input Leakage Current, IS(OFF) Full - - 50 - - 50 nA
ON Channel Leakage Current, lD(ON)
Hl-1818A Full - - 250 - - 250 nA
HI-1828A Full - - 125 - - 125 nA
OFF Output Leakage Current, ID(OFF)
HI-1818A Full - - 250 - - 250 nA
HI-1828A Full - - 125 - - 125 nA
HI-1818A, HI-1828A
5
POWER SUPPLY CHARACTERISTICS
Power Dissipation, PDFull - - 27.5 - - 27.5 mW
Current, I+ Full - - 0.5 - - 0.5 mA
Current, I- Full - - 1 - - 1 mA
Current, ILFull - - 1 - - 1 mA
NOTES:
2. VOUT = ±10V, IOUT = 1mA.
3. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to 5.0V supply are recommended.
4. Time measured to 90% of final output level; VOUT = -5.0V to 5.0V, Digital Inputs = 0V to 4.0V.
Electrical Specifications Supplies = +15V, -15V, +5V; VAL = 0.4V, VAH = 4.0V, Unless Otherwise Specified (Continued)
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5
UNITSMIN TYP MAX MIN TYP MAX
±
Test Circuits and Waveforms
FIGURE 1A. MEASUREMENT POINTS
NOTE:
5. Similar connections for HI-1828A.
FIGURE 1B. TEST CIRCUIT FIGURE 1C. WAVEFORMS
FIGURE 1. ENABLE DELAYS
FIGURE 2A. MEASUREMENT POINTS
NOTE:
6. Similar connections for HI-1828A.
FIGURE 2B. TEST CIRCUIT FIGURE 2C. WAVEFORMS
FIGURE 2. BREAK-BEFORE-MAKE DELAY
VAH = 4.0V
VAL = 0V
OUTPUT
10%
tOFF
(EN)
90%
tON
(EN)
50% ENABLE DRIVE
(VA)
+15V
VA
+5V
-15V +5V
V+ V- VL
IN 1
IN 2-8
OUT
HI-1818A
200 12.5
Ω
50
Ω
A0
EN
A1
A2
pF
(NOTE 5)
ENABLE DRIVE
2V/DIV.
OUTPUT
2V/DIV.
100ns/DIV.
ENABLED
(S1 ON)
DISABLED
50%50%
0V
4.0V
ADDRESS
DRIVE (VA)
tOPEN
OUTPUT
+15V
VA
+5V
-15V +5V
V+ V- VL
IN 1
IN 2
IN 3-8
OUT
HI-1818A
50
Ω
A0
EN
A1
A2
200 12.5
ΩpF
(NOTE 6)
VA INPUT
2V/DIV.
OUTPUT
1V/DIV.
100ns/DIV.
S2 ONS1 ON
HI-1818A, HI-1828A
6
FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE
FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE FIGURE 6. ACCESS TIME
350
300
250
200
150
100-10-8-6-4-20246810
ANALOG INPUT (V)
ON RESISTANCE (Ω)
125oC
25oC
-55oC
OUT
IN
VIN
V2
1mA
RON = V2
1mA
60
20
0
-20
-40
-60-10-8-6-4-20246810
VOLTAGE ACROSS SWITCH (V)
SWITCH CURRENT (mA)
40
OUT
V
A
25oC
-55oC
125oC
-55oC
125oC
25oC
OUT
EN
OUT
±10V
EN 4V
+10V
AID(OFF)
±10V
A
S(OFF)
4V
+10V
OUT
±10V
EN
0.4V
+10V
AID(ON)
A0A1
OFF LEAKAGE ON LEAKAGE
NOTE:
Two measurements per channel:
±10V and 10V
Twomeasurementsperdevicefor
ID(OFF):±10V and 10V
±
±
100nA
10nA
1nA
100pA
10pA25 50 75 100 125
TEMPERATURE (oC)
HI-1818A
ID(ON) - ID(OFF)
HI-1828A
IS(OFF)
HI-1818A
HI-1828A
100ns/DIV.
A0INPUT
2V/DIV.
50Ω
50pF
ENA0
ACCESS TIME TEST CIRCUIT
† Similar connection for HI-1828A.
A1A2
HI-1818A†
0V T O 4V
IN 3-8
IN 2
IN 1
-5V
+5V
10
kΩ
4V
50%
+5V
OUTPUT
5V/DIV.
-5V
10%
tA
OUT
HI-1818A, HI-1828A
7
Die Characteristics
DIE DIMENSIONS:
67.7 mils x 103.5 mils
METALLIZATION:
Type: CuAl
Thickness: 16kű2kÅ
PASSIVATION:
Type: Nitride/Silox
Thickness: Silox: 12kű2kÅ, Nitride: 3.5kű1kÅ
WORST CASE CURRENT DENSITY:
1.43 x 105 A/cm2 at 25mA
Metallization Mask Layout
HI-1818A HI-1828A
VLA1A0
-VSUPPLY
+VSUPPLY
IN 1
OUTPUT
IN 2IN 3IN 4IN 5IN 6
IN 7
IN 8
A2
EN
VLA1A0
-15VSUPPLY
+VSUPPLY
IN 1
OUT 1
IN 2IN 3IN 4IN 5IN 6
IN 7
IN 8
OUT 5
EN
THRU 4
THRU 8
HI-1818A, HI-1828A
8
HI-1818A, HI-1828A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. ControllingDimensions:INCH.IncaseofconflictbetweenEnglishand
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eBand eCare measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
9
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
HI-1818A, HI-1828A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Indexarea:Anotchor a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa C A - B
MD
S S
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N16 168
Rev. 0 4/94
