DESCRIPTION
The A5979 is a complete microstepping motor driver with
built-in translator. It is designed to operate bipolar stepper
motors in full-, half-, quarter-, and sixteenth-step modes, with
output drive capability of 40 V and ±2.8 A. The A5979 includes
a fixed off-time current regulator that has the ability to operate in
slow-, fast-, or mixed-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A5979. Simply inputting one pulse on the STEP input drives the
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or sixteenth-step). There are no phase sequence tables,
high-frequency control lines, or complex interfaces to program.
The A5979 interface is an ideal fit for applications where a
complex microprocessor is unavailable or overburdened.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current
protection. Special power-up sequencing is not required.
The A5979 is supplied in a thin (<1.2 mm) 28-pin TSSOP
with an exposed thermal pad (suffix LP). The package is lead
(Pb) free (suffix -T), with 100% matte-tin leadframe plating.
A5979-DS, Rev. 2
FEATURES AND BENEFITS
• ±2.8 A, 40 V output rating
• Low RDS(on) outputs, 0.22 Ω source, 0.15 Ω sink typical
• Automatic current decay mode detection/selection
• 3 to 5.5 V logic supply voltage range
• Mixed, fast, and slow current decay modes
• Home output
• Synchronous rectification for low power dissipation
• Internal UVLO and thermal shutdown circuitry
• Crossover-current protection
• Short-to-ground protection
• Short-to-VBB protection
• Shorted load protection
Microstepping DMOS Driver with Translator
Package: 28-lead TSSOP (suffix LP) with
exposed thermal pad
Typical Application
A5979
Not to scale
A5979
Microcontroller
or
Controller Logic
Logic
Supply
Load
Supply
VDD
REF
HOMEn
STEP
DIR
RESETn
SLEEPn
ENABLEn
MS1
MS2
SR
RC1
RC2
VREG
CP1
CP2
VCP
VBB1
VBB2
OUT1A
OUT1B
SENSE1
SENSE2
OUT2A
OUT2B
GND
PGND
100 µF
PFD
Microstepping DMOS Driver with Translator
A5979
2
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
SELECTION GUIDE
Part Number Package Packing
A5979GLPTR-T 28-pin TSSOP 4000 pieces per reel
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage VBB 40 V
Logic Supply Voltage VDD 7 V
Logic Input Voltage Range VIN
Pulsed, tW > 30 ns –0.3 to VDD + 0.3 V
Pulsed, tW < 30 ns –1 to VDD + 1 V
SENSEx Voltage (DC) VSENSE 0.5 V
Reference Voltage VREF VDD V
Output Current IOUT
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
±2.8 A
Operating Ambient Temperature TARange G –40 to 105 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg
–55 to 150 °C
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W
*Additional thermal information available on Allegro website.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
SPECIFICATIONS
Microstepping DMOS Driver with Translator
A5979
3
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal List Table
Number Name Description
1 SENSE1 Sense resistor for bridge 1
2 HOMEn Logic output
3 DIR Logic input
4 OUT1A DMOS full-bridge 1, output A
5 PFD Analog input for mixed-decay setting
6 RC1 Analog input for fixed off-time, bridge 1
7 AGND* Analog ground
8 REF Gm reference input
9 RC2 Analog input for fixed off-time, bridge 2
10 VDD Logic supply voltage
11 OUT2A DMOS full-bridge 2, output A
12 MS2 Logic input
13 MS1 Logic input
14 SENSE2 Sense resistor for bridge 2
15 VBB2 Load supply for bridge 2
16 SR Logic input
17 RESETn Logic input
18 OUT2B DMOS full-bridge 2, output B
19 STEP Logic input
20 VREG Regulator decoupling
21 PGND* Power ground
22 VCP Reservoir capacitor
23 CP1 Charge pump capacitor
24 CP2 Charge pump capacitor
25 OUT1B DMOS full-bridge 1, output B
26 ENABLEn Logic input
27 SLEEPn Logic input
28 VBB1 Load supply for bridge 1
– PAD* Thermal pad
* GND, PGND, and thermal pad must be connected together externally under the device.
SENSE1
HOMEn
DIR
OUT1A
PFD
RC1
AGND
REF
RC2
VDD
OUT2A
MS2
MS1
SENSE2
VBB1
SLEEPn
ENABLEn
OUT1B
CP2
CP1
VCP
PGND
VREG
STEP
OUT2B
RESETn
SR
VBB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PAD
PINOUT DIAGRAM AND TERMINAL LIST TABLE
Package LP,
28-Pin TSSOP
Microstepping DMOS Driver with Translator
A5979
4
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
SENSE1
SENSE2
VREG
VCP
CP2
DAC
VDD
PWM Timer
PWM Latch
Blanking
Mixed Decay
DAC
STEP
DIR
MS1
PWM Timer
PWM Latch
Blanking
Mixed Decay
CP1
Charge
Pump
VBB1
OUT1A
OUT1B
VBB2
OUT2A
OUT2B
Translator
Gate
Drive
DMOS
H-BRIDGE
DMOS
H-BRIDGE
MS2
REF
UVLO
Logic
Supply
Reference
Supply
4
4
RESETn
SLEEPn
SR
ENABLEn
PFD
RC2
RC1
HOMEn
Control
Logic
Load
Supply
VDD
Regulator
SENSE1
SENSE1
Exposed Thermal Pad
AGNDPGND
(Required)
÷8
Microstepping DMOS Driver with Translator
A5979
5
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS1: Valid at TA = 25°C, VBB = 40 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Load Supply Voltage Range VBB
Operating 8 – 40 V
During sleep mode 0 – 40 V
Output Leakage Current IDSS
VOUT = VBB – <1 20 µA
VOUT = 0 V – <1 –20 µA
Output On-Resistance RDS(On)
Source driver, IOUT = –2.5 A, TJ = 25°C – 0.22 0.30 Ω
Sink driver, IOUT = 2.5 A, TJ = 25°C – 0.15 0.24 Ω
Body Diode Forward Voltage VF
Source diode, IF = –2.5 A – 1 1.4 V
Source diode, IF = 2.5 A – 1 1.4 V
VBB Supply Current IBB
fPWM < 50 kHz, duty cycle = 50% – – 8 mA
Operating, outputs disabled – – 6 mA
Sleep mode – <1 20 μA
VDD Supply Current IDD
fPWM < 50 kHz, duty cycle = 50% – – 12 mA
Operating, outputs disabled – – 10 mA
Sleep mode – <1 20 μA
Control Logic
Logic Supply Voltage Range VDD Operating 3 – 5.5 V
Logic Input Voltage VIN(1) 0.7× VDD – – V
VIN(0) – – 0.3 ×VDD V
Logic Input Current IIN(1) VIN = 0.7 × VDD –20 <1 20 µA
IIN(0) VIN = 0.3 × VDD –20 <1 20 µA
Maximum Step Frequency3fSTEP 500 – – kHz
HOMEn Output Voltage VOH IOH = –200 µA 0.7× VDD – – V
VOL IOL = 200 µA – – 0.3 ×VDD V
Blank Time tBLANK RT = 56 kΩ, CT = 680 pF 700 950 1200 ns
Fixed Off-Time tOFF RT = 56 kΩ, CT = 680 pF 30 38 46 μs
Reference Input Voltage Range VREFxOperating 0 – VDD V
Reference Input Current IREF – – ±3 μA
Gain (Gm) Error4EG
VREF = 2 V, phase current = 100.0% – – ±5 %
VREF = 2 V, phase current = 70.7% – – ±5 %
VREF = 2 V, phase current = 38.3% – – ±10 %
Crossover Dead Time tDT 100 475 800 ns
Motor Output Slew Time tSR 10% to 90% rising; 90% to 10% falling 20 – 120 ns
Continued on the next page...
Microstepping DMOS Driver with Translator
A5979
6
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Protection Circuits
VDD UVLO Threshold VUV(VBB) VBB rising 2.45 2.7 2.95 V
VDD UVLO Hysteresis VUV(VBB)HYS 50 100 – mV
Overcurrent Protection Threshold IOCPST 3.5 – – A
Overcurrent Latch-Off Time tLATCHOFF(OC) – 1.6 – ms
Overcurrent Protection Blank Time tBLANK(OC) – 1.5 – µs
Thermal Shutdown Temperature TJSD 155 165 175 °C
Thermal Shutdown Hysteresis TJSDHYS – 15 – °C
1 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within
the specified maximum and minimum limits.
2 Negative current is defined as coming out of (sourcing from) the specified device pin.
3 Operation at a step frequency greater than the specified minimum value is possible but not warranteed.
4 EG = ( [ VREF
/ 8] – VSENSE ) / ( VREF
/ 8 ).
ELECTRICAL CHARACTERISTICS1 (continued): Valid at TA = 25°C, VBB = 40 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Microstepping DMOS Driver with Translator
A5979
7
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Table 1: Microstep Resolution Truth Table
MS2 MS1 Microstep Resolution Excitation Mode
L L Full Step 2 Phase
L H Half Step 1-2 Phase
H L Quarter Step W1-2 Phase
H H Sixteenth Step 4W1-2 Phase
Time Duration Symbol Typ. Unit
STEP Minimum, high pulse width tA1 µs
STEP Minimum, low pulse width tB1 µs
Setup time, input change to STEP tC200 ns
Hold time, input change to STEP tD200 ns
Maximum wakeup time tWU 1 ms
STEP
MSx,
RESETn, or DIR
tA
tCtD
tWU
tB
SLEEPn
Figure 1: Logic Interface Timing Diagram
Microstepping DMOS Driver with Translator
A5979
8
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Device Operation
The A5979 is a complete microstepping motor driver with built-
in translator for easy operation with minimal control lines. It is
designed to operate bipolar stepper motors in full-, half-,
quarter-, and sixteenth-step modes. The current in each of the two
output full-bridges, all N-channel DMOS, is regulated with fixed
off-time pulse-width modulated (PWM) control circuitry. The
full-bridge current at each step is set by the value of an external
current-sense resistor (RS), a reference voltage (VREF), and the
output voltage of its DAC (which in turn is controlled by the
output of the translator).
At power-up, or reset, the translator sets the DACs and phase
current polarity to the initial home state (see figures for home-
state conditions), and sets the current regulator for both phases to
mixed-decay mode. When a step command signal occurs on the
STEP input, the translator automatically sequences the DACs to
the next level (see Table 2 for the current level sequence and cur-
rent polarity). The microstep resolution is set by inputs MS1 and
MS2 as shown in Table 1. If the new DAC output level is lower
than the previous level, the decay mode for that full-bridge will
be set by the PFD input (fast, slow, or mixed decay). If the new
DAC level is higher or equal to the previous level, then the decay
mode for that full-bridge will be slow decay. This automatic
current-decay selection will improve microstepping performance
by reducing the distortion of the current waveform due to the
motor BEMF.
When stepping, if the new output levels of the DACs are higher
than or equal to their previous levels, then the decay mode for
that full-bridge is set to slow. If the new output levels of the
DACs are lower than their previous output levels, then the decay
mode for that full-bridge is set by the state of the PFD input (see
PFD input description). This automatic current decay selection
improves microstepping performance by reducing the distortion
of the current waveform that results from the back-EMF of the
motor. See Figure 6 on page 14 for decay mode detail.
Internal PWM Current Control
Each full-bridge is controlled by a fixed off-time PWM current-
control circuit that limits the load current to an appropriate
level (ITRIP). Initially, a diagonal pair of source and sink DMOS
outputs are enabled, and current flows through the motor wind-
ing and the current-sense resistor, RS. When the voltage across
RS rises to the DAC output voltage, the current-sense comparator
resets the PWM latch, which turns off the source driver (in slow-
decay mode) or the sink and source drivers (in fast- or mixed-
decay mode).
The maximum level of current limiting is set by the selection of
RS and the voltage at the VREF input with a transconductance
function approximated by:
ITRIPmax = VREF / (8 × RS)
The DAC output reduces the VREF output to the current-sense
comparator in precise steps (see Table 2 for % ITRIPmax at each
step).
ITRIP = (% ITRIPmax / 100) × ITRIPmax
It is critical to ensure that the maximum rating on the SENSE
terminal is not exceeded (0.5 V). For full-step mode, VREF can be
applied up to the maximum rating of VDD, because the peak sense
value is 0.707 × VREF / 8. In all other modes, VREF should not
exceed 4 V.
Fixed Off-Time
The internal PWM current-control circuitry uses a one-shot to
control the time that the drivers remain off. The one-shot off-
time, tOFF, is determined by the selection of an external resis-
tor (RT) and capacitor (CT) connected between the RC timing
terminal and ground. The off-time, over a range of values of CT
= 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated
by:
tOFF = RT × CT
RC Blanking
In addition to the fixed off-time of the PWM control circuit, the
CT component sets the comparator blanking time. This func-
tion blanks the output of the current-sense comparator when the
outputs are switched by the internal current-control circuitry. The
comparator output is blanked to prevent false overcurrent detec-
tion due to reverse-recovery currents of the clamp diodes, and/
or switching transients related to the capacitance of the load. The
blank time, tBLANK, can be approximated by:
tBLANK = 1400 × CT
Microstepping DMOS Driver with Translator
A5979
9
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Step Input (STEP)
A low-to-high transition on the STEP input sequences the transla-
tor and advances the motor one increment. The translator controls
the input to the DACs and the direction of current flow in each
winding. The size of the increment is determined by the state of
inputs MS1 and MS2 (see Table 1).
Microstep Select (MS1 and MS2)
Input terminals MS1 and MS2 select the microstepping format
per Table 1. Changes to these inputs do not take effect until the
STEP command.
Direction Input (DIR)
The state of the DIR input will determine the direction of rotation
of the motor.
Percent Fast-Decay Input (PFD)
When a STEP input command results in a lower output current
than the previous step, it switches the output current decay for
that bridge to either slow-, fast-, or mixed-decay, depending on
the voltage level at the PFD input. If the voltage at the PFD input
is greater than 0.6 × VDD, then slow-decay is selected. If the
voltage on the PFD input is less than 0.21 × VDD, then fast-decay
is selected. Mixed-decay is selected when the voltage on the
PFD input is between these two levels. This terminal should be
decoupled with a 0.1 µF capacitor.
Mixed-Decay Operation
If the voltage on the PFD input is between 0.6 × VDD and 0.21 ×
VDD, the bridge will operate in mixed-decay mode when a STEP
input command results in a lower output current that the previous
step. As the trip point is reached, the bridge will go into fast-
decay mode until the voltage on the RC terminal decays to the
voltage applied to the PFD terminal. The time the bridge remains
in fast-decay is approximated by:
tFD = RT × CT × In (0.6 × VDD / VPFD)
After this fast-decay portion, tFD, the bridge will switch to slow-
decay mode for the remainder of the fixed off-time period.
Reset Input (RESETn)
The RESETn input (active low) sets the translator to a predefined
home state (see figures for home state conditions) and turns off
all of the DMOS outputs. The HOMEn output goes low and all
STEP inputs are ignored until the RESETn input goes high.
Home Output (HOMEn)
The HOMEn output is a logic output indicator of the initial state
of the translator. At power-up, the translator is reset to the home
state (see figures for home state conditions), and the HOMEn
output will be low. When the translator is not in the home state,
this output is high.
Synchronous Rectification
When a PWM off-cycle is triggered by an internal current con-
trol, load current will recirculate according to the decay mode
selected by the control logic. The A5979 synchronous rectifica-
tion feature will turn on the appropriate MOSFETs during the
current decay and effectively short out the body diodes with the
low RDS(ON) driver. This will reduce power dissipation signifi-
cantly and eliminate the need for external Schottky diodes for
most applications.
The synchronous rectification can be set in either active mode or
disabled mode using the SR pin.
Synchronous Rectification Mode (SR)
When the SR input is logic-low, active mode is enabled and syn-
chronous rectification will occur. Reversal of the current in the
motor winding is prevented when using this mode by turning off
synchronous rectification if the current in the winding decays to
zero. When the SR input is logic-high, synchronous rectification
is disabled. Synchronous rectification is typically disabled only
when external diodes are required to transfer power dissipation
from the A5979 package to the external diodes.
Enable Input (ENABLEn)
This active-low input enables all of the DMOS outputs. When
logic-high, the outputs are disabled. Inputs to the transla-
tor (STEP, DIR, MS1, MS2) are all active independent of the
ENABLEn input state.
Sleep Mode (SLEEPn)
This active-low input is used to minimize power consumption
when the device is not in use. Sleep mode disables much of the
internal circuitry, including the output DMOS, regulator, and
charge pump. A logic-high allows normal operation and a rising
edge on this input resets the translator to the home position.
When coming out of sleep mode, 1 ms is required before issuing
a STEP command, to allow the charge pump to stabilize.
Microstepping DMOS Driver with Translator
A5979
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Charge Pump (CP1 and CP2)
The charge pump is used to generate a gate supply greater than
VBB to drive the source-side DMOS gates. A 0.22 µF ceramic
capacitor is required between CP1 and CP2, and a 0.22 µF
ceramic capacitor is required between VCP and VBB. VCP is
internally monitored, and in the case of a fault condition, the
outputs of the device are disabled.
VREG
This internally generated voltage is used to operate the sink-side
DMOS gates. The VREG terminal should be decoupled with
a 0.22 µF capacitor to ground. VREG is internally monitored,
and in the case of a fault condition, the outputs of the device are
disabled.
Shutdown
In the event of a fault (excessive junction temperature, or low
voltage on VCP or VREG), the outputs of the device are dis-
abled until the fault condition is removed. At power-up, and in
the event of low VDD, the undervoltage lockout (UVLO) circuit
disables the drivers and resets the translator to the home position.
Overcurrent Protection (OCP)
If any FET’s current exceeds IOCP for longer than the blank time,
all FETs are disabled for 1.6 ms. RSENSE is not required for low-
side OCP to function and the OCP threshold is independent of the
RSENSE value.
Microstepping DMOS Driver with Translator
A5979
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
IOUT1(A→B)
IOUT2(A→B)
70%
70%
1
2
34
IOUT1(A→B)
IOUT2(A→B)
70%
70%
2
3
4
5
6
7
8
1
PHASE CURRENT DIAGRAMS
Figure 2: Full Step
MS2 = L, MS1 = L, DIR = H. See Table 2 for step number detail.
Figure 3: Half Step
MS2 = L, MS1 = H, DIR = H. See Table 2 for step number detail.
Microstepping DMOS Driver with Translator
A5979
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
I
OUT1
(A→B)
I
OUT2
(A→B)
70%
70%
3
5
7
9
11
13
15
1
I
OUT1
(A→B)
I
OUT2
(A→B)
70%
70%
9
17
25
33
41
49
57
1
Figure 4: Quarter Step
MS2 = H, MS1 = L, DIR = H. See Table 2 for step number detail.
Figure 5: Sixteenth Step
MS2 = H, MS1 = H, DIR = H. See Table 2 for step number detail.
Microstepping DMOS Driver with Translator
A5979
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Table 2: Step Sequencing Settings
DIR = H; 360° = 4 full steps; home microstep position at step angle 45º
* Home state; HOMEn output low.
Full
Step
#
Half
Step
#
1/4
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
Full
Step
#
Half
Step
#
1/4
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
1 1 1 100.0 0.0 0.0 5 9 33 -100.0 0.0 180.0
2 99.5 9.8 5.6 34 -99.5 -9.8 185.6
3 98.1 19.5 11.3 35 -98.1 -19.5 191.3
4 95.7 29.0 16.9 36 -95.7 -29.0 196.9
2 5 92.4 38.3 22.5 10 37 -92.4 -38.3 202.5
6 88.2 47.1 28.1 38 -88.2 -47.1 208.1
7 83.1 55.6 33.8 39 -83.1 -55.6 213.8
8 77.3 63.4 39.4 40 -77.3 -63.4 219.4
1* 2* 3* 9* 70.7* 70.7* 45.0* 3 6 11 41 -70.7 -70.7 225.0
10 63.4 77.3 50.6 42 -63.4 -77.3 230.6
11 55.6 83.1 56.3 43 -55.6 -83.1 236.3
12 47.1 88.2 61.9 44 -47.1 -88.2 241.9
4 13 38.3 92.4 67.5 12 45 -38.3 -92.4 247.5
14 29.0 95.7 73.1 46 -29.0 -95.7 253.1
15 19.5 98.1 78.8 47 -19.5 -98.1 258.8
16 9.8 99.5 84.4 48 -9.8 -99.5 264.4
3 5 17 0.0 100.0 90.0 7 13 49 0.0 -100.0 270.0
18 -9.8 99.5 95.6 50 9.8 -99.5 275.6
19 -19.5 98.1 101.3 51 19.5 -98.1 281.3
20 -29.0 95.7 106.9 52 29.0 -95.7 286.9
6 21 -38.3 92.4 112.5 14 53 38.3 -92.4 292.5
22 -47.1 88.2 118.1 54 47.1 -88.2 298.1
23 -55.6 83.1 123.8 55 55.6 -83.1 303.8
24 -63.4 77.3 129.4 56 63.4 -77.3 309.4
2 4 7 25 -70.7 70.7 135.0 4 8 15 57 70.7 -70.7 315.0
26 -77.3 63.4 140.6 58 77.3 -63.4 320.6
27 -83.1 55.6 146.3 59 83.1 -55.6 326.3
28 -88.2 47.1 151.9 60 88.2 -47.1 331.9
8 29 -92.4 38.3 157.5 16 61 92.4 -38.3 337.5
30 -95.7 29.0 163.1 62 95.7 -29.0 343.1
31 -98.1 19.5 168.8 63 98.1 -19.5 348.8
32 -99.5 9.8 174.4 64 99.5 -9.8 354.4
Microstepping DMOS Driver with Translator
A5979
14
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Current Decay
Mode
Full-Step
Winding Current
0 A
Current Decay
Mode
Half-Step
Winding Current
0 A
Current Decay
Mode
Quarter-Step
Winding Current
0 A
Slow
Decay
Set
by
PFD
Input
Slow
Decay
Slow
Decay
Slow
Decay
Slow
Decay
Set
by
PFD
Input
Set
by
PFD
Input
Slow
Decay
Set by
PFD
Input
Slow
Decay
Slow
Decay
Slow
Decay
Set by
PFD
Input
Set by
PFD
Input
Figure 6: Automatic Decay Mode
Microstepping DMOS Driver with Translator
A5979
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Figure 7: LP Package, 28-Pin TSSOP with Exposed Thermal Pad
1.20 MAX
0.10 MAX
C
SEATING
PLANE
C0.10
28X
6.10
0.65
0.45
1.65
3.00
3.00
5.00
5.00
0.25
0.65
21
28
GAUGE PLANE
SEATING PLANE
B
A
28
21
ATerminal #1 mark area
B
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
4.40 ±0.10 6.40 ±0.20
(1.00)
9.70 ±0.10
C
C
0.60 ±0.15
4° ±4
0.15 +0.05
–0.06
0.25 +0.05
–0.06
PACKAGE OUTLINE DRAWING
Microstepping DMOS Driver with Translator
A5979
16
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Current
Revision Date Description of Revision
– December 21, 2015 Initial release
1 January 21, 2016 Corrected formula on page 8
2 May 31, 2016 Corrected setup and hold time units on page 7
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
